1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2022 Luca Weiss <luca.weiss@fairphone.com>
4 */
5
6#include <linux/device.h>
7#include <linux/interconnect.h>
8#include <linux/interconnect-provider.h>
9#include <linux/mod_devicetable.h>
10#include <linux/module.h>
11#include <linux/platform_device.h>
12#include <dt-bindings/interconnect/qcom,sm6350.h>
13
14#include "bcm-voter.h"
15#include "icc-rpmh.h"
16#include "sm6350.h"
17
18static struct qcom_icc_node qhm_a1noc_cfg = {
19 .name = "qhm_a1noc_cfg",
20 .id = SM6350_MASTER_A1NOC_CFG,
21 .channels = 1,
22 .buswidth = 4,
23 .num_links = 1,
24 .links = { SM6350_SLAVE_SERVICE_A1NOC },
25};
26
27static struct qcom_icc_node qhm_qup_0 = {
28 .name = "qhm_qup_0",
29 .id = SM6350_MASTER_QUP_0,
30 .channels = 1,
31 .buswidth = 4,
32 .num_links = 1,
33 .links = { SM6350_A1NOC_SNOC_SLV },
34};
35
36static struct qcom_icc_node xm_emmc = {
37 .name = "xm_emmc",
38 .id = SM6350_MASTER_EMMC,
39 .channels = 1,
40 .buswidth = 8,
41 .num_links = 1,
42 .links = { SM6350_A1NOC_SNOC_SLV },
43};
44
45static struct qcom_icc_node xm_ufs_mem = {
46 .name = "xm_ufs_mem",
47 .id = SM6350_MASTER_UFS_MEM,
48 .channels = 1,
49 .buswidth = 8,
50 .num_links = 1,
51 .links = { SM6350_A1NOC_SNOC_SLV },
52};
53
54static struct qcom_icc_node qhm_a2noc_cfg = {
55 .name = "qhm_a2noc_cfg",
56 .id = SM6350_MASTER_A2NOC_CFG,
57 .channels = 1,
58 .buswidth = 4,
59 .num_links = 1,
60 .links = { SM6350_SLAVE_SERVICE_A2NOC },
61};
62
63static struct qcom_icc_node qhm_qdss_bam = {
64 .name = "qhm_qdss_bam",
65 .id = SM6350_MASTER_QDSS_BAM,
66 .channels = 1,
67 .buswidth = 4,
68 .num_links = 1,
69 .links = { SM6350_A2NOC_SNOC_SLV },
70};
71
72static struct qcom_icc_node qhm_qup_1 = {
73 .name = "qhm_qup_1",
74 .id = SM6350_MASTER_QUP_1,
75 .channels = 1,
76 .buswidth = 4,
77 .num_links = 1,
78 .links = { SM6350_A2NOC_SNOC_SLV },
79};
80
81static struct qcom_icc_node qxm_crypto = {
82 .name = "qxm_crypto",
83 .id = SM6350_MASTER_CRYPTO_CORE_0,
84 .channels = 1,
85 .buswidth = 8,
86 .num_links = 1,
87 .links = { SM6350_A2NOC_SNOC_SLV },
88};
89
90static struct qcom_icc_node qxm_ipa = {
91 .name = "qxm_ipa",
92 .id = SM6350_MASTER_IPA,
93 .channels = 1,
94 .buswidth = 8,
95 .num_links = 1,
96 .links = { SM6350_A2NOC_SNOC_SLV },
97};
98
99static struct qcom_icc_node xm_qdss_etr = {
100 .name = "xm_qdss_etr",
101 .id = SM6350_MASTER_QDSS_ETR,
102 .channels = 1,
103 .buswidth = 8,
104 .num_links = 1,
105 .links = { SM6350_A2NOC_SNOC_SLV },
106};
107
108static struct qcom_icc_node xm_sdc2 = {
109 .name = "xm_sdc2",
110 .id = SM6350_MASTER_SDCC_2,
111 .channels = 1,
112 .buswidth = 8,
113 .num_links = 1,
114 .links = { SM6350_A2NOC_SNOC_SLV },
115};
116
117static struct qcom_icc_node xm_usb3_0 = {
118 .name = "xm_usb3_0",
119 .id = SM6350_MASTER_USB3,
120 .channels = 1,
121 .buswidth = 8,
122 .num_links = 1,
123 .links = { SM6350_A2NOC_SNOC_SLV },
124};
125
126static struct qcom_icc_node qxm_camnoc_hf0_uncomp = {
127 .name = "qxm_camnoc_hf0_uncomp",
128 .id = SM6350_MASTER_CAMNOC_HF0_UNCOMP,
129 .channels = 2,
130 .buswidth = 32,
131 .num_links = 1,
132 .links = { SM6350_SLAVE_CAMNOC_UNCOMP },
133};
134
135static struct qcom_icc_node qxm_camnoc_icp_uncomp = {
136 .name = "qxm_camnoc_icp_uncomp",
137 .id = SM6350_MASTER_CAMNOC_ICP_UNCOMP,
138 .channels = 1,
139 .buswidth = 32,
140 .num_links = 1,
141 .links = { SM6350_SLAVE_CAMNOC_UNCOMP },
142};
143
144static struct qcom_icc_node qxm_camnoc_sf_uncomp = {
145 .name = "qxm_camnoc_sf_uncomp",
146 .id = SM6350_MASTER_CAMNOC_SF_UNCOMP,
147 .channels = 1,
148 .buswidth = 32,
149 .num_links = 1,
150 .links = { SM6350_SLAVE_CAMNOC_UNCOMP },
151};
152
153static struct qcom_icc_node qup0_core_master = {
154 .name = "qup0_core_master",
155 .id = SM6350_MASTER_QUP_CORE_0,
156 .channels = 1,
157 .buswidth = 4,
158 .num_links = 1,
159 .links = { SM6350_SLAVE_QUP_CORE_0 },
160};
161
162static struct qcom_icc_node qup1_core_master = {
163 .name = "qup1_core_master",
164 .id = SM6350_MASTER_QUP_CORE_1,
165 .channels = 1,
166 .buswidth = 4,
167 .num_links = 1,
168 .links = { SM6350_SLAVE_QUP_CORE_1 },
169};
170
171static struct qcom_icc_node qnm_npu = {
172 .name = "qnm_npu",
173 .id = SM6350_MASTER_NPU,
174 .channels = 2,
175 .buswidth = 32,
176 .num_links = 1,
177 .links = { SM6350_SLAVE_CDSP_GEM_NOC },
178};
179
180static struct qcom_icc_node qxm_npu_dsp = {
181 .name = "qxm_npu_dsp",
182 .id = SM6350_MASTER_NPU_PROC,
183 .channels = 1,
184 .buswidth = 8,
185 .num_links = 1,
186 .links = { SM6350_SLAVE_CDSP_GEM_NOC },
187};
188
189static struct qcom_icc_node qnm_snoc = {
190 .name = "qnm_snoc",
191 .id = SM6350_SNOC_CNOC_MAS,
192 .channels = 1,
193 .buswidth = 8,
194 .num_links = 42,
195 .links = { SM6350_SLAVE_CAMERA_CFG,
196 SM6350_SLAVE_SDCC_2,
197 SM6350_SLAVE_CNOC_MNOC_CFG,
198 SM6350_SLAVE_UFS_MEM_CFG,
199 SM6350_SLAVE_QM_CFG,
200 SM6350_SLAVE_SNOC_CFG,
201 SM6350_SLAVE_QM_MPU_CFG,
202 SM6350_SLAVE_GLM,
203 SM6350_SLAVE_PDM,
204 SM6350_SLAVE_CAMERA_NRT_THROTTLE_CFG,
205 SM6350_SLAVE_A2NOC_CFG,
206 SM6350_SLAVE_QDSS_CFG,
207 SM6350_SLAVE_VSENSE_CTRL_CFG,
208 SM6350_SLAVE_CAMERA_RT_THROTTLE_CFG,
209 SM6350_SLAVE_DISPLAY_CFG,
210 SM6350_SLAVE_TCSR,
211 SM6350_SLAVE_DCC_CFG,
212 SM6350_SLAVE_CNOC_DDRSS,
213 SM6350_SLAVE_DISPLAY_THROTTLE_CFG,
214 SM6350_SLAVE_NPU_CFG,
215 SM6350_SLAVE_AHB2PHY,
216 SM6350_SLAVE_GRAPHICS_3D_CFG,
217 SM6350_SLAVE_BOOT_ROM,
218 SM6350_SLAVE_VENUS_CFG,
219 SM6350_SLAVE_IPA_CFG,
220 SM6350_SLAVE_SECURITY,
221 SM6350_SLAVE_IMEM_CFG,
222 SM6350_SLAVE_CNOC_MSS,
223 SM6350_SLAVE_SERVICE_CNOC,
224 SM6350_SLAVE_USB3,
225 SM6350_SLAVE_VENUS_THROTTLE_CFG,
226 SM6350_SLAVE_RBCPR_CX_CFG,
227 SM6350_SLAVE_A1NOC_CFG,
228 SM6350_SLAVE_AOSS,
229 SM6350_SLAVE_PRNG,
230 SM6350_SLAVE_EMMC_CFG,
231 SM6350_SLAVE_CRYPTO_0_CFG,
232 SM6350_SLAVE_PIMEM_CFG,
233 SM6350_SLAVE_RBCPR_MX_CFG,
234 SM6350_SLAVE_QUP_0,
235 SM6350_SLAVE_QUP_1,
236 SM6350_SLAVE_CLK_CTL
237 },
238};
239
240static struct qcom_icc_node xm_qdss_dap = {
241 .name = "xm_qdss_dap",
242 .id = SM6350_MASTER_QDSS_DAP,
243 .channels = 1,
244 .buswidth = 8,
245 .num_links = 42,
246 .links = { SM6350_SLAVE_CAMERA_CFG,
247 SM6350_SLAVE_SDCC_2,
248 SM6350_SLAVE_CNOC_MNOC_CFG,
249 SM6350_SLAVE_UFS_MEM_CFG,
250 SM6350_SLAVE_QM_CFG,
251 SM6350_SLAVE_SNOC_CFG,
252 SM6350_SLAVE_QM_MPU_CFG,
253 SM6350_SLAVE_GLM,
254 SM6350_SLAVE_PDM,
255 SM6350_SLAVE_CAMERA_NRT_THROTTLE_CFG,
256 SM6350_SLAVE_A2NOC_CFG,
257 SM6350_SLAVE_QDSS_CFG,
258 SM6350_SLAVE_VSENSE_CTRL_CFG,
259 SM6350_SLAVE_CAMERA_RT_THROTTLE_CFG,
260 SM6350_SLAVE_DISPLAY_CFG,
261 SM6350_SLAVE_TCSR,
262 SM6350_SLAVE_DCC_CFG,
263 SM6350_SLAVE_CNOC_DDRSS,
264 SM6350_SLAVE_DISPLAY_THROTTLE_CFG,
265 SM6350_SLAVE_NPU_CFG,
266 SM6350_SLAVE_AHB2PHY,
267 SM6350_SLAVE_GRAPHICS_3D_CFG,
268 SM6350_SLAVE_BOOT_ROM,
269 SM6350_SLAVE_VENUS_CFG,
270 SM6350_SLAVE_IPA_CFG,
271 SM6350_SLAVE_SECURITY,
272 SM6350_SLAVE_IMEM_CFG,
273 SM6350_SLAVE_CNOC_MSS,
274 SM6350_SLAVE_SERVICE_CNOC,
275 SM6350_SLAVE_USB3,
276 SM6350_SLAVE_VENUS_THROTTLE_CFG,
277 SM6350_SLAVE_RBCPR_CX_CFG,
278 SM6350_SLAVE_A1NOC_CFG,
279 SM6350_SLAVE_AOSS,
280 SM6350_SLAVE_PRNG,
281 SM6350_SLAVE_EMMC_CFG,
282 SM6350_SLAVE_CRYPTO_0_CFG,
283 SM6350_SLAVE_PIMEM_CFG,
284 SM6350_SLAVE_RBCPR_MX_CFG,
285 SM6350_SLAVE_QUP_0,
286 SM6350_SLAVE_QUP_1,
287 SM6350_SLAVE_CLK_CTL
288 },
289};
290
291static struct qcom_icc_node qhm_cnoc_dc_noc = {
292 .name = "qhm_cnoc_dc_noc",
293 .id = SM6350_MASTER_CNOC_DC_NOC,
294 .channels = 1,
295 .buswidth = 4,
296 .num_links = 2,
297 .links = { SM6350_SLAVE_LLCC_CFG,
298 SM6350_SLAVE_GEM_NOC_CFG
299 },
300};
301
302static struct qcom_icc_node acm_apps = {
303 .name = "acm_apps",
304 .id = SM6350_MASTER_AMPSS_M0,
305 .channels = 1,
306 .buswidth = 16,
307 .num_links = 2,
308 .links = { SM6350_SLAVE_LLCC,
309 SM6350_SLAVE_GEM_NOC_SNOC
310 },
311};
312
313static struct qcom_icc_node acm_sys_tcu = {
314 .name = "acm_sys_tcu",
315 .id = SM6350_MASTER_SYS_TCU,
316 .channels = 1,
317 .buswidth = 8,
318 .num_links = 2,
319 .links = { SM6350_SLAVE_LLCC,
320 SM6350_SLAVE_GEM_NOC_SNOC
321 },
322};
323
324static struct qcom_icc_node qhm_gemnoc_cfg = {
325 .name = "qhm_gemnoc_cfg",
326 .id = SM6350_MASTER_GEM_NOC_CFG,
327 .channels = 1,
328 .buswidth = 4,
329 .num_links = 3,
330 .links = { SM6350_SLAVE_MCDMA_MS_MPU_CFG,
331 SM6350_SLAVE_SERVICE_GEM_NOC,
332 SM6350_SLAVE_MSS_PROC_MS_MPU_CFG
333 },
334};
335
336static struct qcom_icc_node qnm_cmpnoc = {
337 .name = "qnm_cmpnoc",
338 .id = SM6350_MASTER_COMPUTE_NOC,
339 .channels = 1,
340 .buswidth = 32,
341 .num_links = 2,
342 .links = { SM6350_SLAVE_LLCC,
343 SM6350_SLAVE_GEM_NOC_SNOC
344 },
345};
346
347static struct qcom_icc_node qnm_mnoc_hf = {
348 .name = "qnm_mnoc_hf",
349 .id = SM6350_MASTER_MNOC_HF_MEM_NOC,
350 .channels = 1,
351 .buswidth = 32,
352 .num_links = 2,
353 .links = { SM6350_SLAVE_LLCC,
354 SM6350_SLAVE_GEM_NOC_SNOC
355 },
356};
357
358static struct qcom_icc_node qnm_mnoc_sf = {
359 .name = "qnm_mnoc_sf",
360 .id = SM6350_MASTER_MNOC_SF_MEM_NOC,
361 .channels = 1,
362 .buswidth = 32,
363 .num_links = 2,
364 .links = { SM6350_SLAVE_LLCC,
365 SM6350_SLAVE_GEM_NOC_SNOC
366 },
367};
368
369static struct qcom_icc_node qnm_snoc_gc = {
370 .name = "qnm_snoc_gc",
371 .id = SM6350_MASTER_SNOC_GC_MEM_NOC,
372 .channels = 1,
373 .buswidth = 8,
374 .num_links = 1,
375 .links = { SM6350_SLAVE_LLCC },
376};
377
378static struct qcom_icc_node qnm_snoc_sf = {
379 .name = "qnm_snoc_sf",
380 .id = SM6350_MASTER_SNOC_SF_MEM_NOC,
381 .channels = 1,
382 .buswidth = 16,
383 .num_links = 1,
384 .links = { SM6350_SLAVE_LLCC },
385};
386
387static struct qcom_icc_node qxm_gpu = {
388 .name = "qxm_gpu",
389 .id = SM6350_MASTER_GRAPHICS_3D,
390 .channels = 2,
391 .buswidth = 32,
392 .num_links = 2,
393 .links = { SM6350_SLAVE_LLCC,
394 SM6350_SLAVE_GEM_NOC_SNOC
395 },
396};
397
398static struct qcom_icc_node llcc_mc = {
399 .name = "llcc_mc",
400 .id = SM6350_MASTER_LLCC,
401 .channels = 2,
402 .buswidth = 4,
403 .num_links = 1,
404 .links = { SM6350_SLAVE_EBI_CH0 },
405};
406
407static struct qcom_icc_node qhm_mnoc_cfg = {
408 .name = "qhm_mnoc_cfg",
409 .id = SM6350_MASTER_CNOC_MNOC_CFG,
410 .channels = 1,
411 .buswidth = 4,
412 .num_links = 1,
413 .links = { SM6350_SLAVE_SERVICE_MNOC },
414};
415
416static struct qcom_icc_node qnm_video0 = {
417 .name = "qnm_video0",
418 .id = SM6350_MASTER_VIDEO_P0,
419 .channels = 1,
420 .buswidth = 32,
421 .num_links = 1,
422 .links = { SM6350_SLAVE_MNOC_SF_MEM_NOC },
423};
424
425static struct qcom_icc_node qnm_video_cvp = {
426 .name = "qnm_video_cvp",
427 .id = SM6350_MASTER_VIDEO_PROC,
428 .channels = 1,
429 .buswidth = 8,
430 .num_links = 1,
431 .links = { SM6350_SLAVE_MNOC_SF_MEM_NOC },
432};
433
434static struct qcom_icc_node qxm_camnoc_hf = {
435 .name = "qxm_camnoc_hf",
436 .id = SM6350_MASTER_CAMNOC_HF,
437 .channels = 2,
438 .buswidth = 32,
439 .num_links = 1,
440 .links = { SM6350_SLAVE_MNOC_HF_MEM_NOC },
441};
442
443static struct qcom_icc_node qxm_camnoc_icp = {
444 .name = "qxm_camnoc_icp",
445 .id = SM6350_MASTER_CAMNOC_ICP,
446 .channels = 1,
447 .buswidth = 8,
448 .num_links = 1,
449 .links = { SM6350_SLAVE_MNOC_SF_MEM_NOC },
450};
451
452static struct qcom_icc_node qxm_camnoc_sf = {
453 .name = "qxm_camnoc_sf",
454 .id = SM6350_MASTER_CAMNOC_SF,
455 .channels = 1,
456 .buswidth = 32,
457 .num_links = 1,
458 .links = { SM6350_SLAVE_MNOC_SF_MEM_NOC },
459};
460
461static struct qcom_icc_node qxm_mdp0 = {
462 .name = "qxm_mdp0",
463 .id = SM6350_MASTER_MDP_PORT0,
464 .channels = 1,
465 .buswidth = 32,
466 .num_links = 1,
467 .links = { SM6350_SLAVE_MNOC_HF_MEM_NOC },
468};
469
470static struct qcom_icc_node amm_npu_sys = {
471 .name = "amm_npu_sys",
472 .id = SM6350_MASTER_NPU_SYS,
473 .channels = 2,
474 .buswidth = 32,
475 .num_links = 1,
476 .links = { SM6350_SLAVE_NPU_COMPUTE_NOC },
477};
478
479static struct qcom_icc_node qhm_npu_cfg = {
480 .name = "qhm_npu_cfg",
481 .id = SM6350_MASTER_NPU_NOC_CFG,
482 .channels = 1,
483 .buswidth = 4,
484 .num_links = 8,
485 .links = { SM6350_SLAVE_SERVICE_NPU_NOC,
486 SM6350_SLAVE_ISENSE_CFG,
487 SM6350_SLAVE_NPU_LLM_CFG,
488 SM6350_SLAVE_NPU_INT_DMA_BWMON_CFG,
489 SM6350_SLAVE_NPU_CP,
490 SM6350_SLAVE_NPU_TCM,
491 SM6350_SLAVE_NPU_CAL_DP0,
492 SM6350_SLAVE_NPU_DPM
493 },
494};
495
496static struct qcom_icc_node qhm_snoc_cfg = {
497 .name = "qhm_snoc_cfg",
498 .id = SM6350_MASTER_SNOC_CFG,
499 .channels = 1,
500 .buswidth = 4,
501 .num_links = 1,
502 .links = { SM6350_SLAVE_SERVICE_SNOC },
503};
504
505static struct qcom_icc_node qnm_aggre1_noc = {
506 .name = "qnm_aggre1_noc",
507 .id = SM6350_A1NOC_SNOC_MAS,
508 .channels = 1,
509 .buswidth = 16,
510 .num_links = 6,
511 .links = { SM6350_SLAVE_SNOC_GEM_NOC_SF,
512 SM6350_SLAVE_PIMEM,
513 SM6350_SLAVE_OCIMEM,
514 SM6350_SLAVE_APPSS,
515 SM6350_SNOC_CNOC_SLV,
516 SM6350_SLAVE_QDSS_STM
517 },
518};
519
520static struct qcom_icc_node qnm_aggre2_noc = {
521 .name = "qnm_aggre2_noc",
522 .id = SM6350_A2NOC_SNOC_MAS,
523 .channels = 1,
524 .buswidth = 16,
525 .num_links = 7,
526 .links = { SM6350_SLAVE_SNOC_GEM_NOC_SF,
527 SM6350_SLAVE_PIMEM,
528 SM6350_SLAVE_OCIMEM,
529 SM6350_SLAVE_APPSS,
530 SM6350_SNOC_CNOC_SLV,
531 SM6350_SLAVE_TCU,
532 SM6350_SLAVE_QDSS_STM
533 },
534};
535
536static struct qcom_icc_node qnm_gemnoc = {
537 .name = "qnm_gemnoc",
538 .id = SM6350_MASTER_GEM_NOC_SNOC,
539 .channels = 1,
540 .buswidth = 8,
541 .num_links = 6,
542 .links = { SM6350_SLAVE_PIMEM,
543 SM6350_SLAVE_OCIMEM,
544 SM6350_SLAVE_APPSS,
545 SM6350_SNOC_CNOC_SLV,
546 SM6350_SLAVE_TCU,
547 SM6350_SLAVE_QDSS_STM
548 },
549};
550
551static struct qcom_icc_node qxm_pimem = {
552 .name = "qxm_pimem",
553 .id = SM6350_MASTER_PIMEM,
554 .channels = 1,
555 .buswidth = 8,
556 .num_links = 2,
557 .links = { SM6350_SLAVE_SNOC_GEM_NOC_GC,
558 SM6350_SLAVE_OCIMEM
559 },
560};
561
562static struct qcom_icc_node xm_gic = {
563 .name = "xm_gic",
564 .id = SM6350_MASTER_GIC,
565 .channels = 1,
566 .buswidth = 8,
567 .num_links = 1,
568 .links = { SM6350_SLAVE_SNOC_GEM_NOC_GC },
569};
570
571static struct qcom_icc_node qns_a1noc_snoc = {
572 .name = "qns_a1noc_snoc",
573 .id = SM6350_A1NOC_SNOC_SLV,
574 .channels = 1,
575 .buswidth = 16,
576 .num_links = 1,
577 .links = { SM6350_A1NOC_SNOC_MAS },
578};
579
580static struct qcom_icc_node srvc_aggre1_noc = {
581 .name = "srvc_aggre1_noc",
582 .id = SM6350_SLAVE_SERVICE_A1NOC,
583 .channels = 1,
584 .buswidth = 4,
585};
586
587static struct qcom_icc_node qns_a2noc_snoc = {
588 .name = "qns_a2noc_snoc",
589 .id = SM6350_A2NOC_SNOC_SLV,
590 .channels = 1,
591 .buswidth = 16,
592 .num_links = 1,
593 .links = { SM6350_A2NOC_SNOC_MAS },
594};
595
596static struct qcom_icc_node srvc_aggre2_noc = {
597 .name = "srvc_aggre2_noc",
598 .id = SM6350_SLAVE_SERVICE_A2NOC,
599 .channels = 1,
600 .buswidth = 4,
601};
602
603static struct qcom_icc_node qns_camnoc_uncomp = {
604 .name = "qns_camnoc_uncomp",
605 .id = SM6350_SLAVE_CAMNOC_UNCOMP,
606 .channels = 1,
607 .buswidth = 32,
608};
609
610static struct qcom_icc_node qup0_core_slave = {
611 .name = "qup0_core_slave",
612 .id = SM6350_SLAVE_QUP_CORE_0,
613 .channels = 1,
614 .buswidth = 4,
615};
616
617static struct qcom_icc_node qup1_core_slave = {
618 .name = "qup1_core_slave",
619 .id = SM6350_SLAVE_QUP_CORE_1,
620 .channels = 1,
621 .buswidth = 4,
622};
623
624static struct qcom_icc_node qns_cdsp_gemnoc = {
625 .name = "qns_cdsp_gemnoc",
626 .id = SM6350_SLAVE_CDSP_GEM_NOC,
627 .channels = 1,
628 .buswidth = 32,
629 .num_links = 1,
630 .links = { SM6350_MASTER_COMPUTE_NOC },
631};
632
633static struct qcom_icc_node qhs_a1_noc_cfg = {
634 .name = "qhs_a1_noc_cfg",
635 .id = SM6350_SLAVE_A1NOC_CFG,
636 .channels = 1,
637 .buswidth = 4,
638 .num_links = 1,
639 .links = { SM6350_MASTER_A1NOC_CFG },
640};
641
642static struct qcom_icc_node qhs_a2_noc_cfg = {
643 .name = "qhs_a2_noc_cfg",
644 .id = SM6350_SLAVE_A2NOC_CFG,
645 .channels = 1,
646 .buswidth = 4,
647 .num_links = 1,
648 .links = { SM6350_MASTER_A2NOC_CFG },
649};
650
651static struct qcom_icc_node qhs_ahb2phy0 = {
652 .name = "qhs_ahb2phy0",
653 .id = SM6350_SLAVE_AHB2PHY,
654 .channels = 1,
655 .buswidth = 4,
656};
657
658static struct qcom_icc_node qhs_ahb2phy2 = {
659 .name = "qhs_ahb2phy2",
660 .id = SM6350_SLAVE_AHB2PHY_2,
661 .channels = 1,
662 .buswidth = 4,
663};
664
665static struct qcom_icc_node qhs_aoss = {
666 .name = "qhs_aoss",
667 .id = SM6350_SLAVE_AOSS,
668 .channels = 1,
669 .buswidth = 4,
670};
671
672static struct qcom_icc_node qhs_boot_rom = {
673 .name = "qhs_boot_rom",
674 .id = SM6350_SLAVE_BOOT_ROM,
675 .channels = 1,
676 .buswidth = 4,
677};
678
679static struct qcom_icc_node qhs_camera_cfg = {
680 .name = "qhs_camera_cfg",
681 .id = SM6350_SLAVE_CAMERA_CFG,
682 .channels = 1,
683 .buswidth = 4,
684};
685
686static struct qcom_icc_node qhs_camera_nrt_thrott_cfg = {
687 .name = "qhs_camera_nrt_thrott_cfg",
688 .id = SM6350_SLAVE_CAMERA_NRT_THROTTLE_CFG,
689 .channels = 1,
690 .buswidth = 4,
691};
692
693static struct qcom_icc_node qhs_camera_rt_throttle_cfg = {
694 .name = "qhs_camera_rt_throttle_cfg",
695 .id = SM6350_SLAVE_CAMERA_RT_THROTTLE_CFG,
696 .channels = 1,
697 .buswidth = 4,
698};
699
700static struct qcom_icc_node qhs_clk_ctl = {
701 .name = "qhs_clk_ctl",
702 .id = SM6350_SLAVE_CLK_CTL,
703 .channels = 1,
704 .buswidth = 4,
705};
706
707static struct qcom_icc_node qhs_cpr_cx = {
708 .name = "qhs_cpr_cx",
709 .id = SM6350_SLAVE_RBCPR_CX_CFG,
710 .channels = 1,
711 .buswidth = 4,
712};
713
714static struct qcom_icc_node qhs_cpr_mx = {
715 .name = "qhs_cpr_mx",
716 .id = SM6350_SLAVE_RBCPR_MX_CFG,
717 .channels = 1,
718 .buswidth = 4,
719};
720
721static struct qcom_icc_node qhs_crypto0_cfg = {
722 .name = "qhs_crypto0_cfg",
723 .id = SM6350_SLAVE_CRYPTO_0_CFG,
724 .channels = 1,
725 .buswidth = 4,
726};
727
728static struct qcom_icc_node qhs_dcc_cfg = {
729 .name = "qhs_dcc_cfg",
730 .id = SM6350_SLAVE_DCC_CFG,
731 .channels = 1,
732 .buswidth = 4,
733};
734
735static struct qcom_icc_node qhs_ddrss_cfg = {
736 .name = "qhs_ddrss_cfg",
737 .id = SM6350_SLAVE_CNOC_DDRSS,
738 .channels = 1,
739 .buswidth = 4,
740 .num_links = 1,
741 .links = { SM6350_MASTER_CNOC_DC_NOC },
742};
743
744static struct qcom_icc_node qhs_display_cfg = {
745 .name = "qhs_display_cfg",
746 .id = SM6350_SLAVE_DISPLAY_CFG,
747 .channels = 1,
748 .buswidth = 4,
749};
750
751static struct qcom_icc_node qhs_display_throttle_cfg = {
752 .name = "qhs_display_throttle_cfg",
753 .id = SM6350_SLAVE_DISPLAY_THROTTLE_CFG,
754 .channels = 1,
755 .buswidth = 4,
756};
757
758static struct qcom_icc_node qhs_emmc_cfg = {
759 .name = "qhs_emmc_cfg",
760 .id = SM6350_SLAVE_EMMC_CFG,
761 .channels = 1,
762 .buswidth = 4,
763};
764
765static struct qcom_icc_node qhs_glm = {
766 .name = "qhs_glm",
767 .id = SM6350_SLAVE_GLM,
768 .channels = 1,
769 .buswidth = 4,
770};
771
772static struct qcom_icc_node qhs_gpuss_cfg = {
773 .name = "qhs_gpuss_cfg",
774 .id = SM6350_SLAVE_GRAPHICS_3D_CFG,
775 .channels = 1,
776 .buswidth = 8,
777};
778
779static struct qcom_icc_node qhs_imem_cfg = {
780 .name = "qhs_imem_cfg",
781 .id = SM6350_SLAVE_IMEM_CFG,
782 .channels = 1,
783 .buswidth = 4,
784};
785
786static struct qcom_icc_node qhs_ipa = {
787 .name = "qhs_ipa",
788 .id = SM6350_SLAVE_IPA_CFG,
789 .channels = 1,
790 .buswidth = 4,
791};
792
793static struct qcom_icc_node qhs_mnoc_cfg = {
794 .name = "qhs_mnoc_cfg",
795 .id = SM6350_SLAVE_CNOC_MNOC_CFG,
796 .channels = 1,
797 .buswidth = 4,
798 .num_links = 1,
799 .links = { SM6350_MASTER_CNOC_MNOC_CFG },
800};
801
802static struct qcom_icc_node qhs_mss_cfg = {
803 .name = "qhs_mss_cfg",
804 .id = SM6350_SLAVE_CNOC_MSS,
805 .channels = 1,
806 .buswidth = 4,
807};
808
809static struct qcom_icc_node qhs_npu_cfg = {
810 .name = "qhs_npu_cfg",
811 .id = SM6350_SLAVE_NPU_CFG,
812 .channels = 1,
813 .buswidth = 4,
814 .num_links = 1,
815 .links = { SM6350_MASTER_NPU_NOC_CFG },
816};
817
818static struct qcom_icc_node qhs_pdm = {
819 .name = "qhs_pdm",
820 .id = SM6350_SLAVE_PDM,
821 .channels = 1,
822 .buswidth = 4,
823};
824
825static struct qcom_icc_node qhs_pimem_cfg = {
826 .name = "qhs_pimem_cfg",
827 .id = SM6350_SLAVE_PIMEM_CFG,
828 .channels = 1,
829 .buswidth = 4,
830};
831
832static struct qcom_icc_node qhs_prng = {
833 .name = "qhs_prng",
834 .id = SM6350_SLAVE_PRNG,
835 .channels = 1,
836 .buswidth = 4,
837};
838
839static struct qcom_icc_node qhs_qdss_cfg = {
840 .name = "qhs_qdss_cfg",
841 .id = SM6350_SLAVE_QDSS_CFG,
842 .channels = 1,
843 .buswidth = 4,
844};
845
846static struct qcom_icc_node qhs_qm_cfg = {
847 .name = "qhs_qm_cfg",
848 .id = SM6350_SLAVE_QM_CFG,
849 .channels = 1,
850 .buswidth = 4,
851};
852
853static struct qcom_icc_node qhs_qm_mpu_cfg = {
854 .name = "qhs_qm_mpu_cfg",
855 .id = SM6350_SLAVE_QM_MPU_CFG,
856 .channels = 1,
857 .buswidth = 4,
858};
859
860static struct qcom_icc_node qhs_qup0 = {
861 .name = "qhs_qup0",
862 .id = SM6350_SLAVE_QUP_0,
863 .channels = 1,
864 .buswidth = 4,
865};
866
867static struct qcom_icc_node qhs_qup1 = {
868 .name = "qhs_qup1",
869 .id = SM6350_SLAVE_QUP_1,
870 .channels = 1,
871 .buswidth = 4,
872};
873
874static struct qcom_icc_node qhs_sdc2 = {
875 .name = "qhs_sdc2",
876 .id = SM6350_SLAVE_SDCC_2,
877 .channels = 1,
878 .buswidth = 4,
879};
880
881static struct qcom_icc_node qhs_security = {
882 .name = "qhs_security",
883 .id = SM6350_SLAVE_SECURITY,
884 .channels = 1,
885 .buswidth = 4,
886};
887
888static struct qcom_icc_node qhs_snoc_cfg = {
889 .name = "qhs_snoc_cfg",
890 .id = SM6350_SLAVE_SNOC_CFG,
891 .channels = 1,
892 .buswidth = 4,
893 .num_links = 1,
894 .links = { SM6350_MASTER_SNOC_CFG },
895};
896
897static struct qcom_icc_node qhs_tcsr = {
898 .name = "qhs_tcsr",
899 .id = SM6350_SLAVE_TCSR,
900 .channels = 1,
901 .buswidth = 4,
902};
903
904static struct qcom_icc_node qhs_ufs_mem_cfg = {
905 .name = "qhs_ufs_mem_cfg",
906 .id = SM6350_SLAVE_UFS_MEM_CFG,
907 .channels = 1,
908 .buswidth = 4,
909};
910
911static struct qcom_icc_node qhs_usb3_0 = {
912 .name = "qhs_usb3_0",
913 .id = SM6350_SLAVE_USB3,
914 .channels = 1,
915 .buswidth = 4,
916};
917
918static struct qcom_icc_node qhs_venus_cfg = {
919 .name = "qhs_venus_cfg",
920 .id = SM6350_SLAVE_VENUS_CFG,
921 .channels = 1,
922 .buswidth = 4,
923};
924
925static struct qcom_icc_node qhs_venus_throttle_cfg = {
926 .name = "qhs_venus_throttle_cfg",
927 .id = SM6350_SLAVE_VENUS_THROTTLE_CFG,
928 .channels = 1,
929 .buswidth = 4,
930};
931
932static struct qcom_icc_node qhs_vsense_ctrl_cfg = {
933 .name = "qhs_vsense_ctrl_cfg",
934 .id = SM6350_SLAVE_VSENSE_CTRL_CFG,
935 .channels = 1,
936 .buswidth = 4,
937};
938
939static struct qcom_icc_node srvc_cnoc = {
940 .name = "srvc_cnoc",
941 .id = SM6350_SLAVE_SERVICE_CNOC,
942 .channels = 1,
943 .buswidth = 4,
944};
945
946static struct qcom_icc_node qhs_gemnoc = {
947 .name = "qhs_gemnoc",
948 .id = SM6350_SLAVE_GEM_NOC_CFG,
949 .channels = 1,
950 .buswidth = 4,
951 .num_links = 1,
952 .links = { SM6350_MASTER_GEM_NOC_CFG },
953};
954
955static struct qcom_icc_node qhs_llcc = {
956 .name = "qhs_llcc",
957 .id = SM6350_SLAVE_LLCC_CFG,
958 .channels = 1,
959 .buswidth = 4,
960};
961
962static struct qcom_icc_node qhs_mcdma_ms_mpu_cfg = {
963 .name = "qhs_mcdma_ms_mpu_cfg",
964 .id = SM6350_SLAVE_MCDMA_MS_MPU_CFG,
965 .channels = 1,
966 .buswidth = 4,
967};
968
969static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = {
970 .name = "qhs_mdsp_ms_mpu_cfg",
971 .id = SM6350_SLAVE_MSS_PROC_MS_MPU_CFG,
972 .channels = 1,
973 .buswidth = 4,
974};
975
976static struct qcom_icc_node qns_gem_noc_snoc = {
977 .name = "qns_gem_noc_snoc",
978 .id = SM6350_SLAVE_GEM_NOC_SNOC,
979 .channels = 1,
980 .buswidth = 8,
981 .num_links = 1,
982 .links = { SM6350_MASTER_GEM_NOC_SNOC },
983};
984
985static struct qcom_icc_node qns_llcc = {
986 .name = "qns_llcc",
987 .id = SM6350_SLAVE_LLCC,
988 .channels = 1,
989 .buswidth = 16,
990 .num_links = 1,
991 .links = { SM6350_MASTER_LLCC },
992};
993
994static struct qcom_icc_node srvc_gemnoc = {
995 .name = "srvc_gemnoc",
996 .id = SM6350_SLAVE_SERVICE_GEM_NOC,
997 .channels = 1,
998 .buswidth = 4,
999};
1000
1001static struct qcom_icc_node ebi = {
1002 .name = "ebi",
1003 .id = SM6350_SLAVE_EBI_CH0,
1004 .channels = 2,
1005 .buswidth = 4,
1006};
1007
1008static struct qcom_icc_node qns_mem_noc_hf = {
1009 .name = "qns_mem_noc_hf",
1010 .id = SM6350_SLAVE_MNOC_HF_MEM_NOC,
1011 .channels = 1,
1012 .buswidth = 32,
1013 .num_links = 1,
1014 .links = { SM6350_MASTER_MNOC_HF_MEM_NOC },
1015};
1016
1017static struct qcom_icc_node qns_mem_noc_sf = {
1018 .name = "qns_mem_noc_sf",
1019 .id = SM6350_SLAVE_MNOC_SF_MEM_NOC,
1020 .channels = 1,
1021 .buswidth = 32,
1022 .num_links = 1,
1023 .links = { SM6350_MASTER_MNOC_SF_MEM_NOC },
1024};
1025
1026static struct qcom_icc_node srvc_mnoc = {
1027 .name = "srvc_mnoc",
1028 .id = SM6350_SLAVE_SERVICE_MNOC,
1029 .channels = 1,
1030 .buswidth = 4,
1031};
1032
1033static struct qcom_icc_node qhs_cal_dp0 = {
1034 .name = "qhs_cal_dp0",
1035 .id = SM6350_SLAVE_NPU_CAL_DP0,
1036 .channels = 1,
1037 .buswidth = 4,
1038};
1039
1040static struct qcom_icc_node qhs_cp = {
1041 .name = "qhs_cp",
1042 .id = SM6350_SLAVE_NPU_CP,
1043 .channels = 1,
1044 .buswidth = 4,
1045};
1046
1047static struct qcom_icc_node qhs_dma_bwmon = {
1048 .name = "qhs_dma_bwmon",
1049 .id = SM6350_SLAVE_NPU_INT_DMA_BWMON_CFG,
1050 .channels = 1,
1051 .buswidth = 4,
1052};
1053
1054static struct qcom_icc_node qhs_dpm = {
1055 .name = "qhs_dpm",
1056 .id = SM6350_SLAVE_NPU_DPM,
1057 .channels = 1,
1058 .buswidth = 4,
1059};
1060
1061static struct qcom_icc_node qhs_isense = {
1062 .name = "qhs_isense",
1063 .id = SM6350_SLAVE_ISENSE_CFG,
1064 .channels = 1,
1065 .buswidth = 4,
1066};
1067
1068static struct qcom_icc_node qhs_llm = {
1069 .name = "qhs_llm",
1070 .id = SM6350_SLAVE_NPU_LLM_CFG,
1071 .channels = 1,
1072 .buswidth = 4,
1073};
1074
1075static struct qcom_icc_node qhs_tcm = {
1076 .name = "qhs_tcm",
1077 .id = SM6350_SLAVE_NPU_TCM,
1078 .channels = 1,
1079 .buswidth = 4,
1080};
1081
1082static struct qcom_icc_node qns_npu_sys = {
1083 .name = "qns_npu_sys",
1084 .id = SM6350_SLAVE_NPU_COMPUTE_NOC,
1085 .channels = 2,
1086 .buswidth = 32,
1087};
1088
1089static struct qcom_icc_node srvc_noc = {
1090 .name = "srvc_noc",
1091 .id = SM6350_SLAVE_SERVICE_NPU_NOC,
1092 .channels = 1,
1093 .buswidth = 4,
1094};
1095
1096static struct qcom_icc_node qhs_apss = {
1097 .name = "qhs_apss",
1098 .id = SM6350_SLAVE_APPSS,
1099 .channels = 1,
1100 .buswidth = 8,
1101};
1102
1103static struct qcom_icc_node qns_cnoc = {
1104 .name = "qns_cnoc",
1105 .id = SM6350_SNOC_CNOC_SLV,
1106 .channels = 1,
1107 .buswidth = 8,
1108 .num_links = 1,
1109 .links = { SM6350_SNOC_CNOC_MAS },
1110};
1111
1112static struct qcom_icc_node qns_gemnoc_gc = {
1113 .name = "qns_gemnoc_gc",
1114 .id = SM6350_SLAVE_SNOC_GEM_NOC_GC,
1115 .channels = 1,
1116 .buswidth = 8,
1117 .num_links = 1,
1118 .links = { SM6350_MASTER_SNOC_GC_MEM_NOC },
1119};
1120
1121static struct qcom_icc_node qns_gemnoc_sf = {
1122 .name = "qns_gemnoc_sf",
1123 .id = SM6350_SLAVE_SNOC_GEM_NOC_SF,
1124 .channels = 1,
1125 .buswidth = 16,
1126 .num_links = 1,
1127 .links = { SM6350_MASTER_SNOC_SF_MEM_NOC },
1128};
1129
1130static struct qcom_icc_node qxs_imem = {
1131 .name = "qxs_imem",
1132 .id = SM6350_SLAVE_OCIMEM,
1133 .channels = 1,
1134 .buswidth = 8,
1135};
1136
1137static struct qcom_icc_node qxs_pimem = {
1138 .name = "qxs_pimem",
1139 .id = SM6350_SLAVE_PIMEM,
1140 .channels = 1,
1141 .buswidth = 8,
1142};
1143
1144static struct qcom_icc_node srvc_snoc = {
1145 .name = "srvc_snoc",
1146 .id = SM6350_SLAVE_SERVICE_SNOC,
1147 .channels = 1,
1148 .buswidth = 4,
1149};
1150
1151static struct qcom_icc_node xs_qdss_stm = {
1152 .name = "xs_qdss_stm",
1153 .id = SM6350_SLAVE_QDSS_STM,
1154 .channels = 1,
1155 .buswidth = 4,
1156};
1157
1158static struct qcom_icc_node xs_sys_tcu_cfg = {
1159 .name = "xs_sys_tcu_cfg",
1160 .id = SM6350_SLAVE_TCU,
1161 .channels = 1,
1162 .buswidth = 8,
1163};
1164
1165static struct qcom_icc_bcm bcm_acv = {
1166 .name = "ACV",
1167 .enable_mask = BIT(3),
1168 .keepalive = false,
1169 .num_nodes = 1,
1170 .nodes = { &ebi },
1171};
1172
1173static struct qcom_icc_bcm bcm_ce0 = {
1174 .name = "CE0",
1175 .keepalive = false,
1176 .num_nodes = 1,
1177 .nodes = { &qxm_crypto },
1178};
1179
1180static struct qcom_icc_bcm bcm_cn0 = {
1181 .name = "CN0",
1182 .keepalive = true,
1183 .num_nodes = 41,
1184 .nodes = { &qnm_snoc,
1185 &xm_qdss_dap,
1186 &qhs_a1_noc_cfg,
1187 &qhs_a2_noc_cfg,
1188 &qhs_ahb2phy0,
1189 &qhs_aoss,
1190 &qhs_boot_rom,
1191 &qhs_camera_cfg,
1192 &qhs_camera_nrt_thrott_cfg,
1193 &qhs_camera_rt_throttle_cfg,
1194 &qhs_clk_ctl,
1195 &qhs_cpr_cx,
1196 &qhs_cpr_mx,
1197 &qhs_crypto0_cfg,
1198 &qhs_dcc_cfg,
1199 &qhs_ddrss_cfg,
1200 &qhs_display_cfg,
1201 &qhs_display_throttle_cfg,
1202 &qhs_glm,
1203 &qhs_gpuss_cfg,
1204 &qhs_imem_cfg,
1205 &qhs_ipa,
1206 &qhs_mnoc_cfg,
1207 &qhs_mss_cfg,
1208 &qhs_npu_cfg,
1209 &qhs_pimem_cfg,
1210 &qhs_prng,
1211 &qhs_qdss_cfg,
1212 &qhs_qm_cfg,
1213 &qhs_qm_mpu_cfg,
1214 &qhs_qup0,
1215 &qhs_qup1,
1216 &qhs_security,
1217 &qhs_snoc_cfg,
1218 &qhs_tcsr,
1219 &qhs_ufs_mem_cfg,
1220 &qhs_usb3_0,
1221 &qhs_venus_cfg,
1222 &qhs_venus_throttle_cfg,
1223 &qhs_vsense_ctrl_cfg,
1224 &srvc_cnoc
1225 },
1226};
1227
1228static struct qcom_icc_bcm bcm_cn1 = {
1229 .name = "CN1",
1230 .keepalive = false,
1231 .num_nodes = 6,
1232 .nodes = { &xm_emmc,
1233 &xm_sdc2,
1234 &qhs_ahb2phy2,
1235 &qhs_emmc_cfg,
1236 &qhs_pdm,
1237 &qhs_sdc2
1238 },
1239};
1240
1241static struct qcom_icc_bcm bcm_co0 = {
1242 .name = "CO0",
1243 .keepalive = false,
1244 .num_nodes = 1,
1245 .nodes = { &qns_cdsp_gemnoc },
1246};
1247
1248static struct qcom_icc_bcm bcm_co2 = {
1249 .name = "CO2",
1250 .keepalive = false,
1251 .num_nodes = 1,
1252 .nodes = { &qnm_npu },
1253};
1254
1255static struct qcom_icc_bcm bcm_co3 = {
1256 .name = "CO3",
1257 .keepalive = false,
1258 .num_nodes = 1,
1259 .nodes = { &qxm_npu_dsp },
1260};
1261
1262static struct qcom_icc_bcm bcm_mc0 = {
1263 .name = "MC0",
1264 .keepalive = true,
1265 .num_nodes = 1,
1266 .nodes = { &ebi },
1267};
1268
1269static struct qcom_icc_bcm bcm_mm0 = {
1270 .name = "MM0",
1271 .keepalive = true,
1272 .num_nodes = 1,
1273 .nodes = { &qns_mem_noc_hf },
1274};
1275
1276static struct qcom_icc_bcm bcm_mm1 = {
1277 .name = "MM1",
1278 .keepalive = true,
1279 .num_nodes = 5,
1280 .nodes = { &qxm_camnoc_hf0_uncomp,
1281 &qxm_camnoc_icp_uncomp,
1282 &qxm_camnoc_sf_uncomp,
1283 &qxm_camnoc_hf,
1284 &qxm_mdp0
1285 },
1286};
1287
1288static struct qcom_icc_bcm bcm_mm2 = {
1289 .name = "MM2",
1290 .keepalive = false,
1291 .num_nodes = 1,
1292 .nodes = { &qns_mem_noc_sf },
1293};
1294
1295static struct qcom_icc_bcm bcm_mm3 = {
1296 .name = "MM3",
1297 .keepalive = false,
1298 .num_nodes = 4,
1299 .nodes = { &qhm_mnoc_cfg, &qnm_video0, &qnm_video_cvp, &qxm_camnoc_sf },
1300};
1301
1302static struct qcom_icc_bcm bcm_qup0 = {
1303 .name = "QUP0",
1304 .keepalive = false,
1305 .num_nodes = 4,
1306 .nodes = { &qup0_core_master, &qup1_core_master, &qup0_core_slave, &qup1_core_slave },
1307};
1308
1309static struct qcom_icc_bcm bcm_sh0 = {
1310 .name = "SH0",
1311 .keepalive = true,
1312 .num_nodes = 1,
1313 .nodes = { &qns_llcc },
1314};
1315
1316static struct qcom_icc_bcm bcm_sh2 = {
1317 .name = "SH2",
1318 .keepalive = false,
1319 .num_nodes = 1,
1320 .nodes = { &acm_sys_tcu },
1321};
1322
1323static struct qcom_icc_bcm bcm_sh3 = {
1324 .name = "SH3",
1325 .keepalive = false,
1326 .num_nodes = 1,
1327 .nodes = { &qnm_cmpnoc },
1328};
1329
1330static struct qcom_icc_bcm bcm_sh4 = {
1331 .name = "SH4",
1332 .keepalive = false,
1333 .num_nodes = 1,
1334 .nodes = { &acm_apps },
1335};
1336
1337static struct qcom_icc_bcm bcm_sn0 = {
1338 .name = "SN0",
1339 .keepalive = true,
1340 .num_nodes = 1,
1341 .nodes = { &qns_gemnoc_sf },
1342};
1343
1344static struct qcom_icc_bcm bcm_sn1 = {
1345 .name = "SN1",
1346 .keepalive = false,
1347 .num_nodes = 1,
1348 .nodes = { &qxs_imem },
1349};
1350
1351static struct qcom_icc_bcm bcm_sn2 = {
1352 .name = "SN2",
1353 .keepalive = false,
1354 .num_nodes = 1,
1355 .nodes = { &qns_gemnoc_gc },
1356};
1357
1358static struct qcom_icc_bcm bcm_sn3 = {
1359 .name = "SN3",
1360 .keepalive = false,
1361 .num_nodes = 1,
1362 .nodes = { &qxs_pimem },
1363};
1364
1365static struct qcom_icc_bcm bcm_sn4 = {
1366 .name = "SN4",
1367 .keepalive = false,
1368 .num_nodes = 1,
1369 .nodes = { &xs_qdss_stm },
1370};
1371
1372static struct qcom_icc_bcm bcm_sn5 = {
1373 .name = "SN5",
1374 .keepalive = false,
1375 .num_nodes = 1,
1376 .nodes = { &qnm_aggre1_noc },
1377};
1378
1379static struct qcom_icc_bcm bcm_sn6 = {
1380 .name = "SN6",
1381 .keepalive = false,
1382 .num_nodes = 1,
1383 .nodes = { &qnm_aggre2_noc },
1384};
1385
1386static struct qcom_icc_bcm bcm_sn10 = {
1387 .name = "SN10",
1388 .keepalive = false,
1389 .num_nodes = 1,
1390 .nodes = { &qnm_gemnoc },
1391};
1392
1393static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
1394 &bcm_cn1,
1395};
1396
1397static struct qcom_icc_node * const aggre1_noc_nodes[] = {
1398 [MASTER_A1NOC_CFG] = &qhm_a1noc_cfg,
1399 [MASTER_QUP_0] = &qhm_qup_0,
1400 [MASTER_EMMC] = &xm_emmc,
1401 [MASTER_UFS_MEM] = &xm_ufs_mem,
1402 [A1NOC_SNOC_SLV] = &qns_a1noc_snoc,
1403 [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc,
1404};
1405
1406static const struct qcom_icc_desc sm6350_aggre1_noc = {
1407 .nodes = aggre1_noc_nodes,
1408 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
1409 .bcms = aggre1_noc_bcms,
1410 .num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
1411};
1412
1413static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {
1414 &bcm_ce0,
1415 &bcm_cn1,
1416};
1417
1418static struct qcom_icc_node * const aggre2_noc_nodes[] = {
1419 [MASTER_A2NOC_CFG] = &qhm_a2noc_cfg,
1420 [MASTER_QDSS_BAM] = &qhm_qdss_bam,
1421 [MASTER_QUP_1] = &qhm_qup_1,
1422 [MASTER_CRYPTO_CORE_0] = &qxm_crypto,
1423 [MASTER_IPA] = &qxm_ipa,
1424 [MASTER_QDSS_ETR] = &xm_qdss_etr,
1425 [MASTER_SDCC_2] = &xm_sdc2,
1426 [MASTER_USB3] = &xm_usb3_0,
1427 [A2NOC_SNOC_SLV] = &qns_a2noc_snoc,
1428 [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc,
1429};
1430
1431static const struct qcom_icc_desc sm6350_aggre2_noc = {
1432 .nodes = aggre2_noc_nodes,
1433 .num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
1434 .bcms = aggre2_noc_bcms,
1435 .num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
1436};
1437
1438static struct qcom_icc_bcm * const clk_virt_bcms[] = {
1439 &bcm_acv,
1440 &bcm_mc0,
1441 &bcm_mm1,
1442 &bcm_qup0,
1443};
1444
1445static struct qcom_icc_node * const clk_virt_nodes[] = {
1446 [MASTER_CAMNOC_HF0_UNCOMP] = &qxm_camnoc_hf0_uncomp,
1447 [MASTER_CAMNOC_ICP_UNCOMP] = &qxm_camnoc_icp_uncomp,
1448 [MASTER_CAMNOC_SF_UNCOMP] = &qxm_camnoc_sf_uncomp,
1449 [MASTER_QUP_CORE_0] = &qup0_core_master,
1450 [MASTER_QUP_CORE_1] = &qup1_core_master,
1451 [MASTER_LLCC] = &llcc_mc,
1452 [SLAVE_CAMNOC_UNCOMP] = &qns_camnoc_uncomp,
1453 [SLAVE_QUP_CORE_0] = &qup0_core_slave,
1454 [SLAVE_QUP_CORE_1] = &qup1_core_slave,
1455 [SLAVE_EBI_CH0] = &ebi,
1456};
1457
1458static const struct qcom_icc_desc sm6350_clk_virt = {
1459 .nodes = clk_virt_nodes,
1460 .num_nodes = ARRAY_SIZE(clk_virt_nodes),
1461 .bcms = clk_virt_bcms,
1462 .num_bcms = ARRAY_SIZE(clk_virt_bcms),
1463};
1464
1465static struct qcom_icc_bcm * const compute_noc_bcms[] = {
1466 &bcm_co0,
1467 &bcm_co2,
1468 &bcm_co3,
1469};
1470
1471static struct qcom_icc_node * const compute_noc_nodes[] = {
1472 [MASTER_NPU] = &qnm_npu,
1473 [MASTER_NPU_PROC] = &qxm_npu_dsp,
1474 [SLAVE_CDSP_GEM_NOC] = &qns_cdsp_gemnoc,
1475};
1476
1477static const struct qcom_icc_desc sm6350_compute_noc = {
1478 .nodes = compute_noc_nodes,
1479 .num_nodes = ARRAY_SIZE(compute_noc_nodes),
1480 .bcms = compute_noc_bcms,
1481 .num_bcms = ARRAY_SIZE(compute_noc_bcms),
1482};
1483
1484static struct qcom_icc_bcm * const config_noc_bcms[] = {
1485 &bcm_cn0,
1486 &bcm_cn1,
1487};
1488
1489static struct qcom_icc_node * const config_noc_nodes[] = {
1490 [SNOC_CNOC_MAS] = &qnm_snoc,
1491 [MASTER_QDSS_DAP] = &xm_qdss_dap,
1492 [SLAVE_A1NOC_CFG] = &qhs_a1_noc_cfg,
1493 [SLAVE_A2NOC_CFG] = &qhs_a2_noc_cfg,
1494 [SLAVE_AHB2PHY] = &qhs_ahb2phy0,
1495 [SLAVE_AHB2PHY_2] = &qhs_ahb2phy2,
1496 [SLAVE_AOSS] = &qhs_aoss,
1497 [SLAVE_BOOT_ROM] = &qhs_boot_rom,
1498 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
1499 [SLAVE_CAMERA_NRT_THROTTLE_CFG] = &qhs_camera_nrt_thrott_cfg,
1500 [SLAVE_CAMERA_RT_THROTTLE_CFG] = &qhs_camera_rt_throttle_cfg,
1501 [SLAVE_CLK_CTL] = &qhs_clk_ctl,
1502 [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
1503 [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx,
1504 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
1505 [SLAVE_DCC_CFG] = &qhs_dcc_cfg,
1506 [SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg,
1507 [SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
1508 [SLAVE_DISPLAY_THROTTLE_CFG] = &qhs_display_throttle_cfg,
1509 [SLAVE_EMMC_CFG] = &qhs_emmc_cfg,
1510 [SLAVE_GLM] = &qhs_glm,
1511 [SLAVE_GRAPHICS_3D_CFG] = &qhs_gpuss_cfg,
1512 [SLAVE_IMEM_CFG] = &qhs_imem_cfg,
1513 [SLAVE_IPA_CFG] = &qhs_ipa,
1514 [SLAVE_CNOC_MNOC_CFG] = &qhs_mnoc_cfg,
1515 [SLAVE_CNOC_MSS] = &qhs_mss_cfg,
1516 [SLAVE_NPU_CFG] = &qhs_npu_cfg,
1517 [SLAVE_PDM] = &qhs_pdm,
1518 [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
1519 [SLAVE_PRNG] = &qhs_prng,
1520 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
1521 [SLAVE_QM_CFG] = &qhs_qm_cfg,
1522 [SLAVE_QM_MPU_CFG] = &qhs_qm_mpu_cfg,
1523 [SLAVE_QUP_0] = &qhs_qup0,
1524 [SLAVE_QUP_1] = &qhs_qup1,
1525 [SLAVE_SDCC_2] = &qhs_sdc2,
1526 [SLAVE_SECURITY] = &qhs_security,
1527 [SLAVE_SNOC_CFG] = &qhs_snoc_cfg,
1528 [SLAVE_TCSR] = &qhs_tcsr,
1529 [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
1530 [SLAVE_USB3] = &qhs_usb3_0,
1531 [SLAVE_VENUS_CFG] = &qhs_venus_cfg,
1532 [SLAVE_VENUS_THROTTLE_CFG] = &qhs_venus_throttle_cfg,
1533 [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
1534 [SLAVE_SERVICE_CNOC] = &srvc_cnoc,
1535};
1536
1537static const struct qcom_icc_desc sm6350_config_noc = {
1538 .nodes = config_noc_nodes,
1539 .num_nodes = ARRAY_SIZE(config_noc_nodes),
1540 .bcms = config_noc_bcms,
1541 .num_bcms = ARRAY_SIZE(config_noc_bcms),
1542};
1543
1544static struct qcom_icc_bcm * const dc_noc_bcms[] = {
1545};
1546
1547static struct qcom_icc_node * const dc_noc_nodes[] = {
1548 [MASTER_CNOC_DC_NOC] = &qhm_cnoc_dc_noc,
1549 [SLAVE_GEM_NOC_CFG] = &qhs_gemnoc,
1550 [SLAVE_LLCC_CFG] = &qhs_llcc,
1551};
1552
1553static const struct qcom_icc_desc sm6350_dc_noc = {
1554 .nodes = dc_noc_nodes,
1555 .num_nodes = ARRAY_SIZE(dc_noc_nodes),
1556 .bcms = dc_noc_bcms,
1557 .num_bcms = ARRAY_SIZE(dc_noc_bcms),
1558};
1559
1560static struct qcom_icc_bcm * const gem_noc_bcms[] = {
1561 &bcm_sh0,
1562 &bcm_sh2,
1563 &bcm_sh3,
1564 &bcm_sh4,
1565};
1566
1567static struct qcom_icc_node * const gem_noc_nodes[] = {
1568 [MASTER_AMPSS_M0] = &acm_apps,
1569 [MASTER_SYS_TCU] = &acm_sys_tcu,
1570 [MASTER_GEM_NOC_CFG] = &qhm_gemnoc_cfg,
1571 [MASTER_COMPUTE_NOC] = &qnm_cmpnoc,
1572 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
1573 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
1574 [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
1575 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
1576 [MASTER_GRAPHICS_3D] = &qxm_gpu,
1577 [SLAVE_MCDMA_MS_MPU_CFG] = &qhs_mcdma_ms_mpu_cfg,
1578 [SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg,
1579 [SLAVE_GEM_NOC_SNOC] = &qns_gem_noc_snoc,
1580 [SLAVE_LLCC] = &qns_llcc,
1581 [SLAVE_SERVICE_GEM_NOC] = &srvc_gemnoc,
1582};
1583
1584static const struct qcom_icc_desc sm6350_gem_noc = {
1585 .nodes = gem_noc_nodes,
1586 .num_nodes = ARRAY_SIZE(gem_noc_nodes),
1587 .bcms = gem_noc_bcms,
1588 .num_bcms = ARRAY_SIZE(gem_noc_bcms),
1589};
1590
1591static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
1592 &bcm_mm0,
1593 &bcm_mm1,
1594 &bcm_mm2,
1595 &bcm_mm3,
1596};
1597
1598static struct qcom_icc_node * const mmss_noc_nodes[] = {
1599 [MASTER_CNOC_MNOC_CFG] = &qhm_mnoc_cfg,
1600 [MASTER_VIDEO_P0] = &qnm_video0,
1601 [MASTER_VIDEO_PROC] = &qnm_video_cvp,
1602 [MASTER_CAMNOC_HF] = &qxm_camnoc_hf,
1603 [MASTER_CAMNOC_ICP] = &qxm_camnoc_icp,
1604 [MASTER_CAMNOC_SF] = &qxm_camnoc_sf,
1605 [MASTER_MDP_PORT0] = &qxm_mdp0,
1606 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
1607 [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
1608 [SLAVE_SERVICE_MNOC] = &srvc_mnoc,
1609};
1610
1611static const struct qcom_icc_desc sm6350_mmss_noc = {
1612 .nodes = mmss_noc_nodes,
1613 .num_nodes = ARRAY_SIZE(mmss_noc_nodes),
1614 .bcms = mmss_noc_bcms,
1615 .num_bcms = ARRAY_SIZE(mmss_noc_bcms),
1616};
1617
1618static struct qcom_icc_bcm * const npu_noc_bcms[] = {
1619};
1620
1621static struct qcom_icc_node * const npu_noc_nodes[] = {
1622 [MASTER_NPU_SYS] = &amm_npu_sys,
1623 [MASTER_NPU_NOC_CFG] = &qhm_npu_cfg,
1624 [SLAVE_NPU_CAL_DP0] = &qhs_cal_dp0,
1625 [SLAVE_NPU_CP] = &qhs_cp,
1626 [SLAVE_NPU_INT_DMA_BWMON_CFG] = &qhs_dma_bwmon,
1627 [SLAVE_NPU_DPM] = &qhs_dpm,
1628 [SLAVE_ISENSE_CFG] = &qhs_isense,
1629 [SLAVE_NPU_LLM_CFG] = &qhs_llm,
1630 [SLAVE_NPU_TCM] = &qhs_tcm,
1631 [SLAVE_NPU_COMPUTE_NOC] = &qns_npu_sys,
1632 [SLAVE_SERVICE_NPU_NOC] = &srvc_noc,
1633};
1634
1635static const struct qcom_icc_desc sm6350_npu_noc = {
1636 .nodes = npu_noc_nodes,
1637 .num_nodes = ARRAY_SIZE(npu_noc_nodes),
1638 .bcms = npu_noc_bcms,
1639 .num_bcms = ARRAY_SIZE(npu_noc_bcms),
1640};
1641
1642static struct qcom_icc_bcm * const system_noc_bcms[] = {
1643 &bcm_sn0,
1644 &bcm_sn1,
1645 &bcm_sn10,
1646 &bcm_sn2,
1647 &bcm_sn3,
1648 &bcm_sn4,
1649 &bcm_sn5,
1650 &bcm_sn6,
1651};
1652
1653static struct qcom_icc_node * const system_noc_nodes[] = {
1654 [MASTER_SNOC_CFG] = &qhm_snoc_cfg,
1655 [A1NOC_SNOC_MAS] = &qnm_aggre1_noc,
1656 [A2NOC_SNOC_MAS] = &qnm_aggre2_noc,
1657 [MASTER_GEM_NOC_SNOC] = &qnm_gemnoc,
1658 [MASTER_PIMEM] = &qxm_pimem,
1659 [MASTER_GIC] = &xm_gic,
1660 [SLAVE_APPSS] = &qhs_apss,
1661 [SNOC_CNOC_SLV] = &qns_cnoc,
1662 [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc,
1663 [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
1664 [SLAVE_OCIMEM] = &qxs_imem,
1665 [SLAVE_PIMEM] = &qxs_pimem,
1666 [SLAVE_SERVICE_SNOC] = &srvc_snoc,
1667 [SLAVE_QDSS_STM] = &xs_qdss_stm,
1668 [SLAVE_TCU] = &xs_sys_tcu_cfg,
1669};
1670
1671static const struct qcom_icc_desc sm6350_system_noc = {
1672 .nodes = system_noc_nodes,
1673 .num_nodes = ARRAY_SIZE(system_noc_nodes),
1674 .bcms = system_noc_bcms,
1675 .num_bcms = ARRAY_SIZE(system_noc_bcms),
1676};
1677
1678static const struct of_device_id qnoc_of_match[] = {
1679 { .compatible = "qcom,sm6350-aggre1-noc",
1680 .data = &sm6350_aggre1_noc},
1681 { .compatible = "qcom,sm6350-aggre2-noc",
1682 .data = &sm6350_aggre2_noc},
1683 { .compatible = "qcom,sm6350-clk-virt",
1684 .data = &sm6350_clk_virt},
1685 { .compatible = "qcom,sm6350-compute-noc",
1686 .data = &sm6350_compute_noc},
1687 { .compatible = "qcom,sm6350-config-noc",
1688 .data = &sm6350_config_noc},
1689 { .compatible = "qcom,sm6350-dc-noc",
1690 .data = &sm6350_dc_noc},
1691 { .compatible = "qcom,sm6350-gem-noc",
1692 .data = &sm6350_gem_noc},
1693 { .compatible = "qcom,sm6350-mmss-noc",
1694 .data = &sm6350_mmss_noc},
1695 { .compatible = "qcom,sm6350-npu-noc",
1696 .data = &sm6350_npu_noc},
1697 { .compatible = "qcom,sm6350-system-noc",
1698 .data = &sm6350_system_noc},
1699 { }
1700};
1701MODULE_DEVICE_TABLE(of, qnoc_of_match);
1702
1703static struct platform_driver qnoc_driver = {
1704 .probe = qcom_icc_rpmh_probe,
1705 .remove_new = qcom_icc_rpmh_remove,
1706 .driver = {
1707 .name = "qnoc-sm6350",
1708 .of_match_table = qnoc_of_match,
1709 .sync_state = icc_sync_state,
1710 },
1711};
1712module_platform_driver(qnoc_driver);
1713
1714MODULE_DESCRIPTION("Qualcomm SM6350 NoC driver");
1715MODULE_LICENSE("GPL v2");
1716

source code of linux/drivers/interconnect/qcom/sm6350.c