1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021, Linaro Limited
5 *
6 */
7
8#include <linux/interconnect-provider.h>
9#include <linux/module.h>
10#include <linux/mod_devicetable.h>
11#include <linux/platform_device.h>
12#include <dt-bindings/interconnect/qcom,sm8350.h>
13
14#include "bcm-voter.h"
15#include "icc-rpmh.h"
16#include "sm8350.h"
17
18static struct qcom_icc_node qhm_qspi = {
19 .name = "qhm_qspi",
20 .id = SM8350_MASTER_QSPI_0,
21 .channels = 1,
22 .buswidth = 4,
23 .num_links = 1,
24 .links = { SM8350_SLAVE_A1NOC_SNOC },
25};
26
27static struct qcom_icc_node qhm_qup0 = {
28 .name = "qhm_qup0",
29 .id = SM8350_MASTER_QUP_0,
30 .channels = 1,
31 .buswidth = 4,
32 .num_links = 1,
33 .links = { SM8350_SLAVE_A2NOC_SNOC },
34};
35
36static struct qcom_icc_node qhm_qup1 = {
37 .name = "qhm_qup1",
38 .id = SM8350_MASTER_QUP_1,
39 .channels = 1,
40 .buswidth = 4,
41 .num_links = 1,
42 .links = { SM8350_SLAVE_A1NOC_SNOC },
43};
44
45static struct qcom_icc_node qhm_qup2 = {
46 .name = "qhm_qup2",
47 .id = SM8350_MASTER_QUP_2,
48 .channels = 1,
49 .buswidth = 4,
50 .num_links = 1,
51 .links = { SM8350_SLAVE_A2NOC_SNOC },
52};
53
54static struct qcom_icc_node qnm_a1noc_cfg = {
55 .name = "qnm_a1noc_cfg",
56 .id = SM8350_MASTER_A1NOC_CFG,
57 .channels = 1,
58 .buswidth = 4,
59 .num_links = 1,
60 .links = { SM8350_SLAVE_SERVICE_A1NOC },
61};
62
63static struct qcom_icc_node xm_sdc4 = {
64 .name = "xm_sdc4",
65 .id = SM8350_MASTER_SDCC_4,
66 .channels = 1,
67 .buswidth = 8,
68 .num_links = 1,
69 .links = { SM8350_SLAVE_A1NOC_SNOC },
70};
71
72static struct qcom_icc_node xm_ufs_mem = {
73 .name = "xm_ufs_mem",
74 .id = SM8350_MASTER_UFS_MEM,
75 .channels = 1,
76 .buswidth = 8,
77 .num_links = 1,
78 .links = { SM8350_SLAVE_A1NOC_SNOC },
79};
80
81static struct qcom_icc_node xm_usb3_0 = {
82 .name = "xm_usb3_0",
83 .id = SM8350_MASTER_USB3_0,
84 .channels = 1,
85 .buswidth = 8,
86 .num_links = 1,
87 .links = { SM8350_SLAVE_A1NOC_SNOC },
88};
89
90static struct qcom_icc_node xm_usb3_1 = {
91 .name = "xm_usb3_1",
92 .id = SM8350_MASTER_USB3_1,
93 .channels = 1,
94 .buswidth = 8,
95 .num_links = 1,
96 .links = { SM8350_SLAVE_A1NOC_SNOC },
97};
98
99static struct qcom_icc_node qhm_qdss_bam = {
100 .name = "qhm_qdss_bam",
101 .id = SM8350_MASTER_QDSS_BAM,
102 .channels = 1,
103 .buswidth = 4,
104 .num_links = 1,
105 .links = { SM8350_SLAVE_A2NOC_SNOC },
106};
107
108static struct qcom_icc_node qnm_a2noc_cfg = {
109 .name = "qnm_a2noc_cfg",
110 .id = SM8350_MASTER_A2NOC_CFG,
111 .channels = 1,
112 .buswidth = 4,
113 .num_links = 1,
114 .links = { SM8350_SLAVE_SERVICE_A2NOC },
115};
116
117static struct qcom_icc_node qxm_crypto = {
118 .name = "qxm_crypto",
119 .id = SM8350_MASTER_CRYPTO,
120 .channels = 1,
121 .buswidth = 8,
122 .num_links = 1,
123 .links = { SM8350_SLAVE_A2NOC_SNOC },
124};
125
126static struct qcom_icc_node qxm_ipa = {
127 .name = "qxm_ipa",
128 .id = SM8350_MASTER_IPA,
129 .channels = 1,
130 .buswidth = 8,
131 .num_links = 1,
132 .links = { SM8350_SLAVE_A2NOC_SNOC },
133};
134
135static struct qcom_icc_node xm_pcie3_0 = {
136 .name = "xm_pcie3_0",
137 .id = SM8350_MASTER_PCIE_0,
138 .channels = 1,
139 .buswidth = 8,
140 .num_links = 1,
141 .links = { SM8350_SLAVE_ANOC_PCIE_GEM_NOC },
142};
143
144static struct qcom_icc_node xm_pcie3_1 = {
145 .name = "xm_pcie3_1",
146 .id = SM8350_MASTER_PCIE_1,
147 .channels = 1,
148 .buswidth = 8,
149 .num_links = 1,
150 .links = { SM8350_SLAVE_ANOC_PCIE_GEM_NOC },
151};
152
153static struct qcom_icc_node xm_qdss_etr = {
154 .name = "xm_qdss_etr",
155 .id = SM8350_MASTER_QDSS_ETR,
156 .channels = 1,
157 .buswidth = 8,
158 .num_links = 1,
159 .links = { SM8350_SLAVE_A2NOC_SNOC },
160};
161
162static struct qcom_icc_node xm_sdc2 = {
163 .name = "xm_sdc2",
164 .id = SM8350_MASTER_SDCC_2,
165 .channels = 1,
166 .buswidth = 8,
167 .num_links = 1,
168 .links = { SM8350_SLAVE_A2NOC_SNOC },
169};
170
171static struct qcom_icc_node xm_ufs_card = {
172 .name = "xm_ufs_card",
173 .id = SM8350_MASTER_UFS_CARD,
174 .channels = 1,
175 .buswidth = 8,
176 .num_links = 1,
177 .links = { SM8350_SLAVE_A2NOC_SNOC },
178};
179
180static struct qcom_icc_node qnm_gemnoc_cnoc = {
181 .name = "qnm_gemnoc_cnoc",
182 .id = SM8350_MASTER_GEM_NOC_CNOC,
183 .channels = 1,
184 .buswidth = 16,
185 .num_links = 56,
186 .links = { SM8350_SLAVE_AHB2PHY_SOUTH,
187 SM8350_SLAVE_AHB2PHY_NORTH,
188 SM8350_SLAVE_AOSS,
189 SM8350_SLAVE_APPSS,
190 SM8350_SLAVE_CAMERA_CFG,
191 SM8350_SLAVE_CLK_CTL,
192 SM8350_SLAVE_CDSP_CFG,
193 SM8350_SLAVE_RBCPR_CX_CFG,
194 SM8350_SLAVE_RBCPR_MMCX_CFG,
195 SM8350_SLAVE_RBCPR_MX_CFG,
196 SM8350_SLAVE_CRYPTO_0_CFG,
197 SM8350_SLAVE_CX_RDPM,
198 SM8350_SLAVE_DCC_CFG,
199 SM8350_SLAVE_DISPLAY_CFG,
200 SM8350_SLAVE_GFX3D_CFG,
201 SM8350_SLAVE_HWKM,
202 SM8350_SLAVE_IMEM_CFG,
203 SM8350_SLAVE_IPA_CFG,
204 SM8350_SLAVE_IPC_ROUTER_CFG,
205 SM8350_SLAVE_LPASS,
206 SM8350_SLAVE_CNOC_MSS,
207 SM8350_SLAVE_MX_RDPM,
208 SM8350_SLAVE_PCIE_0_CFG,
209 SM8350_SLAVE_PCIE_1_CFG,
210 SM8350_SLAVE_PDM,
211 SM8350_SLAVE_PIMEM_CFG,
212 SM8350_SLAVE_PKA_WRAPPER_CFG,
213 SM8350_SLAVE_PMU_WRAPPER_CFG,
214 SM8350_SLAVE_QDSS_CFG,
215 SM8350_SLAVE_QSPI_0,
216 SM8350_SLAVE_QUP_0,
217 SM8350_SLAVE_QUP_1,
218 SM8350_SLAVE_QUP_2,
219 SM8350_SLAVE_SDCC_2,
220 SM8350_SLAVE_SDCC_4,
221 SM8350_SLAVE_SECURITY,
222 SM8350_SLAVE_SPSS_CFG,
223 SM8350_SLAVE_TCSR,
224 SM8350_SLAVE_TLMM,
225 SM8350_SLAVE_UFS_CARD_CFG,
226 SM8350_SLAVE_UFS_MEM_CFG,
227 SM8350_SLAVE_USB3_0,
228 SM8350_SLAVE_USB3_1,
229 SM8350_SLAVE_VENUS_CFG,
230 SM8350_SLAVE_VSENSE_CTRL_CFG,
231 SM8350_SLAVE_A1NOC_CFG,
232 SM8350_SLAVE_A2NOC_CFG,
233 SM8350_SLAVE_DDRSS_CFG,
234 SM8350_SLAVE_CNOC_MNOC_CFG,
235 SM8350_SLAVE_SNOC_CFG,
236 SM8350_SLAVE_BOOT_IMEM,
237 SM8350_SLAVE_IMEM,
238 SM8350_SLAVE_PIMEM,
239 SM8350_SLAVE_SERVICE_CNOC,
240 SM8350_SLAVE_QDSS_STM,
241 SM8350_SLAVE_TCU
242 },
243};
244
245static struct qcom_icc_node qnm_gemnoc_pcie = {
246 .name = "qnm_gemnoc_pcie",
247 .id = SM8350_MASTER_GEM_NOC_PCIE_SNOC,
248 .channels = 1,
249 .buswidth = 8,
250 .num_links = 2,
251 .links = { SM8350_SLAVE_PCIE_0,
252 SM8350_SLAVE_PCIE_1
253 },
254};
255
256static struct qcom_icc_node xm_qdss_dap = {
257 .name = "xm_qdss_dap",
258 .id = SM8350_MASTER_QDSS_DAP,
259 .channels = 1,
260 .buswidth = 8,
261 .num_links = 56,
262 .links = { SM8350_SLAVE_AHB2PHY_SOUTH,
263 SM8350_SLAVE_AHB2PHY_NORTH,
264 SM8350_SLAVE_AOSS,
265 SM8350_SLAVE_APPSS,
266 SM8350_SLAVE_CAMERA_CFG,
267 SM8350_SLAVE_CLK_CTL,
268 SM8350_SLAVE_CDSP_CFG,
269 SM8350_SLAVE_RBCPR_CX_CFG,
270 SM8350_SLAVE_RBCPR_MMCX_CFG,
271 SM8350_SLAVE_RBCPR_MX_CFG,
272 SM8350_SLAVE_CRYPTO_0_CFG,
273 SM8350_SLAVE_CX_RDPM,
274 SM8350_SLAVE_DCC_CFG,
275 SM8350_SLAVE_DISPLAY_CFG,
276 SM8350_SLAVE_GFX3D_CFG,
277 SM8350_SLAVE_HWKM,
278 SM8350_SLAVE_IMEM_CFG,
279 SM8350_SLAVE_IPA_CFG,
280 SM8350_SLAVE_IPC_ROUTER_CFG,
281 SM8350_SLAVE_LPASS,
282 SM8350_SLAVE_CNOC_MSS,
283 SM8350_SLAVE_MX_RDPM,
284 SM8350_SLAVE_PCIE_0_CFG,
285 SM8350_SLAVE_PCIE_1_CFG,
286 SM8350_SLAVE_PDM,
287 SM8350_SLAVE_PIMEM_CFG,
288 SM8350_SLAVE_PKA_WRAPPER_CFG,
289 SM8350_SLAVE_PMU_WRAPPER_CFG,
290 SM8350_SLAVE_QDSS_CFG,
291 SM8350_SLAVE_QSPI_0,
292 SM8350_SLAVE_QUP_0,
293 SM8350_SLAVE_QUP_1,
294 SM8350_SLAVE_QUP_2,
295 SM8350_SLAVE_SDCC_2,
296 SM8350_SLAVE_SDCC_4,
297 SM8350_SLAVE_SECURITY,
298 SM8350_SLAVE_SPSS_CFG,
299 SM8350_SLAVE_TCSR,
300 SM8350_SLAVE_TLMM,
301 SM8350_SLAVE_UFS_CARD_CFG,
302 SM8350_SLAVE_UFS_MEM_CFG,
303 SM8350_SLAVE_USB3_0,
304 SM8350_SLAVE_USB3_1,
305 SM8350_SLAVE_VENUS_CFG,
306 SM8350_SLAVE_VSENSE_CTRL_CFG,
307 SM8350_SLAVE_A1NOC_CFG,
308 SM8350_SLAVE_A2NOC_CFG,
309 SM8350_SLAVE_DDRSS_CFG,
310 SM8350_SLAVE_CNOC_MNOC_CFG,
311 SM8350_SLAVE_SNOC_CFG,
312 SM8350_SLAVE_BOOT_IMEM,
313 SM8350_SLAVE_IMEM,
314 SM8350_SLAVE_PIMEM,
315 SM8350_SLAVE_SERVICE_CNOC,
316 SM8350_SLAVE_QDSS_STM,
317 SM8350_SLAVE_TCU
318 },
319};
320
321static struct qcom_icc_node qnm_cnoc_dc_noc = {
322 .name = "qnm_cnoc_dc_noc",
323 .id = SM8350_MASTER_CNOC_DC_NOC,
324 .channels = 1,
325 .buswidth = 4,
326 .num_links = 2,
327 .links = { SM8350_SLAVE_LLCC_CFG,
328 SM8350_SLAVE_GEM_NOC_CFG
329 },
330};
331
332static struct qcom_icc_node alm_gpu_tcu = {
333 .name = "alm_gpu_tcu",
334 .id = SM8350_MASTER_GPU_TCU,
335 .channels = 1,
336 .buswidth = 8,
337 .num_links = 2,
338 .links = { SM8350_SLAVE_GEM_NOC_CNOC,
339 SM8350_SLAVE_LLCC
340 },
341};
342
343static struct qcom_icc_node alm_sys_tcu = {
344 .name = "alm_sys_tcu",
345 .id = SM8350_MASTER_SYS_TCU,
346 .channels = 1,
347 .buswidth = 8,
348 .num_links = 2,
349 .links = { SM8350_SLAVE_GEM_NOC_CNOC,
350 SM8350_SLAVE_LLCC
351 },
352};
353
354static struct qcom_icc_node chm_apps = {
355 .name = "chm_apps",
356 .id = SM8350_MASTER_APPSS_PROC,
357 .channels = 2,
358 .buswidth = 32,
359 .num_links = 3,
360 .links = { SM8350_SLAVE_GEM_NOC_CNOC,
361 SM8350_SLAVE_LLCC,
362 SM8350_SLAVE_MEM_NOC_PCIE_SNOC
363 },
364};
365
366static struct qcom_icc_node qnm_cmpnoc = {
367 .name = "qnm_cmpnoc",
368 .id = SM8350_MASTER_COMPUTE_NOC,
369 .channels = 2,
370 .buswidth = 32,
371 .num_links = 2,
372 .links = { SM8350_SLAVE_GEM_NOC_CNOC,
373 SM8350_SLAVE_LLCC
374 },
375};
376
377static struct qcom_icc_node qnm_gemnoc_cfg = {
378 .name = "qnm_gemnoc_cfg",
379 .id = SM8350_MASTER_GEM_NOC_CFG,
380 .channels = 1,
381 .buswidth = 4,
382 .num_links = 5,
383 .links = { SM8350_SLAVE_MSS_PROC_MS_MPU_CFG,
384 SM8350_SLAVE_MCDMA_MS_MPU_CFG,
385 SM8350_SLAVE_SERVICE_GEM_NOC_1,
386 SM8350_SLAVE_SERVICE_GEM_NOC_2,
387 SM8350_SLAVE_SERVICE_GEM_NOC
388 },
389};
390
391static struct qcom_icc_node qnm_gpu = {
392 .name = "qnm_gpu",
393 .id = SM8350_MASTER_GFX3D,
394 .channels = 2,
395 .buswidth = 32,
396 .num_links = 2,
397 .links = { SM8350_SLAVE_GEM_NOC_CNOC,
398 SM8350_SLAVE_LLCC
399 },
400};
401
402static struct qcom_icc_node qnm_mnoc_hf = {
403 .name = "qnm_mnoc_hf",
404 .id = SM8350_MASTER_MNOC_HF_MEM_NOC,
405 .channels = 2,
406 .buswidth = 32,
407 .num_links = 1,
408 .links = { SM8350_SLAVE_LLCC },
409};
410
411static struct qcom_icc_node qnm_mnoc_sf = {
412 .name = "qnm_mnoc_sf",
413 .id = SM8350_MASTER_MNOC_SF_MEM_NOC,
414 .channels = 2,
415 .buswidth = 32,
416 .num_links = 2,
417 .links = { SM8350_SLAVE_GEM_NOC_CNOC,
418 SM8350_SLAVE_LLCC
419 },
420};
421
422static struct qcom_icc_node qnm_pcie = {
423 .name = "qnm_pcie",
424 .id = SM8350_MASTER_ANOC_PCIE_GEM_NOC,
425 .channels = 1,
426 .buswidth = 16,
427 .num_links = 2,
428 .links = { SM8350_SLAVE_GEM_NOC_CNOC,
429 SM8350_SLAVE_LLCC
430 },
431};
432
433static struct qcom_icc_node qnm_snoc_gc = {
434 .name = "qnm_snoc_gc",
435 .id = SM8350_MASTER_SNOC_GC_MEM_NOC,
436 .channels = 1,
437 .buswidth = 8,
438 .num_links = 1,
439 .links = { SM8350_SLAVE_LLCC },
440};
441
442static struct qcom_icc_node qnm_snoc_sf = {
443 .name = "qnm_snoc_sf",
444 .id = SM8350_MASTER_SNOC_SF_MEM_NOC,
445 .channels = 1,
446 .buswidth = 16,
447 .num_links = 3,
448 .links = { SM8350_SLAVE_GEM_NOC_CNOC,
449 SM8350_SLAVE_LLCC,
450 SM8350_SLAVE_MEM_NOC_PCIE_SNOC
451 },
452};
453
454static struct qcom_icc_node qhm_config_noc = {
455 .name = "qhm_config_noc",
456 .id = SM8350_MASTER_CNOC_LPASS_AG_NOC,
457 .channels = 1,
458 .buswidth = 4,
459 .num_links = 6,
460 .links = { SM8350_SLAVE_LPASS_CORE_CFG,
461 SM8350_SLAVE_LPASS_LPI_CFG,
462 SM8350_SLAVE_LPASS_MPU_CFG,
463 SM8350_SLAVE_LPASS_TOP_CFG,
464 SM8350_SLAVE_SERVICES_LPASS_AML_NOC,
465 SM8350_SLAVE_SERVICE_LPASS_AG_NOC
466 },
467};
468
469static struct qcom_icc_node llcc_mc = {
470 .name = "llcc_mc",
471 .id = SM8350_MASTER_LLCC,
472 .channels = 4,
473 .buswidth = 4,
474 .num_links = 1,
475 .links = { SM8350_SLAVE_EBI1 },
476};
477
478static struct qcom_icc_node qnm_camnoc_hf = {
479 .name = "qnm_camnoc_hf",
480 .id = SM8350_MASTER_CAMNOC_HF,
481 .channels = 2,
482 .buswidth = 32,
483 .num_links = 1,
484 .links = { SM8350_SLAVE_MNOC_HF_MEM_NOC },
485};
486
487static struct qcom_icc_node qnm_camnoc_icp = {
488 .name = "qnm_camnoc_icp",
489 .id = SM8350_MASTER_CAMNOC_ICP,
490 .channels = 1,
491 .buswidth = 8,
492 .num_links = 1,
493 .links = { SM8350_SLAVE_MNOC_SF_MEM_NOC },
494};
495
496static struct qcom_icc_node qnm_camnoc_sf = {
497 .name = "qnm_camnoc_sf",
498 .id = SM8350_MASTER_CAMNOC_SF,
499 .channels = 2,
500 .buswidth = 32,
501 .num_links = 1,
502 .links = { SM8350_SLAVE_MNOC_SF_MEM_NOC },
503};
504
505static struct qcom_icc_node qnm_mnoc_cfg = {
506 .name = "qnm_mnoc_cfg",
507 .id = SM8350_MASTER_CNOC_MNOC_CFG,
508 .channels = 1,
509 .buswidth = 4,
510 .num_links = 1,
511 .links = { SM8350_SLAVE_SERVICE_MNOC },
512};
513
514static struct qcom_icc_node qnm_video0 = {
515 .name = "qnm_video0",
516 .id = SM8350_MASTER_VIDEO_P0,
517 .channels = 1,
518 .buswidth = 32,
519 .num_links = 1,
520 .links = { SM8350_SLAVE_MNOC_SF_MEM_NOC },
521};
522
523static struct qcom_icc_node qnm_video1 = {
524 .name = "qnm_video1",
525 .id = SM8350_MASTER_VIDEO_P1,
526 .channels = 1,
527 .buswidth = 32,
528 .num_links = 1,
529 .links = { SM8350_SLAVE_MNOC_SF_MEM_NOC },
530};
531
532static struct qcom_icc_node qnm_video_cvp = {
533 .name = "qnm_video_cvp",
534 .id = SM8350_MASTER_VIDEO_PROC,
535 .channels = 1,
536 .buswidth = 32,
537 .num_links = 1,
538 .links = { SM8350_SLAVE_MNOC_SF_MEM_NOC },
539};
540
541static struct qcom_icc_node qxm_mdp0 = {
542 .name = "qxm_mdp0",
543 .id = SM8350_MASTER_MDP0,
544 .channels = 1,
545 .buswidth = 32,
546 .num_links = 1,
547 .links = { SM8350_SLAVE_MNOC_HF_MEM_NOC },
548};
549
550static struct qcom_icc_node qxm_mdp1 = {
551 .name = "qxm_mdp1",
552 .id = SM8350_MASTER_MDP1,
553 .channels = 1,
554 .buswidth = 32,
555 .num_links = 1,
556 .links = { SM8350_SLAVE_MNOC_HF_MEM_NOC },
557};
558
559static struct qcom_icc_node qxm_rot = {
560 .name = "qxm_rot",
561 .id = SM8350_MASTER_ROTATOR,
562 .channels = 1,
563 .buswidth = 32,
564 .num_links = 1,
565 .links = { SM8350_SLAVE_MNOC_SF_MEM_NOC },
566};
567
568static struct qcom_icc_node qhm_nsp_noc_config = {
569 .name = "qhm_nsp_noc_config",
570 .id = SM8350_MASTER_CDSP_NOC_CFG,
571 .channels = 1,
572 .buswidth = 4,
573 .num_links = 1,
574 .links = { SM8350_SLAVE_SERVICE_NSP_NOC },
575};
576
577static struct qcom_icc_node qxm_nsp = {
578 .name = "qxm_nsp",
579 .id = SM8350_MASTER_CDSP_PROC,
580 .channels = 2,
581 .buswidth = 32,
582 .num_links = 1,
583 .links = { SM8350_SLAVE_CDSP_MEM_NOC },
584};
585
586static struct qcom_icc_node qnm_aggre1_noc = {
587 .name = "qnm_aggre1_noc",
588 .id = SM8350_MASTER_A1NOC_SNOC,
589 .channels = 1,
590 .buswidth = 16,
591 .num_links = 1,
592 .links = { SM8350_SLAVE_SNOC_GEM_NOC_SF },
593};
594
595static struct qcom_icc_node qnm_aggre2_noc = {
596 .name = "qnm_aggre2_noc",
597 .id = SM8350_MASTER_A2NOC_SNOC,
598 .channels = 1,
599 .buswidth = 16,
600 .num_links = 1,
601 .links = { SM8350_SLAVE_SNOC_GEM_NOC_SF },
602};
603
604static struct qcom_icc_node qnm_snoc_cfg = {
605 .name = "qnm_snoc_cfg",
606 .id = SM8350_MASTER_SNOC_CFG,
607 .channels = 1,
608 .buswidth = 4,
609 .num_links = 1,
610 .links = { SM8350_SLAVE_SERVICE_SNOC },
611};
612
613static struct qcom_icc_node qxm_pimem = {
614 .name = "qxm_pimem",
615 .id = SM8350_MASTER_PIMEM,
616 .channels = 1,
617 .buswidth = 8,
618 .num_links = 1,
619 .links = { SM8350_SLAVE_SNOC_GEM_NOC_GC },
620};
621
622static struct qcom_icc_node xm_gic = {
623 .name = "xm_gic",
624 .id = SM8350_MASTER_GIC,
625 .channels = 1,
626 .buswidth = 8,
627 .num_links = 1,
628 .links = { SM8350_SLAVE_SNOC_GEM_NOC_GC },
629};
630
631static struct qcom_icc_node qnm_mnoc_hf_disp = {
632 .name = "qnm_mnoc_hf_disp",
633 .id = SM8350_MASTER_MNOC_HF_MEM_NOC_DISP,
634 .channels = 2,
635 .buswidth = 32,
636 .num_links = 1,
637 .links = { SM8350_SLAVE_LLCC_DISP },
638};
639
640static struct qcom_icc_node qnm_mnoc_sf_disp = {
641 .name = "qnm_mnoc_sf_disp",
642 .id = SM8350_MASTER_MNOC_SF_MEM_NOC_DISP,
643 .channels = 2,
644 .buswidth = 32,
645 .num_links = 1,
646 .links = { SM8350_SLAVE_LLCC_DISP },
647};
648
649static struct qcom_icc_node llcc_mc_disp = {
650 .name = "llcc_mc_disp",
651 .id = SM8350_MASTER_LLCC_DISP,
652 .channels = 4,
653 .buswidth = 4,
654 .num_links = 1,
655 .links = { SM8350_SLAVE_EBI1_DISP },
656};
657
658static struct qcom_icc_node qxm_mdp0_disp = {
659 .name = "qxm_mdp0_disp",
660 .id = SM8350_MASTER_MDP0_DISP,
661 .channels = 1,
662 .buswidth = 32,
663 .num_links = 1,
664 .links = { SM8350_SLAVE_MNOC_HF_MEM_NOC_DISP },
665};
666
667static struct qcom_icc_node qxm_mdp1_disp = {
668 .name = "qxm_mdp1_disp",
669 .id = SM8350_MASTER_MDP1_DISP,
670 .channels = 1,
671 .buswidth = 32,
672 .num_links = 1,
673 .links = { SM8350_SLAVE_MNOC_HF_MEM_NOC_DISP },
674};
675
676static struct qcom_icc_node qxm_rot_disp = {
677 .name = "qxm_rot_disp",
678 .id = SM8350_MASTER_ROTATOR_DISP,
679 .channels = 1,
680 .buswidth = 32,
681 .num_links = 1,
682 .links = { SM8350_SLAVE_MNOC_SF_MEM_NOC_DISP },
683};
684
685static struct qcom_icc_node qns_a1noc_snoc = {
686 .name = "qns_a1noc_snoc",
687 .id = SM8350_SLAVE_A1NOC_SNOC,
688 .channels = 1,
689 .buswidth = 16,
690 .num_links = 1,
691 .links = { SM8350_MASTER_A1NOC_SNOC },
692};
693
694static struct qcom_icc_node srvc_aggre1_noc = {
695 .name = "srvc_aggre1_noc",
696 .id = SM8350_SLAVE_SERVICE_A1NOC,
697 .channels = 1,
698 .buswidth = 4,
699};
700
701static struct qcom_icc_node qns_a2noc_snoc = {
702 .name = "qns_a2noc_snoc",
703 .id = SM8350_SLAVE_A2NOC_SNOC,
704 .channels = 1,
705 .buswidth = 16,
706 .num_links = 1,
707 .links = { SM8350_MASTER_A2NOC_SNOC },
708};
709
710static struct qcom_icc_node qns_pcie_mem_noc = {
711 .name = "qns_pcie_mem_noc",
712 .id = SM8350_SLAVE_ANOC_PCIE_GEM_NOC,
713 .channels = 1,
714 .buswidth = 16,
715 .num_links = 1,
716 .links = { SM8350_MASTER_ANOC_PCIE_GEM_NOC },
717};
718
719static struct qcom_icc_node srvc_aggre2_noc = {
720 .name = "srvc_aggre2_noc",
721 .id = SM8350_SLAVE_SERVICE_A2NOC,
722 .channels = 1,
723 .buswidth = 4,
724};
725
726static struct qcom_icc_node qhs_ahb2phy0 = {
727 .name = "qhs_ahb2phy0",
728 .id = SM8350_SLAVE_AHB2PHY_SOUTH,
729 .channels = 1,
730 .buswidth = 4,
731};
732
733static struct qcom_icc_node qhs_ahb2phy1 = {
734 .name = "qhs_ahb2phy1",
735 .id = SM8350_SLAVE_AHB2PHY_NORTH,
736 .channels = 1,
737 .buswidth = 4,
738};
739
740static struct qcom_icc_node qhs_aoss = {
741 .name = "qhs_aoss",
742 .id = SM8350_SLAVE_AOSS,
743 .channels = 1,
744 .buswidth = 4,
745};
746
747static struct qcom_icc_node qhs_apss = {
748 .name = "qhs_apss",
749 .id = SM8350_SLAVE_APPSS,
750 .channels = 1,
751 .buswidth = 8,
752};
753
754static struct qcom_icc_node qhs_camera_cfg = {
755 .name = "qhs_camera_cfg",
756 .id = SM8350_SLAVE_CAMERA_CFG,
757 .channels = 1,
758 .buswidth = 4,
759};
760
761static struct qcom_icc_node qhs_clk_ctl = {
762 .name = "qhs_clk_ctl",
763 .id = SM8350_SLAVE_CLK_CTL,
764 .channels = 1,
765 .buswidth = 4,
766};
767
768static struct qcom_icc_node qhs_compute_cfg = {
769 .name = "qhs_compute_cfg",
770 .id = SM8350_SLAVE_CDSP_CFG,
771 .channels = 1,
772 .buswidth = 4,
773};
774
775static struct qcom_icc_node qhs_cpr_cx = {
776 .name = "qhs_cpr_cx",
777 .id = SM8350_SLAVE_RBCPR_CX_CFG,
778 .channels = 1,
779 .buswidth = 4,
780};
781
782static struct qcom_icc_node qhs_cpr_mmcx = {
783 .name = "qhs_cpr_mmcx",
784 .id = SM8350_SLAVE_RBCPR_MMCX_CFG,
785 .channels = 1,
786 .buswidth = 4,
787};
788
789static struct qcom_icc_node qhs_cpr_mx = {
790 .name = "qhs_cpr_mx",
791 .id = SM8350_SLAVE_RBCPR_MX_CFG,
792 .channels = 1,
793 .buswidth = 4,
794};
795
796static struct qcom_icc_node qhs_crypto0_cfg = {
797 .name = "qhs_crypto0_cfg",
798 .id = SM8350_SLAVE_CRYPTO_0_CFG,
799 .channels = 1,
800 .buswidth = 4,
801};
802
803static struct qcom_icc_node qhs_cx_rdpm = {
804 .name = "qhs_cx_rdpm",
805 .id = SM8350_SLAVE_CX_RDPM,
806 .channels = 1,
807 .buswidth = 4,
808};
809
810static struct qcom_icc_node qhs_dcc_cfg = {
811 .name = "qhs_dcc_cfg",
812 .id = SM8350_SLAVE_DCC_CFG,
813 .channels = 1,
814 .buswidth = 4,
815};
816
817static struct qcom_icc_node qhs_display_cfg = {
818 .name = "qhs_display_cfg",
819 .id = SM8350_SLAVE_DISPLAY_CFG,
820 .channels = 1,
821 .buswidth = 4,
822};
823
824static struct qcom_icc_node qhs_gpuss_cfg = {
825 .name = "qhs_gpuss_cfg",
826 .id = SM8350_SLAVE_GFX3D_CFG,
827 .channels = 1,
828 .buswidth = 8,
829};
830
831static struct qcom_icc_node qhs_hwkm = {
832 .name = "qhs_hwkm",
833 .id = SM8350_SLAVE_HWKM,
834 .channels = 1,
835 .buswidth = 4,
836};
837
838static struct qcom_icc_node qhs_imem_cfg = {
839 .name = "qhs_imem_cfg",
840 .id = SM8350_SLAVE_IMEM_CFG,
841 .channels = 1,
842 .buswidth = 4,
843};
844
845static struct qcom_icc_node qhs_ipa = {
846 .name = "qhs_ipa",
847 .id = SM8350_SLAVE_IPA_CFG,
848 .channels = 1,
849 .buswidth = 4,
850};
851
852static struct qcom_icc_node qhs_ipc_router = {
853 .name = "qhs_ipc_router",
854 .id = SM8350_SLAVE_IPC_ROUTER_CFG,
855 .channels = 1,
856 .buswidth = 4,
857};
858
859static struct qcom_icc_node qhs_lpass_cfg = {
860 .name = "qhs_lpass_cfg",
861 .id = SM8350_SLAVE_LPASS,
862 .channels = 1,
863 .buswidth = 4,
864 .num_links = 1,
865 .links = { SM8350_MASTER_CNOC_LPASS_AG_NOC },
866};
867
868static struct qcom_icc_node qhs_mss_cfg = {
869 .name = "qhs_mss_cfg",
870 .id = SM8350_SLAVE_CNOC_MSS,
871 .channels = 1,
872 .buswidth = 4,
873};
874
875static struct qcom_icc_node qhs_mx_rdpm = {
876 .name = "qhs_mx_rdpm",
877 .id = SM8350_SLAVE_MX_RDPM,
878 .channels = 1,
879 .buswidth = 4,
880};
881
882static struct qcom_icc_node qhs_pcie0_cfg = {
883 .name = "qhs_pcie0_cfg",
884 .id = SM8350_SLAVE_PCIE_0_CFG,
885 .channels = 1,
886 .buswidth = 4,
887};
888
889static struct qcom_icc_node qhs_pcie1_cfg = {
890 .name = "qhs_pcie1_cfg",
891 .id = SM8350_SLAVE_PCIE_1_CFG,
892 .channels = 1,
893 .buswidth = 4,
894};
895
896static struct qcom_icc_node qhs_pdm = {
897 .name = "qhs_pdm",
898 .id = SM8350_SLAVE_PDM,
899 .channels = 1,
900 .buswidth = 4,
901};
902
903static struct qcom_icc_node qhs_pimem_cfg = {
904 .name = "qhs_pimem_cfg",
905 .id = SM8350_SLAVE_PIMEM_CFG,
906 .channels = 1,
907 .buswidth = 4,
908};
909
910static struct qcom_icc_node qhs_pka_wrapper_cfg = {
911 .name = "qhs_pka_wrapper_cfg",
912 .id = SM8350_SLAVE_PKA_WRAPPER_CFG,
913 .channels = 1,
914 .buswidth = 4,
915};
916
917static struct qcom_icc_node qhs_pmu_wrapper_cfg = {
918 .name = "qhs_pmu_wrapper_cfg",
919 .id = SM8350_SLAVE_PMU_WRAPPER_CFG,
920 .channels = 1,
921 .buswidth = 4,
922};
923
924static struct qcom_icc_node qhs_qdss_cfg = {
925 .name = "qhs_qdss_cfg",
926 .id = SM8350_SLAVE_QDSS_CFG,
927 .channels = 1,
928 .buswidth = 4,
929};
930
931static struct qcom_icc_node qhs_qspi = {
932 .name = "qhs_qspi",
933 .id = SM8350_SLAVE_QSPI_0,
934 .channels = 1,
935 .buswidth = 4,
936};
937
938static struct qcom_icc_node qhs_qup0 = {
939 .name = "qhs_qup0",
940 .id = SM8350_SLAVE_QUP_0,
941 .channels = 1,
942 .buswidth = 4,
943};
944
945static struct qcom_icc_node qhs_qup1 = {
946 .name = "qhs_qup1",
947 .id = SM8350_SLAVE_QUP_1,
948 .channels = 1,
949 .buswidth = 4,
950};
951
952static struct qcom_icc_node qhs_qup2 = {
953 .name = "qhs_qup2",
954 .id = SM8350_SLAVE_QUP_2,
955 .channels = 1,
956 .buswidth = 4,
957};
958
959static struct qcom_icc_node qhs_sdc2 = {
960 .name = "qhs_sdc2",
961 .id = SM8350_SLAVE_SDCC_2,
962 .channels = 1,
963 .buswidth = 4,
964};
965
966static struct qcom_icc_node qhs_sdc4 = {
967 .name = "qhs_sdc4",
968 .id = SM8350_SLAVE_SDCC_4,
969 .channels = 1,
970 .buswidth = 4,
971};
972
973static struct qcom_icc_node qhs_security = {
974 .name = "qhs_security",
975 .id = SM8350_SLAVE_SECURITY,
976 .channels = 1,
977 .buswidth = 4,
978};
979
980static struct qcom_icc_node qhs_spss_cfg = {
981 .name = "qhs_spss_cfg",
982 .id = SM8350_SLAVE_SPSS_CFG,
983 .channels = 1,
984 .buswidth = 4,
985};
986
987static struct qcom_icc_node qhs_tcsr = {
988 .name = "qhs_tcsr",
989 .id = SM8350_SLAVE_TCSR,
990 .channels = 1,
991 .buswidth = 4,
992};
993
994static struct qcom_icc_node qhs_tlmm = {
995 .name = "qhs_tlmm",
996 .id = SM8350_SLAVE_TLMM,
997 .channels = 1,
998 .buswidth = 4,
999};
1000
1001static struct qcom_icc_node qhs_ufs_card_cfg = {
1002 .name = "qhs_ufs_card_cfg",
1003 .id = SM8350_SLAVE_UFS_CARD_CFG,
1004 .channels = 1,
1005 .buswidth = 4,
1006};
1007
1008static struct qcom_icc_node qhs_ufs_mem_cfg = {
1009 .name = "qhs_ufs_mem_cfg",
1010 .id = SM8350_SLAVE_UFS_MEM_CFG,
1011 .channels = 1,
1012 .buswidth = 4,
1013};
1014
1015static struct qcom_icc_node qhs_usb3_0 = {
1016 .name = "qhs_usb3_0",
1017 .id = SM8350_SLAVE_USB3_0,
1018 .channels = 1,
1019 .buswidth = 4,
1020};
1021
1022static struct qcom_icc_node qhs_usb3_1 = {
1023 .name = "qhs_usb3_1",
1024 .id = SM8350_SLAVE_USB3_1,
1025 .channels = 1,
1026 .buswidth = 4,
1027};
1028
1029static struct qcom_icc_node qhs_venus_cfg = {
1030 .name = "qhs_venus_cfg",
1031 .id = SM8350_SLAVE_VENUS_CFG,
1032 .channels = 1,
1033 .buswidth = 4,
1034};
1035
1036static struct qcom_icc_node qhs_vsense_ctrl_cfg = {
1037 .name = "qhs_vsense_ctrl_cfg",
1038 .id = SM8350_SLAVE_VSENSE_CTRL_CFG,
1039 .channels = 1,
1040 .buswidth = 4,
1041};
1042
1043static struct qcom_icc_node qns_a1_noc_cfg = {
1044 .name = "qns_a1_noc_cfg",
1045 .id = SM8350_SLAVE_A1NOC_CFG,
1046 .channels = 1,
1047 .buswidth = 4,
1048};
1049
1050static struct qcom_icc_node qns_a2_noc_cfg = {
1051 .name = "qns_a2_noc_cfg",
1052 .id = SM8350_SLAVE_A2NOC_CFG,
1053 .channels = 1,
1054 .buswidth = 4,
1055};
1056
1057static struct qcom_icc_node qns_ddrss_cfg = {
1058 .name = "qns_ddrss_cfg",
1059 .id = SM8350_SLAVE_DDRSS_CFG,
1060 .channels = 1,
1061 .buswidth = 4,
1062};
1063
1064static struct qcom_icc_node qns_mnoc_cfg = {
1065 .name = "qns_mnoc_cfg",
1066 .id = SM8350_SLAVE_CNOC_MNOC_CFG,
1067 .channels = 1,
1068 .buswidth = 4,
1069};
1070
1071static struct qcom_icc_node qns_snoc_cfg = {
1072 .name = "qns_snoc_cfg",
1073 .id = SM8350_SLAVE_SNOC_CFG,
1074 .channels = 1,
1075 .buswidth = 4,
1076};
1077
1078static struct qcom_icc_node qxs_boot_imem = {
1079 .name = "qxs_boot_imem",
1080 .id = SM8350_SLAVE_BOOT_IMEM,
1081 .channels = 1,
1082 .buswidth = 8,
1083};
1084
1085static struct qcom_icc_node qxs_imem = {
1086 .name = "qxs_imem",
1087 .id = SM8350_SLAVE_IMEM,
1088 .channels = 1,
1089 .buswidth = 8,
1090};
1091
1092static struct qcom_icc_node qxs_pimem = {
1093 .name = "qxs_pimem",
1094 .id = SM8350_SLAVE_PIMEM,
1095 .channels = 1,
1096 .buswidth = 8,
1097};
1098
1099static struct qcom_icc_node srvc_cnoc = {
1100 .name = "srvc_cnoc",
1101 .id = SM8350_SLAVE_SERVICE_CNOC,
1102 .channels = 1,
1103 .buswidth = 4,
1104};
1105
1106static struct qcom_icc_node xs_pcie_0 = {
1107 .name = "xs_pcie_0",
1108 .id = SM8350_SLAVE_PCIE_0,
1109 .channels = 1,
1110 .buswidth = 8,
1111};
1112
1113static struct qcom_icc_node xs_pcie_1 = {
1114 .name = "xs_pcie_1",
1115 .id = SM8350_SLAVE_PCIE_1,
1116 .channels = 1,
1117 .buswidth = 8,
1118};
1119
1120static struct qcom_icc_node xs_qdss_stm = {
1121 .name = "xs_qdss_stm",
1122 .id = SM8350_SLAVE_QDSS_STM,
1123 .channels = 1,
1124 .buswidth = 4,
1125};
1126
1127static struct qcom_icc_node xs_sys_tcu_cfg = {
1128 .name = "xs_sys_tcu_cfg",
1129 .id = SM8350_SLAVE_TCU,
1130 .channels = 1,
1131 .buswidth = 8,
1132};
1133
1134static struct qcom_icc_node qhs_llcc = {
1135 .name = "qhs_llcc",
1136 .id = SM8350_SLAVE_LLCC_CFG,
1137 .channels = 1,
1138 .buswidth = 4,
1139};
1140
1141static struct qcom_icc_node qns_gemnoc = {
1142 .name = "qns_gemnoc",
1143 .id = SM8350_SLAVE_GEM_NOC_CFG,
1144 .channels = 1,
1145 .buswidth = 4,
1146};
1147
1148static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = {
1149 .name = "qhs_mdsp_ms_mpu_cfg",
1150 .id = SM8350_SLAVE_MSS_PROC_MS_MPU_CFG,
1151 .channels = 1,
1152 .buswidth = 4,
1153};
1154
1155static struct qcom_icc_node qhs_modem_ms_mpu_cfg = {
1156 .name = "qhs_modem_ms_mpu_cfg",
1157 .id = SM8350_SLAVE_MCDMA_MS_MPU_CFG,
1158 .channels = 1,
1159 .buswidth = 4,
1160};
1161
1162static struct qcom_icc_node qns_gem_noc_cnoc = {
1163 .name = "qns_gem_noc_cnoc",
1164 .id = SM8350_SLAVE_GEM_NOC_CNOC,
1165 .channels = 1,
1166 .buswidth = 16,
1167 .num_links = 1,
1168 .links = { SM8350_MASTER_GEM_NOC_CNOC },
1169};
1170
1171static struct qcom_icc_node qns_llcc = {
1172 .name = "qns_llcc",
1173 .id = SM8350_SLAVE_LLCC,
1174 .channels = 4,
1175 .buswidth = 16,
1176 .num_links = 1,
1177 .links = { SM8350_MASTER_LLCC },
1178};
1179
1180static struct qcom_icc_node qns_pcie = {
1181 .name = "qns_pcie",
1182 .id = SM8350_SLAVE_MEM_NOC_PCIE_SNOC,
1183 .channels = 1,
1184 .buswidth = 8,
1185};
1186
1187static struct qcom_icc_node srvc_even_gemnoc = {
1188 .name = "srvc_even_gemnoc",
1189 .id = SM8350_SLAVE_SERVICE_GEM_NOC_1,
1190 .channels = 1,
1191 .buswidth = 4,
1192};
1193
1194static struct qcom_icc_node srvc_odd_gemnoc = {
1195 .name = "srvc_odd_gemnoc",
1196 .id = SM8350_SLAVE_SERVICE_GEM_NOC_2,
1197 .channels = 1,
1198 .buswidth = 4,
1199};
1200
1201static struct qcom_icc_node srvc_sys_gemnoc = {
1202 .name = "srvc_sys_gemnoc",
1203 .id = SM8350_SLAVE_SERVICE_GEM_NOC,
1204 .channels = 1,
1205 .buswidth = 4,
1206};
1207
1208static struct qcom_icc_node qhs_lpass_core = {
1209 .name = "qhs_lpass_core",
1210 .id = SM8350_SLAVE_LPASS_CORE_CFG,
1211 .channels = 1,
1212 .buswidth = 4,
1213};
1214
1215static struct qcom_icc_node qhs_lpass_lpi = {
1216 .name = "qhs_lpass_lpi",
1217 .id = SM8350_SLAVE_LPASS_LPI_CFG,
1218 .channels = 1,
1219 .buswidth = 4,
1220};
1221
1222static struct qcom_icc_node qhs_lpass_mpu = {
1223 .name = "qhs_lpass_mpu",
1224 .id = SM8350_SLAVE_LPASS_MPU_CFG,
1225 .channels = 1,
1226 .buswidth = 4,
1227};
1228
1229static struct qcom_icc_node qhs_lpass_top = {
1230 .name = "qhs_lpass_top",
1231 .id = SM8350_SLAVE_LPASS_TOP_CFG,
1232 .channels = 1,
1233 .buswidth = 4,
1234};
1235
1236static struct qcom_icc_node srvc_niu_aml_noc = {
1237 .name = "srvc_niu_aml_noc",
1238 .id = SM8350_SLAVE_SERVICES_LPASS_AML_NOC,
1239 .channels = 1,
1240 .buswidth = 4,
1241};
1242
1243static struct qcom_icc_node srvc_niu_lpass_agnoc = {
1244 .name = "srvc_niu_lpass_agnoc",
1245 .id = SM8350_SLAVE_SERVICE_LPASS_AG_NOC,
1246 .channels = 1,
1247 .buswidth = 4,
1248};
1249
1250static struct qcom_icc_node ebi = {
1251 .name = "ebi",
1252 .id = SM8350_SLAVE_EBI1,
1253 .channels = 4,
1254 .buswidth = 4,
1255};
1256
1257static struct qcom_icc_node qns_mem_noc_hf = {
1258 .name = "qns_mem_noc_hf",
1259 .id = SM8350_SLAVE_MNOC_HF_MEM_NOC,
1260 .channels = 2,
1261 .buswidth = 32,
1262 .num_links = 1,
1263 .links = { SM8350_MASTER_MNOC_HF_MEM_NOC },
1264};
1265
1266static struct qcom_icc_node qns_mem_noc_sf = {
1267 .name = "qns_mem_noc_sf",
1268 .id = SM8350_SLAVE_MNOC_SF_MEM_NOC,
1269 .channels = 2,
1270 .buswidth = 32,
1271 .num_links = 1,
1272 .links = { SM8350_MASTER_MNOC_SF_MEM_NOC },
1273};
1274
1275static struct qcom_icc_node srvc_mnoc = {
1276 .name = "srvc_mnoc",
1277 .id = SM8350_SLAVE_SERVICE_MNOC,
1278 .channels = 1,
1279 .buswidth = 4,
1280};
1281
1282static struct qcom_icc_node qns_nsp_gemnoc = {
1283 .name = "qns_nsp_gemnoc",
1284 .id = SM8350_SLAVE_CDSP_MEM_NOC,
1285 .channels = 2,
1286 .buswidth = 32,
1287 .num_links = 1,
1288 .links = { SM8350_MASTER_COMPUTE_NOC },
1289};
1290
1291static struct qcom_icc_node service_nsp_noc = {
1292 .name = "service_nsp_noc",
1293 .id = SM8350_SLAVE_SERVICE_NSP_NOC,
1294 .channels = 1,
1295 .buswidth = 4,
1296};
1297
1298static struct qcom_icc_node qns_gemnoc_gc = {
1299 .name = "qns_gemnoc_gc",
1300 .id = SM8350_SLAVE_SNOC_GEM_NOC_GC,
1301 .channels = 1,
1302 .buswidth = 8,
1303 .num_links = 1,
1304 .links = { SM8350_MASTER_SNOC_GC_MEM_NOC },
1305};
1306
1307static struct qcom_icc_node qns_gemnoc_sf = {
1308 .name = "qns_gemnoc_sf",
1309 .id = SM8350_SLAVE_SNOC_GEM_NOC_SF,
1310 .channels = 1,
1311 .buswidth = 16,
1312 .num_links = 1,
1313 .links = { SM8350_MASTER_SNOC_SF_MEM_NOC },
1314};
1315
1316static struct qcom_icc_node srvc_snoc = {
1317 .name = "srvc_snoc",
1318 .id = SM8350_SLAVE_SERVICE_SNOC,
1319 .channels = 1,
1320 .buswidth = 4,
1321};
1322
1323static struct qcom_icc_node qns_llcc_disp = {
1324 .name = "qns_llcc_disp",
1325 .id = SM8350_SLAVE_LLCC_DISP,
1326 .channels = 4,
1327 .buswidth = 16,
1328 .num_links = 1,
1329 .links = { SM8350_MASTER_LLCC_DISP },
1330};
1331
1332static struct qcom_icc_node ebi_disp = {
1333 .name = "ebi_disp",
1334 .id = SM8350_SLAVE_EBI1_DISP,
1335 .channels = 4,
1336 .buswidth = 4,
1337};
1338
1339static struct qcom_icc_node qns_mem_noc_hf_disp = {
1340 .name = "qns_mem_noc_hf_disp",
1341 .id = SM8350_SLAVE_MNOC_HF_MEM_NOC_DISP,
1342 .channels = 2,
1343 .buswidth = 32,
1344 .num_links = 1,
1345 .links = { SM8350_MASTER_MNOC_HF_MEM_NOC_DISP },
1346};
1347
1348static struct qcom_icc_node qns_mem_noc_sf_disp = {
1349 .name = "qns_mem_noc_sf_disp",
1350 .id = SM8350_SLAVE_MNOC_SF_MEM_NOC_DISP,
1351 .channels = 2,
1352 .buswidth = 32,
1353 .num_links = 1,
1354 .links = { SM8350_MASTER_MNOC_SF_MEM_NOC_DISP },
1355};
1356
1357static struct qcom_icc_bcm bcm_acv = {
1358 .name = "ACV",
1359 .enable_mask = BIT(3),
1360 .keepalive = false,
1361 .num_nodes = 1,
1362 .nodes = { &ebi },
1363};
1364
1365static struct qcom_icc_bcm bcm_ce0 = {
1366 .name = "CE0",
1367 .keepalive = false,
1368 .num_nodes = 1,
1369 .nodes = { &qxm_crypto },
1370};
1371
1372static struct qcom_icc_bcm bcm_cn0 = {
1373 .name = "CN0",
1374 .keepalive = true,
1375 .num_nodes = 2,
1376 .nodes = { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie },
1377};
1378
1379static struct qcom_icc_bcm bcm_cn1 = {
1380 .name = "CN1",
1381 .keepalive = false,
1382 .num_nodes = 47,
1383 .nodes = { &xm_qdss_dap,
1384 &qhs_ahb2phy0,
1385 &qhs_ahb2phy1,
1386 &qhs_aoss,
1387 &qhs_apss,
1388 &qhs_camera_cfg,
1389 &qhs_clk_ctl,
1390 &qhs_compute_cfg,
1391 &qhs_cpr_cx,
1392 &qhs_cpr_mmcx,
1393 &qhs_cpr_mx,
1394 &qhs_crypto0_cfg,
1395 &qhs_cx_rdpm,
1396 &qhs_dcc_cfg,
1397 &qhs_display_cfg,
1398 &qhs_gpuss_cfg,
1399 &qhs_hwkm,
1400 &qhs_imem_cfg,
1401 &qhs_ipa,
1402 &qhs_ipc_router,
1403 &qhs_mss_cfg,
1404 &qhs_mx_rdpm,
1405 &qhs_pcie0_cfg,
1406 &qhs_pcie1_cfg,
1407 &qhs_pimem_cfg,
1408 &qhs_pka_wrapper_cfg,
1409 &qhs_pmu_wrapper_cfg,
1410 &qhs_qdss_cfg,
1411 &qhs_qup0,
1412 &qhs_qup1,
1413 &qhs_qup2,
1414 &qhs_security,
1415 &qhs_spss_cfg,
1416 &qhs_tcsr,
1417 &qhs_tlmm,
1418 &qhs_ufs_card_cfg,
1419 &qhs_ufs_mem_cfg,
1420 &qhs_usb3_0,
1421 &qhs_usb3_1,
1422 &qhs_venus_cfg,
1423 &qhs_vsense_ctrl_cfg,
1424 &qns_a1_noc_cfg,
1425 &qns_a2_noc_cfg,
1426 &qns_ddrss_cfg,
1427 &qns_mnoc_cfg,
1428 &qns_snoc_cfg,
1429 &srvc_cnoc
1430 },
1431};
1432
1433static struct qcom_icc_bcm bcm_cn2 = {
1434 .name = "CN2",
1435 .keepalive = false,
1436 .num_nodes = 5,
1437 .nodes = { &qhs_lpass_cfg, &qhs_pdm, &qhs_qspi, &qhs_sdc2, &qhs_sdc4 },
1438};
1439
1440static struct qcom_icc_bcm bcm_co0 = {
1441 .name = "CO0",
1442 .keepalive = false,
1443 .num_nodes = 1,
1444 .nodes = { &qns_nsp_gemnoc },
1445};
1446
1447static struct qcom_icc_bcm bcm_co3 = {
1448 .name = "CO3",
1449 .keepalive = false,
1450 .num_nodes = 1,
1451 .nodes = { &qxm_nsp },
1452};
1453
1454static struct qcom_icc_bcm bcm_mc0 = {
1455 .name = "MC0",
1456 .keepalive = true,
1457 .num_nodes = 1,
1458 .nodes = { &ebi },
1459};
1460
1461static struct qcom_icc_bcm bcm_mm0 = {
1462 .name = "MM0",
1463 .keepalive = true,
1464 .num_nodes = 1,
1465 .nodes = { &qns_mem_noc_hf },
1466};
1467
1468static struct qcom_icc_bcm bcm_mm1 = {
1469 .name = "MM1",
1470 .keepalive = false,
1471 .num_nodes = 3,
1472 .nodes = { &qnm_camnoc_hf, &qxm_mdp0, &qxm_mdp1 },
1473};
1474
1475static struct qcom_icc_bcm bcm_mm4 = {
1476 .name = "MM4",
1477 .keepalive = false,
1478 .num_nodes = 1,
1479 .nodes = { &qns_mem_noc_sf },
1480};
1481
1482static struct qcom_icc_bcm bcm_mm5 = {
1483 .name = "MM5",
1484 .keepalive = false,
1485 .num_nodes = 6,
1486 .nodes = { &qnm_camnoc_icp,
1487 &qnm_camnoc_sf,
1488 &qnm_video0,
1489 &qnm_video1,
1490 &qnm_video_cvp,
1491 &qxm_rot
1492 },
1493};
1494
1495static struct qcom_icc_bcm bcm_sh0 = {
1496 .name = "SH0",
1497 .keepalive = true,
1498 .num_nodes = 1,
1499 .nodes = { &qns_llcc },
1500};
1501
1502static struct qcom_icc_bcm bcm_sh2 = {
1503 .name = "SH2",
1504 .keepalive = false,
1505 .num_nodes = 2,
1506 .nodes = { &alm_gpu_tcu, &alm_sys_tcu },
1507};
1508
1509static struct qcom_icc_bcm bcm_sh3 = {
1510 .name = "SH3",
1511 .keepalive = false,
1512 .num_nodes = 1,
1513 .nodes = { &qnm_cmpnoc },
1514};
1515
1516static struct qcom_icc_bcm bcm_sh4 = {
1517 .name = "SH4",
1518 .keepalive = false,
1519 .num_nodes = 1,
1520 .nodes = { &chm_apps },
1521};
1522
1523static struct qcom_icc_bcm bcm_sn0 = {
1524 .name = "SN0",
1525 .keepalive = true,
1526 .num_nodes = 1,
1527 .nodes = { &qns_gemnoc_sf },
1528};
1529
1530static struct qcom_icc_bcm bcm_sn2 = {
1531 .name = "SN2",
1532 .keepalive = false,
1533 .num_nodes = 1,
1534 .nodes = { &qns_gemnoc_gc },
1535};
1536
1537static struct qcom_icc_bcm bcm_sn3 = {
1538 .name = "SN3",
1539 .keepalive = false,
1540 .num_nodes = 1,
1541 .nodes = { &qxs_pimem },
1542};
1543
1544static struct qcom_icc_bcm bcm_sn4 = {
1545 .name = "SN4",
1546 .keepalive = false,
1547 .num_nodes = 1,
1548 .nodes = { &xs_qdss_stm },
1549};
1550
1551static struct qcom_icc_bcm bcm_sn5 = {
1552 .name = "SN5",
1553 .keepalive = false,
1554 .num_nodes = 1,
1555 .nodes = { &xm_pcie3_0 },
1556};
1557
1558static struct qcom_icc_bcm bcm_sn6 = {
1559 .name = "SN6",
1560 .keepalive = false,
1561 .num_nodes = 1,
1562 .nodes = { &xm_pcie3_1 },
1563};
1564
1565static struct qcom_icc_bcm bcm_sn7 = {
1566 .name = "SN7",
1567 .keepalive = false,
1568 .num_nodes = 1,
1569 .nodes = { &qnm_aggre1_noc },
1570};
1571
1572static struct qcom_icc_bcm bcm_sn8 = {
1573 .name = "SN8",
1574 .keepalive = false,
1575 .num_nodes = 1,
1576 .nodes = { &qnm_aggre2_noc },
1577};
1578
1579static struct qcom_icc_bcm bcm_sn14 = {
1580 .name = "SN14",
1581 .keepalive = false,
1582 .num_nodes = 1,
1583 .nodes = { &qns_pcie_mem_noc },
1584};
1585
1586static struct qcom_icc_bcm bcm_acv_disp = {
1587 .name = "ACV",
1588 .keepalive = false,
1589 .num_nodes = 1,
1590 .nodes = { &ebi_disp },
1591};
1592
1593static struct qcom_icc_bcm bcm_mc0_disp = {
1594 .name = "MC0",
1595 .keepalive = false,
1596 .num_nodes = 1,
1597 .nodes = { &ebi_disp },
1598};
1599
1600static struct qcom_icc_bcm bcm_mm0_disp = {
1601 .name = "MM0",
1602 .keepalive = false,
1603 .num_nodes = 1,
1604 .nodes = { &qns_mem_noc_hf_disp },
1605};
1606
1607static struct qcom_icc_bcm bcm_mm1_disp = {
1608 .name = "MM1",
1609 .keepalive = false,
1610 .num_nodes = 2,
1611 .nodes = { &qxm_mdp0_disp, &qxm_mdp1_disp },
1612};
1613
1614static struct qcom_icc_bcm bcm_mm4_disp = {
1615 .name = "MM4",
1616 .keepalive = false,
1617 .num_nodes = 1,
1618 .nodes = { &qns_mem_noc_sf_disp },
1619};
1620
1621static struct qcom_icc_bcm bcm_mm5_disp = {
1622 .name = "MM5",
1623 .keepalive = false,
1624 .num_nodes = 1,
1625 .nodes = { &qxm_rot_disp },
1626};
1627
1628static struct qcom_icc_bcm bcm_sh0_disp = {
1629 .name = "SH0",
1630 .keepalive = false,
1631 .num_nodes = 1,
1632 .nodes = { &qns_llcc_disp },
1633};
1634
1635static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
1636};
1637
1638static struct qcom_icc_node * const aggre1_noc_nodes[] = {
1639 [MASTER_QSPI_0] = &qhm_qspi,
1640 [MASTER_QUP_1] = &qhm_qup1,
1641 [MASTER_A1NOC_CFG] = &qnm_a1noc_cfg,
1642 [MASTER_SDCC_4] = &xm_sdc4,
1643 [MASTER_UFS_MEM] = &xm_ufs_mem,
1644 [MASTER_USB3_0] = &xm_usb3_0,
1645 [MASTER_USB3_1] = &xm_usb3_1,
1646 [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
1647 [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc,
1648};
1649
1650static const struct qcom_icc_desc sm8350_aggre1_noc = {
1651 .nodes = aggre1_noc_nodes,
1652 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
1653 .bcms = aggre1_noc_bcms,
1654 .num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
1655};
1656
1657static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {
1658 &bcm_ce0,
1659 &bcm_sn5,
1660 &bcm_sn6,
1661 &bcm_sn14,
1662};
1663
1664static struct qcom_icc_node * const aggre2_noc_nodes[] = {
1665 [MASTER_QDSS_BAM] = &qhm_qdss_bam,
1666 [MASTER_QUP_0] = &qhm_qup0,
1667 [MASTER_QUP_2] = &qhm_qup2,
1668 [MASTER_A2NOC_CFG] = &qnm_a2noc_cfg,
1669 [MASTER_CRYPTO] = &qxm_crypto,
1670 [MASTER_IPA] = &qxm_ipa,
1671 [MASTER_PCIE_0] = &xm_pcie3_0,
1672 [MASTER_PCIE_1] = &xm_pcie3_1,
1673 [MASTER_QDSS_ETR] = &xm_qdss_etr,
1674 [MASTER_SDCC_2] = &xm_sdc2,
1675 [MASTER_UFS_CARD] = &xm_ufs_card,
1676 [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc,
1677 [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc,
1678 [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc,
1679};
1680
1681static const struct qcom_icc_desc sm8350_aggre2_noc = {
1682 .nodes = aggre2_noc_nodes,
1683 .num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
1684 .bcms = aggre2_noc_bcms,
1685 .num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
1686};
1687
1688static struct qcom_icc_bcm * const config_noc_bcms[] = {
1689 &bcm_cn0,
1690 &bcm_cn1,
1691 &bcm_cn2,
1692 &bcm_sn3,
1693 &bcm_sn4,
1694};
1695
1696static struct qcom_icc_node * const config_noc_nodes[] = {
1697 [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc,
1698 [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie,
1699 [MASTER_QDSS_DAP] = &xm_qdss_dap,
1700 [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0,
1701 [SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1,
1702 [SLAVE_AOSS] = &qhs_aoss,
1703 [SLAVE_APPSS] = &qhs_apss,
1704 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
1705 [SLAVE_CLK_CTL] = &qhs_clk_ctl,
1706 [SLAVE_CDSP_CFG] = &qhs_compute_cfg,
1707 [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
1708 [SLAVE_RBCPR_MMCX_CFG] = &qhs_cpr_mmcx,
1709 [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx,
1710 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
1711 [SLAVE_CX_RDPM] = &qhs_cx_rdpm,
1712 [SLAVE_DCC_CFG] = &qhs_dcc_cfg,
1713 [SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
1714 [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg,
1715 [SLAVE_HWKM] = &qhs_hwkm,
1716 [SLAVE_IMEM_CFG] = &qhs_imem_cfg,
1717 [SLAVE_IPA_CFG] = &qhs_ipa,
1718 [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router,
1719 [SLAVE_LPASS] = &qhs_lpass_cfg,
1720 [SLAVE_CNOC_MSS] = &qhs_mss_cfg,
1721 [SLAVE_MX_RDPM] = &qhs_mx_rdpm,
1722 [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg,
1723 [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg,
1724 [SLAVE_PDM] = &qhs_pdm,
1725 [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
1726 [SLAVE_PKA_WRAPPER_CFG] = &qhs_pka_wrapper_cfg,
1727 [SLAVE_PMU_WRAPPER_CFG] = &qhs_pmu_wrapper_cfg,
1728 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
1729 [SLAVE_QSPI_0] = &qhs_qspi,
1730 [SLAVE_QUP_0] = &qhs_qup0,
1731 [SLAVE_QUP_1] = &qhs_qup1,
1732 [SLAVE_QUP_2] = &qhs_qup2,
1733 [SLAVE_SDCC_2] = &qhs_sdc2,
1734 [SLAVE_SDCC_4] = &qhs_sdc4,
1735 [SLAVE_SECURITY] = &qhs_security,
1736 [SLAVE_SPSS_CFG] = &qhs_spss_cfg,
1737 [SLAVE_TCSR] = &qhs_tcsr,
1738 [SLAVE_TLMM] = &qhs_tlmm,
1739 [SLAVE_UFS_CARD_CFG] = &qhs_ufs_card_cfg,
1740 [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
1741 [SLAVE_USB3_0] = &qhs_usb3_0,
1742 [SLAVE_USB3_1] = &qhs_usb3_1,
1743 [SLAVE_VENUS_CFG] = &qhs_venus_cfg,
1744 [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
1745 [SLAVE_A1NOC_CFG] = &qns_a1_noc_cfg,
1746 [SLAVE_A2NOC_CFG] = &qns_a2_noc_cfg,
1747 [SLAVE_DDRSS_CFG] = &qns_ddrss_cfg,
1748 [SLAVE_CNOC_MNOC_CFG] = &qns_mnoc_cfg,
1749 [SLAVE_SNOC_CFG] = &qns_snoc_cfg,
1750 [SLAVE_BOOT_IMEM] = &qxs_boot_imem,
1751 [SLAVE_IMEM] = &qxs_imem,
1752 [SLAVE_PIMEM] = &qxs_pimem,
1753 [SLAVE_SERVICE_CNOC] = &srvc_cnoc,
1754 [SLAVE_PCIE_0] = &xs_pcie_0,
1755 [SLAVE_PCIE_1] = &xs_pcie_1,
1756 [SLAVE_QDSS_STM] = &xs_qdss_stm,
1757 [SLAVE_TCU] = &xs_sys_tcu_cfg,
1758};
1759
1760static const struct qcom_icc_desc sm8350_config_noc = {
1761 .nodes = config_noc_nodes,
1762 .num_nodes = ARRAY_SIZE(config_noc_nodes),
1763 .bcms = config_noc_bcms,
1764 .num_bcms = ARRAY_SIZE(config_noc_bcms),
1765};
1766
1767static struct qcom_icc_bcm * const dc_noc_bcms[] = {
1768};
1769
1770static struct qcom_icc_node * const dc_noc_nodes[] = {
1771 [MASTER_CNOC_DC_NOC] = &qnm_cnoc_dc_noc,
1772 [SLAVE_LLCC_CFG] = &qhs_llcc,
1773 [SLAVE_GEM_NOC_CFG] = &qns_gemnoc,
1774};
1775
1776static const struct qcom_icc_desc sm8350_dc_noc = {
1777 .nodes = dc_noc_nodes,
1778 .num_nodes = ARRAY_SIZE(dc_noc_nodes),
1779 .bcms = dc_noc_bcms,
1780 .num_bcms = ARRAY_SIZE(dc_noc_bcms),
1781};
1782
1783static struct qcom_icc_bcm * const gem_noc_bcms[] = {
1784 &bcm_sh0,
1785 &bcm_sh2,
1786 &bcm_sh3,
1787 &bcm_sh4,
1788 &bcm_sh0_disp,
1789};
1790
1791static struct qcom_icc_node * const gem_noc_nodes[] = {
1792 [MASTER_GPU_TCU] = &alm_gpu_tcu,
1793 [MASTER_SYS_TCU] = &alm_sys_tcu,
1794 [MASTER_APPSS_PROC] = &chm_apps,
1795 [MASTER_COMPUTE_NOC] = &qnm_cmpnoc,
1796 [MASTER_GEM_NOC_CFG] = &qnm_gemnoc_cfg,
1797 [MASTER_GFX3D] = &qnm_gpu,
1798 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
1799 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
1800 [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie,
1801 [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
1802 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
1803 [SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg,
1804 [SLAVE_MCDMA_MS_MPU_CFG] = &qhs_modem_ms_mpu_cfg,
1805 [SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc,
1806 [SLAVE_LLCC] = &qns_llcc,
1807 [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie,
1808 [SLAVE_SERVICE_GEM_NOC_1] = &srvc_even_gemnoc,
1809 [SLAVE_SERVICE_GEM_NOC_2] = &srvc_odd_gemnoc,
1810 [SLAVE_SERVICE_GEM_NOC] = &srvc_sys_gemnoc,
1811 [MASTER_MNOC_HF_MEM_NOC_DISP] = &qnm_mnoc_hf_disp,
1812 [MASTER_MNOC_SF_MEM_NOC_DISP] = &qnm_mnoc_sf_disp,
1813 [SLAVE_LLCC_DISP] = &qns_llcc_disp,
1814};
1815
1816static const struct qcom_icc_desc sm8350_gem_noc = {
1817 .nodes = gem_noc_nodes,
1818 .num_nodes = ARRAY_SIZE(gem_noc_nodes),
1819 .bcms = gem_noc_bcms,
1820 .num_bcms = ARRAY_SIZE(gem_noc_bcms),
1821};
1822
1823static struct qcom_icc_bcm * const lpass_ag_noc_bcms[] = {
1824};
1825
1826static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
1827 [MASTER_CNOC_LPASS_AG_NOC] = &qhm_config_noc,
1828 [SLAVE_LPASS_CORE_CFG] = &qhs_lpass_core,
1829 [SLAVE_LPASS_LPI_CFG] = &qhs_lpass_lpi,
1830 [SLAVE_LPASS_MPU_CFG] = &qhs_lpass_mpu,
1831 [SLAVE_LPASS_TOP_CFG] = &qhs_lpass_top,
1832 [SLAVE_SERVICES_LPASS_AML_NOC] = &srvc_niu_aml_noc,
1833 [SLAVE_SERVICE_LPASS_AG_NOC] = &srvc_niu_lpass_agnoc,
1834};
1835
1836static const struct qcom_icc_desc sm8350_lpass_ag_noc = {
1837 .nodes = lpass_ag_noc_nodes,
1838 .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
1839 .bcms = lpass_ag_noc_bcms,
1840 .num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms),
1841};
1842
1843static struct qcom_icc_bcm * const mc_virt_bcms[] = {
1844 &bcm_acv,
1845 &bcm_mc0,
1846 &bcm_acv_disp,
1847 &bcm_mc0_disp,
1848};
1849
1850static struct qcom_icc_node * const mc_virt_nodes[] = {
1851 [MASTER_LLCC] = &llcc_mc,
1852 [SLAVE_EBI1] = &ebi,
1853 [MASTER_LLCC_DISP] = &llcc_mc_disp,
1854 [SLAVE_EBI1_DISP] = &ebi_disp,
1855};
1856
1857static const struct qcom_icc_desc sm8350_mc_virt = {
1858 .nodes = mc_virt_nodes,
1859 .num_nodes = ARRAY_SIZE(mc_virt_nodes),
1860 .bcms = mc_virt_bcms,
1861 .num_bcms = ARRAY_SIZE(mc_virt_bcms),
1862};
1863
1864static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
1865 &bcm_mm0,
1866 &bcm_mm1,
1867 &bcm_mm4,
1868 &bcm_mm5,
1869 &bcm_mm0_disp,
1870 &bcm_mm1_disp,
1871 &bcm_mm4_disp,
1872 &bcm_mm5_disp,
1873};
1874
1875static struct qcom_icc_node * const mmss_noc_nodes[] = {
1876 [MASTER_CAMNOC_HF] = &qnm_camnoc_hf,
1877 [MASTER_CAMNOC_ICP] = &qnm_camnoc_icp,
1878 [MASTER_CAMNOC_SF] = &qnm_camnoc_sf,
1879 [MASTER_CNOC_MNOC_CFG] = &qnm_mnoc_cfg,
1880 [MASTER_VIDEO_P0] = &qnm_video0,
1881 [MASTER_VIDEO_P1] = &qnm_video1,
1882 [MASTER_VIDEO_PROC] = &qnm_video_cvp,
1883 [MASTER_MDP0] = &qxm_mdp0,
1884 [MASTER_MDP1] = &qxm_mdp1,
1885 [MASTER_ROTATOR] = &qxm_rot,
1886 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
1887 [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
1888 [SLAVE_SERVICE_MNOC] = &srvc_mnoc,
1889 [MASTER_MDP0_DISP] = &qxm_mdp0_disp,
1890 [MASTER_MDP1_DISP] = &qxm_mdp1_disp,
1891 [MASTER_ROTATOR_DISP] = &qxm_rot_disp,
1892 [SLAVE_MNOC_HF_MEM_NOC_DISP] = &qns_mem_noc_hf_disp,
1893 [SLAVE_MNOC_SF_MEM_NOC_DISP] = &qns_mem_noc_sf_disp,
1894};
1895
1896static const struct qcom_icc_desc sm8350_mmss_noc = {
1897 .nodes = mmss_noc_nodes,
1898 .num_nodes = ARRAY_SIZE(mmss_noc_nodes),
1899 .bcms = mmss_noc_bcms,
1900 .num_bcms = ARRAY_SIZE(mmss_noc_bcms),
1901};
1902
1903static struct qcom_icc_bcm * const nsp_noc_bcms[] = {
1904 &bcm_co0,
1905 &bcm_co3,
1906};
1907
1908static struct qcom_icc_node * const nsp_noc_nodes[] = {
1909 [MASTER_CDSP_NOC_CFG] = &qhm_nsp_noc_config,
1910 [MASTER_CDSP_PROC] = &qxm_nsp,
1911 [SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc,
1912 [SLAVE_SERVICE_NSP_NOC] = &service_nsp_noc,
1913};
1914
1915static const struct qcom_icc_desc sm8350_compute_noc = {
1916 .nodes = nsp_noc_nodes,
1917 .num_nodes = ARRAY_SIZE(nsp_noc_nodes),
1918 .bcms = nsp_noc_bcms,
1919 .num_bcms = ARRAY_SIZE(nsp_noc_bcms),
1920};
1921
1922static struct qcom_icc_bcm * const system_noc_bcms[] = {
1923 &bcm_sn0,
1924 &bcm_sn2,
1925 &bcm_sn7,
1926 &bcm_sn8,
1927};
1928
1929static struct qcom_icc_node * const system_noc_nodes[] = {
1930 [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc,
1931 [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc,
1932 [MASTER_SNOC_CFG] = &qnm_snoc_cfg,
1933 [MASTER_PIMEM] = &qxm_pimem,
1934 [MASTER_GIC] = &xm_gic,
1935 [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc,
1936 [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
1937 [SLAVE_SERVICE_SNOC] = &srvc_snoc,
1938};
1939
1940static const struct qcom_icc_desc sm8350_system_noc = {
1941 .nodes = system_noc_nodes,
1942 .num_nodes = ARRAY_SIZE(system_noc_nodes),
1943 .bcms = system_noc_bcms,
1944 .num_bcms = ARRAY_SIZE(system_noc_bcms),
1945};
1946
1947static const struct of_device_id qnoc_of_match[] = {
1948 { .compatible = "qcom,sm8350-aggre1-noc", .data = &sm8350_aggre1_noc},
1949 { .compatible = "qcom,sm8350-aggre2-noc", .data = &sm8350_aggre2_noc},
1950 { .compatible = "qcom,sm8350-config-noc", .data = &sm8350_config_noc},
1951 { .compatible = "qcom,sm8350-dc-noc", .data = &sm8350_dc_noc},
1952 { .compatible = "qcom,sm8350-gem-noc", .data = &sm8350_gem_noc},
1953 { .compatible = "qcom,sm8350-lpass-ag-noc", .data = &sm8350_lpass_ag_noc},
1954 { .compatible = "qcom,sm8350-mc-virt", .data = &sm8350_mc_virt},
1955 { .compatible = "qcom,sm8350-mmss-noc", .data = &sm8350_mmss_noc},
1956 { .compatible = "qcom,sm8350-compute-noc", .data = &sm8350_compute_noc},
1957 { .compatible = "qcom,sm8350-system-noc", .data = &sm8350_system_noc},
1958 { }
1959};
1960MODULE_DEVICE_TABLE(of, qnoc_of_match);
1961
1962static struct platform_driver qnoc_driver = {
1963 .probe = qcom_icc_rpmh_probe,
1964 .remove_new = qcom_icc_rpmh_remove,
1965 .driver = {
1966 .name = "qnoc-sm8350",
1967 .of_match_table = qnoc_of_match,
1968 },
1969};
1970module_platform_driver(qnoc_driver);
1971
1972MODULE_DESCRIPTION("SM8350 NoC driver");
1973MODULE_LICENSE("GPL v2");
1974

source code of linux/drivers/interconnect/qcom/sm8350.c