1 | /* |
2 | * J-Core SoC AIC driver |
3 | * |
4 | * Copyright (C) 2015-2016 Smart Energy Instruments, Inc. |
5 | * |
6 | * This file is subject to the terms and conditions of the GNU General Public |
7 | * License. See the file "COPYING" in the main directory of this archive |
8 | * for more details. |
9 | */ |
10 | |
11 | #include <linux/irq.h> |
12 | #include <linux/io.h> |
13 | #include <linux/irqchip.h> |
14 | #include <linux/irqdomain.h> |
15 | #include <linux/cpu.h> |
16 | #include <linux/of.h> |
17 | #include <linux/of_address.h> |
18 | #include <linux/of_irq.h> |
19 | |
20 | #define JCORE_AIC_MAX_HWIRQ 127 |
21 | #define JCORE_AIC1_MIN_HWIRQ 16 |
22 | #define JCORE_AIC2_MIN_HWIRQ 64 |
23 | |
24 | #define JCORE_AIC1_INTPRI_REG 8 |
25 | |
26 | static struct irq_chip jcore_aic; |
27 | |
28 | /* |
29 | * The J-Core AIC1 and AIC2 are cpu-local interrupt controllers and do |
30 | * not distinguish or use distinct irq number ranges for per-cpu event |
31 | * interrupts (timer, IPI). Since information to determine whether a |
32 | * particular irq number should be treated as per-cpu is not available |
33 | * at mapping time, we use a wrapper handler function which chooses |
34 | * the right handler at runtime based on whether IRQF_PERCPU was used |
35 | * when requesting the irq. |
36 | */ |
37 | |
38 | static void handle_jcore_irq(struct irq_desc *desc) |
39 | { |
40 | if (irqd_is_per_cpu(d: irq_desc_get_irq_data(desc))) |
41 | handle_percpu_irq(desc); |
42 | else |
43 | handle_simple_irq(desc); |
44 | } |
45 | |
46 | static int jcore_aic_irqdomain_map(struct irq_domain *d, unsigned int irq, |
47 | irq_hw_number_t hwirq) |
48 | { |
49 | struct irq_chip *aic = d->host_data; |
50 | |
51 | irq_set_chip_and_handler(irq, chip: aic, handle: handle_jcore_irq); |
52 | |
53 | return 0; |
54 | } |
55 | |
56 | static const struct irq_domain_ops jcore_aic_irqdomain_ops = { |
57 | .map = jcore_aic_irqdomain_map, |
58 | .xlate = irq_domain_xlate_onecell, |
59 | }; |
60 | |
61 | static void noop(struct irq_data *data) |
62 | { |
63 | } |
64 | |
65 | static int __init aic_irq_of_init(struct device_node *node, |
66 | struct device_node *parent) |
67 | { |
68 | unsigned min_irq = JCORE_AIC2_MIN_HWIRQ; |
69 | unsigned dom_sz = JCORE_AIC_MAX_HWIRQ+1; |
70 | struct irq_domain *domain; |
71 | int ret; |
72 | |
73 | pr_info("Initializing J-Core AIC\n" ); |
74 | |
75 | /* AIC1 needs priority initialization to receive interrupts. */ |
76 | if (of_device_is_compatible(device: node, "jcore,aic1" )) { |
77 | unsigned cpu; |
78 | |
79 | for_each_present_cpu(cpu) { |
80 | void __iomem *base = of_iomap(node, index: cpu); |
81 | |
82 | if (!base) { |
83 | pr_err("Unable to map AIC for cpu %u\n" , cpu); |
84 | return -ENOMEM; |
85 | } |
86 | __raw_writel(val: 0xffffffff, addr: base + JCORE_AIC1_INTPRI_REG); |
87 | iounmap(addr: base); |
88 | } |
89 | min_irq = JCORE_AIC1_MIN_HWIRQ; |
90 | } |
91 | |
92 | /* |
93 | * The irq chip framework requires either mask/unmask or enable/disable |
94 | * function pointers to be provided, but the hardware does not have any |
95 | * such mechanism; the only interrupt masking is at the cpu level and |
96 | * it affects all interrupts. We provide dummy mask/unmask. The hardware |
97 | * handles all interrupt control and clears pending status when the cpu |
98 | * accepts the interrupt. |
99 | */ |
100 | jcore_aic.irq_mask = noop; |
101 | jcore_aic.irq_unmask = noop; |
102 | jcore_aic.name = "AIC" ; |
103 | |
104 | ret = irq_alloc_descs(-1, min_irq, dom_sz - min_irq, |
105 | of_node_to_nid(node)); |
106 | |
107 | if (ret < 0) |
108 | return ret; |
109 | |
110 | domain = irq_domain_add_legacy(of_node: node, size: dom_sz - min_irq, first_irq: min_irq, first_hwirq: min_irq, |
111 | ops: &jcore_aic_irqdomain_ops, |
112 | host_data: &jcore_aic); |
113 | if (!domain) |
114 | return -ENOMEM; |
115 | |
116 | return 0; |
117 | } |
118 | |
119 | IRQCHIP_DECLARE(jcore_aic2, "jcore,aic2" , aic_irq_of_init); |
120 | IRQCHIP_DECLARE(jcore_aic1, "jcore,aic1" , aic_irq_of_init); |
121 | |