1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * Copyright (C) 2017 SiFive |
4 | * Copyright (C) 2018 Christoph Hellwig |
5 | */ |
6 | #define pr_fmt(fmt) "plic: " fmt |
7 | #include <linux/cpu.h> |
8 | #include <linux/interrupt.h> |
9 | #include <linux/io.h> |
10 | #include <linux/irq.h> |
11 | #include <linux/irqchip.h> |
12 | #include <linux/irqchip/chained_irq.h> |
13 | #include <linux/irqdomain.h> |
14 | #include <linux/module.h> |
15 | #include <linux/of.h> |
16 | #include <linux/of_address.h> |
17 | #include <linux/of_irq.h> |
18 | #include <linux/platform_device.h> |
19 | #include <linux/spinlock.h> |
20 | #include <linux/syscore_ops.h> |
21 | #include <asm/smp.h> |
22 | |
23 | /* |
24 | * This driver implements a version of the RISC-V PLIC with the actual layout |
25 | * specified in chapter 8 of the SiFive U5 Coreplex Series Manual: |
26 | * |
27 | * https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf |
28 | * |
29 | * The largest number supported by devices marked as 'sifive,plic-1.0.0', is |
30 | * 1024, of which device 0 is defined as non-existent by the RISC-V Privileged |
31 | * Spec. |
32 | */ |
33 | |
34 | #define MAX_DEVICES 1024 |
35 | #define MAX_CONTEXTS 15872 |
36 | |
37 | /* |
38 | * Each interrupt source has a priority register associated with it. |
39 | * We always hardwire it to one in Linux. |
40 | */ |
41 | #define PRIORITY_BASE 0 |
42 | #define PRIORITY_PER_ID 4 |
43 | |
44 | /* |
45 | * Each hart context has a vector of interrupt enable bits associated with it. |
46 | * There's one bit for each interrupt source. |
47 | */ |
48 | #define CONTEXT_ENABLE_BASE 0x2000 |
49 | #define CONTEXT_ENABLE_SIZE 0x80 |
50 | |
51 | /* |
52 | * Each hart context has a set of control registers associated with it. Right |
53 | * now there's only two: a source priority threshold over which the hart will |
54 | * take an interrupt, and a register to claim interrupts. |
55 | */ |
56 | #define CONTEXT_BASE 0x200000 |
57 | #define CONTEXT_SIZE 0x1000 |
58 | #define CONTEXT_THRESHOLD 0x00 |
59 | #define CONTEXT_CLAIM 0x04 |
60 | |
61 | #define PLIC_DISABLE_THRESHOLD 0x7 |
62 | #define PLIC_ENABLE_THRESHOLD 0 |
63 | |
64 | #define PLIC_QUIRK_EDGE_INTERRUPT 0 |
65 | |
66 | struct plic_priv { |
67 | struct cpumask lmask; |
68 | struct irq_domain *irqdomain; |
69 | void __iomem *regs; |
70 | unsigned long plic_quirks; |
71 | unsigned int nr_irqs; |
72 | unsigned long *prio_save; |
73 | }; |
74 | |
75 | struct plic_handler { |
76 | bool present; |
77 | void __iomem *hart_base; |
78 | /* |
79 | * Protect mask operations on the registers given that we can't |
80 | * assume atomic memory operations work on them. |
81 | */ |
82 | raw_spinlock_t enable_lock; |
83 | void __iomem *enable_base; |
84 | u32 *enable_save; |
85 | struct plic_priv *priv; |
86 | }; |
87 | static int plic_parent_irq __ro_after_init; |
88 | static bool plic_cpuhp_setup_done __ro_after_init; |
89 | static DEFINE_PER_CPU(struct plic_handler, plic_handlers); |
90 | |
91 | static int plic_irq_set_type(struct irq_data *d, unsigned int type); |
92 | |
93 | static void __plic_toggle(void __iomem *enable_base, int hwirq, int enable) |
94 | { |
95 | u32 __iomem *reg = enable_base + (hwirq / 32) * sizeof(u32); |
96 | u32 hwirq_mask = 1 << (hwirq % 32); |
97 | |
98 | if (enable) |
99 | writel(readl(addr: reg) | hwirq_mask, addr: reg); |
100 | else |
101 | writel(readl(addr: reg) & ~hwirq_mask, addr: reg); |
102 | } |
103 | |
104 | static void plic_toggle(struct plic_handler *handler, int hwirq, int enable) |
105 | { |
106 | raw_spin_lock(&handler->enable_lock); |
107 | __plic_toggle(enable_base: handler->enable_base, hwirq, enable); |
108 | raw_spin_unlock(&handler->enable_lock); |
109 | } |
110 | |
111 | static inline void plic_irq_toggle(const struct cpumask *mask, |
112 | struct irq_data *d, int enable) |
113 | { |
114 | int cpu; |
115 | |
116 | for_each_cpu(cpu, mask) { |
117 | struct plic_handler *handler = per_cpu_ptr(&plic_handlers, cpu); |
118 | |
119 | plic_toggle(handler, hwirq: d->hwirq, enable); |
120 | } |
121 | } |
122 | |
123 | static void plic_irq_enable(struct irq_data *d) |
124 | { |
125 | plic_irq_toggle(mask: irq_data_get_effective_affinity_mask(d), d, enable: 1); |
126 | } |
127 | |
128 | static void plic_irq_disable(struct irq_data *d) |
129 | { |
130 | plic_irq_toggle(mask: irq_data_get_effective_affinity_mask(d), d, enable: 0); |
131 | } |
132 | |
133 | static void plic_irq_unmask(struct irq_data *d) |
134 | { |
135 | struct plic_priv *priv = irq_data_get_irq_chip_data(d); |
136 | |
137 | writel(val: 1, addr: priv->regs + PRIORITY_BASE + d->hwirq * PRIORITY_PER_ID); |
138 | } |
139 | |
140 | static void plic_irq_mask(struct irq_data *d) |
141 | { |
142 | struct plic_priv *priv = irq_data_get_irq_chip_data(d); |
143 | |
144 | writel(val: 0, addr: priv->regs + PRIORITY_BASE + d->hwirq * PRIORITY_PER_ID); |
145 | } |
146 | |
147 | static void plic_irq_eoi(struct irq_data *d) |
148 | { |
149 | struct plic_handler *handler = this_cpu_ptr(&plic_handlers); |
150 | |
151 | writel(val: d->hwirq, addr: handler->hart_base + CONTEXT_CLAIM); |
152 | } |
153 | |
154 | #ifdef CONFIG_SMP |
155 | static int plic_set_affinity(struct irq_data *d, |
156 | const struct cpumask *mask_val, bool force) |
157 | { |
158 | unsigned int cpu; |
159 | struct cpumask amask; |
160 | struct plic_priv *priv = irq_data_get_irq_chip_data(d); |
161 | |
162 | cpumask_and(dstp: &amask, src1p: &priv->lmask, src2p: mask_val); |
163 | |
164 | if (force) |
165 | cpu = cpumask_first(srcp: &amask); |
166 | else |
167 | cpu = cpumask_any_and(&amask, cpu_online_mask); |
168 | |
169 | if (cpu >= nr_cpu_ids) |
170 | return -EINVAL; |
171 | |
172 | plic_irq_disable(d); |
173 | |
174 | irq_data_update_effective_affinity(d, cpumask_of(cpu)); |
175 | |
176 | if (!irqd_irq_disabled(d)) |
177 | plic_irq_enable(d); |
178 | |
179 | return IRQ_SET_MASK_OK_DONE; |
180 | } |
181 | #endif |
182 | |
183 | static struct irq_chip plic_edge_chip = { |
184 | .name = "SiFive PLIC" , |
185 | .irq_enable = plic_irq_enable, |
186 | .irq_disable = plic_irq_disable, |
187 | .irq_ack = plic_irq_eoi, |
188 | .irq_mask = plic_irq_mask, |
189 | .irq_unmask = plic_irq_unmask, |
190 | #ifdef CONFIG_SMP |
191 | .irq_set_affinity = plic_set_affinity, |
192 | #endif |
193 | .irq_set_type = plic_irq_set_type, |
194 | .flags = IRQCHIP_SKIP_SET_WAKE | |
195 | IRQCHIP_AFFINITY_PRE_STARTUP, |
196 | }; |
197 | |
198 | static struct irq_chip plic_chip = { |
199 | .name = "SiFive PLIC" , |
200 | .irq_enable = plic_irq_enable, |
201 | .irq_disable = plic_irq_disable, |
202 | .irq_mask = plic_irq_mask, |
203 | .irq_unmask = plic_irq_unmask, |
204 | .irq_eoi = plic_irq_eoi, |
205 | #ifdef CONFIG_SMP |
206 | .irq_set_affinity = plic_set_affinity, |
207 | #endif |
208 | .irq_set_type = plic_irq_set_type, |
209 | .flags = IRQCHIP_SKIP_SET_WAKE | |
210 | IRQCHIP_AFFINITY_PRE_STARTUP, |
211 | }; |
212 | |
213 | static int plic_irq_set_type(struct irq_data *d, unsigned int type) |
214 | { |
215 | struct plic_priv *priv = irq_data_get_irq_chip_data(d); |
216 | |
217 | if (!test_bit(PLIC_QUIRK_EDGE_INTERRUPT, &priv->plic_quirks)) |
218 | return IRQ_SET_MASK_OK_NOCOPY; |
219 | |
220 | switch (type) { |
221 | case IRQ_TYPE_EDGE_RISING: |
222 | irq_set_chip_handler_name_locked(data: d, chip: &plic_edge_chip, |
223 | handler: handle_edge_irq, NULL); |
224 | break; |
225 | case IRQ_TYPE_LEVEL_HIGH: |
226 | irq_set_chip_handler_name_locked(data: d, chip: &plic_chip, |
227 | handler: handle_fasteoi_irq, NULL); |
228 | break; |
229 | default: |
230 | return -EINVAL; |
231 | } |
232 | |
233 | return IRQ_SET_MASK_OK; |
234 | } |
235 | |
236 | static int plic_irq_suspend(void) |
237 | { |
238 | unsigned int i, cpu; |
239 | u32 __iomem *reg; |
240 | struct plic_priv *priv; |
241 | |
242 | priv = per_cpu_ptr(&plic_handlers, smp_processor_id())->priv; |
243 | |
244 | for (i = 0; i < priv->nr_irqs; i++) |
245 | if (readl(addr: priv->regs + PRIORITY_BASE + i * PRIORITY_PER_ID)) |
246 | __set_bit(i, priv->prio_save); |
247 | else |
248 | __clear_bit(i, priv->prio_save); |
249 | |
250 | for_each_cpu(cpu, cpu_present_mask) { |
251 | struct plic_handler *handler = per_cpu_ptr(&plic_handlers, cpu); |
252 | |
253 | if (!handler->present) |
254 | continue; |
255 | |
256 | raw_spin_lock(&handler->enable_lock); |
257 | for (i = 0; i < DIV_ROUND_UP(priv->nr_irqs, 32); i++) { |
258 | reg = handler->enable_base + i * sizeof(u32); |
259 | handler->enable_save[i] = readl(addr: reg); |
260 | } |
261 | raw_spin_unlock(&handler->enable_lock); |
262 | } |
263 | |
264 | return 0; |
265 | } |
266 | |
267 | static void plic_irq_resume(void) |
268 | { |
269 | unsigned int i, index, cpu; |
270 | u32 __iomem *reg; |
271 | struct plic_priv *priv; |
272 | |
273 | priv = per_cpu_ptr(&plic_handlers, smp_processor_id())->priv; |
274 | |
275 | for (i = 0; i < priv->nr_irqs; i++) { |
276 | index = BIT_WORD(i); |
277 | writel(val: (priv->prio_save[index] & BIT_MASK(i)) ? 1 : 0, |
278 | addr: priv->regs + PRIORITY_BASE + i * PRIORITY_PER_ID); |
279 | } |
280 | |
281 | for_each_cpu(cpu, cpu_present_mask) { |
282 | struct plic_handler *handler = per_cpu_ptr(&plic_handlers, cpu); |
283 | |
284 | if (!handler->present) |
285 | continue; |
286 | |
287 | raw_spin_lock(&handler->enable_lock); |
288 | for (i = 0; i < DIV_ROUND_UP(priv->nr_irqs, 32); i++) { |
289 | reg = handler->enable_base + i * sizeof(u32); |
290 | writel(val: handler->enable_save[i], addr: reg); |
291 | } |
292 | raw_spin_unlock(&handler->enable_lock); |
293 | } |
294 | } |
295 | |
296 | static struct syscore_ops plic_irq_syscore_ops = { |
297 | .suspend = plic_irq_suspend, |
298 | .resume = plic_irq_resume, |
299 | }; |
300 | |
301 | static int plic_irqdomain_map(struct irq_domain *d, unsigned int irq, |
302 | irq_hw_number_t hwirq) |
303 | { |
304 | struct plic_priv *priv = d->host_data; |
305 | |
306 | irq_domain_set_info(domain: d, virq: irq, hwirq, chip: &plic_chip, chip_data: d->host_data, |
307 | handler: handle_fasteoi_irq, NULL, NULL); |
308 | irq_set_noprobe(irq); |
309 | irq_set_affinity(irq, cpumask: &priv->lmask); |
310 | return 0; |
311 | } |
312 | |
313 | static int plic_irq_domain_translate(struct irq_domain *d, |
314 | struct irq_fwspec *fwspec, |
315 | unsigned long *hwirq, |
316 | unsigned int *type) |
317 | { |
318 | struct plic_priv *priv = d->host_data; |
319 | |
320 | if (test_bit(PLIC_QUIRK_EDGE_INTERRUPT, &priv->plic_quirks)) |
321 | return irq_domain_translate_twocell(d, fwspec, out_hwirq: hwirq, out_type: type); |
322 | |
323 | return irq_domain_translate_onecell(d, fwspec, out_hwirq: hwirq, out_type: type); |
324 | } |
325 | |
326 | static int plic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, |
327 | unsigned int nr_irqs, void *arg) |
328 | { |
329 | int i, ret; |
330 | irq_hw_number_t hwirq; |
331 | unsigned int type; |
332 | struct irq_fwspec *fwspec = arg; |
333 | |
334 | ret = plic_irq_domain_translate(d: domain, fwspec, hwirq: &hwirq, type: &type); |
335 | if (ret) |
336 | return ret; |
337 | |
338 | for (i = 0; i < nr_irqs; i++) { |
339 | ret = plic_irqdomain_map(d: domain, irq: virq + i, hwirq: hwirq + i); |
340 | if (ret) |
341 | return ret; |
342 | } |
343 | |
344 | return 0; |
345 | } |
346 | |
347 | static const struct irq_domain_ops plic_irqdomain_ops = { |
348 | .translate = plic_irq_domain_translate, |
349 | .alloc = plic_irq_domain_alloc, |
350 | .free = irq_domain_free_irqs_top, |
351 | }; |
352 | |
353 | /* |
354 | * Handling an interrupt is a two-step process: first you claim the interrupt |
355 | * by reading the claim register, then you complete the interrupt by writing |
356 | * that source ID back to the same claim register. This automatically enables |
357 | * and disables the interrupt, so there's nothing else to do. |
358 | */ |
359 | static void plic_handle_irq(struct irq_desc *desc) |
360 | { |
361 | struct plic_handler *handler = this_cpu_ptr(&plic_handlers); |
362 | struct irq_chip *chip = irq_desc_get_chip(desc); |
363 | void __iomem *claim = handler->hart_base + CONTEXT_CLAIM; |
364 | irq_hw_number_t hwirq; |
365 | |
366 | WARN_ON_ONCE(!handler->present); |
367 | |
368 | chained_irq_enter(chip, desc); |
369 | |
370 | while ((hwirq = readl(addr: claim))) { |
371 | int err = generic_handle_domain_irq(domain: handler->priv->irqdomain, |
372 | hwirq); |
373 | if (unlikely(err)) |
374 | pr_warn_ratelimited("can't find mapping for hwirq %lu\n" , |
375 | hwirq); |
376 | } |
377 | |
378 | chained_irq_exit(chip, desc); |
379 | } |
380 | |
381 | static void plic_set_threshold(struct plic_handler *handler, u32 threshold) |
382 | { |
383 | /* priority must be > threshold to trigger an interrupt */ |
384 | writel(val: threshold, addr: handler->hart_base + CONTEXT_THRESHOLD); |
385 | } |
386 | |
387 | static int plic_dying_cpu(unsigned int cpu) |
388 | { |
389 | if (plic_parent_irq) |
390 | disable_percpu_irq(irq: plic_parent_irq); |
391 | |
392 | return 0; |
393 | } |
394 | |
395 | static int plic_starting_cpu(unsigned int cpu) |
396 | { |
397 | struct plic_handler *handler = this_cpu_ptr(&plic_handlers); |
398 | |
399 | if (plic_parent_irq) |
400 | enable_percpu_irq(irq: plic_parent_irq, |
401 | type: irq_get_trigger_type(irq: plic_parent_irq)); |
402 | else |
403 | pr_warn("cpu%d: parent irq not available\n" , cpu); |
404 | plic_set_threshold(handler, PLIC_ENABLE_THRESHOLD); |
405 | |
406 | return 0; |
407 | } |
408 | |
409 | static int __init __plic_init(struct device_node *node, |
410 | struct device_node *parent, |
411 | unsigned long plic_quirks) |
412 | { |
413 | int error = 0, nr_contexts, nr_handlers = 0, i; |
414 | u32 nr_irqs; |
415 | struct plic_priv *priv; |
416 | struct plic_handler *handler; |
417 | unsigned int cpu; |
418 | |
419 | priv = kzalloc(size: sizeof(*priv), GFP_KERNEL); |
420 | if (!priv) |
421 | return -ENOMEM; |
422 | |
423 | priv->plic_quirks = plic_quirks; |
424 | |
425 | priv->regs = of_iomap(node, index: 0); |
426 | if (WARN_ON(!priv->regs)) { |
427 | error = -EIO; |
428 | goto out_free_priv; |
429 | } |
430 | |
431 | error = -EINVAL; |
432 | of_property_read_u32(np: node, propname: "riscv,ndev" , out_value: &nr_irqs); |
433 | if (WARN_ON(!nr_irqs)) |
434 | goto out_iounmap; |
435 | |
436 | priv->nr_irqs = nr_irqs; |
437 | |
438 | priv->prio_save = bitmap_alloc(nbits: nr_irqs, GFP_KERNEL); |
439 | if (!priv->prio_save) |
440 | goto out_free_priority_reg; |
441 | |
442 | nr_contexts = of_irq_count(dev: node); |
443 | if (WARN_ON(!nr_contexts)) |
444 | goto out_free_priority_reg; |
445 | |
446 | error = -ENOMEM; |
447 | priv->irqdomain = irq_domain_add_linear(of_node: node, size: nr_irqs + 1, |
448 | ops: &plic_irqdomain_ops, host_data: priv); |
449 | if (WARN_ON(!priv->irqdomain)) |
450 | goto out_free_priority_reg; |
451 | |
452 | for (i = 0; i < nr_contexts; i++) { |
453 | struct of_phandle_args parent; |
454 | irq_hw_number_t hwirq; |
455 | int cpu; |
456 | unsigned long hartid; |
457 | |
458 | if (of_irq_parse_one(device: node, index: i, out_irq: &parent)) { |
459 | pr_err("failed to parse parent for context %d.\n" , i); |
460 | continue; |
461 | } |
462 | |
463 | /* |
464 | * Skip contexts other than external interrupts for our |
465 | * privilege level. |
466 | */ |
467 | if (parent.args[0] != RV_IRQ_EXT) { |
468 | /* Disable S-mode enable bits if running in M-mode. */ |
469 | if (IS_ENABLED(CONFIG_RISCV_M_MODE)) { |
470 | void __iomem *enable_base = priv->regs + |
471 | CONTEXT_ENABLE_BASE + |
472 | i * CONTEXT_ENABLE_SIZE; |
473 | |
474 | for (hwirq = 1; hwirq <= nr_irqs; hwirq++) |
475 | __plic_toggle(enable_base, hwirq, enable: 0); |
476 | } |
477 | continue; |
478 | } |
479 | |
480 | error = riscv_of_parent_hartid(parent.np, &hartid); |
481 | if (error < 0) { |
482 | pr_warn("failed to parse hart ID for context %d.\n" , i); |
483 | continue; |
484 | } |
485 | |
486 | cpu = riscv_hartid_to_cpuid(hartid); |
487 | if (cpu < 0) { |
488 | pr_warn("Invalid cpuid for context %d\n" , i); |
489 | continue; |
490 | } |
491 | |
492 | /* Find parent domain and register chained handler */ |
493 | if (!plic_parent_irq && irq_find_host(node: parent.np)) { |
494 | plic_parent_irq = irq_of_parse_and_map(node, index: i); |
495 | if (plic_parent_irq) |
496 | irq_set_chained_handler(irq: plic_parent_irq, |
497 | handle: plic_handle_irq); |
498 | } |
499 | |
500 | /* |
501 | * When running in M-mode we need to ignore the S-mode handler. |
502 | * Here we assume it always comes later, but that might be a |
503 | * little fragile. |
504 | */ |
505 | handler = per_cpu_ptr(&plic_handlers, cpu); |
506 | if (handler->present) { |
507 | pr_warn("handler already present for context %d.\n" , i); |
508 | plic_set_threshold(handler, PLIC_DISABLE_THRESHOLD); |
509 | goto done; |
510 | } |
511 | |
512 | cpumask_set_cpu(cpu, dstp: &priv->lmask); |
513 | handler->present = true; |
514 | handler->hart_base = priv->regs + CONTEXT_BASE + |
515 | i * CONTEXT_SIZE; |
516 | raw_spin_lock_init(&handler->enable_lock); |
517 | handler->enable_base = priv->regs + CONTEXT_ENABLE_BASE + |
518 | i * CONTEXT_ENABLE_SIZE; |
519 | handler->priv = priv; |
520 | |
521 | handler->enable_save = kcalloc(DIV_ROUND_UP(nr_irqs, 32), |
522 | size: sizeof(*handler->enable_save), GFP_KERNEL); |
523 | if (!handler->enable_save) |
524 | goto out_free_enable_reg; |
525 | done: |
526 | for (hwirq = 1; hwirq <= nr_irqs; hwirq++) { |
527 | plic_toggle(handler, hwirq, enable: 0); |
528 | writel(val: 1, addr: priv->regs + PRIORITY_BASE + |
529 | hwirq * PRIORITY_PER_ID); |
530 | } |
531 | nr_handlers++; |
532 | } |
533 | |
534 | /* |
535 | * We can have multiple PLIC instances so setup cpuhp state |
536 | * and register syscore operations only when context handler |
537 | * for current/boot CPU is present. |
538 | */ |
539 | handler = this_cpu_ptr(&plic_handlers); |
540 | if (handler->present && !plic_cpuhp_setup_done) { |
541 | cpuhp_setup_state(state: CPUHP_AP_IRQ_SIFIVE_PLIC_STARTING, |
542 | name: "irqchip/sifive/plic:starting" , |
543 | startup: plic_starting_cpu, teardown: plic_dying_cpu); |
544 | register_syscore_ops(ops: &plic_irq_syscore_ops); |
545 | plic_cpuhp_setup_done = true; |
546 | } |
547 | |
548 | pr_info("%pOFP: mapped %d interrupts with %d handlers for" |
549 | " %d contexts.\n" , node, nr_irqs, nr_handlers, nr_contexts); |
550 | return 0; |
551 | |
552 | out_free_enable_reg: |
553 | for_each_cpu(cpu, cpu_present_mask) { |
554 | handler = per_cpu_ptr(&plic_handlers, cpu); |
555 | kfree(objp: handler->enable_save); |
556 | } |
557 | out_free_priority_reg: |
558 | kfree(objp: priv->prio_save); |
559 | out_iounmap: |
560 | iounmap(addr: priv->regs); |
561 | out_free_priv: |
562 | kfree(objp: priv); |
563 | return error; |
564 | } |
565 | |
566 | static int __init plic_init(struct device_node *node, |
567 | struct device_node *parent) |
568 | { |
569 | return __plic_init(node, parent, plic_quirks: 0); |
570 | } |
571 | |
572 | IRQCHIP_DECLARE(sifive_plic, "sifive,plic-1.0.0" , plic_init); |
573 | IRQCHIP_DECLARE(riscv_plic0, "riscv,plic0" , plic_init); /* for legacy systems */ |
574 | |
575 | static int __init plic_edge_init(struct device_node *node, |
576 | struct device_node *parent) |
577 | { |
578 | return __plic_init(node, parent, BIT(PLIC_QUIRK_EDGE_INTERRUPT)); |
579 | } |
580 | |
581 | IRQCHIP_DECLARE(andestech_nceplic100, "andestech,nceplic100" , plic_edge_init); |
582 | IRQCHIP_DECLARE(thead_c900_plic, "thead,c900-plic" , plic_edge_init); |
583 | |