1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* |
3 | * Winbond W6692 specific defines |
4 | * |
5 | * Author Karsten Keil <keil@isdn4linux.de> |
6 | * based on the w6692 I4L driver from Petr Novak <petr.novak@i.cz> |
7 | * |
8 | * Copyright 2009 by Karsten Keil <keil@isdn4linux.de> |
9 | */ |
10 | |
11 | /* Specifications of W6692 registers */ |
12 | |
13 | #define W_D_RFIFO 0x00 /* R */ |
14 | #define W_D_XFIFO 0x04 /* W */ |
15 | #define W_D_CMDR 0x08 /* W */ |
16 | #define W_D_MODE 0x0c /* R/W */ |
17 | #define W_D_TIMR 0x10 /* R/W */ |
18 | #define W_ISTA 0x14 /* R_clr */ |
19 | #define W_IMASK 0x18 /* R/W */ |
20 | #define W_D_EXIR 0x1c /* R_clr */ |
21 | #define W_D_EXIM 0x20 /* R/W */ |
22 | #define W_D_STAR 0x24 /* R */ |
23 | #define W_D_RSTA 0x28 /* R */ |
24 | #define W_D_SAM 0x2c /* R/W */ |
25 | #define W_D_SAP1 0x30 /* R/W */ |
26 | #define W_D_SAP2 0x34 /* R/W */ |
27 | #define W_D_TAM 0x38 /* R/W */ |
28 | #define W_D_TEI1 0x3c /* R/W */ |
29 | #define W_D_TEI2 0x40 /* R/W */ |
30 | #define W_D_RBCH 0x44 /* R */ |
31 | #define W_D_RBCL 0x48 /* R */ |
32 | #define W_TIMR2 0x4c /* W */ |
33 | #define W_L1_RC 0x50 /* R/W */ |
34 | #define W_D_CTL 0x54 /* R/W */ |
35 | #define W_CIR 0x58 /* R */ |
36 | #define W_CIX 0x5c /* W */ |
37 | #define W_SQR 0x60 /* R */ |
38 | #define W_SQX 0x64 /* W */ |
39 | #define W_PCTL 0x68 /* R/W */ |
40 | #define W_MOR 0x6c /* R */ |
41 | #define W_MOX 0x70 /* R/W */ |
42 | #define W_MOSR 0x74 /* R_clr */ |
43 | #define W_MOCR 0x78 /* R/W */ |
44 | #define W_GCR 0x7c /* R/W */ |
45 | |
46 | #define W_B_RFIFO 0x80 /* R */ |
47 | #define W_B_XFIFO 0x84 /* W */ |
48 | #define W_B_CMDR 0x88 /* W */ |
49 | #define W_B_MODE 0x8c /* R/W */ |
50 | #define W_B_EXIR 0x90 /* R_clr */ |
51 | #define W_B_EXIM 0x94 /* R/W */ |
52 | #define W_B_STAR 0x98 /* R */ |
53 | #define W_B_ADM1 0x9c /* R/W */ |
54 | #define W_B_ADM2 0xa0 /* R/W */ |
55 | #define W_B_ADR1 0xa4 /* R/W */ |
56 | #define W_B_ADR2 0xa8 /* R/W */ |
57 | #define W_B_RBCL 0xac /* R */ |
58 | #define W_B_RBCH 0xb0 /* R */ |
59 | |
60 | #define W_XADDR 0xf4 /* R/W */ |
61 | #define W_XDATA 0xf8 /* R/W */ |
62 | #define W_EPCTL 0xfc /* W */ |
63 | |
64 | /* W6692 register bits */ |
65 | |
66 | #define W_D_CMDR_XRST 0x01 |
67 | #define W_D_CMDR_XME 0x02 |
68 | #define W_D_CMDR_XMS 0x08 |
69 | #define W_D_CMDR_STT 0x10 |
70 | #define W_D_CMDR_RRST 0x40 |
71 | #define W_D_CMDR_RACK 0x80 |
72 | |
73 | #define W_D_MODE_RLP 0x01 |
74 | #define W_D_MODE_DLP 0x02 |
75 | #define W_D_MODE_MFD 0x04 |
76 | #define W_D_MODE_TEE 0x08 |
77 | #define W_D_MODE_TMS 0x10 |
78 | #define W_D_MODE_RACT 0x40 |
79 | #define W_D_MODE_MMS 0x80 |
80 | |
81 | #define W_INT_B2_EXI 0x01 |
82 | #define W_INT_B1_EXI 0x02 |
83 | #define W_INT_D_EXI 0x04 |
84 | #define W_INT_XINT0 0x08 |
85 | #define W_INT_XINT1 0x10 |
86 | #define W_INT_D_XFR 0x20 |
87 | #define W_INT_D_RME 0x40 |
88 | #define W_INT_D_RMR 0x80 |
89 | |
90 | #define W_D_EXI_WEXP 0x01 |
91 | #define W_D_EXI_TEXP 0x02 |
92 | #define W_D_EXI_ISC 0x04 |
93 | #define W_D_EXI_MOC 0x08 |
94 | #define W_D_EXI_TIN2 0x10 |
95 | #define W_D_EXI_XCOL 0x20 |
96 | #define W_D_EXI_XDUN 0x40 |
97 | #define W_D_EXI_RDOV 0x80 |
98 | |
99 | #define W_D_STAR_DRDY 0x10 |
100 | #define W_D_STAR_XBZ 0x20 |
101 | #define W_D_STAR_XDOW 0x80 |
102 | |
103 | #define W_D_RSTA_RMB 0x10 |
104 | #define W_D_RSTA_CRCE 0x20 |
105 | #define W_D_RSTA_RDOV 0x40 |
106 | |
107 | #define W_D_CTL_SRST 0x20 |
108 | |
109 | #define W_CIR_SCC 0x80 |
110 | #define W_CIR_ICC 0x40 |
111 | #define W_CIR_COD_MASK 0x0f |
112 | |
113 | #define W_PCTL_PCX 0x01 |
114 | #define W_PCTL_XMODE 0x02 |
115 | #define W_PCTL_OE0 0x04 |
116 | #define W_PCTL_OE1 0x08 |
117 | #define W_PCTL_OE2 0x10 |
118 | #define W_PCTL_OE3 0x20 |
119 | #define W_PCTL_OE4 0x40 |
120 | #define W_PCTL_OE5 0x80 |
121 | |
122 | #define W_B_CMDR_XRST 0x01 |
123 | #define W_B_CMDR_XME 0x02 |
124 | #define W_B_CMDR_XMS 0x04 |
125 | #define W_B_CMDR_RACT 0x20 |
126 | #define W_B_CMDR_RRST 0x40 |
127 | #define W_B_CMDR_RACK 0x80 |
128 | |
129 | #define W_B_MODE_FTS0 0x01 |
130 | #define W_B_MODE_FTS1 0x02 |
131 | #define W_B_MODE_SW56 0x04 |
132 | #define W_B_MODE_BSW0 0x08 |
133 | #define W_B_MODE_BSW1 0x10 |
134 | #define W_B_MODE_EPCM 0x20 |
135 | #define W_B_MODE_ITF 0x40 |
136 | #define W_B_MODE_MMS 0x80 |
137 | |
138 | #define W_B_EXI_XDUN 0x01 |
139 | #define W_B_EXI_XFR 0x02 |
140 | #define W_B_EXI_RDOV 0x10 |
141 | #define W_B_EXI_RME 0x20 |
142 | #define W_B_EXI_RMR 0x40 |
143 | |
144 | #define W_B_STAR_XBZ 0x01 |
145 | #define W_B_STAR_XDOW 0x04 |
146 | #define W_B_STAR_RMB 0x10 |
147 | #define W_B_STAR_CRCE 0x20 |
148 | #define W_B_STAR_RDOV 0x40 |
149 | |
150 | #define W_B_RBCH_LOV 0x20 |
151 | |
152 | /* W6692 Layer1 commands */ |
153 | |
154 | #define W_L1CMD_ECK 0x00 |
155 | #define W_L1CMD_RST 0x01 |
156 | #define W_L1CMD_SCP 0x04 |
157 | #define W_L1CMD_SSP 0x02 |
158 | #define W_L1CMD_AR8 0x08 |
159 | #define W_L1CMD_AR10 0x09 |
160 | #define W_L1CMD_EAL 0x0a |
161 | #define W_L1CMD_DRC 0x0f |
162 | |
163 | /* W6692 Layer1 indications */ |
164 | |
165 | #define W_L1IND_CE 0x07 |
166 | #define W_L1IND_DRD 0x00 |
167 | #define W_L1IND_LD 0x04 |
168 | #define W_L1IND_ARD 0x08 |
169 | #define W_L1IND_TI 0x0a |
170 | #define W_L1IND_ATI 0x0b |
171 | #define W_L1IND_AI8 0x0c |
172 | #define W_L1IND_AI10 0x0d |
173 | #define W_L1IND_CD 0x0f |
174 | |
175 | /* FIFO thresholds */ |
176 | #define W_D_FIFO_THRESH 64 |
177 | #define W_B_FIFO_THRESH 64 |
178 | |