| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * ADV7343 encoder related structure and register definitions |
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| 4 | * |
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| 5 | * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ |
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| 6 | */ |
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| 7 | |
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| 8 | #ifndef ADV7343_REGS_H |
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| 9 | #define ADV7343_REGS_H |
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| 10 | |
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| 11 | struct adv7343_std_info { |
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| 12 | u32 standard_val3; |
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| 13 | u32 fsc_val; |
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| 14 | v4l2_std_id stdid; |
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| 15 | }; |
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| 16 | |
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| 17 | /* Register offset macros */ |
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| 18 | #define ADV7343_POWER_MODE_REG (0x00) |
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| 19 | #define ADV7343_MODE_SELECT_REG (0x01) |
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| 20 | #define ADV7343_MODE_REG0 (0x02) |
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| 21 | |
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| 22 | #define ADV7343_DAC2_OUTPUT_LEVEL (0x0b) |
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| 23 | |
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| 24 | #define ADV7343_SOFT_RESET (0x17) |
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| 25 | |
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| 26 | #define ADV7343_HD_MODE_REG1 (0x30) |
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| 27 | #define ADV7343_HD_MODE_REG2 (0x31) |
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| 28 | #define ADV7343_HD_MODE_REG3 (0x32) |
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| 29 | #define ADV7343_HD_MODE_REG4 (0x33) |
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| 30 | #define ADV7343_HD_MODE_REG5 (0x34) |
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| 31 | #define ADV7343_HD_MODE_REG6 (0x35) |
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| 32 | |
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| 33 | #define ADV7343_HD_MODE_REG7 (0x39) |
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| 34 | |
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| 35 | #define ADV7343_SD_MODE_REG1 (0x80) |
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| 36 | #define ADV7343_SD_MODE_REG2 (0x82) |
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| 37 | #define ADV7343_SD_MODE_REG3 (0x83) |
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| 38 | #define ADV7343_SD_MODE_REG4 (0x84) |
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| 39 | #define ADV7343_SD_MODE_REG5 (0x86) |
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| 40 | #define ADV7343_SD_MODE_REG6 (0x87) |
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| 41 | #define ADV7343_SD_MODE_REG7 (0x88) |
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| 42 | #define ADV7343_SD_MODE_REG8 (0x89) |
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| 43 | |
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| 44 | #define ADV7343_FSC_REG0 (0x8C) |
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| 45 | #define ADV7343_FSC_REG1 (0x8D) |
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| 46 | #define ADV7343_FSC_REG2 (0x8E) |
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| 47 | #define ADV7343_FSC_REG3 (0x8F) |
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| 48 | |
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| 49 | #define ADV7343_SD_CGMS_WSS0 (0x99) |
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| 50 | |
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| 51 | #define ADV7343_SD_HUE_REG (0xA0) |
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| 52 | #define ADV7343_SD_BRIGHTNESS_WSS (0xA1) |
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| 53 | |
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| 54 | /* Default values for the registers */ |
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| 55 | #define ADV7343_POWER_MODE_REG_DEFAULT (0x10) |
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| 56 | #define ADV7343_HD_MODE_REG1_DEFAULT (0x3C) /* Changed Default |
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| 57 | 720p EAVSAV code*/ |
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| 58 | #define ADV7343_HD_MODE_REG2_DEFAULT (0x01) /* Changed Pixel data |
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| 59 | valid */ |
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| 60 | #define ADV7343_HD_MODE_REG3_DEFAULT (0x00) /* Color delay 0 clks */ |
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| 61 | #define ADV7343_HD_MODE_REG4_DEFAULT (0xE8) /* Changed */ |
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| 62 | #define ADV7343_HD_MODE_REG5_DEFAULT (0x08) |
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| 63 | #define ADV7343_HD_MODE_REG6_DEFAULT (0x00) |
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| 64 | #define ADV7343_HD_MODE_REG7_DEFAULT (0x00) |
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| 65 | #define ADV7343_SD_MODE_REG8_DEFAULT (0x00) |
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| 66 | #define ADV7343_SOFT_RESET_DEFAULT (0x02) |
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| 67 | #define ADV7343_COMPOSITE_POWER_VALUE (0x80) |
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| 68 | #define ADV7343_COMPONENT_POWER_VALUE (0x1C) |
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| 69 | #define ADV7343_SVIDEO_POWER_VALUE (0x60) |
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| 70 | #define ADV7343_SD_HUE_REG_DEFAULT (127) |
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| 71 | #define ADV7343_SD_BRIGHTNESS_WSS_DEFAULT (0x03) |
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| 72 | |
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| 73 | #define ADV7343_SD_CGMS_WSS0_DEFAULT (0x10) |
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| 74 | |
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| 75 | #define ADV7343_SD_MODE_REG1_DEFAULT (0x00) |
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| 76 | #define ADV7343_SD_MODE_REG2_DEFAULT (0xC9) |
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| 77 | #define ADV7343_SD_MODE_REG3_DEFAULT (0x10) |
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| 78 | #define ADV7343_SD_MODE_REG4_DEFAULT (0x01) |
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| 79 | #define ADV7343_SD_MODE_REG5_DEFAULT (0x02) |
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| 80 | #define ADV7343_SD_MODE_REG6_DEFAULT (0x0C) |
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| 81 | #define ADV7343_SD_MODE_REG7_DEFAULT (0x04) |
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| 82 | #define ADV7343_SD_MODE_REG8_DEFAULT (0x00) |
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| 83 | |
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| 84 | /* Bit masks for Mode Select Register */ |
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| 85 | #define INPUT_MODE_MASK (0x70) |
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| 86 | #define SD_INPUT_MODE (0x00) |
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| 87 | #define HD_720P_INPUT_MODE (0x10) |
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| 88 | #define HD_1080I_INPUT_MODE (0x10) |
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| 89 | |
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| 90 | /* Bit masks for Mode Register 0 */ |
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| 91 | #define TEST_PATTERN_BLACK_BAR_EN (0x04) |
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| 92 | #define YUV_OUTPUT_SELECT (0x20) |
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| 93 | #define RGB_OUTPUT_SELECT (0xDF) |
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| 94 | |
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| 95 | /* Bit masks for DAC output levels */ |
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| 96 | #define DAC_OUTPUT_LEVEL_MASK (0xFF) |
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| 97 | |
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| 98 | /* Bit masks for soft reset register */ |
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| 99 | #define SOFT_RESET (0x02) |
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| 100 | |
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| 101 | /* Bit masks for HD Mode Register 1 */ |
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| 102 | #define OUTPUT_STD_MASK (0x03) |
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| 103 | #define OUTPUT_STD_SHIFT (0) |
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| 104 | #define OUTPUT_STD_EIA0_2 (0x00) |
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| 105 | #define OUTPUT_STD_EIA0_1 (0x01) |
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| 106 | #define OUTPUT_STD_FULL (0x02) |
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| 107 | #define EMBEDDED_SYNC (0x04) |
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| 108 | #define EXTERNAL_SYNC (0xFB) |
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| 109 | #define STD_MODE_SHIFT (3) |
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| 110 | #define STD_MODE_MASK (0x1F) |
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| 111 | #define STD_MODE_720P (0x05) |
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| 112 | #define STD_MODE_720P_25 (0x08) |
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| 113 | #define STD_MODE_720P_30 (0x07) |
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| 114 | #define STD_MODE_720P_50 (0x06) |
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| 115 | #define STD_MODE_1080I (0x0D) |
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| 116 | #define STD_MODE_1080I_25fps (0x0E) |
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| 117 | #define STD_MODE_1080P_24 (0x12) |
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| 118 | #define STD_MODE_1080P_25 (0x10) |
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| 119 | #define STD_MODE_1080P_30 (0x0F) |
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| 120 | #define STD_MODE_525P (0x00) |
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| 121 | #define STD_MODE_625P (0x03) |
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| 122 | |
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| 123 | /* Bit masks for SD Mode Register 1 */ |
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| 124 | #define SD_STD_MASK (0x03) |
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| 125 | #define SD_STD_NTSC (0x00) |
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| 126 | #define SD_STD_PAL_BDGHI (0x01) |
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| 127 | #define SD_STD_PAL_M (0x02) |
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| 128 | #define SD_STD_PAL_N (0x03) |
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| 129 | #define SD_LUMA_FLTR_MASK (0x7) |
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| 130 | #define SD_LUMA_FLTR_SHIFT (0x2) |
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| 131 | #define SD_CHROMA_FLTR_MASK (0x7) |
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| 132 | #define SD_CHROMA_FLTR_SHIFT (0x5) |
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| 133 | |
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| 134 | /* Bit masks for SD Mode Register 2 */ |
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| 135 | #define SD_PBPR_SSAF_EN (0x01) |
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| 136 | #define SD_PBPR_SSAF_DI (0xFE) |
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| 137 | #define SD_DAC_1_DI (0xFD) |
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| 138 | #define SD_DAC_2_DI (0xFB) |
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| 139 | #define SD_PEDESTAL_EN (0x08) |
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| 140 | #define SD_PEDESTAL_DI (0xF7) |
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| 141 | #define SD_SQUARE_PIXEL_EN (0x10) |
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| 142 | #define SD_SQUARE_PIXEL_DI (0xEF) |
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| 143 | #define SD_PIXEL_DATA_VALID (0x40) |
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| 144 | #define SD_ACTIVE_EDGE_EN (0x80) |
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| 145 | #define SD_ACTIVE_EDGE_DI (0x7F) |
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| 146 | |
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| 147 | /* Bit masks for HD Mode Register 6 */ |
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| 148 | #define HD_RGB_INPUT_EN (0x02) |
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| 149 | #define HD_RGB_INPUT_DI (0xFD) |
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| 150 | #define HD_PBPR_SYNC_EN (0x04) |
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| 151 | #define HD_PBPR_SYNC_DI (0xFB) |
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| 152 | #define HD_DAC_SWAP_EN (0x08) |
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| 153 | #define HD_DAC_SWAP_DI (0xF7) |
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| 154 | #define HD_GAMMA_CURVE_A (0xEF) |
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| 155 | #define HD_GAMMA_CURVE_B (0x10) |
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| 156 | #define HD_GAMMA_EN (0x20) |
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| 157 | #define HD_GAMMA_DI (0xDF) |
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| 158 | #define HD_ADPT_FLTR_MODEB (0x40) |
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| 159 | #define HD_ADPT_FLTR_MODEA (0xBF) |
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| 160 | #define HD_ADPT_FLTR_EN (0x80) |
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| 161 | #define HD_ADPT_FLTR_DI (0x7F) |
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| 162 | |
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| 163 | #define ADV7343_BRIGHTNESS_MAX (127) |
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| 164 | #define ADV7343_BRIGHTNESS_MIN (0) |
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| 165 | #define ADV7343_BRIGHTNESS_DEF (3) |
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| 166 | #define ADV7343_HUE_MAX (255) |
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| 167 | #define ADV7343_HUE_MIN (0) |
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| 168 | #define ADV7343_HUE_DEF (127) |
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| 169 | #define ADV7343_GAIN_MAX (64) |
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| 170 | #define ADV7343_GAIN_MIN (-64) |
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| 171 | #define ADV7343_GAIN_DEF (0) |
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| 172 | |
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| 173 | #endif |
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| 174 | |
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