1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * Copyright (c) 2023 Intel Corporation. |
4 | */ |
5 | |
6 | #include <asm/unaligned.h> |
7 | |
8 | #include <linux/acpi.h> |
9 | #include <linux/bitfield.h> |
10 | #include <linux/i2c.h> |
11 | #include <linux/module.h> |
12 | #include <linux/pm_runtime.h> |
13 | |
14 | #include <media/v4l2-ctrls.h> |
15 | #include <media/v4l2-device.h> |
16 | #include <media/v4l2-event.h> |
17 | #include <media/v4l2-fwnode.h> |
18 | |
19 | #define OV01A10_LINK_FREQ_400MHZ 400000000ULL |
20 | #define OV01A10_SCLK 40000000LL |
21 | #define OV01A10_DATA_LANES 1 |
22 | |
23 | #define OV01A10_REG_CHIP_ID 0x300a |
24 | #define OV01A10_CHIP_ID 0x560141 |
25 | |
26 | #define OV01A10_REG_MODE_SELECT 0x0100 |
27 | #define OV01A10_MODE_STANDBY 0x00 |
28 | #define OV01A10_MODE_STREAMING 0x01 |
29 | |
30 | /* pixel array */ |
31 | #define OV01A10_PIXEL_ARRAY_WIDTH 1296 |
32 | #define OV01A10_PIXEL_ARRAY_HEIGHT 816 |
33 | #define OV01A10_ACITVE_WIDTH 1280 |
34 | #define OV01A10_ACITVE_HEIGHT 800 |
35 | |
36 | /* vertical and horizontal timings */ |
37 | #define OV01A10_REG_VTS 0x380e |
38 | #define OV01A10_VTS_DEF 0x0380 |
39 | #define OV01A10_VTS_MIN 0x0380 |
40 | #define OV01A10_VTS_MAX 0xffff |
41 | #define OV01A10_HTS_DEF 1488 |
42 | |
43 | /* exposure controls */ |
44 | #define OV01A10_REG_EXPOSURE 0x3501 |
45 | #define OV01A10_EXPOSURE_MIN 4 |
46 | #define OV01A10_EXPOSURE_MAX_MARGIN 8 |
47 | #define OV01A10_EXPOSURE_STEP 1 |
48 | |
49 | /* analog gain controls */ |
50 | #define OV01A10_REG_ANALOG_GAIN 0x3508 |
51 | #define OV01A10_ANAL_GAIN_MIN 0x100 |
52 | #define OV01A10_ANAL_GAIN_MAX 0xffff |
53 | #define OV01A10_ANAL_GAIN_STEP 1 |
54 | |
55 | /* digital gain controls */ |
56 | #define OV01A10_REG_DIGITAL_GAIN_B 0x350a |
57 | #define OV01A10_REG_DIGITAL_GAIN_GB 0x3510 |
58 | #define OV01A10_REG_DIGITAL_GAIN_GR 0x3513 |
59 | #define OV01A10_REG_DIGITAL_GAIN_R 0x3516 |
60 | #define OV01A10_DGTL_GAIN_MIN 0 |
61 | #define OV01A10_DGTL_GAIN_MAX 0x3ffff |
62 | #define OV01A10_DGTL_GAIN_STEP 1 |
63 | #define OV01A10_DGTL_GAIN_DEFAULT 1024 |
64 | |
65 | /* test pattern control */ |
66 | #define OV01A10_REG_TEST_PATTERN 0x4503 |
67 | #define OV01A10_TEST_PATTERN_ENABLE BIT(7) |
68 | #define OV01A10_LINK_FREQ_400MHZ_INDEX 0 |
69 | |
70 | /* flip and mirror control */ |
71 | #define OV01A10_REG_FORMAT1 0x3820 |
72 | #define OV01A10_VFLIP_MASK BIT(4) |
73 | #define OV01A10_HFLIP_MASK BIT(3) |
74 | |
75 | /* window offset */ |
76 | #define OV01A10_REG_X_WIN 0x3811 |
77 | #define OV01A10_REG_Y_WIN 0x3813 |
78 | |
79 | struct ov01a10_reg { |
80 | u16 address; |
81 | u8 val; |
82 | }; |
83 | |
84 | struct ov01a10_reg_list { |
85 | u32 num_of_regs; |
86 | const struct ov01a10_reg *regs; |
87 | }; |
88 | |
89 | struct ov01a10_link_freq_config { |
90 | const struct ov01a10_reg_list reg_list; |
91 | }; |
92 | |
93 | struct ov01a10_mode { |
94 | u32 width; |
95 | u32 height; |
96 | u32 hts; |
97 | u32 vts_def; |
98 | u32 vts_min; |
99 | u32 link_freq_index; |
100 | |
101 | const struct ov01a10_reg_list reg_list; |
102 | }; |
103 | |
104 | static const struct ov01a10_reg mipi_data_rate_720mbps[] = { |
105 | {0x0103, 0x01}, |
106 | {0x0302, 0x00}, |
107 | {0x0303, 0x06}, |
108 | {0x0304, 0x01}, |
109 | {0x0305, 0xe0}, |
110 | {0x0306, 0x00}, |
111 | {0x0308, 0x01}, |
112 | {0x0309, 0x00}, |
113 | {0x030c, 0x01}, |
114 | {0x0322, 0x01}, |
115 | {0x0323, 0x06}, |
116 | {0x0324, 0x01}, |
117 | {0x0325, 0x68}, |
118 | }; |
119 | |
120 | static const struct ov01a10_reg sensor_1280x800_setting[] = { |
121 | {0x3002, 0xa1}, |
122 | {0x301e, 0xf0}, |
123 | {0x3022, 0x01}, |
124 | {0x3501, 0x03}, |
125 | {0x3502, 0x78}, |
126 | {0x3504, 0x0c}, |
127 | {0x3508, 0x01}, |
128 | {0x3509, 0x00}, |
129 | {0x3601, 0xc0}, |
130 | {0x3603, 0x71}, |
131 | {0x3610, 0x68}, |
132 | {0x3611, 0x86}, |
133 | {0x3640, 0x10}, |
134 | {0x3641, 0x80}, |
135 | {0x3642, 0xdc}, |
136 | {0x3646, 0x55}, |
137 | {0x3647, 0x57}, |
138 | {0x364b, 0x00}, |
139 | {0x3653, 0x10}, |
140 | {0x3655, 0x00}, |
141 | {0x3656, 0x00}, |
142 | {0x365f, 0x0f}, |
143 | {0x3661, 0x45}, |
144 | {0x3662, 0x24}, |
145 | {0x3663, 0x11}, |
146 | {0x3664, 0x07}, |
147 | {0x3709, 0x34}, |
148 | {0x370b, 0x6f}, |
149 | {0x3714, 0x22}, |
150 | {0x371b, 0x27}, |
151 | {0x371c, 0x67}, |
152 | {0x371d, 0xa7}, |
153 | {0x371e, 0xe7}, |
154 | {0x3730, 0x81}, |
155 | {0x3733, 0x10}, |
156 | {0x3734, 0x40}, |
157 | {0x3737, 0x04}, |
158 | {0x3739, 0x1c}, |
159 | {0x3767, 0x00}, |
160 | {0x376c, 0x81}, |
161 | {0x3772, 0x14}, |
162 | {0x37c2, 0x04}, |
163 | {0x37d8, 0x03}, |
164 | {0x37d9, 0x0c}, |
165 | {0x37e0, 0x00}, |
166 | {0x37e1, 0x08}, |
167 | {0x37e2, 0x10}, |
168 | {0x37e3, 0x04}, |
169 | {0x37e4, 0x04}, |
170 | {0x37e5, 0x03}, |
171 | {0x37e6, 0x04}, |
172 | {0x3800, 0x00}, |
173 | {0x3801, 0x00}, |
174 | {0x3802, 0x00}, |
175 | {0x3803, 0x00}, |
176 | {0x3804, 0x05}, |
177 | {0x3805, 0x0f}, |
178 | {0x3806, 0x03}, |
179 | {0x3807, 0x2f}, |
180 | {0x3808, 0x05}, |
181 | {0x3809, 0x00}, |
182 | {0x380a, 0x03}, |
183 | {0x380b, 0x20}, |
184 | {0x380c, 0x02}, |
185 | {0x380d, 0xe8}, |
186 | {0x380e, 0x03}, |
187 | {0x380f, 0x80}, |
188 | {0x3810, 0x00}, |
189 | {0x3811, 0x08}, |
190 | {0x3812, 0x00}, |
191 | {0x3813, 0x08}, |
192 | {0x3814, 0x01}, |
193 | {0x3815, 0x01}, |
194 | {0x3816, 0x01}, |
195 | {0x3817, 0x01}, |
196 | {0x3820, 0xa0}, |
197 | {0x3822, 0x13}, |
198 | {0x3832, 0x28}, |
199 | {0x3833, 0x10}, |
200 | {0x3b00, 0x00}, |
201 | {0x3c80, 0x00}, |
202 | {0x3c88, 0x02}, |
203 | {0x3c8c, 0x07}, |
204 | {0x3c8d, 0x40}, |
205 | {0x3cc7, 0x80}, |
206 | {0x4000, 0xc3}, |
207 | {0x4001, 0xe0}, |
208 | {0x4003, 0x40}, |
209 | {0x4008, 0x02}, |
210 | {0x4009, 0x19}, |
211 | {0x400a, 0x01}, |
212 | {0x400b, 0x6c}, |
213 | {0x4011, 0x00}, |
214 | {0x4041, 0x00}, |
215 | {0x4300, 0xff}, |
216 | {0x4301, 0x00}, |
217 | {0x4302, 0x0f}, |
218 | {0x4503, 0x00}, |
219 | {0x4601, 0x50}, |
220 | {0x4800, 0x64}, |
221 | {0x481f, 0x34}, |
222 | {0x4825, 0x33}, |
223 | {0x4837, 0x11}, |
224 | {0x4881, 0x40}, |
225 | {0x4883, 0x01}, |
226 | {0x4890, 0x00}, |
227 | {0x4901, 0x00}, |
228 | {0x4902, 0x00}, |
229 | {0x4b00, 0x2a}, |
230 | {0x4b0d, 0x00}, |
231 | {0x450a, 0x04}, |
232 | {0x450b, 0x00}, |
233 | {0x5000, 0x65}, |
234 | {0x5200, 0x18}, |
235 | {0x5004, 0x00}, |
236 | {0x5080, 0x40}, |
237 | {0x0305, 0xf4}, |
238 | {0x0325, 0xc2}, |
239 | }; |
240 | |
241 | static const char * const [] = { |
242 | "Disabled" , |
243 | "Color Bar" , |
244 | "Top-Bottom Darker Color Bar" , |
245 | "Right-Left Darker Color Bar" , |
246 | "Color Bar type 4" , |
247 | }; |
248 | |
249 | static const s64 [] = { |
250 | OV01A10_LINK_FREQ_400MHZ, |
251 | }; |
252 | |
253 | static const struct ov01a10_link_freq_config link_freq_configs[] = { |
254 | [OV01A10_LINK_FREQ_400MHZ_INDEX] = { |
255 | .reg_list = { |
256 | .num_of_regs = ARRAY_SIZE(mipi_data_rate_720mbps), |
257 | .regs = mipi_data_rate_720mbps, |
258 | } |
259 | }, |
260 | }; |
261 | |
262 | static const struct ov01a10_mode supported_modes[] = { |
263 | { |
264 | .width = OV01A10_ACITVE_WIDTH, |
265 | .height = OV01A10_ACITVE_HEIGHT, |
266 | .hts = OV01A10_HTS_DEF, |
267 | .vts_def = OV01A10_VTS_DEF, |
268 | .vts_min = OV01A10_VTS_MIN, |
269 | .reg_list = { |
270 | .num_of_regs = ARRAY_SIZE(sensor_1280x800_setting), |
271 | .regs = sensor_1280x800_setting, |
272 | }, |
273 | .link_freq_index = OV01A10_LINK_FREQ_400MHZ_INDEX, |
274 | }, |
275 | }; |
276 | |
277 | struct ov01a10 { |
278 | struct v4l2_subdev sd; |
279 | struct media_pad pad; |
280 | struct v4l2_ctrl_handler ctrl_handler; |
281 | |
282 | /* v4l2 controls */ |
283 | struct v4l2_ctrl *link_freq; |
284 | struct v4l2_ctrl *pixel_rate; |
285 | struct v4l2_ctrl *vblank; |
286 | struct v4l2_ctrl *hblank; |
287 | struct v4l2_ctrl *exposure; |
288 | |
289 | const struct ov01a10_mode *cur_mode; |
290 | }; |
291 | |
292 | static inline struct ov01a10 *to_ov01a10(struct v4l2_subdev *subdev) |
293 | { |
294 | return container_of(subdev, struct ov01a10, sd); |
295 | } |
296 | |
297 | static int ov01a10_read_reg(struct ov01a10 *ov01a10, u16 reg, u16 len, u32 *val) |
298 | { |
299 | struct i2c_client *client = v4l2_get_subdevdata(sd: &ov01a10->sd); |
300 | struct i2c_msg msgs[2]; |
301 | u8 addr_buf[2]; |
302 | u8 data_buf[4] = {0}; |
303 | int ret = 0; |
304 | |
305 | if (len > sizeof(data_buf)) |
306 | return -EINVAL; |
307 | |
308 | put_unaligned_be16(val: reg, p: addr_buf); |
309 | msgs[0].addr = client->addr; |
310 | msgs[0].flags = 0; |
311 | msgs[0].len = sizeof(addr_buf); |
312 | msgs[0].buf = addr_buf; |
313 | msgs[1].addr = client->addr; |
314 | msgs[1].flags = I2C_M_RD; |
315 | msgs[1].len = len; |
316 | msgs[1].buf = &data_buf[sizeof(data_buf) - len]; |
317 | |
318 | ret = i2c_transfer(adap: client->adapter, msgs, ARRAY_SIZE(msgs)); |
319 | |
320 | if (ret != ARRAY_SIZE(msgs)) |
321 | return ret < 0 ? ret : -EIO; |
322 | |
323 | *val = get_unaligned_be32(p: data_buf); |
324 | |
325 | return 0; |
326 | } |
327 | |
328 | static int ov01a10_write_reg(struct ov01a10 *ov01a10, u16 reg, u16 len, u32 val) |
329 | { |
330 | struct i2c_client *client = v4l2_get_subdevdata(sd: &ov01a10->sd); |
331 | u8 buf[6]; |
332 | int ret = 0; |
333 | |
334 | if (len > 4) |
335 | return -EINVAL; |
336 | |
337 | put_unaligned_be16(val: reg, p: buf); |
338 | put_unaligned_be32(val: val << 8 * (4 - len), p: buf + 2); |
339 | |
340 | ret = i2c_master_send(client, buf, count: len + 2); |
341 | if (ret != len + 2) |
342 | return ret < 0 ? ret : -EIO; |
343 | |
344 | return 0; |
345 | } |
346 | |
347 | static int ov01a10_write_reg_list(struct ov01a10 *ov01a10, |
348 | const struct ov01a10_reg_list *r_list) |
349 | { |
350 | struct i2c_client *client = v4l2_get_subdevdata(sd: &ov01a10->sd); |
351 | unsigned int i; |
352 | int ret = 0; |
353 | |
354 | for (i = 0; i < r_list->num_of_regs; i++) { |
355 | ret = ov01a10_write_reg(ov01a10, reg: r_list->regs[i].address, len: 1, |
356 | val: r_list->regs[i].val); |
357 | if (ret) { |
358 | dev_err_ratelimited(&client->dev, |
359 | "write reg 0x%4.4x err = %d\n" , |
360 | r_list->regs[i].address, ret); |
361 | return ret; |
362 | } |
363 | } |
364 | |
365 | return 0; |
366 | } |
367 | |
368 | static int ov01a10_update_digital_gain(struct ov01a10 *ov01a10, u32 d_gain) |
369 | { |
370 | struct i2c_client *client = v4l2_get_subdevdata(sd: &ov01a10->sd); |
371 | u32 real = d_gain << 6; |
372 | int ret = 0; |
373 | |
374 | ret = ov01a10_write_reg(ov01a10, OV01A10_REG_DIGITAL_GAIN_B, len: 3, val: real); |
375 | if (ret) { |
376 | dev_err(&client->dev, "failed to set DIGITAL_GAIN_B\n" ); |
377 | return ret; |
378 | } |
379 | |
380 | ret = ov01a10_write_reg(ov01a10, OV01A10_REG_DIGITAL_GAIN_GB, len: 3, val: real); |
381 | if (ret) { |
382 | dev_err(&client->dev, "failed to set DIGITAL_GAIN_GB\n" ); |
383 | return ret; |
384 | } |
385 | |
386 | ret = ov01a10_write_reg(ov01a10, OV01A10_REG_DIGITAL_GAIN_GR, len: 3, val: real); |
387 | if (ret) { |
388 | dev_err(&client->dev, "failed to set DIGITAL_GAIN_GR\n" ); |
389 | return ret; |
390 | } |
391 | |
392 | ret = ov01a10_write_reg(ov01a10, OV01A10_REG_DIGITAL_GAIN_R, len: 3, val: real); |
393 | if (ret) |
394 | dev_err(&client->dev, "failed to set DIGITAL_GAIN_R\n" ); |
395 | |
396 | return ret; |
397 | } |
398 | |
399 | static int ov01a10_test_pattern(struct ov01a10 *ov01a10, u32 pattern) |
400 | { |
401 | if (!pattern) |
402 | return 0; |
403 | |
404 | pattern = (pattern - 1) | OV01A10_TEST_PATTERN_ENABLE; |
405 | |
406 | return ov01a10_write_reg(ov01a10, OV01A10_REG_TEST_PATTERN, len: 1, val: pattern); |
407 | } |
408 | |
409 | /* for vflip and hflip, use 0x9 as window offset to keep the bayer */ |
410 | static int ov01a10_set_hflip(struct ov01a10 *ov01a10, u32 hflip) |
411 | { |
412 | int ret; |
413 | u32 val, offset; |
414 | |
415 | offset = hflip ? 0x9 : 0x8; |
416 | ret = ov01a10_write_reg(ov01a10, OV01A10_REG_X_WIN, len: 1, val: offset); |
417 | if (ret) |
418 | return ret; |
419 | |
420 | ret = ov01a10_read_reg(ov01a10, OV01A10_REG_FORMAT1, len: 1, val: &val); |
421 | if (ret) |
422 | return ret; |
423 | |
424 | val = hflip ? val | FIELD_PREP(OV01A10_HFLIP_MASK, 0x1) : |
425 | val & ~OV01A10_HFLIP_MASK; |
426 | |
427 | return ov01a10_write_reg(ov01a10, OV01A10_REG_FORMAT1, len: 1, val); |
428 | } |
429 | |
430 | static int ov01a10_set_vflip(struct ov01a10 *ov01a10, u32 vflip) |
431 | { |
432 | int ret; |
433 | u32 val, offset; |
434 | |
435 | offset = vflip ? 0x9 : 0x8; |
436 | ret = ov01a10_write_reg(ov01a10, OV01A10_REG_Y_WIN, len: 1, val: offset); |
437 | if (ret) |
438 | return ret; |
439 | |
440 | ret = ov01a10_read_reg(ov01a10, OV01A10_REG_FORMAT1, len: 1, val: &val); |
441 | if (ret) |
442 | return ret; |
443 | |
444 | val = vflip ? val | FIELD_PREP(OV01A10_VFLIP_MASK, 0x1) : |
445 | val & ~OV01A10_VFLIP_MASK; |
446 | |
447 | return ov01a10_write_reg(ov01a10, OV01A10_REG_FORMAT1, len: 1, val); |
448 | } |
449 | |
450 | static int ov01a10_set_ctrl(struct v4l2_ctrl *ctrl) |
451 | { |
452 | struct ov01a10 *ov01a10 = container_of(ctrl->handler, |
453 | struct ov01a10, ctrl_handler); |
454 | struct i2c_client *client = v4l2_get_subdevdata(sd: &ov01a10->sd); |
455 | s64 exposure_max; |
456 | int ret = 0; |
457 | |
458 | if (ctrl->id == V4L2_CID_VBLANK) { |
459 | exposure_max = ov01a10->cur_mode->height + ctrl->val - |
460 | OV01A10_EXPOSURE_MAX_MARGIN; |
461 | __v4l2_ctrl_modify_range(ctrl: ov01a10->exposure, |
462 | min: ov01a10->exposure->minimum, |
463 | max: exposure_max, step: ov01a10->exposure->step, |
464 | def: exposure_max); |
465 | } |
466 | |
467 | if (!pm_runtime_get_if_in_use(dev: &client->dev)) |
468 | return 0; |
469 | |
470 | switch (ctrl->id) { |
471 | case V4L2_CID_ANALOGUE_GAIN: |
472 | ret = ov01a10_write_reg(ov01a10, OV01A10_REG_ANALOG_GAIN, len: 2, |
473 | val: ctrl->val); |
474 | break; |
475 | |
476 | case V4L2_CID_DIGITAL_GAIN: |
477 | ret = ov01a10_update_digital_gain(ov01a10, d_gain: ctrl->val); |
478 | break; |
479 | |
480 | case V4L2_CID_EXPOSURE: |
481 | ret = ov01a10_write_reg(ov01a10, OV01A10_REG_EXPOSURE, len: 2, |
482 | val: ctrl->val); |
483 | break; |
484 | |
485 | case V4L2_CID_VBLANK: |
486 | ret = ov01a10_write_reg(ov01a10, OV01A10_REG_VTS, len: 2, |
487 | val: ov01a10->cur_mode->height + ctrl->val); |
488 | break; |
489 | |
490 | case V4L2_CID_TEST_PATTERN: |
491 | ret = ov01a10_test_pattern(ov01a10, pattern: ctrl->val); |
492 | break; |
493 | |
494 | case V4L2_CID_HFLIP: |
495 | ov01a10_set_hflip(ov01a10, hflip: ctrl->val); |
496 | break; |
497 | |
498 | case V4L2_CID_VFLIP: |
499 | ov01a10_set_vflip(ov01a10, vflip: ctrl->val); |
500 | break; |
501 | |
502 | default: |
503 | ret = -EINVAL; |
504 | break; |
505 | } |
506 | |
507 | pm_runtime_put(dev: &client->dev); |
508 | |
509 | return ret; |
510 | } |
511 | |
512 | static const struct v4l2_ctrl_ops ov01a10_ctrl_ops = { |
513 | .s_ctrl = ov01a10_set_ctrl, |
514 | }; |
515 | |
516 | static int ov01a10_init_controls(struct ov01a10 *ov01a10) |
517 | { |
518 | struct i2c_client *client = v4l2_get_subdevdata(sd: &ov01a10->sd); |
519 | struct v4l2_fwnode_device_properties props; |
520 | u32 vblank_min, vblank_max, vblank_default; |
521 | struct v4l2_ctrl_handler *ctrl_hdlr; |
522 | const struct ov01a10_mode *cur_mode; |
523 | s64 exposure_max, h_blank; |
524 | int ret = 0; |
525 | int size; |
526 | |
527 | ret = v4l2_fwnode_device_parse(dev: &client->dev, props: &props); |
528 | if (ret) |
529 | return ret; |
530 | |
531 | ctrl_hdlr = &ov01a10->ctrl_handler; |
532 | ret = v4l2_ctrl_handler_init(ctrl_hdlr, 12); |
533 | if (ret) |
534 | return ret; |
535 | |
536 | cur_mode = ov01a10->cur_mode; |
537 | size = ARRAY_SIZE(link_freq_menu_items); |
538 | |
539 | ov01a10->link_freq = v4l2_ctrl_new_int_menu(hdl: ctrl_hdlr, |
540 | ops: &ov01a10_ctrl_ops, |
541 | V4L2_CID_LINK_FREQ, |
542 | max: size - 1, def: 0, |
543 | qmenu_int: link_freq_menu_items); |
544 | if (ov01a10->link_freq) |
545 | ov01a10->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY; |
546 | |
547 | ov01a10->pixel_rate = v4l2_ctrl_new_std(hdl: ctrl_hdlr, ops: &ov01a10_ctrl_ops, |
548 | V4L2_CID_PIXEL_RATE, min: 0, |
549 | OV01A10_SCLK, step: 1, OV01A10_SCLK); |
550 | |
551 | vblank_min = cur_mode->vts_min - cur_mode->height; |
552 | vblank_max = OV01A10_VTS_MAX - cur_mode->height; |
553 | vblank_default = cur_mode->vts_def - cur_mode->height; |
554 | ov01a10->vblank = v4l2_ctrl_new_std(hdl: ctrl_hdlr, ops: &ov01a10_ctrl_ops, |
555 | V4L2_CID_VBLANK, min: vblank_min, |
556 | max: vblank_max, step: 1, def: vblank_default); |
557 | |
558 | h_blank = cur_mode->hts - cur_mode->width; |
559 | ov01a10->hblank = v4l2_ctrl_new_std(hdl: ctrl_hdlr, ops: &ov01a10_ctrl_ops, |
560 | V4L2_CID_HBLANK, min: h_blank, max: h_blank, |
561 | step: 1, def: h_blank); |
562 | if (ov01a10->hblank) |
563 | ov01a10->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY; |
564 | |
565 | v4l2_ctrl_new_std(hdl: ctrl_hdlr, ops: &ov01a10_ctrl_ops, V4L2_CID_ANALOGUE_GAIN, |
566 | OV01A10_ANAL_GAIN_MIN, OV01A10_ANAL_GAIN_MAX, |
567 | OV01A10_ANAL_GAIN_STEP, OV01A10_ANAL_GAIN_MIN); |
568 | v4l2_ctrl_new_std(hdl: ctrl_hdlr, ops: &ov01a10_ctrl_ops, V4L2_CID_DIGITAL_GAIN, |
569 | OV01A10_DGTL_GAIN_MIN, OV01A10_DGTL_GAIN_MAX, |
570 | OV01A10_DGTL_GAIN_STEP, OV01A10_DGTL_GAIN_DEFAULT); |
571 | |
572 | exposure_max = cur_mode->vts_def - OV01A10_EXPOSURE_MAX_MARGIN; |
573 | ov01a10->exposure = v4l2_ctrl_new_std(hdl: ctrl_hdlr, ops: &ov01a10_ctrl_ops, |
574 | V4L2_CID_EXPOSURE, |
575 | OV01A10_EXPOSURE_MIN, |
576 | max: exposure_max, |
577 | OV01A10_EXPOSURE_STEP, |
578 | def: exposure_max); |
579 | |
580 | v4l2_ctrl_new_std_menu_items(hdl: ctrl_hdlr, ops: &ov01a10_ctrl_ops, |
581 | V4L2_CID_TEST_PATTERN, |
582 | ARRAY_SIZE(ov01a10_test_pattern_menu) - 1, |
583 | mask: 0, def: 0, qmenu: ov01a10_test_pattern_menu); |
584 | |
585 | v4l2_ctrl_new_std(hdl: ctrl_hdlr, ops: &ov01a10_ctrl_ops, V4L2_CID_HFLIP, |
586 | min: 0, max: 1, step: 1, def: 0); |
587 | v4l2_ctrl_new_std(hdl: ctrl_hdlr, ops: &ov01a10_ctrl_ops, V4L2_CID_VFLIP, |
588 | min: 0, max: 1, step: 1, def: 0); |
589 | |
590 | ret = v4l2_ctrl_new_fwnode_properties(hdl: ctrl_hdlr, ctrl_ops: &ov01a10_ctrl_ops, |
591 | p: &props); |
592 | if (ret) |
593 | goto fail; |
594 | |
595 | if (ctrl_hdlr->error) { |
596 | ret = ctrl_hdlr->error; |
597 | goto fail; |
598 | } |
599 | |
600 | ov01a10->sd.ctrl_handler = ctrl_hdlr; |
601 | |
602 | return 0; |
603 | fail: |
604 | v4l2_ctrl_handler_free(hdl: ctrl_hdlr); |
605 | |
606 | return ret; |
607 | } |
608 | |
609 | static void ov01a10_update_pad_format(const struct ov01a10_mode *mode, |
610 | struct v4l2_mbus_framefmt *fmt) |
611 | { |
612 | fmt->width = mode->width; |
613 | fmt->height = mode->height; |
614 | fmt->code = MEDIA_BUS_FMT_SBGGR10_1X10; |
615 | fmt->field = V4L2_FIELD_NONE; |
616 | fmt->colorspace = V4L2_COLORSPACE_RAW; |
617 | } |
618 | |
619 | static int ov01a10_start_streaming(struct ov01a10 *ov01a10) |
620 | { |
621 | struct i2c_client *client = v4l2_get_subdevdata(sd: &ov01a10->sd); |
622 | const struct ov01a10_reg_list *reg_list; |
623 | int link_freq_index; |
624 | int ret = 0; |
625 | |
626 | link_freq_index = ov01a10->cur_mode->link_freq_index; |
627 | reg_list = &link_freq_configs[link_freq_index].reg_list; |
628 | ret = ov01a10_write_reg_list(ov01a10, r_list: reg_list); |
629 | if (ret) { |
630 | dev_err(&client->dev, "failed to set plls\n" ); |
631 | return ret; |
632 | } |
633 | |
634 | reg_list = &ov01a10->cur_mode->reg_list; |
635 | ret = ov01a10_write_reg_list(ov01a10, r_list: reg_list); |
636 | if (ret) { |
637 | dev_err(&client->dev, "failed to set mode\n" ); |
638 | return ret; |
639 | } |
640 | |
641 | ret = __v4l2_ctrl_handler_setup(hdl: ov01a10->sd.ctrl_handler); |
642 | if (ret) |
643 | return ret; |
644 | |
645 | ret = ov01a10_write_reg(ov01a10, OV01A10_REG_MODE_SELECT, len: 1, |
646 | OV01A10_MODE_STREAMING); |
647 | if (ret) |
648 | dev_err(&client->dev, "failed to start streaming\n" ); |
649 | |
650 | return ret; |
651 | } |
652 | |
653 | static void ov01a10_stop_streaming(struct ov01a10 *ov01a10) |
654 | { |
655 | struct i2c_client *client = v4l2_get_subdevdata(sd: &ov01a10->sd); |
656 | int ret = 0; |
657 | |
658 | ret = ov01a10_write_reg(ov01a10, OV01A10_REG_MODE_SELECT, len: 1, |
659 | OV01A10_MODE_STANDBY); |
660 | if (ret) |
661 | dev_err(&client->dev, "failed to stop streaming\n" ); |
662 | } |
663 | |
664 | static int ov01a10_set_stream(struct v4l2_subdev *sd, int enable) |
665 | { |
666 | struct ov01a10 *ov01a10 = to_ov01a10(subdev: sd); |
667 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
668 | struct v4l2_subdev_state *state; |
669 | int ret = 0; |
670 | |
671 | state = v4l2_subdev_lock_and_get_active_state(sd); |
672 | |
673 | if (enable) { |
674 | ret = pm_runtime_resume_and_get(dev: &client->dev); |
675 | if (ret < 0) |
676 | goto unlock; |
677 | |
678 | ret = ov01a10_start_streaming(ov01a10); |
679 | if (ret) { |
680 | pm_runtime_put(dev: &client->dev); |
681 | goto unlock; |
682 | } |
683 | } else { |
684 | ov01a10_stop_streaming(ov01a10); |
685 | pm_runtime_put(dev: &client->dev); |
686 | } |
687 | |
688 | unlock: |
689 | v4l2_subdev_unlock_state(state); |
690 | |
691 | return ret; |
692 | } |
693 | |
694 | static int ov01a10_set_format(struct v4l2_subdev *sd, |
695 | struct v4l2_subdev_state *sd_state, |
696 | struct v4l2_subdev_format *fmt) |
697 | { |
698 | struct ov01a10 *ov01a10 = to_ov01a10(subdev: sd); |
699 | const struct ov01a10_mode *mode; |
700 | struct v4l2_mbus_framefmt *format; |
701 | s32 vblank_def, h_blank; |
702 | |
703 | mode = v4l2_find_nearest_size(supported_modes, |
704 | ARRAY_SIZE(supported_modes), width, |
705 | height, fmt->format.width, |
706 | fmt->format.height); |
707 | |
708 | ov01a10_update_pad_format(mode, fmt: &fmt->format); |
709 | |
710 | if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE) { |
711 | ov01a10->cur_mode = mode; |
712 | __v4l2_ctrl_s_ctrl(ctrl: ov01a10->link_freq, val: mode->link_freq_index); |
713 | __v4l2_ctrl_s_ctrl_int64(ctrl: ov01a10->pixel_rate, OV01A10_SCLK); |
714 | |
715 | vblank_def = mode->vts_def - mode->height; |
716 | __v4l2_ctrl_modify_range(ctrl: ov01a10->vblank, |
717 | min: mode->vts_min - mode->height, |
718 | OV01A10_VTS_MAX - mode->height, step: 1, |
719 | def: vblank_def); |
720 | __v4l2_ctrl_s_ctrl(ctrl: ov01a10->vblank, val: vblank_def); |
721 | h_blank = mode->hts - mode->width; |
722 | __v4l2_ctrl_modify_range(ctrl: ov01a10->hblank, min: h_blank, max: h_blank, step: 1, |
723 | def: h_blank); |
724 | } |
725 | |
726 | format = v4l2_subdev_state_get_format(sd_state, fmt->stream); |
727 | *format = fmt->format; |
728 | |
729 | return 0; |
730 | } |
731 | |
732 | static int ov01a10_init_state(struct v4l2_subdev *sd, |
733 | struct v4l2_subdev_state *state) |
734 | { |
735 | struct v4l2_subdev_format fmt = { |
736 | .which = V4L2_SUBDEV_FORMAT_TRY, |
737 | .format = { |
738 | .width = OV01A10_ACITVE_WIDTH, |
739 | .height = OV01A10_ACITVE_HEIGHT, |
740 | }, |
741 | }; |
742 | |
743 | ov01a10_set_format(sd, sd_state: state, fmt: &fmt); |
744 | |
745 | return 0; |
746 | } |
747 | |
748 | static int ov01a10_enum_mbus_code(struct v4l2_subdev *sd, |
749 | struct v4l2_subdev_state *sd_state, |
750 | struct v4l2_subdev_mbus_code_enum *code) |
751 | { |
752 | if (code->index > 0) |
753 | return -EINVAL; |
754 | |
755 | code->code = MEDIA_BUS_FMT_SBGGR10_1X10; |
756 | |
757 | return 0; |
758 | } |
759 | |
760 | static int ov01a10_enum_frame_size(struct v4l2_subdev *sd, |
761 | struct v4l2_subdev_state *sd_state, |
762 | struct v4l2_subdev_frame_size_enum *fse) |
763 | { |
764 | if (fse->index >= ARRAY_SIZE(supported_modes) || |
765 | fse->code != MEDIA_BUS_FMT_SBGGR10_1X10) |
766 | return -EINVAL; |
767 | |
768 | fse->min_width = supported_modes[fse->index].width; |
769 | fse->max_width = fse->min_width; |
770 | fse->min_height = supported_modes[fse->index].height; |
771 | fse->max_height = fse->min_height; |
772 | |
773 | return 0; |
774 | } |
775 | |
776 | static int ov01a10_get_selection(struct v4l2_subdev *sd, |
777 | struct v4l2_subdev_state *state, |
778 | struct v4l2_subdev_selection *sel) |
779 | { |
780 | if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE) |
781 | return -EINVAL; |
782 | |
783 | switch (sel->target) { |
784 | case V4L2_SEL_TGT_NATIVE_SIZE: |
785 | case V4L2_SEL_TGT_CROP_BOUNDS: |
786 | sel->r.top = 0; |
787 | sel->r.left = 0; |
788 | sel->r.width = OV01A10_PIXEL_ARRAY_WIDTH; |
789 | sel->r.height = OV01A10_PIXEL_ARRAY_HEIGHT; |
790 | return 0; |
791 | case V4L2_SEL_TGT_CROP: |
792 | case V4L2_SEL_TGT_CROP_DEFAULT: |
793 | sel->r.top = (OV01A10_PIXEL_ARRAY_HEIGHT - |
794 | OV01A10_ACITVE_HEIGHT) / 2; |
795 | sel->r.left = (OV01A10_PIXEL_ARRAY_WIDTH - |
796 | OV01A10_ACITVE_WIDTH) / 2; |
797 | sel->r.width = OV01A10_ACITVE_WIDTH; |
798 | sel->r.height = OV01A10_ACITVE_HEIGHT; |
799 | return 0; |
800 | } |
801 | |
802 | return -EINVAL; |
803 | } |
804 | |
805 | static const struct v4l2_subdev_core_ops ov01a10_core_ops = { |
806 | .log_status = v4l2_ctrl_subdev_log_status, |
807 | .subscribe_event = v4l2_ctrl_subdev_subscribe_event, |
808 | .unsubscribe_event = v4l2_event_subdev_unsubscribe, |
809 | }; |
810 | |
811 | static const struct v4l2_subdev_video_ops ov01a10_video_ops = { |
812 | .s_stream = ov01a10_set_stream, |
813 | }; |
814 | |
815 | static const struct v4l2_subdev_pad_ops ov01a10_pad_ops = { |
816 | .set_fmt = ov01a10_set_format, |
817 | .get_fmt = v4l2_subdev_get_fmt, |
818 | .get_selection = ov01a10_get_selection, |
819 | .enum_mbus_code = ov01a10_enum_mbus_code, |
820 | .enum_frame_size = ov01a10_enum_frame_size, |
821 | }; |
822 | |
823 | static const struct v4l2_subdev_ops ov01a10_subdev_ops = { |
824 | .core = &ov01a10_core_ops, |
825 | .video = &ov01a10_video_ops, |
826 | .pad = &ov01a10_pad_ops, |
827 | }; |
828 | |
829 | static const struct v4l2_subdev_internal_ops ov01a10_internal_ops = { |
830 | .init_state = ov01a10_init_state, |
831 | }; |
832 | |
833 | static const struct media_entity_operations ov01a10_subdev_entity_ops = { |
834 | .link_validate = v4l2_subdev_link_validate, |
835 | }; |
836 | |
837 | static int ov01a10_identify_module(struct ov01a10 *ov01a10) |
838 | { |
839 | struct i2c_client *client = v4l2_get_subdevdata(sd: &ov01a10->sd); |
840 | int ret; |
841 | u32 val; |
842 | |
843 | ret = ov01a10_read_reg(ov01a10, OV01A10_REG_CHIP_ID, len: 3, val: &val); |
844 | if (ret) |
845 | return ret; |
846 | |
847 | if (val != OV01A10_CHIP_ID) { |
848 | dev_err(&client->dev, "chip id mismatch: %x!=%x\n" , |
849 | OV01A10_CHIP_ID, val); |
850 | return -EIO; |
851 | } |
852 | |
853 | return 0; |
854 | } |
855 | |
856 | static void ov01a10_remove(struct i2c_client *client) |
857 | { |
858 | struct v4l2_subdev *sd = i2c_get_clientdata(client); |
859 | |
860 | v4l2_async_unregister_subdev(sd); |
861 | media_entity_cleanup(entity: &sd->entity); |
862 | v4l2_ctrl_handler_free(hdl: sd->ctrl_handler); |
863 | |
864 | pm_runtime_disable(dev: &client->dev); |
865 | pm_runtime_set_suspended(dev: &client->dev); |
866 | } |
867 | |
868 | static int ov01a10_probe(struct i2c_client *client) |
869 | { |
870 | struct device *dev = &client->dev; |
871 | struct ov01a10 *ov01a10; |
872 | int ret = 0; |
873 | |
874 | ov01a10 = devm_kzalloc(dev, size: sizeof(*ov01a10), GFP_KERNEL); |
875 | if (!ov01a10) |
876 | return -ENOMEM; |
877 | |
878 | v4l2_i2c_subdev_init(sd: &ov01a10->sd, client, ops: &ov01a10_subdev_ops); |
879 | ov01a10->sd.internal_ops = &ov01a10_internal_ops; |
880 | |
881 | ret = ov01a10_identify_module(ov01a10); |
882 | if (ret) |
883 | return dev_err_probe(dev, err: ret, |
884 | fmt: "failed to find sensor\n" ); |
885 | |
886 | ov01a10->cur_mode = &supported_modes[0]; |
887 | |
888 | ret = ov01a10_init_controls(ov01a10); |
889 | if (ret) { |
890 | dev_err(dev, "failed to init controls: %d\n" , ret); |
891 | return ret; |
892 | } |
893 | |
894 | ov01a10->sd.state_lock = ov01a10->ctrl_handler.lock; |
895 | ov01a10->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | |
896 | V4L2_SUBDEV_FL_HAS_EVENTS; |
897 | ov01a10->sd.entity.ops = &ov01a10_subdev_entity_ops; |
898 | ov01a10->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; |
899 | ov01a10->pad.flags = MEDIA_PAD_FL_SOURCE; |
900 | |
901 | ret = media_entity_pads_init(entity: &ov01a10->sd.entity, num_pads: 1, pads: &ov01a10->pad); |
902 | if (ret) { |
903 | dev_err(dev, "Failed to init entity pads: %d\n" , ret); |
904 | goto err_handler_free; |
905 | } |
906 | |
907 | ret = v4l2_subdev_init_finalize(&ov01a10->sd); |
908 | if (ret) { |
909 | dev_err(dev, "Failed to allocate subdev state: %d\n" , ret); |
910 | goto err_media_entity_cleanup; |
911 | } |
912 | |
913 | /* |
914 | * Device is already turned on by i2c-core with ACPI domain PM. |
915 | * Enable runtime PM and turn off the device. |
916 | */ |
917 | pm_runtime_set_active(dev: &client->dev); |
918 | pm_runtime_enable(dev); |
919 | pm_runtime_idle(dev); |
920 | |
921 | ret = v4l2_async_register_subdev_sensor(sd: &ov01a10->sd); |
922 | if (ret < 0) { |
923 | dev_err(dev, "Failed to register subdev: %d\n" , ret); |
924 | goto err_pm_disable; |
925 | } |
926 | |
927 | return 0; |
928 | |
929 | err_pm_disable: |
930 | pm_runtime_disable(dev); |
931 | pm_runtime_set_suspended(dev: &client->dev); |
932 | |
933 | err_media_entity_cleanup: |
934 | media_entity_cleanup(entity: &ov01a10->sd.entity); |
935 | |
936 | err_handler_free: |
937 | v4l2_ctrl_handler_free(hdl: ov01a10->sd.ctrl_handler); |
938 | |
939 | return ret; |
940 | } |
941 | |
942 | #ifdef CONFIG_ACPI |
943 | static const struct acpi_device_id ov01a10_acpi_ids[] = { |
944 | { "OVTI01A0" }, |
945 | { } |
946 | }; |
947 | |
948 | MODULE_DEVICE_TABLE(acpi, ov01a10_acpi_ids); |
949 | #endif |
950 | |
951 | static struct i2c_driver ov01a10_i2c_driver = { |
952 | .driver = { |
953 | .name = "ov01a10" , |
954 | .acpi_match_table = ACPI_PTR(ov01a10_acpi_ids), |
955 | }, |
956 | .probe = ov01a10_probe, |
957 | .remove = ov01a10_remove, |
958 | }; |
959 | |
960 | module_i2c_driver(ov01a10_i2c_driver); |
961 | |
962 | MODULE_AUTHOR("Bingbu Cao <bingbu.cao@intel.com>" ); |
963 | MODULE_AUTHOR("Wang Yating <yating.wang@intel.com>" ); |
964 | MODULE_DESCRIPTION("OmniVision OV01A10 sensor driver" ); |
965 | MODULE_LICENSE("GPL" ); |
966 | |