1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * V4L2 subdevice driver for OmniVision OV6650 Camera Sensor |
4 | * |
5 | * Copyright (C) 2010 Janusz Krzysztofik <jkrzyszt@tis.icnet.pl> |
6 | * |
7 | * Based on OmniVision OV96xx Camera Driver |
8 | * Copyright (C) 2009 Marek Vasut <marek.vasut@gmail.com> |
9 | * |
10 | * Based on ov772x camera driver: |
11 | * Copyright (C) 2008 Renesas Solutions Corp. |
12 | * Kuninori Morimoto <morimoto.kuninori@renesas.com> |
13 | * |
14 | * Based on ov7670 and soc_camera_platform driver, |
15 | * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net> |
16 | * Copyright (C) 2008 Magnus Damm |
17 | * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de> |
18 | * |
19 | * Hardware specific bits initially based on former work by Matt Callow |
20 | * drivers/media/video/omap/sensor_ov6650.c |
21 | * Copyright (C) 2006 Matt Callow |
22 | */ |
23 | |
24 | #include <linux/bitops.h> |
25 | #include <linux/clk.h> |
26 | #include <linux/delay.h> |
27 | #include <linux/i2c.h> |
28 | #include <linux/slab.h> |
29 | #include <linux/v4l2-mediabus.h> |
30 | #include <linux/module.h> |
31 | |
32 | #include <media/v4l2-ctrls.h> |
33 | #include <media/v4l2-device.h> |
34 | |
35 | /* Register definitions */ |
36 | #define REG_GAIN 0x00 /* range 00 - 3F */ |
37 | #define REG_BLUE 0x01 |
38 | #define REG_RED 0x02 |
39 | #define REG_SAT 0x03 /* [7:4] saturation [0:3] reserved */ |
40 | #define REG_HUE 0x04 /* [7:6] rsrvd [5] hue en [4:0] hue */ |
41 | |
42 | #define REG_BRT 0x06 |
43 | |
44 | #define REG_PIDH 0x0a |
45 | #define REG_PIDL 0x0b |
46 | |
47 | #define REG_AECH 0x10 |
48 | #define REG_CLKRC 0x11 /* Data Format and Internal Clock */ |
49 | /* [7:6] Input system clock (MHz)*/ |
50 | /* 00=8, 01=12, 10=16, 11=24 */ |
51 | /* [5:0]: Internal Clock Pre-Scaler */ |
52 | #define REG_COMA 0x12 /* [7] Reset */ |
53 | #define REG_COMB 0x13 |
54 | #define REG_COMC 0x14 |
55 | #define REG_COMD 0x15 |
56 | #define REG_COML 0x16 |
57 | #define REG_HSTRT 0x17 |
58 | #define REG_HSTOP 0x18 |
59 | #define REG_VSTRT 0x19 |
60 | #define REG_VSTOP 0x1a |
61 | #define REG_PSHFT 0x1b |
62 | #define REG_MIDH 0x1c |
63 | #define REG_MIDL 0x1d |
64 | #define REG_HSYNS 0x1e |
65 | #define REG_HSYNE 0x1f |
66 | #define REG_COME 0x20 |
67 | #define REG_YOFF 0x21 |
68 | #define REG_UOFF 0x22 |
69 | #define REG_VOFF 0x23 |
70 | #define REG_AEW 0x24 |
71 | #define REG_AEB 0x25 |
72 | #define REG_COMF 0x26 |
73 | #define REG_COMG 0x27 |
74 | #define REG_COMH 0x28 |
75 | #define REG_COMI 0x29 |
76 | |
77 | #define REG_FRARL 0x2b |
78 | #define REG_COMJ 0x2c |
79 | #define REG_COMK 0x2d |
80 | #define REG_AVGY 0x2e |
81 | #define REG_REF0 0x2f |
82 | #define REG_REF1 0x30 |
83 | #define REG_REF2 0x31 |
84 | #define REG_FRAJH 0x32 |
85 | #define REG_FRAJL 0x33 |
86 | #define REG_FACT 0x34 |
87 | #define REG_L1AEC 0x35 |
88 | #define REG_AVGU 0x36 |
89 | #define REG_AVGV 0x37 |
90 | |
91 | #define REG_SPCB 0x60 |
92 | #define REG_SPCC 0x61 |
93 | #define REG_GAM1 0x62 |
94 | #define REG_GAM2 0x63 |
95 | #define REG_GAM3 0x64 |
96 | #define REG_SPCD 0x65 |
97 | |
98 | #define REG_SPCE 0x68 |
99 | #define REG_ADCL 0x69 |
100 | |
101 | #define REG_RMCO 0x6c |
102 | #define REG_GMCO 0x6d |
103 | #define REG_BMCO 0x6e |
104 | |
105 | |
106 | /* Register bits, values, etc. */ |
107 | #define OV6650_PIDH 0x66 /* high byte of product ID number */ |
108 | #define OV6650_PIDL 0x50 /* low byte of product ID number */ |
109 | #define OV6650_MIDH 0x7F /* high byte of mfg ID */ |
110 | #define OV6650_MIDL 0xA2 /* low byte of mfg ID */ |
111 | |
112 | #define DEF_GAIN 0x00 |
113 | #define DEF_BLUE 0x80 |
114 | #define DEF_RED 0x80 |
115 | |
116 | #define SAT_SHIFT 4 |
117 | #define SAT_MASK (0xf << SAT_SHIFT) |
118 | #define SET_SAT(x) (((x) << SAT_SHIFT) & SAT_MASK) |
119 | |
120 | #define HUE_EN BIT(5) |
121 | #define HUE_MASK 0x1f |
122 | #define DEF_HUE 0x10 |
123 | #define SET_HUE(x) (HUE_EN | ((x) & HUE_MASK)) |
124 | |
125 | #define DEF_AECH 0x4D |
126 | |
127 | #define CLKRC_8MHz 0x00 |
128 | #define CLKRC_12MHz 0x40 |
129 | #define CLKRC_16MHz 0x80 |
130 | #define CLKRC_24MHz 0xc0 |
131 | #define CLKRC_DIV_MASK 0x3f |
132 | #define GET_CLKRC_DIV(x) (((x) & CLKRC_DIV_MASK) + 1) |
133 | #define DEF_CLKRC 0x00 |
134 | |
135 | #define COMA_RESET BIT(7) |
136 | #define COMA_QCIF BIT(5) |
137 | #define COMA_RAW_RGB BIT(4) |
138 | #define COMA_RGB BIT(3) |
139 | #define COMA_BW BIT(2) |
140 | #define COMA_WORD_SWAP BIT(1) |
141 | #define COMA_BYTE_SWAP BIT(0) |
142 | #define DEF_COMA 0x00 |
143 | |
144 | #define COMB_FLIP_V BIT(7) |
145 | #define COMB_FLIP_H BIT(5) |
146 | #define COMB_BAND_FILTER BIT(4) |
147 | #define COMB_AWB BIT(2) |
148 | #define COMB_AGC BIT(1) |
149 | #define COMB_AEC BIT(0) |
150 | #define DEF_COMB 0x5f |
151 | |
152 | #define COML_ONE_CHANNEL BIT(7) |
153 | |
154 | #define DEF_HSTRT 0x24 |
155 | #define DEF_HSTOP 0xd4 |
156 | #define DEF_VSTRT 0x04 |
157 | #define DEF_VSTOP 0x94 |
158 | |
159 | #define COMF_HREF_LOW BIT(4) |
160 | |
161 | #define COMJ_PCLK_RISING BIT(4) |
162 | #define COMJ_VSYNC_HIGH BIT(0) |
163 | |
164 | /* supported resolutions */ |
165 | #define W_QCIF (DEF_HSTOP - DEF_HSTRT) |
166 | #define W_CIF (W_QCIF << 1) |
167 | #define H_QCIF (DEF_VSTOP - DEF_VSTRT) |
168 | #define H_CIF (H_QCIF << 1) |
169 | |
170 | #define FRAME_RATE_MAX 30 |
171 | |
172 | |
173 | struct ov6650_reg { |
174 | u8 reg; |
175 | u8 val; |
176 | }; |
177 | |
178 | struct ov6650 { |
179 | struct v4l2_subdev subdev; |
180 | struct v4l2_ctrl_handler hdl; |
181 | struct { |
182 | /* exposure/autoexposure cluster */ |
183 | struct v4l2_ctrl *autoexposure; |
184 | struct v4l2_ctrl *exposure; |
185 | }; |
186 | struct { |
187 | /* gain/autogain cluster */ |
188 | struct v4l2_ctrl *autogain; |
189 | struct v4l2_ctrl *gain; |
190 | }; |
191 | struct { |
192 | /* blue/red/autowhitebalance cluster */ |
193 | struct v4l2_ctrl *autowb; |
194 | struct v4l2_ctrl *blue; |
195 | struct v4l2_ctrl *red; |
196 | }; |
197 | struct clk *clk; |
198 | bool half_scale; /* scale down output by 2 */ |
199 | struct v4l2_rect rect; /* sensor cropping window */ |
200 | struct v4l2_fract tpf; /* as requested with set_frame_interval */ |
201 | u32 code; |
202 | }; |
203 | |
204 | struct ov6650_xclk { |
205 | unsigned long rate; |
206 | u8 clkrc; |
207 | }; |
208 | |
209 | static const struct ov6650_xclk ov6650_xclk[] = { |
210 | { |
211 | .rate = 8000000, |
212 | .clkrc = CLKRC_8MHz, |
213 | }, |
214 | { |
215 | .rate = 12000000, |
216 | .clkrc = CLKRC_12MHz, |
217 | }, |
218 | { |
219 | .rate = 16000000, |
220 | .clkrc = CLKRC_16MHz, |
221 | }, |
222 | { |
223 | .rate = 24000000, |
224 | .clkrc = CLKRC_24MHz, |
225 | }, |
226 | }; |
227 | |
228 | static u32 ov6650_codes[] = { |
229 | MEDIA_BUS_FMT_YUYV8_2X8, |
230 | MEDIA_BUS_FMT_UYVY8_2X8, |
231 | MEDIA_BUS_FMT_YVYU8_2X8, |
232 | MEDIA_BUS_FMT_VYUY8_2X8, |
233 | MEDIA_BUS_FMT_SBGGR8_1X8, |
234 | MEDIA_BUS_FMT_Y8_1X8, |
235 | }; |
236 | |
237 | static const struct v4l2_mbus_framefmt ov6650_def_fmt = { |
238 | .width = W_CIF, |
239 | .height = H_CIF, |
240 | .code = MEDIA_BUS_FMT_SBGGR8_1X8, |
241 | .colorspace = V4L2_COLORSPACE_SRGB, |
242 | .field = V4L2_FIELD_NONE, |
243 | .ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT, |
244 | .quantization = V4L2_QUANTIZATION_DEFAULT, |
245 | .xfer_func = V4L2_XFER_FUNC_DEFAULT, |
246 | }; |
247 | |
248 | /* read a register */ |
249 | static int ov6650_reg_read(struct i2c_client *client, u8 reg, u8 *val) |
250 | { |
251 | int ret; |
252 | u8 data = reg; |
253 | struct i2c_msg msg = { |
254 | .addr = client->addr, |
255 | .flags = 0, |
256 | .len = 1, |
257 | .buf = &data, |
258 | }; |
259 | |
260 | ret = i2c_transfer(adap: client->adapter, msgs: &msg, num: 1); |
261 | if (ret < 0) |
262 | goto err; |
263 | |
264 | msg.flags = I2C_M_RD; |
265 | ret = i2c_transfer(adap: client->adapter, msgs: &msg, num: 1); |
266 | if (ret < 0) |
267 | goto err; |
268 | |
269 | *val = data; |
270 | return 0; |
271 | |
272 | err: |
273 | dev_err(&client->dev, "Failed reading register 0x%02x!\n" , reg); |
274 | return ret; |
275 | } |
276 | |
277 | /* write a register */ |
278 | static int ov6650_reg_write(struct i2c_client *client, u8 reg, u8 val) |
279 | { |
280 | int ret; |
281 | unsigned char data[2] = { reg, val }; |
282 | struct i2c_msg msg = { |
283 | .addr = client->addr, |
284 | .flags = 0, |
285 | .len = 2, |
286 | .buf = data, |
287 | }; |
288 | |
289 | ret = i2c_transfer(adap: client->adapter, msgs: &msg, num: 1); |
290 | udelay(100); |
291 | |
292 | if (ret < 0) { |
293 | dev_err(&client->dev, "Failed writing register 0x%02x!\n" , reg); |
294 | return ret; |
295 | } |
296 | return 0; |
297 | } |
298 | |
299 | |
300 | /* Read a register, alter its bits, write it back */ |
301 | static int ov6650_reg_rmw(struct i2c_client *client, u8 reg, u8 set, u8 mask) |
302 | { |
303 | u8 val; |
304 | int ret; |
305 | |
306 | ret = ov6650_reg_read(client, reg, val: &val); |
307 | if (ret) { |
308 | dev_err(&client->dev, |
309 | "[Read]-Modify-Write of register 0x%02x failed!\n" , |
310 | reg); |
311 | return ret; |
312 | } |
313 | |
314 | val &= ~mask; |
315 | val |= set; |
316 | |
317 | ret = ov6650_reg_write(client, reg, val); |
318 | if (ret) |
319 | dev_err(&client->dev, |
320 | "Read-Modify-[Write] of register 0x%02x failed!\n" , |
321 | reg); |
322 | |
323 | return ret; |
324 | } |
325 | |
326 | static struct ov6650 *to_ov6650(const struct i2c_client *client) |
327 | { |
328 | return container_of(i2c_get_clientdata(client), struct ov6650, subdev); |
329 | } |
330 | |
331 | /* Start/Stop streaming from the device */ |
332 | static int ov6650_s_stream(struct v4l2_subdev *sd, int enable) |
333 | { |
334 | return 0; |
335 | } |
336 | |
337 | /* Get status of additional camera capabilities */ |
338 | static int ov6550_g_volatile_ctrl(struct v4l2_ctrl *ctrl) |
339 | { |
340 | struct ov6650 *priv = container_of(ctrl->handler, struct ov6650, hdl); |
341 | struct v4l2_subdev *sd = &priv->subdev; |
342 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
343 | uint8_t reg, reg2; |
344 | int ret; |
345 | |
346 | switch (ctrl->id) { |
347 | case V4L2_CID_AUTOGAIN: |
348 | ret = ov6650_reg_read(client, REG_GAIN, val: ®); |
349 | if (!ret) |
350 | priv->gain->val = reg; |
351 | return ret; |
352 | case V4L2_CID_AUTO_WHITE_BALANCE: |
353 | ret = ov6650_reg_read(client, REG_BLUE, val: ®); |
354 | if (!ret) |
355 | ret = ov6650_reg_read(client, REG_RED, val: ®2); |
356 | if (!ret) { |
357 | priv->blue->val = reg; |
358 | priv->red->val = reg2; |
359 | } |
360 | return ret; |
361 | case V4L2_CID_EXPOSURE_AUTO: |
362 | ret = ov6650_reg_read(client, REG_AECH, val: ®); |
363 | if (!ret) |
364 | priv->exposure->val = reg; |
365 | return ret; |
366 | } |
367 | return -EINVAL; |
368 | } |
369 | |
370 | /* Set status of additional camera capabilities */ |
371 | static int ov6550_s_ctrl(struct v4l2_ctrl *ctrl) |
372 | { |
373 | struct ov6650 *priv = container_of(ctrl->handler, struct ov6650, hdl); |
374 | struct v4l2_subdev *sd = &priv->subdev; |
375 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
376 | int ret; |
377 | |
378 | switch (ctrl->id) { |
379 | case V4L2_CID_AUTOGAIN: |
380 | ret = ov6650_reg_rmw(client, REG_COMB, |
381 | set: ctrl->val ? COMB_AGC : 0, COMB_AGC); |
382 | if (!ret && !ctrl->val) |
383 | ret = ov6650_reg_write(client, REG_GAIN, val: priv->gain->val); |
384 | return ret; |
385 | case V4L2_CID_AUTO_WHITE_BALANCE: |
386 | ret = ov6650_reg_rmw(client, REG_COMB, |
387 | set: ctrl->val ? COMB_AWB : 0, COMB_AWB); |
388 | if (!ret && !ctrl->val) { |
389 | ret = ov6650_reg_write(client, REG_BLUE, val: priv->blue->val); |
390 | if (!ret) |
391 | ret = ov6650_reg_write(client, REG_RED, |
392 | val: priv->red->val); |
393 | } |
394 | return ret; |
395 | case V4L2_CID_SATURATION: |
396 | return ov6650_reg_rmw(client, REG_SAT, SET_SAT(ctrl->val), |
397 | SAT_MASK); |
398 | case V4L2_CID_HUE: |
399 | return ov6650_reg_rmw(client, REG_HUE, SET_HUE(ctrl->val), |
400 | HUE_MASK); |
401 | case V4L2_CID_BRIGHTNESS: |
402 | return ov6650_reg_write(client, REG_BRT, val: ctrl->val); |
403 | case V4L2_CID_EXPOSURE_AUTO: |
404 | ret = ov6650_reg_rmw(client, REG_COMB, set: ctrl->val == |
405 | V4L2_EXPOSURE_AUTO ? COMB_AEC : 0, COMB_AEC); |
406 | if (!ret && ctrl->val == V4L2_EXPOSURE_MANUAL) |
407 | ret = ov6650_reg_write(client, REG_AECH, |
408 | val: priv->exposure->val); |
409 | return ret; |
410 | case V4L2_CID_GAMMA: |
411 | return ov6650_reg_write(client, REG_GAM1, val: ctrl->val); |
412 | case V4L2_CID_VFLIP: |
413 | return ov6650_reg_rmw(client, REG_COMB, |
414 | set: ctrl->val ? COMB_FLIP_V : 0, COMB_FLIP_V); |
415 | case V4L2_CID_HFLIP: |
416 | return ov6650_reg_rmw(client, REG_COMB, |
417 | set: ctrl->val ? COMB_FLIP_H : 0, COMB_FLIP_H); |
418 | } |
419 | |
420 | return -EINVAL; |
421 | } |
422 | |
423 | #ifdef CONFIG_VIDEO_ADV_DEBUG |
424 | static int ov6650_get_register(struct v4l2_subdev *sd, |
425 | struct v4l2_dbg_register *reg) |
426 | { |
427 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
428 | int ret; |
429 | u8 val; |
430 | |
431 | if (reg->reg & ~0xff) |
432 | return -EINVAL; |
433 | |
434 | reg->size = 1; |
435 | |
436 | ret = ov6650_reg_read(client, reg: reg->reg, val: &val); |
437 | if (!ret) |
438 | reg->val = (__u64)val; |
439 | |
440 | return ret; |
441 | } |
442 | |
443 | static int ov6650_set_register(struct v4l2_subdev *sd, |
444 | const struct v4l2_dbg_register *reg) |
445 | { |
446 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
447 | |
448 | if (reg->reg & ~0xff || reg->val & ~0xff) |
449 | return -EINVAL; |
450 | |
451 | return ov6650_reg_write(client, reg: reg->reg, val: reg->val); |
452 | } |
453 | #endif |
454 | |
455 | static int ov6650_s_power(struct v4l2_subdev *sd, int on) |
456 | { |
457 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
458 | struct ov6650 *priv = to_ov6650(client); |
459 | int ret = 0; |
460 | |
461 | if (on) |
462 | ret = clk_prepare_enable(clk: priv->clk); |
463 | else |
464 | clk_disable_unprepare(clk: priv->clk); |
465 | |
466 | return ret; |
467 | } |
468 | |
469 | static int ov6650_get_selection(struct v4l2_subdev *sd, |
470 | struct v4l2_subdev_state *sd_state, |
471 | struct v4l2_subdev_selection *sel) |
472 | { |
473 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
474 | struct ov6650 *priv = to_ov6650(client); |
475 | struct v4l2_rect *rect; |
476 | |
477 | if (sel->which == V4L2_SUBDEV_FORMAT_TRY) { |
478 | /* pre-select try crop rectangle */ |
479 | rect = v4l2_subdev_state_get_crop(sd_state, 0); |
480 | |
481 | } else { |
482 | /* pre-select active crop rectangle */ |
483 | rect = &priv->rect; |
484 | } |
485 | |
486 | switch (sel->target) { |
487 | case V4L2_SEL_TGT_CROP_BOUNDS: |
488 | sel->r.left = DEF_HSTRT << 1; |
489 | sel->r.top = DEF_VSTRT << 1; |
490 | sel->r.width = W_CIF; |
491 | sel->r.height = H_CIF; |
492 | return 0; |
493 | |
494 | case V4L2_SEL_TGT_CROP: |
495 | /* use selected crop rectangle */ |
496 | sel->r = *rect; |
497 | return 0; |
498 | |
499 | default: |
500 | return -EINVAL; |
501 | } |
502 | } |
503 | |
504 | static bool is_unscaled_ok(int width, int height, struct v4l2_rect *rect) |
505 | { |
506 | return width > rect->width >> 1 || height > rect->height >> 1; |
507 | } |
508 | |
509 | static void ov6650_bind_align_crop_rectangle(struct v4l2_rect *rect) |
510 | { |
511 | v4l_bound_align_image(width: &rect->width, wmin: 2, W_CIF, walign: 1, |
512 | height: &rect->height, hmin: 2, H_CIF, halign: 1, salign: 0); |
513 | v4l_bound_align_image(width: &rect->left, DEF_HSTRT << 1, |
514 | wmax: (DEF_HSTRT << 1) + W_CIF - (__s32)rect->width, walign: 1, |
515 | height: &rect->top, DEF_VSTRT << 1, |
516 | hmax: (DEF_VSTRT << 1) + H_CIF - (__s32)rect->height, |
517 | halign: 1, salign: 0); |
518 | } |
519 | |
520 | static int ov6650_set_selection(struct v4l2_subdev *sd, |
521 | struct v4l2_subdev_state *sd_state, |
522 | struct v4l2_subdev_selection *sel) |
523 | { |
524 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
525 | struct ov6650 *priv = to_ov6650(client); |
526 | int ret; |
527 | |
528 | if (sel->target != V4L2_SEL_TGT_CROP) |
529 | return -EINVAL; |
530 | |
531 | ov6650_bind_align_crop_rectangle(rect: &sel->r); |
532 | |
533 | if (sel->which == V4L2_SUBDEV_FORMAT_TRY) { |
534 | struct v4l2_rect *crop = |
535 | v4l2_subdev_state_get_crop(sd_state, 0); |
536 | struct v4l2_mbus_framefmt *mf = |
537 | v4l2_subdev_state_get_format(sd_state, 0); |
538 | /* detect current pad config scaling factor */ |
539 | bool half_scale = !is_unscaled_ok(width: mf->width, height: mf->height, rect: crop); |
540 | |
541 | /* store new crop rectangle */ |
542 | *crop = sel->r; |
543 | |
544 | /* adjust frame size */ |
545 | mf->width = crop->width >> half_scale; |
546 | mf->height = crop->height >> half_scale; |
547 | |
548 | return 0; |
549 | } |
550 | |
551 | /* V4L2_SUBDEV_FORMAT_ACTIVE */ |
552 | |
553 | /* apply new crop rectangle */ |
554 | ret = ov6650_reg_write(client, REG_HSTRT, val: sel->r.left >> 1); |
555 | if (!ret) { |
556 | priv->rect.width += priv->rect.left - sel->r.left; |
557 | priv->rect.left = sel->r.left; |
558 | ret = ov6650_reg_write(client, REG_HSTOP, |
559 | val: (sel->r.left + sel->r.width) >> 1); |
560 | } |
561 | if (!ret) { |
562 | priv->rect.width = sel->r.width; |
563 | ret = ov6650_reg_write(client, REG_VSTRT, val: sel->r.top >> 1); |
564 | } |
565 | if (!ret) { |
566 | priv->rect.height += priv->rect.top - sel->r.top; |
567 | priv->rect.top = sel->r.top; |
568 | ret = ov6650_reg_write(client, REG_VSTOP, |
569 | val: (sel->r.top + sel->r.height) >> 1); |
570 | } |
571 | if (!ret) |
572 | priv->rect.height = sel->r.height; |
573 | |
574 | return ret; |
575 | } |
576 | |
577 | static int ov6650_get_fmt(struct v4l2_subdev *sd, |
578 | struct v4l2_subdev_state *sd_state, |
579 | struct v4l2_subdev_format *format) |
580 | { |
581 | struct v4l2_mbus_framefmt *mf = &format->format; |
582 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
583 | struct ov6650 *priv = to_ov6650(client); |
584 | |
585 | if (format->pad) |
586 | return -EINVAL; |
587 | |
588 | /* initialize response with default media bus frame format */ |
589 | *mf = ov6650_def_fmt; |
590 | |
591 | /* update media bus format code and frame size */ |
592 | if (format->which == V4L2_SUBDEV_FORMAT_TRY) { |
593 | struct v4l2_mbus_framefmt *try_fmt = |
594 | v4l2_subdev_state_get_format(sd_state, 0); |
595 | |
596 | mf->width = try_fmt->width; |
597 | mf->height = try_fmt->height; |
598 | mf->code = try_fmt->code; |
599 | |
600 | } else { |
601 | mf->width = priv->rect.width >> priv->half_scale; |
602 | mf->height = priv->rect.height >> priv->half_scale; |
603 | mf->code = priv->code; |
604 | } |
605 | return 0; |
606 | } |
607 | |
608 | #define to_clkrc(div) ((div) - 1) |
609 | |
610 | /* set the format we will capture in */ |
611 | static int ov6650_s_fmt(struct v4l2_subdev *sd, u32 code, bool half_scale) |
612 | { |
613 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
614 | struct ov6650 *priv = to_ov6650(client); |
615 | u8 coma_set = 0, coma_mask = 0, coml_set, coml_mask; |
616 | int ret; |
617 | |
618 | /* select color matrix configuration for given color encoding */ |
619 | switch (code) { |
620 | case MEDIA_BUS_FMT_Y8_1X8: |
621 | dev_dbg(&client->dev, "pixel format GREY8_1X8\n" ); |
622 | coma_mask |= COMA_RGB | COMA_WORD_SWAP | COMA_BYTE_SWAP; |
623 | coma_set |= COMA_BW; |
624 | break; |
625 | case MEDIA_BUS_FMT_YUYV8_2X8: |
626 | dev_dbg(&client->dev, "pixel format YUYV8_2X8_LE\n" ); |
627 | coma_mask |= COMA_RGB | COMA_BW | COMA_BYTE_SWAP; |
628 | coma_set |= COMA_WORD_SWAP; |
629 | break; |
630 | case MEDIA_BUS_FMT_YVYU8_2X8: |
631 | dev_dbg(&client->dev, "pixel format YVYU8_2X8_LE (untested)\n" ); |
632 | coma_mask |= COMA_RGB | COMA_BW | COMA_WORD_SWAP | |
633 | COMA_BYTE_SWAP; |
634 | break; |
635 | case MEDIA_BUS_FMT_UYVY8_2X8: |
636 | dev_dbg(&client->dev, "pixel format YUYV8_2X8_BE\n" ); |
637 | if (half_scale) { |
638 | coma_mask |= COMA_RGB | COMA_BW | COMA_WORD_SWAP; |
639 | coma_set |= COMA_BYTE_SWAP; |
640 | } else { |
641 | coma_mask |= COMA_RGB | COMA_BW; |
642 | coma_set |= COMA_BYTE_SWAP | COMA_WORD_SWAP; |
643 | } |
644 | break; |
645 | case MEDIA_BUS_FMT_VYUY8_2X8: |
646 | dev_dbg(&client->dev, "pixel format YVYU8_2X8_BE (untested)\n" ); |
647 | if (half_scale) { |
648 | coma_mask |= COMA_RGB | COMA_BW; |
649 | coma_set |= COMA_BYTE_SWAP | COMA_WORD_SWAP; |
650 | } else { |
651 | coma_mask |= COMA_RGB | COMA_BW | COMA_WORD_SWAP; |
652 | coma_set |= COMA_BYTE_SWAP; |
653 | } |
654 | break; |
655 | case MEDIA_BUS_FMT_SBGGR8_1X8: |
656 | dev_dbg(&client->dev, "pixel format SBGGR8_1X8 (untested)\n" ); |
657 | coma_mask |= COMA_BW | COMA_BYTE_SWAP | COMA_WORD_SWAP; |
658 | coma_set |= COMA_RAW_RGB | COMA_RGB; |
659 | break; |
660 | default: |
661 | dev_err(&client->dev, "Pixel format not handled: 0x%x\n" , code); |
662 | return -EINVAL; |
663 | } |
664 | |
665 | if (code == MEDIA_BUS_FMT_Y8_1X8 || |
666 | code == MEDIA_BUS_FMT_SBGGR8_1X8) { |
667 | coml_mask = COML_ONE_CHANNEL; |
668 | coml_set = 0; |
669 | } else { |
670 | coml_mask = 0; |
671 | coml_set = COML_ONE_CHANNEL; |
672 | } |
673 | |
674 | if (half_scale) { |
675 | dev_dbg(&client->dev, "max resolution: QCIF\n" ); |
676 | coma_set |= COMA_QCIF; |
677 | } else { |
678 | dev_dbg(&client->dev, "max resolution: CIF\n" ); |
679 | coma_mask |= COMA_QCIF; |
680 | } |
681 | |
682 | ret = ov6650_reg_rmw(client, REG_COMA, set: coma_set, mask: coma_mask); |
683 | if (!ret) { |
684 | priv->half_scale = half_scale; |
685 | |
686 | ret = ov6650_reg_rmw(client, REG_COML, set: coml_set, mask: coml_mask); |
687 | } |
688 | if (!ret) |
689 | priv->code = code; |
690 | |
691 | return ret; |
692 | } |
693 | |
694 | static int ov6650_set_fmt(struct v4l2_subdev *sd, |
695 | struct v4l2_subdev_state *sd_state, |
696 | struct v4l2_subdev_format *format) |
697 | { |
698 | struct v4l2_mbus_framefmt *mf = &format->format; |
699 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
700 | struct ov6650 *priv = to_ov6650(client); |
701 | struct v4l2_rect *crop; |
702 | bool half_scale; |
703 | |
704 | if (format->pad) |
705 | return -EINVAL; |
706 | |
707 | switch (mf->code) { |
708 | case MEDIA_BUS_FMT_Y10_1X10: |
709 | mf->code = MEDIA_BUS_FMT_Y8_1X8; |
710 | fallthrough; |
711 | case MEDIA_BUS_FMT_Y8_1X8: |
712 | case MEDIA_BUS_FMT_YVYU8_2X8: |
713 | case MEDIA_BUS_FMT_YUYV8_2X8: |
714 | case MEDIA_BUS_FMT_VYUY8_2X8: |
715 | case MEDIA_BUS_FMT_UYVY8_2X8: |
716 | break; |
717 | default: |
718 | mf->code = MEDIA_BUS_FMT_SBGGR8_1X8; |
719 | fallthrough; |
720 | case MEDIA_BUS_FMT_SBGGR8_1X8: |
721 | break; |
722 | } |
723 | |
724 | if (format->which == V4L2_SUBDEV_FORMAT_TRY) |
725 | crop = v4l2_subdev_state_get_crop(sd_state, 0); |
726 | else |
727 | crop = &priv->rect; |
728 | |
729 | half_scale = !is_unscaled_ok(width: mf->width, height: mf->height, rect: crop); |
730 | |
731 | if (format->which == V4L2_SUBDEV_FORMAT_TRY) { |
732 | struct v4l2_mbus_framefmt *try_fmt = |
733 | v4l2_subdev_state_get_format(sd_state, 0); |
734 | |
735 | /* store new mbus frame format code and size in pad config */ |
736 | try_fmt->width = crop->width >> half_scale; |
737 | try_fmt->height = crop->height >> half_scale; |
738 | try_fmt->code = mf->code; |
739 | |
740 | /* return default mbus frame format updated with pad config */ |
741 | *mf = ov6650_def_fmt; |
742 | mf->width = try_fmt->width; |
743 | mf->height = try_fmt->height; |
744 | mf->code = try_fmt->code; |
745 | |
746 | } else { |
747 | int ret = 0; |
748 | |
749 | /* apply new media bus frame format and scaling if changed */ |
750 | if (mf->code != priv->code || half_scale != priv->half_scale) |
751 | ret = ov6650_s_fmt(sd, code: mf->code, half_scale); |
752 | if (ret) |
753 | return ret; |
754 | |
755 | /* return default format updated with active size and code */ |
756 | *mf = ov6650_def_fmt; |
757 | mf->width = priv->rect.width >> priv->half_scale; |
758 | mf->height = priv->rect.height >> priv->half_scale; |
759 | mf->code = priv->code; |
760 | } |
761 | return 0; |
762 | } |
763 | |
764 | static int ov6650_enum_mbus_code(struct v4l2_subdev *sd, |
765 | struct v4l2_subdev_state *sd_state, |
766 | struct v4l2_subdev_mbus_code_enum *code) |
767 | { |
768 | if (code->pad || code->index >= ARRAY_SIZE(ov6650_codes)) |
769 | return -EINVAL; |
770 | |
771 | code->code = ov6650_codes[code->index]; |
772 | return 0; |
773 | } |
774 | |
775 | static int ov6650_enum_frame_interval(struct v4l2_subdev *sd, |
776 | struct v4l2_subdev_state *sd_state, |
777 | struct v4l2_subdev_frame_interval_enum *fie) |
778 | { |
779 | int i; |
780 | |
781 | /* enumerate supported frame intervals not exceeding 1 second */ |
782 | if (fie->index > CLKRC_DIV_MASK || |
783 | GET_CLKRC_DIV(fie->index) > FRAME_RATE_MAX) |
784 | return -EINVAL; |
785 | |
786 | for (i = 0; i < ARRAY_SIZE(ov6650_codes); i++) |
787 | if (fie->code == ov6650_codes[i]) |
788 | break; |
789 | if (i == ARRAY_SIZE(ov6650_codes)) |
790 | return -EINVAL; |
791 | |
792 | if (!fie->width || fie->width > W_CIF || |
793 | !fie->height || fie->height > H_CIF) |
794 | return -EINVAL; |
795 | |
796 | fie->interval.numerator = GET_CLKRC_DIV(fie->index); |
797 | fie->interval.denominator = FRAME_RATE_MAX; |
798 | |
799 | return 0; |
800 | } |
801 | |
802 | static int ov6650_get_frame_interval(struct v4l2_subdev *sd, |
803 | struct v4l2_subdev_state *sd_state, |
804 | struct v4l2_subdev_frame_interval *ival) |
805 | { |
806 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
807 | struct ov6650 *priv = to_ov6650(client); |
808 | |
809 | /* |
810 | * FIXME: Implement support for V4L2_SUBDEV_FORMAT_TRY, using the V4L2 |
811 | * subdev active state API. |
812 | */ |
813 | if (ival->which != V4L2_SUBDEV_FORMAT_ACTIVE) |
814 | return -EINVAL; |
815 | |
816 | ival->interval = priv->tpf; |
817 | |
818 | dev_dbg(&client->dev, "Frame interval: %u/%u s\n" , |
819 | ival->interval.numerator, ival->interval.denominator); |
820 | |
821 | return 0; |
822 | } |
823 | |
824 | static int ov6650_set_frame_interval(struct v4l2_subdev *sd, |
825 | struct v4l2_subdev_state *sd_state, |
826 | struct v4l2_subdev_frame_interval *ival) |
827 | { |
828 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
829 | struct ov6650 *priv = to_ov6650(client); |
830 | struct v4l2_fract *tpf = &ival->interval; |
831 | int div, ret; |
832 | |
833 | /* |
834 | * FIXME: Implement support for V4L2_SUBDEV_FORMAT_TRY, using the V4L2 |
835 | * subdev active state API. |
836 | */ |
837 | if (ival->which != V4L2_SUBDEV_FORMAT_ACTIVE) |
838 | return -EINVAL; |
839 | |
840 | if (tpf->numerator == 0 || tpf->denominator == 0) |
841 | div = 1; /* Reset to full rate */ |
842 | else |
843 | div = (tpf->numerator * FRAME_RATE_MAX) / tpf->denominator; |
844 | |
845 | if (div == 0) |
846 | div = 1; |
847 | else if (div > GET_CLKRC_DIV(CLKRC_DIV_MASK)) |
848 | div = GET_CLKRC_DIV(CLKRC_DIV_MASK); |
849 | |
850 | ret = ov6650_reg_rmw(client, REG_CLKRC, to_clkrc(div), CLKRC_DIV_MASK); |
851 | if (!ret) { |
852 | priv->tpf.numerator = div; |
853 | priv->tpf.denominator = FRAME_RATE_MAX; |
854 | |
855 | *tpf = priv->tpf; |
856 | } |
857 | |
858 | return ret; |
859 | } |
860 | |
861 | /* Soft reset the camera. This has nothing to do with the RESET pin! */ |
862 | static int ov6650_reset(struct i2c_client *client) |
863 | { |
864 | int ret; |
865 | |
866 | dev_dbg(&client->dev, "reset\n" ); |
867 | |
868 | ret = ov6650_reg_rmw(client, REG_COMA, COMA_RESET, mask: 0); |
869 | if (ret) |
870 | dev_err(&client->dev, |
871 | "An error occurred while entering soft reset!\n" ); |
872 | |
873 | return ret; |
874 | } |
875 | |
876 | /* program default register values */ |
877 | static int ov6650_prog_dflt(struct i2c_client *client, u8 clkrc) |
878 | { |
879 | int ret; |
880 | |
881 | dev_dbg(&client->dev, "initializing\n" ); |
882 | |
883 | ret = ov6650_reg_write(client, REG_COMA, val: 0); /* ~COMA_RESET */ |
884 | if (!ret) |
885 | ret = ov6650_reg_write(client, REG_CLKRC, val: clkrc); |
886 | if (!ret) |
887 | ret = ov6650_reg_rmw(client, REG_COMB, set: 0, COMB_BAND_FILTER); |
888 | |
889 | return ret; |
890 | } |
891 | |
892 | static int ov6650_video_probe(struct v4l2_subdev *sd) |
893 | { |
894 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
895 | struct ov6650 *priv = to_ov6650(client); |
896 | const struct ov6650_xclk *xclk = NULL; |
897 | unsigned long rate; |
898 | u8 pidh, pidl, midh, midl; |
899 | int i, ret = 0; |
900 | |
901 | priv->clk = devm_clk_get(dev: &client->dev, NULL); |
902 | if (IS_ERR(ptr: priv->clk)) { |
903 | ret = PTR_ERR(ptr: priv->clk); |
904 | dev_err(&client->dev, "clk request err: %d\n" , ret); |
905 | return ret; |
906 | } |
907 | |
908 | rate = clk_get_rate(clk: priv->clk); |
909 | for (i = 0; rate && i < ARRAY_SIZE(ov6650_xclk); i++) { |
910 | if (rate != ov6650_xclk[i].rate) |
911 | continue; |
912 | |
913 | xclk = &ov6650_xclk[i]; |
914 | dev_info(&client->dev, "using host default clock rate %lukHz\n" , |
915 | rate / 1000); |
916 | break; |
917 | } |
918 | for (i = 0; !xclk && i < ARRAY_SIZE(ov6650_xclk); i++) { |
919 | ret = clk_set_rate(clk: priv->clk, rate: ov6650_xclk[i].rate); |
920 | if (ret || clk_get_rate(clk: priv->clk) != ov6650_xclk[i].rate) |
921 | continue; |
922 | |
923 | xclk = &ov6650_xclk[i]; |
924 | dev_info(&client->dev, "using negotiated clock rate %lukHz\n" , |
925 | xclk->rate / 1000); |
926 | break; |
927 | } |
928 | if (!xclk) { |
929 | dev_err(&client->dev, "unable to get supported clock rate\n" ); |
930 | if (!ret) |
931 | ret = -EINVAL; |
932 | return ret; |
933 | } |
934 | |
935 | ret = ov6650_s_power(sd, on: 1); |
936 | if (ret < 0) |
937 | return ret; |
938 | |
939 | msleep(msecs: 20); |
940 | |
941 | /* |
942 | * check and show product ID and manufacturer ID |
943 | */ |
944 | ret = ov6650_reg_read(client, REG_PIDH, val: &pidh); |
945 | if (!ret) |
946 | ret = ov6650_reg_read(client, REG_PIDL, val: &pidl); |
947 | if (!ret) |
948 | ret = ov6650_reg_read(client, REG_MIDH, val: &midh); |
949 | if (!ret) |
950 | ret = ov6650_reg_read(client, REG_MIDL, val: &midl); |
951 | |
952 | if (ret) |
953 | goto done; |
954 | |
955 | if ((pidh != OV6650_PIDH) || (pidl != OV6650_PIDL)) { |
956 | dev_err(&client->dev, "Product ID error 0x%02x:0x%02x\n" , |
957 | pidh, pidl); |
958 | ret = -ENODEV; |
959 | goto done; |
960 | } |
961 | |
962 | dev_info(&client->dev, |
963 | "ov6650 Product ID 0x%02x:0x%02x Manufacturer ID 0x%02x:0x%02x\n" , |
964 | pidh, pidl, midh, midl); |
965 | |
966 | ret = ov6650_reset(client); |
967 | if (!ret) |
968 | ret = ov6650_prog_dflt(client, clkrc: xclk->clkrc); |
969 | if (!ret) { |
970 | /* driver default frame format, no scaling */ |
971 | ret = ov6650_s_fmt(sd, code: ov6650_def_fmt.code, half_scale: false); |
972 | } |
973 | if (!ret) |
974 | ret = v4l2_ctrl_handler_setup(hdl: &priv->hdl); |
975 | |
976 | done: |
977 | ov6650_s_power(sd, on: 0); |
978 | return ret; |
979 | } |
980 | |
981 | static const struct v4l2_ctrl_ops ov6550_ctrl_ops = { |
982 | .g_volatile_ctrl = ov6550_g_volatile_ctrl, |
983 | .s_ctrl = ov6550_s_ctrl, |
984 | }; |
985 | |
986 | static const struct v4l2_subdev_core_ops ov6650_core_ops = { |
987 | #ifdef CONFIG_VIDEO_ADV_DEBUG |
988 | .g_register = ov6650_get_register, |
989 | .s_register = ov6650_set_register, |
990 | #endif |
991 | .s_power = ov6650_s_power, |
992 | }; |
993 | |
994 | /* Request bus settings on camera side */ |
995 | static int ov6650_get_mbus_config(struct v4l2_subdev *sd, |
996 | unsigned int pad, |
997 | struct v4l2_mbus_config *cfg) |
998 | { |
999 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
1000 | u8 comj, comf; |
1001 | int ret; |
1002 | |
1003 | ret = ov6650_reg_read(client, REG_COMJ, val: &comj); |
1004 | if (ret) |
1005 | return ret; |
1006 | |
1007 | ret = ov6650_reg_read(client, REG_COMF, val: &comf); |
1008 | if (ret) |
1009 | return ret; |
1010 | |
1011 | cfg->type = V4L2_MBUS_PARALLEL; |
1012 | |
1013 | cfg->bus.parallel.flags = V4L2_MBUS_MASTER | V4L2_MBUS_DATA_ACTIVE_HIGH |
1014 | | ((comj & COMJ_VSYNC_HIGH) ? V4L2_MBUS_VSYNC_ACTIVE_HIGH |
1015 | : V4L2_MBUS_VSYNC_ACTIVE_LOW) |
1016 | | ((comf & COMF_HREF_LOW) ? V4L2_MBUS_HSYNC_ACTIVE_LOW |
1017 | : V4L2_MBUS_HSYNC_ACTIVE_HIGH) |
1018 | | ((comj & COMJ_PCLK_RISING) ? V4L2_MBUS_PCLK_SAMPLE_RISING |
1019 | : V4L2_MBUS_PCLK_SAMPLE_FALLING); |
1020 | return 0; |
1021 | } |
1022 | |
1023 | static const struct v4l2_subdev_video_ops ov6650_video_ops = { |
1024 | .s_stream = ov6650_s_stream, |
1025 | }; |
1026 | |
1027 | static const struct v4l2_subdev_pad_ops ov6650_pad_ops = { |
1028 | .enum_mbus_code = ov6650_enum_mbus_code, |
1029 | .enum_frame_interval = ov6650_enum_frame_interval, |
1030 | .get_selection = ov6650_get_selection, |
1031 | .set_selection = ov6650_set_selection, |
1032 | .get_fmt = ov6650_get_fmt, |
1033 | .set_fmt = ov6650_set_fmt, |
1034 | .get_frame_interval = ov6650_get_frame_interval, |
1035 | .set_frame_interval = ov6650_set_frame_interval, |
1036 | .get_mbus_config = ov6650_get_mbus_config, |
1037 | }; |
1038 | |
1039 | static const struct v4l2_subdev_ops ov6650_subdev_ops = { |
1040 | .core = &ov6650_core_ops, |
1041 | .video = &ov6650_video_ops, |
1042 | .pad = &ov6650_pad_ops, |
1043 | }; |
1044 | |
1045 | static const struct v4l2_subdev_internal_ops ov6650_internal_ops = { |
1046 | .registered = ov6650_video_probe, |
1047 | }; |
1048 | |
1049 | /* |
1050 | * i2c_driver function |
1051 | */ |
1052 | static int ov6650_probe(struct i2c_client *client) |
1053 | { |
1054 | struct ov6650 *priv; |
1055 | int ret; |
1056 | |
1057 | priv = devm_kzalloc(dev: &client->dev, size: sizeof(*priv), GFP_KERNEL); |
1058 | if (!priv) |
1059 | return -ENOMEM; |
1060 | |
1061 | v4l2_i2c_subdev_init(sd: &priv->subdev, client, ops: &ov6650_subdev_ops); |
1062 | v4l2_ctrl_handler_init(&priv->hdl, 13); |
1063 | v4l2_ctrl_new_std(hdl: &priv->hdl, ops: &ov6550_ctrl_ops, |
1064 | V4L2_CID_VFLIP, min: 0, max: 1, step: 1, def: 0); |
1065 | v4l2_ctrl_new_std(hdl: &priv->hdl, ops: &ov6550_ctrl_ops, |
1066 | V4L2_CID_HFLIP, min: 0, max: 1, step: 1, def: 0); |
1067 | priv->autogain = v4l2_ctrl_new_std(hdl: &priv->hdl, ops: &ov6550_ctrl_ops, |
1068 | V4L2_CID_AUTOGAIN, min: 0, max: 1, step: 1, def: 1); |
1069 | priv->gain = v4l2_ctrl_new_std(hdl: &priv->hdl, ops: &ov6550_ctrl_ops, |
1070 | V4L2_CID_GAIN, min: 0, max: 0x3f, step: 1, DEF_GAIN); |
1071 | priv->autowb = v4l2_ctrl_new_std(hdl: &priv->hdl, ops: &ov6550_ctrl_ops, |
1072 | V4L2_CID_AUTO_WHITE_BALANCE, min: 0, max: 1, step: 1, def: 1); |
1073 | priv->blue = v4l2_ctrl_new_std(hdl: &priv->hdl, ops: &ov6550_ctrl_ops, |
1074 | V4L2_CID_BLUE_BALANCE, min: 0, max: 0xff, step: 1, DEF_BLUE); |
1075 | priv->red = v4l2_ctrl_new_std(hdl: &priv->hdl, ops: &ov6550_ctrl_ops, |
1076 | V4L2_CID_RED_BALANCE, min: 0, max: 0xff, step: 1, DEF_RED); |
1077 | v4l2_ctrl_new_std(hdl: &priv->hdl, ops: &ov6550_ctrl_ops, |
1078 | V4L2_CID_SATURATION, min: 0, max: 0xf, step: 1, def: 0x8); |
1079 | v4l2_ctrl_new_std(hdl: &priv->hdl, ops: &ov6550_ctrl_ops, |
1080 | V4L2_CID_HUE, min: 0, HUE_MASK, step: 1, DEF_HUE); |
1081 | v4l2_ctrl_new_std(hdl: &priv->hdl, ops: &ov6550_ctrl_ops, |
1082 | V4L2_CID_BRIGHTNESS, min: 0, max: 0xff, step: 1, def: 0x80); |
1083 | priv->autoexposure = v4l2_ctrl_new_std_menu(hdl: &priv->hdl, |
1084 | ops: &ov6550_ctrl_ops, V4L2_CID_EXPOSURE_AUTO, |
1085 | max: V4L2_EXPOSURE_MANUAL, mask: 0, def: V4L2_EXPOSURE_AUTO); |
1086 | priv->exposure = v4l2_ctrl_new_std(hdl: &priv->hdl, ops: &ov6550_ctrl_ops, |
1087 | V4L2_CID_EXPOSURE, min: 0, max: 0xff, step: 1, DEF_AECH); |
1088 | v4l2_ctrl_new_std(hdl: &priv->hdl, ops: &ov6550_ctrl_ops, |
1089 | V4L2_CID_GAMMA, min: 0, max: 0xff, step: 1, def: 0x12); |
1090 | |
1091 | priv->subdev.ctrl_handler = &priv->hdl; |
1092 | if (priv->hdl.error) { |
1093 | ret = priv->hdl.error; |
1094 | goto ectlhdlfree; |
1095 | } |
1096 | |
1097 | v4l2_ctrl_auto_cluster(ncontrols: 2, controls: &priv->autogain, manual_val: 0, set_volatile: true); |
1098 | v4l2_ctrl_auto_cluster(ncontrols: 3, controls: &priv->autowb, manual_val: 0, set_volatile: true); |
1099 | v4l2_ctrl_auto_cluster(ncontrols: 2, controls: &priv->autoexposure, |
1100 | manual_val: V4L2_EXPOSURE_MANUAL, set_volatile: true); |
1101 | |
1102 | priv->rect.left = DEF_HSTRT << 1; |
1103 | priv->rect.top = DEF_VSTRT << 1; |
1104 | priv->rect.width = W_CIF; |
1105 | priv->rect.height = H_CIF; |
1106 | |
1107 | /* Hardware default frame interval */ |
1108 | priv->tpf.numerator = GET_CLKRC_DIV(DEF_CLKRC); |
1109 | priv->tpf.denominator = FRAME_RATE_MAX; |
1110 | |
1111 | priv->subdev.internal_ops = &ov6650_internal_ops; |
1112 | |
1113 | ret = v4l2_async_register_subdev(sd: &priv->subdev); |
1114 | if (!ret) |
1115 | return 0; |
1116 | ectlhdlfree: |
1117 | v4l2_ctrl_handler_free(hdl: &priv->hdl); |
1118 | |
1119 | return ret; |
1120 | } |
1121 | |
1122 | static void ov6650_remove(struct i2c_client *client) |
1123 | { |
1124 | struct ov6650 *priv = to_ov6650(client); |
1125 | |
1126 | v4l2_async_unregister_subdev(sd: &priv->subdev); |
1127 | v4l2_ctrl_handler_free(hdl: &priv->hdl); |
1128 | } |
1129 | |
1130 | static const struct i2c_device_id ov6650_id[] = { |
1131 | { "ov6650" , 0 }, |
1132 | { } |
1133 | }; |
1134 | MODULE_DEVICE_TABLE(i2c, ov6650_id); |
1135 | |
1136 | static struct i2c_driver ov6650_i2c_driver = { |
1137 | .driver = { |
1138 | .name = "ov6650" , |
1139 | }, |
1140 | .probe = ov6650_probe, |
1141 | .remove = ov6650_remove, |
1142 | .id_table = ov6650_id, |
1143 | }; |
1144 | |
1145 | module_i2c_driver(ov6650_i2c_driver); |
1146 | |
1147 | MODULE_DESCRIPTION("V4L2 subdevice driver for OmniVision OV6650 camera sensor" ); |
1148 | MODULE_AUTHOR("Janusz Krzysztofik <jmkrzyszt@gmail.com" ); |
1149 | MODULE_LICENSE("GPL v2" ); |
1150 | |