| 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
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| 2 | /* |
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| 3 | * Driver for the NXP SAA7164 PCIe bridge |
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| 4 | * |
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| 5 | * Copyright (c) 2010-2015 Steven Toth <stoth@kernellabs.com> |
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| 6 | */ |
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| 7 | |
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| 8 | /* TODO: Retest the driver with errors expressed as negatives */ |
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| 9 | |
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| 10 | /* Result codes */ |
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| 11 | #define SAA_OK 0 |
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| 12 | #define SAA_ERR_BAD_PARAMETER 0x09 |
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| 13 | #define SAA_ERR_NO_RESOURCES 0x0c |
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| 14 | #define SAA_ERR_NOT_SUPPORTED 0x13 |
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| 15 | #define SAA_ERR_BUSY 0x15 |
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| 16 | #define SAA_ERR_READ 0x17 |
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| 17 | #define SAA_ERR_TIMEOUT 0x1f |
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| 18 | #define SAA_ERR_OVERFLOW 0x20 |
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| 19 | #define SAA_ERR_EMPTY 0x22 |
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| 20 | #define SAA_ERR_NOT_STARTED 0x23 |
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| 21 | #define SAA_ERR_ALREADY_STARTED 0x24 |
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| 22 | #define SAA_ERR_NOT_STOPPED 0x25 |
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| 23 | #define SAA_ERR_ALREADY_STOPPED 0x26 |
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| 24 | #define SAA_ERR_INVALID_COMMAND 0x3e |
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| 25 | #define SAA_ERR_NULL_PACKET 0x59 |
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| 26 | |
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| 27 | /* Errors and flags from the silicon */ |
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| 28 | #define PVC_ERRORCODE_UNKNOWN 0x00 |
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| 29 | #define PVC_ERRORCODE_INVALID_COMMAND 0x01 |
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| 30 | #define PVC_ERRORCODE_INVALID_CONTROL 0x02 |
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| 31 | #define PVC_ERRORCODE_INVALID_DATA 0x03 |
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| 32 | #define PVC_ERRORCODE_TIMEOUT 0x04 |
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| 33 | #define PVC_ERRORCODE_NAK 0x05 |
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| 34 | #define PVC_RESPONSEFLAG_ERROR 0x01 |
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| 35 | #define PVC_RESPONSEFLAG_OVERFLOW 0x02 |
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| 36 | #define PVC_RESPONSEFLAG_RESET 0x04 |
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| 37 | #define PVC_RESPONSEFLAG_INTERFACE 0x08 |
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| 38 | #define PVC_RESPONSEFLAG_CONTINUED 0x10 |
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| 39 | #define PVC_CMDFLAG_INTERRUPT 0x02 |
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| 40 | #define PVC_CMDFLAG_INTERFACE 0x04 |
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| 41 | #define PVC_CMDFLAG_SERIALIZE 0x08 |
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| 42 | #define PVC_CMDFLAG_CONTINUE 0x10 |
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| 43 | |
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| 44 | /* Silicon Commands */ |
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| 45 | #define GET_DESCRIPTORS_CONTROL 0x01 |
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| 46 | #define GET_STRING_CONTROL 0x03 |
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| 47 | #define GET_LANGUAGE_CONTROL 0x05 |
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| 48 | #define SET_POWER_CONTROL 0x07 |
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| 49 | #define GET_FW_STATUS_CONTROL 0x08 |
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| 50 | #define GET_FW_VERSION_CONTROL 0x09 |
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| 51 | #define SET_DEBUG_LEVEL_CONTROL 0x0B |
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| 52 | #define GET_DEBUG_DATA_CONTROL 0x0C |
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| 53 | #define GET_PRODUCTION_INFO_CONTROL 0x0D |
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| 54 | |
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| 55 | /* cmd defines */ |
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| 56 | #define SAA_CMDFLAG_CONTINUE 0x10 |
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| 57 | #define SAA_CMD_MAX_MSG_UNITS 256 |
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| 58 | |
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| 59 | /* Some defines */ |
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| 60 | #define SAA_BUS_TIMEOUT 50 |
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| 61 | #define SAA_DEVICE_TIMEOUT 5000 |
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| 62 | #define SAA_DEVICE_MAXREQUESTSIZE 256 |
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| 63 | |
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| 64 | /* Register addresses */ |
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| 65 | #define SAA_DEVICE_VERSION 0x30 |
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| 66 | #define SAA_DOWNLOAD_FLAGS 0x34 |
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| 67 | #define SAA_DOWNLOAD_FLAG 0x34 |
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| 68 | #define SAA_DOWNLOAD_FLAG_ACK 0x38 |
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| 69 | #define SAA_DATAREADY_FLAG 0x3C |
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| 70 | #define SAA_DATAREADY_FLAG_ACK 0x40 |
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| 71 | |
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| 72 | /* Boot loader register and bit definitions */ |
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| 73 | #define SAA_BOOTLOADERERROR_FLAGS 0x44 |
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| 74 | #define SAA_DEVICE_IMAGE_SEARCHING 0x01 |
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| 75 | #define SAA_DEVICE_IMAGE_LOADING 0x02 |
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| 76 | #define SAA_DEVICE_IMAGE_BOOTING 0x03 |
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| 77 | #define SAA_DEVICE_IMAGE_CORRUPT 0x04 |
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| 78 | #define SAA_DEVICE_MEMORY_CORRUPT 0x08 |
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| 79 | #define SAA_DEVICE_NO_IMAGE 0x10 |
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| 80 | |
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| 81 | /* Register addresses */ |
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| 82 | #define SAA_DEVICE_2ND_VERSION 0x50 |
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| 83 | #define SAA_DEVICE_2ND_DOWNLOADFLAG_OFFSET 0x54 |
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| 84 | |
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| 85 | /* Register addresses */ |
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| 86 | #define SAA_SECONDSTAGEERROR_FLAGS 0x64 |
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| 87 | |
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| 88 | /* Bootloader regs and flags */ |
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| 89 | #define SAA_DEVICE_DEADLOCK_DETECTED_OFFSET 0x6C |
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| 90 | #define SAA_DEVICE_DEADLOCK_DETECTED 0xDEADDEAD |
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| 91 | |
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| 92 | /* Basic firmware status registers */ |
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| 93 | #define SAA_DEVICE_SYSINIT_STATUS_OFFSET 0x70 |
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| 94 | #define SAA_DEVICE_SYSINIT_STATUS 0x70 |
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| 95 | #define SAA_DEVICE_SYSINIT_MODE 0x74 |
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| 96 | #define SAA_DEVICE_SYSINIT_SPEC 0x78 |
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| 97 | #define SAA_DEVICE_SYSINIT_INST 0x7C |
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| 98 | #define SAA_DEVICE_SYSINIT_CPULOAD 0x80 |
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| 99 | #define SAA_DEVICE_SYSINIT_REMAINHEAP 0x84 |
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| 100 | |
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| 101 | #define SAA_DEVICE_DOWNLOAD_OFFSET 0x1000 |
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| 102 | #define SAA_DEVICE_BUFFERBLOCKSIZE 0x1000 |
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| 103 | |
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| 104 | #define SAA_DEVICE_2ND_BUFFERBLOCKSIZE 0x100000 |
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| 105 | #define SAA_DEVICE_2ND_DOWNLOAD_OFFSET 0x200000 |
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| 106 | |
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| 107 | /* Descriptors */ |
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| 108 | #define CS_INTERFACE 0x24 |
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| 109 | |
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| 110 | /* Descriptor subtypes */ |
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| 111 | #define VC_INPUT_TERMINAL 0x02 |
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| 112 | #define VC_OUTPUT_TERMINAL 0x03 |
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| 113 | #define VC_SELECTOR_UNIT 0x04 |
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| 114 | #define VC_PROCESSING_UNIT 0x05 |
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| 115 | #define FEATURE_UNIT 0x06 |
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| 116 | #define TUNER_UNIT 0x09 |
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| 117 | #define ENCODER_UNIT 0x0A |
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| 118 | #define EXTENSION_UNIT 0x0B |
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| 119 | #define VC_TUNER_PATH 0xF0 |
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| 120 | #define PVC_HARDWARE_DESCRIPTOR 0xF1 |
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| 121 | #define PVC_INTERFACE_DESCRIPTOR 0xF2 |
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| 122 | #define PVC_INFRARED_UNIT 0xF3 |
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| 123 | #define DRM_UNIT 0xF4 |
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| 124 | #define GENERAL_REQUEST 0xF5 |
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| 125 | |
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| 126 | /* Format Types */ |
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| 127 | #define VS_FORMAT_TYPE 0x02 |
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| 128 | #define VS_FORMAT_TYPE_I 0x01 |
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| 129 | #define VS_FORMAT_UNCOMPRESSED 0x04 |
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| 130 | #define VS_FRAME_UNCOMPRESSED 0x05 |
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| 131 | #define VS_FORMAT_MPEG2PS 0x09 |
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| 132 | #define VS_FORMAT_MPEG2TS 0x0A |
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| 133 | #define VS_FORMAT_MPEG4SL 0x0B |
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| 134 | #define VS_FORMAT_WM9 0x0C |
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| 135 | #define VS_FORMAT_DIVX 0x0D |
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| 136 | #define VS_FORMAT_VBI 0x0E |
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| 137 | #define VS_FORMAT_RDS 0x0F |
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| 138 | |
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| 139 | /* Device extension commands */ |
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| 140 | #define EXU_REGISTER_ACCESS_CONTROL 0x00 |
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| 141 | #define EXU_GPIO_CONTROL 0x01 |
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| 142 | #define EXU_GPIO_GROUP_CONTROL 0x02 |
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| 143 | #define EXU_INTERRUPT_CONTROL 0x03 |
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| 144 | |
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| 145 | /* State Transition and args */ |
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| 146 | #define SAA_PROBE_CONTROL 0x01 |
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| 147 | #define SAA_COMMIT_CONTROL 0x02 |
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| 148 | #define SAA_STATE_CONTROL 0x03 |
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| 149 | #define SAA_DMASTATE_STOP 0x00 |
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| 150 | #define SAA_DMASTATE_ACQUIRE 0x01 |
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| 151 | #define SAA_DMASTATE_PAUSE 0x02 |
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| 152 | #define SAA_DMASTATE_RUN 0x03 |
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| 153 | |
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| 154 | /* A/V Mux Input Selector */ |
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| 155 | #define SU_INPUT_SELECT_CONTROL 0x01 |
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| 156 | |
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| 157 | /* Encoder Profiles */ |
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| 158 | #define EU_PROFILE_PS_DVD 0x06 |
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| 159 | #define EU_PROFILE_TS_HQ 0x09 |
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| 160 | #define EU_VIDEO_FORMAT_MPEG_2 0x02 |
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| 161 | |
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| 162 | /* Tuner */ |
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| 163 | #define TU_AUDIO_MODE_CONTROL 0x17 |
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| 164 | |
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| 165 | /* Video Formats */ |
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| 166 | #define TU_STANDARD_CONTROL 0x00 |
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| 167 | #define TU_STANDARD_AUTO_CONTROL 0x01 |
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| 168 | #define TU_STANDARD_NONE 0x00 |
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| 169 | #define TU_STANDARD_NTSC_M 0x01 |
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| 170 | #define TU_STANDARD_PAL_I 0x08 |
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| 171 | #define TU_STANDARD_MANUAL 0x00 |
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| 172 | #define TU_STANDARD_AUTO 0x01 |
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| 173 | |
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| 174 | /* Video Controls */ |
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| 175 | #define PU_BRIGHTNESS_CONTROL 0x02 |
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| 176 | #define PU_CONTRAST_CONTROL 0x03 |
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| 177 | #define PU_HUE_CONTROL 0x06 |
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| 178 | #define PU_SATURATION_CONTROL 0x07 |
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| 179 | #define PU_SHARPNESS_CONTROL 0x08 |
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| 180 | |
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| 181 | /* Audio Controls */ |
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| 182 | #define MUTE_CONTROL 0x01 |
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| 183 | #define VOLUME_CONTROL 0x02 |
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| 184 | #define AUDIO_DEFAULT_CONTROL 0x0D |
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| 185 | |
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| 186 | /* Default Volume Levels */ |
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| 187 | #define TMHW_LEV_ADJ_DECLEV_DEFAULT 0x00 |
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| 188 | #define TMHW_LEV_ADJ_MONOLEV_DEFAULT 0x00 |
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| 189 | #define TMHW_LEV_ADJ_NICLEV_DEFAULT 0x00 |
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| 190 | #define TMHW_LEV_ADJ_SAPLEV_DEFAULT 0x00 |
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| 191 | #define TMHW_LEV_ADJ_ADCLEV_DEFAULT 0x00 |
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| 192 | |
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| 193 | /* Encoder Related Commands */ |
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| 194 | #define EU_PROFILE_CONTROL 0x00 |
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| 195 | #define EU_VIDEO_FORMAT_CONTROL 0x01 |
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| 196 | #define EU_VIDEO_BIT_RATE_CONTROL 0x02 |
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| 197 | #define EU_VIDEO_RESOLUTION_CONTROL 0x03 |
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| 198 | #define EU_VIDEO_GOP_STRUCTURE_CONTROL 0x04 |
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| 199 | #define EU_VIDEO_INPUT_ASPECT_CONTROL 0x0A |
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| 200 | #define EU_AUDIO_FORMAT_CONTROL 0x0C |
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| 201 | #define EU_AUDIO_BIT_RATE_CONTROL 0x0D |
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| 202 | |
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| 203 | /* Firmware Debugging */ |
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| 204 | #define SET_DEBUG_LEVEL_CONTROL 0x0B |
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| 205 | #define GET_DEBUG_DATA_CONTROL 0x0C |
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| 206 | |
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