1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* |
3 | * Copyright 2020-2021 NXP |
4 | */ |
5 | |
6 | #ifndef _AMPHION_VPU_CODEC_H |
7 | #define _AMPHION_VPU_CODEC_H |
8 | |
9 | struct vpu_encode_params { |
10 | u32 input_format; |
11 | u32 codec_format; |
12 | u32 profile; |
13 | u32 tier; |
14 | u32 level; |
15 | struct v4l2_fract frame_rate; |
16 | u32 src_stride; |
17 | u32 src_width; |
18 | u32 src_height; |
19 | struct v4l2_rect crop; |
20 | u32 out_width; |
21 | u32 out_height; |
22 | |
23 | u32 gop_length; |
24 | u32 bframes; |
25 | |
26 | u32 rc_enable; |
27 | u32 rc_mode; |
28 | u32 bitrate; |
29 | u32 bitrate_min; |
30 | u32 bitrate_max; |
31 | |
32 | u32 i_frame_qp; |
33 | u32 p_frame_qp; |
34 | u32 b_frame_qp; |
35 | u32 qp_min; |
36 | u32 qp_max; |
37 | u32 qp_min_i; |
38 | u32 qp_max_i; |
39 | |
40 | struct { |
41 | u32 enable; |
42 | u32 idc; |
43 | u32 width; |
44 | u32 height; |
45 | } sar; |
46 | |
47 | struct { |
48 | u32 primaries; |
49 | u32 transfer; |
50 | u32 matrix; |
51 | u32 full_range; |
52 | } color; |
53 | }; |
54 | |
55 | struct vpu_decode_params { |
56 | u32 codec_format; |
57 | u32 output_format; |
58 | u32 display_delay_enable; |
59 | u32 display_delay; |
60 | u32 b_non_frame; |
61 | u32 frame_count; |
62 | u32 end_flag; |
63 | struct { |
64 | u32 base; |
65 | u32 size; |
66 | } udata; |
67 | }; |
68 | |
69 | #endif |
70 | |