1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* |
3 | * Copyright 2020-2021 NXP |
4 | */ |
5 | |
6 | #ifndef _AMPHION_VPU_IMX8Q_H |
7 | #define _AMPHION_VPU_IMX8Q_H |
8 | |
9 | #define SCB_XREG_SLV_BASE 0x00000000 |
10 | #define SCB_SCB_BLK_CTRL 0x00070000 |
11 | #define SCB_BLK_CTRL_XMEM_RESET_SET 0x00000090 |
12 | #define SCB_BLK_CTRL_CACHE_RESET_SET 0x000000A0 |
13 | #define SCB_BLK_CTRL_CACHE_RESET_CLR 0x000000A4 |
14 | #define SCB_BLK_CTRL_SCB_CLK_ENABLE_SET 0x00000100 |
15 | |
16 | #define XMEM_CONTROL 0x00041000 |
17 | |
18 | #define MC_CACHE_0_BASE 0x00060000 |
19 | #define MC_CACHE_1_BASE 0x00068000 |
20 | |
21 | #define DEC_MFD_XREG_SLV_BASE 0x00180000 |
22 | #define ENC_MFD_XREG_SLV_0_BASE 0x00800000 |
23 | #define ENC_MFD_XREG_SLV_1_BASE 0x00A00000 |
24 | |
25 | #define MFD_HIF 0x0001C000 |
26 | #define MFD_HIF_MSD_REG_INTERRUPT_STATUS 0x00000018 |
27 | #define MFD_SIF 0x0001D000 |
28 | #define MFD_SIF_CTRL_STATUS 0x000000F0 |
29 | #define MFD_SIF_INTR_STATUS 0x000000F4 |
30 | #define MFD_MCX 0x00020800 |
31 | #define MFD_MCX_OFF 0x00000020 |
32 | #define MFD_PIX_IF 0x00020000 |
33 | |
34 | #define MFD_BLK_CTRL 0x00030000 |
35 | #define MFD_BLK_CTRL_MFD_SYS_RESET_SET 0x00000000 |
36 | #define MFD_BLK_CTRL_MFD_SYS_RESET_CLR 0x00000004 |
37 | #define MFD_BLK_CTRL_MFD_SYS_CLOCK_ENABLE_SET 0x00000100 |
38 | #define MFD_BLK_CTRL_MFD_SYS_CLOCK_ENABLE_CLR 0x00000104 |
39 | |
40 | #define VID_API_NUM_STREAMS 8 |
41 | #define VID_API_MAX_BUF_PER_STR 3 |
42 | #define VID_API_MAX_NUM_MVC_VIEWS 4 |
43 | #define MEDIAIP_MAX_NUM_MALONES 2 |
44 | #define MEDIAIP_MAX_NUM_MALONE_IRQ_PINS 2 |
45 | #define MEDIAIP_MAX_NUM_WINDSORS 1 |
46 | #define MEDIAIP_MAX_NUM_WINDSOR_IRQ_PINS 2 |
47 | #define MEDIAIP_MAX_NUM_CMD_IRQ_PINS 2 |
48 | #define MEDIAIP_MAX_NUM_MSG_IRQ_PINS 1 |
49 | #define MEDIAIP_MAX_NUM_TIMER_IRQ_PINS 4 |
50 | #define MEDIAIP_MAX_NUM_TIMER_IRQ_SLOTS 4 |
51 | |
52 | #define WINDSOR_PAL_IRQ_PIN_L 0x4 |
53 | #define WINDSOR_PAL_IRQ_PIN_H 0x5 |
54 | |
55 | struct vpu_rpc_system_config { |
56 | u32 cfg_cookie; |
57 | |
58 | u32 num_malones; |
59 | u32 malone_base_addr[MEDIAIP_MAX_NUM_MALONES]; |
60 | u32 hif_offset[MEDIAIP_MAX_NUM_MALONES]; |
61 | u32 malone_irq_pin[MEDIAIP_MAX_NUM_MALONES][MEDIAIP_MAX_NUM_MALONE_IRQ_PINS]; |
62 | u32 malone_irq_target[MEDIAIP_MAX_NUM_MALONES][MEDIAIP_MAX_NUM_MALONE_IRQ_PINS]; |
63 | |
64 | u32 num_windsors; |
65 | u32 windsor_base_addr[MEDIAIP_MAX_NUM_WINDSORS]; |
66 | u32 windsor_irq_pin[MEDIAIP_MAX_NUM_WINDSORS][MEDIAIP_MAX_NUM_WINDSOR_IRQ_PINS]; |
67 | u32 windsor_irq_target[MEDIAIP_MAX_NUM_WINDSORS][MEDIAIP_MAX_NUM_WINDSOR_IRQ_PINS]; |
68 | |
69 | u32 cmd_irq_pin[MEDIAIP_MAX_NUM_CMD_IRQ_PINS]; |
70 | u32 cmd_irq_target[MEDIAIP_MAX_NUM_CMD_IRQ_PINS]; |
71 | |
72 | u32 msg_irq_pin[MEDIAIP_MAX_NUM_MSG_IRQ_PINS]; |
73 | u32 msg_irq_target[MEDIAIP_MAX_NUM_MSG_IRQ_PINS]; |
74 | |
75 | u32 sys_clk_freq; |
76 | u32 num_timers; |
77 | u32 timer_base_addr; |
78 | u32 timer_irq_pin[MEDIAIP_MAX_NUM_TIMER_IRQ_PINS]; |
79 | u32 timer_irq_target[MEDIAIP_MAX_NUM_TIMER_IRQ_PINS]; |
80 | u32 timer_slots[MEDIAIP_MAX_NUM_TIMER_IRQ_SLOTS]; |
81 | |
82 | u32 gic_base_addr; |
83 | u32 uart_base_addr; |
84 | |
85 | u32 dpv_base_addr; |
86 | u32 dpv_irq_pin; |
87 | u32 dpv_irq_target; |
88 | |
89 | u32 pixif_base_addr; |
90 | |
91 | u32 pal_trace_level; |
92 | u32 pal_trace_destination; |
93 | |
94 | u32 pal_trace_level1; |
95 | u32 pal_trace_destination1; |
96 | |
97 | u32 heap_base; |
98 | u32 heap_size; |
99 | |
100 | u32 cache_base_addr[2]; |
101 | }; |
102 | |
103 | int vpu_imx8q_setup_dec(struct vpu_dev *vpu); |
104 | int vpu_imx8q_setup_enc(struct vpu_dev *vpu); |
105 | int vpu_imx8q_setup(struct vpu_dev *vpu); |
106 | int vpu_imx8q_reset(struct vpu_dev *vpu); |
107 | int vpu_imx8q_set_system_cfg_common(struct vpu_rpc_system_config *config, u32 regs, u32 core_id); |
108 | int vpu_imx8q_boot_core(struct vpu_core *core); |
109 | int vpu_imx8q_get_power_state(struct vpu_core *core); |
110 | int vpu_imx8q_on_firmware_loaded(struct vpu_core *core); |
111 | int vpu_imx8q_check_memory_region(dma_addr_t base, dma_addr_t addr, u32 size); |
112 | bool vpu_imx8q_check_codec(enum vpu_core_type type); |
113 | bool vpu_imx8q_check_fmt(enum vpu_core_type type, u32 pixelfmt); |
114 | |
115 | #endif |
116 | |