1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* |
3 | * Register definition file for Samsung MFC V6.x Interface (FIMV) driver |
4 | * |
5 | * Copyright (c) 2012 Samsung Electronics Co., Ltd. |
6 | * http://www.samsung.com/ |
7 | */ |
8 | |
9 | #ifndef _REGS_FIMV_V6_H |
10 | #define _REGS_FIMV_V6_H |
11 | |
12 | #include <linux/kernel.h> |
13 | #include <linux/sizes.h> |
14 | |
15 | #define S5P_FIMV_REG_SIZE_V6 (S5P_FIMV_END_ADDR - S5P_FIMV_START_ADDR) |
16 | #define S5P_FIMV_REG_COUNT_V6 ((S5P_FIMV_END_ADDR - S5P_FIMV_START_ADDR) / 4) |
17 | |
18 | /* Number of bits that the buffer address should be shifted for particular |
19 | * MFC buffers. */ |
20 | #define S5P_FIMV_MEM_OFFSET_V6 0 |
21 | |
22 | #define S5P_FIMV_START_ADDR_V6 0x0000 |
23 | #define S5P_FIMV_END_ADDR_V6 0xfd80 |
24 | |
25 | #define S5P_FIMV_REG_CLEAR_BEGIN_V6 0xf000 |
26 | #define S5P_FIMV_REG_CLEAR_COUNT_V6 1024 |
27 | |
28 | /* Codec Common Registers */ |
29 | #define S5P_FIMV_RISC_ON_V6 0x0000 |
30 | #define S5P_FIMV_RISC2HOST_INT_V6 0x003C |
31 | #define S5P_FIMV_HOST2RISC_INT_V6 0x0044 |
32 | #define S5P_FIMV_RISC_BASE_ADDRESS_V6 0x0054 |
33 | |
34 | #define S5P_FIMV_MFC_RESET_V6 0x1070 |
35 | |
36 | #define S5P_FIMV_HOST2RISC_CMD_V6 0x1100 |
37 | #define S5P_FIMV_H2R_CMD_EMPTY_V6 0 |
38 | #define S5P_FIMV_H2R_CMD_SYS_INIT_V6 1 |
39 | #define S5P_FIMV_H2R_CMD_OPEN_INSTANCE_V6 2 |
40 | #define 3 |
41 | #define S5P_FIMV_CH_INIT_BUFS_V6 4 |
42 | #define S5P_FIMV_CH_FRAME_START_V6 5 |
43 | #define S5P_FIMV_H2R_CMD_CLOSE_INSTANCE_V6 6 |
44 | #define S5P_FIMV_H2R_CMD_SLEEP_V6 7 |
45 | #define S5P_FIMV_H2R_CMD_WAKEUP_V6 8 |
46 | #define S5P_FIMV_CH_LAST_FRAME_V6 9 |
47 | #define S5P_FIMV_H2R_CMD_FLUSH_V6 10 |
48 | /* RMVME: REALLOC used? */ |
49 | #define S5P_FIMV_CH_FRAME_START_REALLOC_V6 5 |
50 | |
51 | #define S5P_FIMV_RISC2HOST_CMD_V6 0x1104 |
52 | #define S5P_FIMV_R2H_CMD_EMPTY_V6 0 |
53 | #define S5P_FIMV_R2H_CMD_SYS_INIT_RET_V6 1 |
54 | #define S5P_FIMV_R2H_CMD_OPEN_INSTANCE_RET_V6 2 |
55 | #define S5P_FIMV_R2H_CMD_SEQ_DONE_RET_V6 3 |
56 | #define S5P_FIMV_R2H_CMD_INIT_BUFFERS_RET_V6 4 |
57 | |
58 | #define S5P_FIMV_R2H_CMD_CLOSE_INSTANCE_RET_V6 6 |
59 | #define S5P_FIMV_R2H_CMD_SLEEP_RET_V6 7 |
60 | #define S5P_FIMV_R2H_CMD_WAKEUP_RET_V6 8 |
61 | #define S5P_FIMV_R2H_CMD_COMPLETE_SEQ_RET_V6 9 |
62 | #define S5P_FIMV_R2H_CMD_DPB_FLUSH_RET_V6 10 |
63 | #define S5P_FIMV_R2H_CMD_NAL_ABORT_RET_V6 11 |
64 | #define S5P_FIMV_R2H_CMD_FW_STATUS_RET_V6 12 |
65 | #define S5P_FIMV_R2H_CMD_FRAME_DONE_RET_V6 13 |
66 | #define S5P_FIMV_R2H_CMD_FIELD_DONE_RET_V6 14 |
67 | #define S5P_FIMV_R2H_CMD_SLICE_DONE_RET_V6 15 |
68 | #define S5P_FIMV_R2H_CMD_ENC_BUFFER_FUL_RET_V6 16 |
69 | #define S5P_FIMV_R2H_CMD_ERR_RET_V6 32 |
70 | |
71 | #define S5P_FIMV_MFC_BUS_RESET_CTRL 0x7110 |
72 | #define S5P_FIMV_FW_VERSION_V6 0xf000 |
73 | |
74 | #define S5P_FIMV_INSTANCE_ID_V6 0xf008 |
75 | #define S5P_FIMV_CODEC_TYPE_V6 0xf00c |
76 | #define S5P_FIMV_CONTEXT_MEM_ADDR_V6 0xf014 |
77 | #define S5P_FIMV_CONTEXT_MEM_SIZE_V6 0xf018 |
78 | #define S5P_FIMV_PIXEL_FORMAT_V6 0xf020 |
79 | |
80 | #define S5P_FIMV_METADATA_ENABLE_V6 0xf024 |
81 | #define S5P_FIMV_DBG_BUFFER_ADDR_V6 0xf030 |
82 | #define S5P_FIMV_DBG_BUFFER_SIZE_V6 0xf034 |
83 | #define S5P_FIMV_RET_INSTANCE_ID_V6 0xf070 |
84 | |
85 | #define S5P_FIMV_ERROR_CODE_V6 0xf074 |
86 | #define S5P_FIMV_ERR_WARNINGS_START_V6 160 |
87 | #define S5P_FIMV_ERR_DEC_MASK_V6 0xffff |
88 | #define S5P_FIMV_ERR_DEC_SHIFT_V6 0 |
89 | #define S5P_FIMV_ERR_DSPL_MASK_V6 0xffff0000 |
90 | #define S5P_FIMV_ERR_DSPL_SHIFT_V6 16 |
91 | |
92 | #define S5P_FIMV_DBG_BUFFER_OUTPUT_SIZE_V6 0xf078 |
93 | #define S5P_FIMV_METADATA_STATUS_V6 0xf07C |
94 | #define S5P_FIMV_METADATA_ADDR_MB_INFO_V6 0xf080 |
95 | #define S5P_FIMV_METADATA_SIZE_MB_INFO_V6 0xf084 |
96 | |
97 | /* Decoder Registers */ |
98 | #define S5P_FIMV_D_CRC_CTRL_V6 0xf0b0 |
99 | #define S5P_FIMV_D_DEC_OPTIONS_V6 0xf0b4 |
100 | #define S5P_FIMV_D_OPT_FMO_ASO_CTRL_MASK_V6 4 |
101 | #define S5P_FIMV_D_OPT_DDELAY_EN_SHIFT_V6 3 |
102 | #define S5P_FIMV_D_OPT_LF_CTRL_SHIFT_V6 1 |
103 | #define S5P_FIMV_D_OPT_LF_CTRL_MASK_V6 0x3 |
104 | #define S5P_FIMV_D_OPT_TILE_MODE_SHIFT_V6 0 |
105 | |
106 | #define S5P_FIMV_D_DISPLAY_DELAY_V6 0xf0b8 |
107 | |
108 | #define S5P_FIMV_D_SET_FRAME_WIDTH_V6 0xf0bc |
109 | #define S5P_FIMV_D_SET_FRAME_HEIGHT_V6 0xf0c0 |
110 | |
111 | #define S5P_FIMV_D_SEI_ENABLE_V6 0xf0c4 |
112 | |
113 | /* Buffer setting registers */ |
114 | #define S5P_FIMV_D_MIN_NUM_DPB_V6 0xf0f0 |
115 | #define S5P_FIMV_D_MIN_LUMA_DPB_SIZE_V6 0xf0f4 |
116 | #define S5P_FIMV_D_MIN_CHROMA_DPB_SIZE_V6 0xf0f8 |
117 | #define S5P_FIMV_D_MVC_NUM_VIEWS_V6 0xf0fc |
118 | #define S5P_FIMV_D_MIN_NUM_MV_V6 0xf100 |
119 | #define S5P_FIMV_D_NUM_DPB_V6 0xf130 |
120 | #define S5P_FIMV_D_LUMA_DPB_SIZE_V6 0xf134 |
121 | #define S5P_FIMV_D_CHROMA_DPB_SIZE_V6 0xf138 |
122 | #define S5P_FIMV_D_MV_BUFFER_SIZE_V6 0xf13c |
123 | |
124 | #define S5P_FIMV_D_LUMA_DPB_V6 0xf140 |
125 | #define S5P_FIMV_D_CHROMA_DPB_V6 0xf240 |
126 | #define S5P_FIMV_D_MV_BUFFER_V6 0xf340 |
127 | |
128 | #define S5P_FIMV_D_SCRATCH_BUFFER_ADDR_V6 0xf440 |
129 | #define S5P_FIMV_D_SCRATCH_BUFFER_SIZE_V6 0xf444 |
130 | #define S5P_FIMV_D_METADATA_BUFFER_ADDR_V6 0xf448 |
131 | #define S5P_FIMV_D_METADATA_BUFFER_SIZE_V6 0xf44c |
132 | #define S5P_FIMV_D_NUM_MV_V6 0xf478 |
133 | #define S5P_FIMV_D_CPB_BUFFER_ADDR_V6 0xf4b0 |
134 | #define S5P_FIMV_D_CPB_BUFFER_SIZE_V6 0xf4b4 |
135 | |
136 | #define S5P_FIMV_D_AVAILABLE_DPB_FLAG_UPPER_V6 0xf4b8 |
137 | #define S5P_FIMV_D_AVAILABLE_DPB_FLAG_LOWER_V6 0xf4bc |
138 | #define S5P_FIMV_D_CPB_BUFFER_OFFSET_V6 0xf4c0 |
139 | #define S5P_FIMV_D_SLICE_IF_ENABLE_V6 0xf4c4 |
140 | #define S5P_FIMV_D_PICTURE_TAG_V6 0xf4c8 |
141 | #define S5P_FIMV_D_STREAM_DATA_SIZE_V6 0xf4d0 |
142 | #define S5P_FIMV_D_INIT_BUFFER_OPTIONS_V6 0xf47c |
143 | |
144 | /* Display information register */ |
145 | #define S5P_FIMV_D_DISPLAY_FRAME_WIDTH_V6 0xf500 |
146 | #define S5P_FIMV_D_DISPLAY_FRAME_HEIGHT_V6 0xf504 |
147 | |
148 | /* Display status */ |
149 | #define S5P_FIMV_D_DISPLAY_STATUS_V6 0xf508 |
150 | |
151 | #define S5P_FIMV_D_DISPLAY_LUMA_ADDR_V6 0xf50c |
152 | #define S5P_FIMV_D_DISPLAY_CHROMA_ADDR_V6 0xf510 |
153 | |
154 | #define S5P_FIMV_D_DISPLAY_FRAME_TYPE_V6 0xf514 |
155 | |
156 | #define S5P_FIMV_D_DISPLAY_CROP_INFO1_V6 0xf518 |
157 | #define S5P_FIMV_D_DISPLAY_CROP_INFO2_V6 0xf51c |
158 | #define S5P_FIMV_D_DISPLAY_PICTURE_PROFILE_V6 0xf520 |
159 | #define S5P_FIMV_D_DISPLAY_LUMA_CRC_TOP_V6 0xf524 |
160 | #define S5P_FIMV_D_DISPLAY_CHROMA_CRC_TOP_V6 0xf528 |
161 | #define S5P_FIMV_D_DISPLAY_LUMA_CRC_BOT_V6 0xf52c |
162 | #define S5P_FIMV_D_DISPLAY_CHROMA_CRC_BOT_V6 0xf530 |
163 | #define S5P_FIMV_D_DISPLAY_ASPECT_RATIO_V6 0xf534 |
164 | #define S5P_FIMV_D_DISPLAY_EXTENDED_AR_V6 0xf538 |
165 | |
166 | /* Decoded picture information register */ |
167 | #define S5P_FIMV_D_DECODED_FRAME_WIDTH_V6 0xf53c |
168 | #define S5P_FIMV_D_DECODED_FRAME_HEIGHT_V6 0xf540 |
169 | #define S5P_FIMV_D_DECODED_STATUS_V6 0xf544 |
170 | #define S5P_FIMV_DEC_CRC_GEN_MASK_V6 0x1 |
171 | #define S5P_FIMV_DEC_CRC_GEN_SHIFT_V6 6 |
172 | |
173 | #define S5P_FIMV_D_DECODED_LUMA_ADDR_V6 0xf548 |
174 | #define S5P_FIMV_D_DECODED_CHROMA_ADDR_V6 0xf54c |
175 | |
176 | #define S5P_FIMV_D_DECODED_FRAME_TYPE_V6 0xf550 |
177 | #define S5P_FIMV_DECODE_FRAME_MASK_V6 7 |
178 | |
179 | #define S5P_FIMV_D_DECODED_CROP_INFO1_V6 0xf554 |
180 | #define S5P_FIMV_D_DECODED_CROP_INFO2_V6 0xf558 |
181 | #define S5P_FIMV_D_DECODED_PICTURE_PROFILE_V6 0xf55c |
182 | #define S5P_FIMV_D_DECODED_NAL_SIZE_V6 0xf560 |
183 | #define S5P_FIMV_D_DECODED_LUMA_CRC_TOP_V6 0xf564 |
184 | #define S5P_FIMV_D_DECODED_CHROMA_CRC_TOP_V6 0xf568 |
185 | #define S5P_FIMV_D_DECODED_LUMA_CRC_BOT_V6 0xf56c |
186 | #define S5P_FIMV_D_DECODED_CHROMA_CRC_BOT_V6 0xf570 |
187 | |
188 | /* Returned value register for specific setting */ |
189 | #define S5P_FIMV_D_RET_PICTURE_TAG_TOP_V6 0xf574 |
190 | #define S5P_FIMV_D_RET_PICTURE_TAG_BOT_V6 0xf578 |
191 | #define S5P_FIMV_D_RET_PICTURE_TIME_TOP_V6 0xf57c |
192 | #define S5P_FIMV_D_RET_PICTURE_TIME_BOT_V6 0xf580 |
193 | #define S5P_FIMV_D_CHROMA_FORMAT_V6 0xf588 |
194 | #define S5P_FIMV_D_MPEG4_INFO_V6 0xf58c |
195 | #define S5P_FIMV_D_H264_INFO_V6 0xf590 |
196 | |
197 | #define S5P_FIMV_D_METADATA_ADDR_CONCEALED_MB_V6 0xf594 |
198 | #define S5P_FIMV_D_METADATA_SIZE_CONCEALED_MB_V6 0xf598 |
199 | #define S5P_FIMV_D_METADATA_ADDR_VC1_PARAM_V6 0xf59c |
200 | #define S5P_FIMV_D_METADATA_SIZE_VC1_PARAM_V6 0xf5a0 |
201 | #define S5P_FIMV_D_METADATA_ADDR_SEI_NAL_V6 0xf5a4 |
202 | #define S5P_FIMV_D_METADATA_SIZE_SEI_NAL_V6 0xf5a8 |
203 | #define S5P_FIMV_D_METADATA_ADDR_VUI_V6 0xf5ac |
204 | #define S5P_FIMV_D_METADATA_SIZE_VUI_V6 0xf5b0 |
205 | |
206 | #define S5P_FIMV_D_MVC_VIEW_ID_V6 0xf5b4 |
207 | |
208 | /* SEI related information */ |
209 | #define S5P_FIMV_D_FRAME_PACK_SEI_AVAIL_V6 0xf5f0 |
210 | #define S5P_FIMV_D_FRAME_PACK_ARRGMENT_ID_V6 0xf5f4 |
211 | #define S5P_FIMV_D_FRAME_PACK_SEI_INFO_V6 0xf5f8 |
212 | #define S5P_FIMV_D_FRAME_PACK_GRID_POS_V6 0xf5fc |
213 | |
214 | /* Encoder Registers */ |
215 | #define S5P_FIMV_E_FRAME_WIDTH_V6 0xf770 |
216 | #define S5P_FIMV_E_FRAME_HEIGHT_V6 0xf774 |
217 | #define S5P_FIMV_E_CROPPED_FRAME_WIDTH_V6 0xf778 |
218 | #define S5P_FIMV_E_CROPPED_FRAME_HEIGHT_V6 0xf77c |
219 | #define S5P_FIMV_E_FRAME_CROP_OFFSET_V6 0xf780 |
220 | #define S5P_FIMV_E_ENC_OPTIONS_V6 0xf784 |
221 | #define S5P_FIMV_E_PICTURE_PROFILE_V6 0xf788 |
222 | #define S5P_FIMV_E_FIXED_PICTURE_QP_V6 0xf790 |
223 | |
224 | #define S5P_FIMV_E_RC_CONFIG_V6 0xf794 |
225 | #define S5P_FIMV_E_RC_QP_BOUND_V6 0xf798 |
226 | #define S5P_FIMV_E_RC_RPARAM_V6 0xf79c |
227 | #define S5P_FIMV_E_MB_RC_CONFIG_V6 0xf7a0 |
228 | #define S5P_FIMV_E_PADDING_CTRL_V6 0xf7a4 |
229 | #define S5P_FIMV_E_MV_HOR_RANGE_V6 0xf7ac |
230 | #define S5P_FIMV_E_MV_VER_RANGE_V6 0xf7b0 |
231 | #define S5P_FIMV_E_MV_RANGE_V6_MASK 0x3fff |
232 | |
233 | #define S5P_FIMV_E_VBV_BUFFER_SIZE_V6 0xf84c |
234 | #define S5P_FIMV_E_VBV_INIT_DELAY_V6 0xf850 |
235 | #define S5P_FIMV_E_NUM_DPB_V6 0xf890 |
236 | #define S5P_FIMV_E_LUMA_DPB_V6 0xf8c0 |
237 | #define S5P_FIMV_E_CHROMA_DPB_V6 0xf904 |
238 | #define S5P_FIMV_E_ME_BUFFER_V6 0xf948 |
239 | |
240 | #define S5P_FIMV_E_SCRATCH_BUFFER_ADDR_V6 0xf98c |
241 | #define S5P_FIMV_E_SCRATCH_BUFFER_SIZE_V6 0xf990 |
242 | #define S5P_FIMV_E_TMV_BUFFER0_V6 0xf994 |
243 | #define S5P_FIMV_E_TMV_BUFFER1_V6 0xf998 |
244 | #define S5P_FIMV_E_SOURCE_LUMA_ADDR_V6 0xf9f0 |
245 | #define S5P_FIMV_E_SOURCE_CHROMA_ADDR_V6 0xf9f4 |
246 | #define S5P_FIMV_E_STREAM_BUFFER_ADDR_V6 0xf9f8 |
247 | #define S5P_FIMV_E_STREAM_BUFFER_SIZE_V6 0xf9fc |
248 | #define S5P_FIMV_E_ROI_BUFFER_ADDR_V6 0xfA00 |
249 | |
250 | #define S5P_FIMV_E_PARAM_CHANGE_V6 0xfa04 |
251 | #define S5P_FIMV_E_IR_SIZE_V6 0xfa08 |
252 | #define S5P_FIMV_E_GOP_CONFIG_V6 0xfa0c |
253 | #define S5P_FIMV_E_MSLICE_MODE_V6 0xfa10 |
254 | #define S5P_FIMV_E_MSLICE_SIZE_MB_V6 0xfa14 |
255 | #define S5P_FIMV_E_MSLICE_SIZE_BITS_V6 0xfa18 |
256 | #define S5P_FIMV_E_FRAME_INSERTION_V6 0xfa1c |
257 | |
258 | #define S5P_FIMV_E_RC_FRAME_RATE_V6 0xfa20 |
259 | #define S5P_FIMV_E_RC_BIT_RATE_V6 0xfa24 |
260 | #define S5P_FIMV_E_RC_QP_OFFSET_V6 0xfa28 |
261 | #define S5P_FIMV_E_RC_ROI_CTRL_V6 0xfa2c |
262 | #define S5P_FIMV_E_PICTURE_TAG_V6 0xfa30 |
263 | #define S5P_FIMV_E_BIT_COUNT_ENABLE_V6 0xfa34 |
264 | #define S5P_FIMV_E_MAX_BIT_COUNT_V6 0xfa38 |
265 | #define S5P_FIMV_E_MIN_BIT_COUNT_V6 0xfa3c |
266 | |
267 | #define S5P_FIMV_E_METADATA_BUFFER_ADDR_V6 0xfa40 |
268 | #define S5P_FIMV_E_METADATA_BUFFER_SIZE_V6 0xfa44 |
269 | #define S5P_FIMV_E_STREAM_SIZE_V6 0xfa80 |
270 | #define S5P_FIMV_E_SLICE_TYPE_V6 0xfa84 |
271 | #define S5P_FIMV_E_PICTURE_COUNT_V6 0xfa88 |
272 | #define S5P_FIMV_E_RET_PICTURE_TAG_V6 0xfa8c |
273 | #define S5P_FIMV_E_STREAM_BUFFER_WRITE_POINTER_V6 0xfa90 |
274 | |
275 | #define S5P_FIMV_E_ENCODED_SOURCE_LUMA_ADDR_V6 0xfa94 |
276 | #define S5P_FIMV_E_ENCODED_SOURCE_CHROMA_ADDR_V6 0xfa98 |
277 | #define S5P_FIMV_E_RECON_LUMA_DPB_ADDR_V6 0xfa9c |
278 | #define S5P_FIMV_E_RECON_CHROMA_DPB_ADDR_V6 0xfaa0 |
279 | #define S5P_FIMV_E_METADATA_ADDR_ENC_SLICE_V6 0xfaa4 |
280 | #define S5P_FIMV_E_METADATA_SIZE_ENC_SLICE_V6 0xfaa8 |
281 | |
282 | #define S5P_FIMV_E_MPEG4_OPTIONS_V6 0xfb10 |
283 | #define S5P_FIMV_E_MPEG4_HEC_PERIOD_V6 0xfb14 |
284 | #define S5P_FIMV_E_ASPECT_RATIO_V6 0xfb50 |
285 | #define S5P_FIMV_E_EXTENDED_SAR_V6 0xfb54 |
286 | |
287 | #define S5P_FIMV_E_H264_OPTIONS_V6 0xfb58 |
288 | #define S5P_FIMV_E_H264_LF_ALPHA_OFFSET_V6 0xfb5c |
289 | #define S5P_FIMV_E_H264_LF_BETA_OFFSET_V6 0xfb60 |
290 | #define S5P_FIMV_E_H264_I_PERIOD_V6 0xfb64 |
291 | |
292 | #define S5P_FIMV_E_H264_FMO_SLICE_GRP_MAP_TYPE_V6 0xfb68 |
293 | #define S5P_FIMV_E_H264_FMO_NUM_SLICE_GRP_MINUS1_V6 0xfb6c |
294 | #define S5P_FIMV_E_H264_FMO_SLICE_GRP_CHANGE_DIR_V6 0xfb70 |
295 | #define S5P_FIMV_E_H264_FMO_SLICE_GRP_CHANGE_RATE_MINUS1_V6 0xfb74 |
296 | #define S5P_FIMV_E_H264_FMO_RUN_LENGTH_MINUS1_0_V6 0xfb78 |
297 | #define S5P_FIMV_E_H264_FMO_RUN_LENGTH_MINUS1_1_V6 0xfb7c |
298 | #define S5P_FIMV_E_H264_FMO_RUN_LENGTH_MINUS1_2_V6 0xfb80 |
299 | #define S5P_FIMV_E_H264_FMO_RUN_LENGTH_MINUS1_3_V6 0xfb84 |
300 | |
301 | #define S5P_FIMV_E_H264_ASO_SLICE_ORDER_0_V6 0xfb88 |
302 | #define S5P_FIMV_E_H264_ASO_SLICE_ORDER_1_V6 0xfb8c |
303 | #define S5P_FIMV_E_H264_ASO_SLICE_ORDER_2_V6 0xfb90 |
304 | #define S5P_FIMV_E_H264_ASO_SLICE_ORDER_3_V6 0xfb94 |
305 | #define S5P_FIMV_E_H264_ASO_SLICE_ORDER_4_V6 0xfb98 |
306 | #define S5P_FIMV_E_H264_ASO_SLICE_ORDER_5_V6 0xfb9c |
307 | #define S5P_FIMV_E_H264_ASO_SLICE_ORDER_6_V6 0xfba0 |
308 | #define S5P_FIMV_E_H264_ASO_SLICE_ORDER_7_V6 0xfba4 |
309 | |
310 | #define S5P_FIMV_E_H264_CHROMA_QP_OFFSET_V6 0xfba8 |
311 | #define S5P_FIMV_E_H264_NUM_T_LAYER_V6 0xfbac |
312 | |
313 | #define S5P_FIMV_E_H264_HIERARCHICAL_QP_LAYER0_V6 0xfbb0 |
314 | #define S5P_FIMV_E_H264_HIERARCHICAL_QP_LAYER1_V6 0xfbb4 |
315 | #define S5P_FIMV_E_H264_HIERARCHICAL_QP_LAYER2_V6 0xfbb8 |
316 | #define S5P_FIMV_E_H264_HIERARCHICAL_QP_LAYER3_V6 0xfbbc |
317 | #define S5P_FIMV_E_H264_HIERARCHICAL_QP_LAYER4_V6 0xfbc0 |
318 | #define S5P_FIMV_E_H264_HIERARCHICAL_QP_LAYER5_V6 0xfbc4 |
319 | #define S5P_FIMV_E_H264_HIERARCHICAL_QP_LAYER6_V6 0xfbc8 |
320 | |
321 | #define S5P_FIMV_E_H264_FRAME_PACKING_SEI_INFO_V6 0xfc4c |
322 | #define S5P_FIMV_ENC_FP_ARRANGEMENT_TYPE_SIDE_BY_SIDE_V6 0 |
323 | #define S5P_FIMV_ENC_FP_ARRANGEMENT_TYPE_TOP_BOTTOM_V6 1 |
324 | #define S5P_FIMV_ENC_FP_ARRANGEMENT_TYPE_TEMPORAL_V6 2 |
325 | |
326 | #define S5P_FIMV_E_MVC_FRAME_QP_VIEW1_V6 0xfd40 |
327 | #define S5P_FIMV_E_MVC_RC_FRAME_RATE_VIEW1_V6 0xfd44 |
328 | #define S5P_FIMV_E_MVC_RC_BIT_RATE_VIEW1_V6 0xfd48 |
329 | #define S5P_FIMV_E_MVC_RC_QBOUND_VIEW1_V6 0xfd4c |
330 | #define S5P_FIMV_E_MVC_RC_RPARA_VIEW1_V6 0xfd50 |
331 | #define S5P_FIMV_E_MVC_INTER_VIEW_PREDICTION_ON_V6 0xfd80 |
332 | |
333 | /* Codec numbers */ |
334 | #define S5P_FIMV_CODEC_NONE_V6 -1 |
335 | |
336 | |
337 | #define S5P_FIMV_CODEC_H264_DEC_V6 0 |
338 | #define S5P_FIMV_CODEC_H264_MVC_DEC_V6 1 |
339 | |
340 | #define S5P_FIMV_CODEC_MPEG4_DEC_V6 3 |
341 | #define S5P_FIMV_CODEC_FIMV1_DEC_V6 4 |
342 | #define S5P_FIMV_CODEC_FIMV2_DEC_V6 5 |
343 | #define S5P_FIMV_CODEC_FIMV3_DEC_V6 6 |
344 | #define S5P_FIMV_CODEC_FIMV4_DEC_V6 7 |
345 | #define S5P_FIMV_CODEC_H263_DEC_V6 8 |
346 | #define S5P_FIMV_CODEC_VC1RCV_DEC_V6 9 |
347 | #define S5P_FIMV_CODEC_VC1_DEC_V6 10 |
348 | /* FIXME: Add 11~12 */ |
349 | #define S5P_FIMV_CODEC_MPEG2_DEC_V6 13 |
350 | #define S5P_FIMV_CODEC_VP8_DEC_V6 14 |
351 | /* FIXME: Add 15~16 */ |
352 | #define S5P_FIMV_CODEC_H264_ENC_V6 20 |
353 | #define S5P_FIMV_CODEC_H264_MVC_ENC_V6 21 |
354 | |
355 | #define S5P_FIMV_CODEC_MPEG4_ENC_V6 23 |
356 | #define S5P_FIMV_CODEC_H263_ENC_V6 24 |
357 | |
358 | #define S5P_FIMV_NV12M_HALIGN_V6 16 |
359 | #define S5P_FIMV_NV12MT_HALIGN_V6 16 |
360 | #define S5P_FIMV_NV12MT_VALIGN_V6 16 |
361 | |
362 | #define S5P_FIMV_TMV_BUFFER_ALIGN_V6 16 |
363 | #define S5P_FIMV_LUMA_DPB_BUFFER_ALIGN_V6 256 |
364 | #define S5P_FIMV_CHROMA_DPB_BUFFER_ALIGN_V6 256 |
365 | #define S5P_FIMV_ME_BUFFER_ALIGN_V6 256 |
366 | #define S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6 256 |
367 | |
368 | #define S5P_FIMV_LUMA_MB_TO_PIXEL_V6 256 |
369 | #define S5P_FIMV_CHROMA_MB_TO_PIXEL_V6 128 |
370 | #define S5P_FIMV_NUM_TMV_BUFFERS_V6 2 |
371 | |
372 | #define S5P_FIMV_MAX_FRAME_SIZE_V6 (2 * SZ_1M) |
373 | #define S5P_FIMV_NUM_PIXELS_IN_MB_ROW_V6 16 |
374 | #define S5P_FIMV_NUM_PIXELS_IN_MB_COL_V6 16 |
375 | |
376 | /* Buffer size requirements defined by hardware */ |
377 | #define S5P_FIMV_TMV_BUFFER_SIZE_V6(w, h) (((w) + 1) * ((h) + 3) * 8) |
378 | #define S5P_FIMV_ME_BUFFER_SIZE_V6(imw, imh, mbw, mbh) \ |
379 | (((((imw + 127) / 64) * 16) * DIV_ROUND_UP(imh, 64) * 256) + \ |
380 | (DIV_ROUND_UP((mbw) * (mbh), 32) * 16)) |
381 | #define S5P_FIMV_SCRATCH_BUF_SIZE_H264_DEC_V6(w, h) (((w) * 192) + 64) |
382 | #define S5P_FIMV_SCRATCH_BUF_SIZE_MPEG4_DEC_V6(w, h) \ |
383 | ((w) * 144 + 8192 * (h) + 49216 + 1048576) |
384 | #define S5P_FIMV_SCRATCH_BUF_SIZE_VC1_DEC_V6(w, h) \ |
385 | (2096 * ((w) + (h) + 1)) |
386 | #define S5P_FIMV_SCRATCH_BUF_SIZE_H263_DEC_V6(w, h) \ |
387 | S5P_FIMV_SCRATCH_BUF_SIZE_MPEG4_DEC_V6(w, h) |
388 | #define S5P_FIMV_SCRATCH_BUF_SIZE_VP8_DEC_V6(w, h) \ |
389 | ((w) * 32 + (h) * 128 + (((w) + 1) / 2) * 64 + 2112) |
390 | #define S5P_FIMV_SCRATCH_BUF_SIZE_H264_ENC_V6(w, h) \ |
391 | (((w) * 64) + (((w) + 1) * 16) + (4096 * 16)) |
392 | #define S5P_FIMV_SCRATCH_BUF_SIZE_MPEG4_ENC_V6(w, h) \ |
393 | (((w) * 16) + (((w) + 1) * 16)) |
394 | |
395 | /* MFC Context buffer sizes */ |
396 | #define MFC_CTX_BUF_SIZE_V6 (28 * SZ_1K) /* 28KB */ |
397 | #define MFC_H264_DEC_CTX_BUF_SIZE_V6 (2 * SZ_1M) /* 2MB */ |
398 | #define MFC_OTHER_DEC_CTX_BUF_SIZE_V6 (20 * SZ_1K) /* 20KB */ |
399 | #define MFC_H264_ENC_CTX_BUF_SIZE_V6 (100 * SZ_1K) /* 100KB */ |
400 | #define MFC_OTHER_ENC_CTX_BUF_SIZE_V6 (12 * SZ_1K) /* 12KB */ |
401 | |
402 | /* MFCv6 variant defines */ |
403 | #define MAX_FW_SIZE_V6 (SZ_512K) /* 512KB */ |
404 | #define MAX_CPB_SIZE_V6 (3 * SZ_1M) /* 3MB */ |
405 | #define MFC_VERSION_V6 0x61 |
406 | #define MFC_NUM_PORTS_V6 1 |
407 | |
408 | #endif /* _REGS_FIMV_V6_H */ |
409 | |