1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* |
3 | * Copyright (c) 2013 Texas Instruments Inc. |
4 | * |
5 | * David Griego, <dagriego@biglakesoftware.com> |
6 | * Dale Farnsworth, <dale@farnsworth.org> |
7 | * Archit Taneja, <archit@ti.com> |
8 | */ |
9 | #ifndef TI_SC_H |
10 | #define TI_SC_H |
11 | |
12 | /* Scaler regs */ |
13 | #define CFG_SC0 0x0 |
14 | #define CFG_INTERLACE_O (1 << 0) |
15 | #define CFG_LINEAR (1 << 1) |
16 | #define CFG_SC_BYPASS (1 << 2) |
17 | #define CFG_INVT_FID (1 << 3) |
18 | #define CFG_USE_RAV (1 << 4) |
19 | #define CFG_ENABLE_EV (1 << 5) |
20 | #define CFG_AUTO_HS (1 << 6) |
21 | #define CFG_DCM_2X (1 << 7) |
22 | #define CFG_DCM_4X (1 << 8) |
23 | #define CFG_HP_BYPASS (1 << 9) |
24 | #define CFG_INTERLACE_I (1 << 10) |
25 | #define CFG_ENABLE_SIN2_VER_INTP (1 << 11) |
26 | #define CFG_Y_PK_EN (1 << 14) |
27 | #define CFG_TRIM (1 << 15) |
28 | #define CFG_SELFGEN_FID (1 << 16) |
29 | |
30 | #define CFG_SC1 0x4 |
31 | #define CFG_ROW_ACC_INC_MASK 0x07ffffff |
32 | #define CFG_ROW_ACC_INC_SHIFT 0 |
33 | |
34 | #define CFG_SC2 0x08 |
35 | #define CFG_ROW_ACC_OFFSET_MASK 0x0fffffff |
36 | #define CFG_ROW_ACC_OFFSET_SHIFT 0 |
37 | |
38 | #define CFG_SC3 0x0c |
39 | #define CFG_ROW_ACC_OFFSET_B_MASK 0x0fffffff |
40 | #define CFG_ROW_ACC_OFFSET_B_SHIFT 0 |
41 | |
42 | #define CFG_SC4 0x10 |
43 | #define CFG_TAR_H_MASK 0x07ff |
44 | #define CFG_TAR_H_SHIFT 0 |
45 | #define CFG_TAR_W_MASK 0x07ff |
46 | #define CFG_TAR_W_SHIFT 12 |
47 | #define CFG_LIN_ACC_INC_U_MASK 0x07 |
48 | #define CFG_LIN_ACC_INC_U_SHIFT 24 |
49 | #define CFG_NLIN_ACC_INIT_U_MASK 0x07 |
50 | #define CFG_NLIN_ACC_INIT_U_SHIFT 28 |
51 | |
52 | #define CFG_SC5 0x14 |
53 | #define CFG_SRC_H_MASK 0x07ff |
54 | #define CFG_SRC_H_SHIFT 0 |
55 | #define CFG_SRC_W_MASK 0x07ff |
56 | #define CFG_SRC_W_SHIFT 12 |
57 | #define CFG_NLIN_ACC_INC_U_MASK 0x07 |
58 | #define CFG_NLIN_ACC_INC_U_SHIFT 24 |
59 | |
60 | #define CFG_SC6 0x18 |
61 | #define CFG_ROW_ACC_INIT_RAV_MASK 0x03ff |
62 | #define CFG_ROW_ACC_INIT_RAV_SHIFT 0 |
63 | #define CFG_ROW_ACC_INIT_RAV_B_MASK 0x03ff |
64 | #define CFG_ROW_ACC_INIT_RAV_B_SHIFT 10 |
65 | |
66 | #define CFG_SC8 0x20 |
67 | #define CFG_NLIN_LEFT_MASK 0x07ff |
68 | #define CFG_NLIN_LEFT_SHIFT 0 |
69 | #define CFG_NLIN_RIGHT_MASK 0x07ff |
70 | #define CFG_NLIN_RIGHT_SHIFT 12 |
71 | |
72 | #define CFG_SC9 0x24 |
73 | #define CFG_LIN_ACC_INC CFG_SC9 |
74 | |
75 | #define CFG_SC10 0x28 |
76 | #define CFG_NLIN_ACC_INIT CFG_SC10 |
77 | |
78 | #define CFG_SC11 0x2c |
79 | #define CFG_NLIN_ACC_INC CFG_SC11 |
80 | |
81 | #define CFG_SC12 0x30 |
82 | #define CFG_COL_ACC_OFFSET_MASK 0x01ffffff |
83 | #define CFG_COL_ACC_OFFSET_SHIFT 0 |
84 | |
85 | #define CFG_SC13 0x34 |
86 | #define CFG_SC_FACTOR_RAV_MASK 0xff |
87 | #define CFG_SC_FACTOR_RAV_SHIFT 0 |
88 | #define CFG_CHROMA_INTP_THR_MASK 0x03ff |
89 | #define CFG_CHROMA_INTP_THR_SHIFT 12 |
90 | #define CFG_DELTA_CHROMA_THR_MASK 0x0f |
91 | #define CFG_DELTA_CHROMA_THR_SHIFT 24 |
92 | |
93 | #define CFG_SC17 0x44 |
94 | #define CFG_EV_THR_MASK 0x03ff |
95 | #define CFG_EV_THR_SHIFT 12 |
96 | #define CFG_DELTA_LUMA_THR_MASK 0x0f |
97 | #define CFG_DELTA_LUMA_THR_SHIFT 24 |
98 | #define CFG_DELTA_EV_THR_MASK 0x0f |
99 | #define CFG_DELTA_EV_THR_SHIFT 28 |
100 | |
101 | #define CFG_SC18 0x48 |
102 | #define CFG_HS_FACTOR_MASK 0x03ff |
103 | #define CFG_HS_FACTOR_SHIFT 0 |
104 | #define CFG_CONF_DEFAULT_MASK 0x01ff |
105 | #define CFG_CONF_DEFAULT_SHIFT 16 |
106 | |
107 | #define CFG_SC19 0x4c |
108 | #define CFG_HPF_COEFF0_MASK 0xff |
109 | #define CFG_HPF_COEFF0_SHIFT 0 |
110 | #define CFG_HPF_COEFF1_MASK 0xff |
111 | #define CFG_HPF_COEFF1_SHIFT 8 |
112 | #define CFG_HPF_COEFF2_MASK 0xff |
113 | #define CFG_HPF_COEFF2_SHIFT 16 |
114 | #define CFG_HPF_COEFF3_MASK 0xff |
115 | #define CFG_HPF_COEFF3_SHIFT 23 |
116 | |
117 | #define CFG_SC20 0x50 |
118 | #define CFG_HPF_COEFF4_MASK 0xff |
119 | #define CFG_HPF_COEFF4_SHIFT 0 |
120 | #define CFG_HPF_COEFF5_MASK 0xff |
121 | #define CFG_HPF_COEFF5_SHIFT 8 |
122 | #define CFG_HPF_NORM_SHIFT_MASK 0x07 |
123 | #define CFG_HPF_NORM_SHIFT_SHIFT 16 |
124 | #define CFG_NL_LIMIT_MASK 0x1ff |
125 | #define CFG_NL_LIMIT_SHIFT 20 |
126 | |
127 | #define CFG_SC21 0x54 |
128 | #define CFG_NL_LO_THR_MASK 0x01ff |
129 | #define CFG_NL_LO_THR_SHIFT 0 |
130 | #define CFG_NL_LO_SLOPE_MASK 0xff |
131 | #define CFG_NL_LO_SLOPE_SHIFT 16 |
132 | |
133 | #define CFG_SC22 0x58 |
134 | #define CFG_NL_HI_THR_MASK 0x01ff |
135 | #define CFG_NL_HI_THR_SHIFT 0 |
136 | #define CFG_NL_HI_SLOPE_SH_MASK 0x07 |
137 | #define CFG_NL_HI_SLOPE_SH_SHIFT 16 |
138 | |
139 | #define CFG_SC23 0x5c |
140 | #define CFG_GRADIENT_THR_MASK 0x07ff |
141 | #define CFG_GRADIENT_THR_SHIFT 0 |
142 | #define CFG_GRADIENT_THR_RANGE_MASK 0x0f |
143 | #define CFG_GRADIENT_THR_RANGE_SHIFT 12 |
144 | #define CFG_MIN_GY_THR_MASK 0xff |
145 | #define CFG_MIN_GY_THR_SHIFT 16 |
146 | #define CFG_MIN_GY_THR_RANGE_MASK 0x0f |
147 | #define CFG_MIN_GY_THR_RANGE_SHIFT 28 |
148 | |
149 | #define CFG_SC24 0x60 |
150 | #define CFG_ORG_H_MASK 0x07ff |
151 | #define CFG_ORG_H_SHIFT 0 |
152 | #define CFG_ORG_W_MASK 0x07ff |
153 | #define CFG_ORG_W_SHIFT 16 |
154 | |
155 | #define CFG_SC25 0x64 |
156 | #define CFG_OFF_H_MASK 0x07ff |
157 | #define CFG_OFF_H_SHIFT 0 |
158 | #define CFG_OFF_W_MASK 0x07ff |
159 | #define CFG_OFF_W_SHIFT 16 |
160 | |
161 | /* number of phases supported by the polyphase scalers */ |
162 | #define SC_NUM_PHASES 32 |
163 | |
164 | /* number of taps used by horizontal polyphase scaler */ |
165 | #define SC_H_NUM_TAPS 7 |
166 | |
167 | /* number of taps used by vertical polyphase scaler */ |
168 | #define SC_V_NUM_TAPS 5 |
169 | |
170 | /* number of taps expected by the scaler in it's coefficient memory */ |
171 | #define SC_NUM_TAPS_MEM_ALIGN 8 |
172 | |
173 | /* Maximum frame width the scaler can handle (in pixels) */ |
174 | #define SC_MAX_PIXEL_WIDTH 2047 |
175 | |
176 | /* Maximum frame height the scaler can handle (in lines) */ |
177 | #define SC_MAX_PIXEL_HEIGHT 2047 |
178 | |
179 | /* |
180 | * coefficient memory size in bytes: |
181 | * num phases x num sets(luma and chroma) x num taps(aligned) x coeff size |
182 | */ |
183 | #define SC_COEF_SRAM_SIZE (SC_NUM_PHASES * 2 * SC_NUM_TAPS_MEM_ALIGN * 2) |
184 | |
185 | struct sc_data { |
186 | void __iomem *base; |
187 | struct resource *res; |
188 | |
189 | dma_addr_t loaded_coeff_h; /* loaded h coeffs in SC */ |
190 | dma_addr_t loaded_coeff_v; /* loaded v coeffs in SC */ |
191 | |
192 | bool load_coeff_h; /* have new h SC coeffs */ |
193 | bool load_coeff_v; /* have new v SC coeffs */ |
194 | |
195 | struct platform_device *pdev; |
196 | }; |
197 | |
198 | void sc_dump_regs(struct sc_data *sc); |
199 | void sc_set_hs_coeffs(struct sc_data *sc, void *addr, unsigned int src_w, |
200 | unsigned int dst_w); |
201 | void sc_set_vs_coeffs(struct sc_data *sc, void *addr, unsigned int src_h, |
202 | unsigned int dst_h); |
203 | void sc_config_scaler(struct sc_data *sc, u32 *sc_reg0, u32 *sc_reg8, |
204 | u32 *sc_reg17, unsigned int src_w, unsigned int src_h, |
205 | unsigned int dst_w, unsigned int dst_h); |
206 | struct sc_data *sc_create(struct platform_device *pdev, const char *res_name); |
207 | |
208 | #endif |
209 | |