| 1 | // SPDX-License-Identifier: GPL-2.0 |
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| 2 | /* |
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| 3 | * Hantro VPU codec driver |
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| 4 | * |
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| 5 | * Copyright (C) 2018 Rockchip Electronics Co., Ltd. |
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| 6 | * Jeffy Chen <jeffy.chen@rock-chips.com> |
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| 7 | * Copyright (C) 2019 Pengutronix, Philipp Zabel <kernel@pengutronix.de> |
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| 8 | * Copyright (C) 2021 Collabora Ltd, Emil Velikov <emil.velikov@collabora.com> |
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| 9 | */ |
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| 10 | |
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| 11 | #include "hantro.h" |
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| 12 | #include "hantro_g1_regs.h" |
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| 13 | |
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| 14 | irqreturn_t hantro_g1_irq(int irq, void *dev_id) |
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| 15 | { |
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| 16 | struct hantro_dev *vpu = dev_id; |
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| 17 | enum vb2_buffer_state state; |
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| 18 | u32 status; |
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| 19 | |
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| 20 | status = vdpu_read(vpu, G1_REG_INTERRUPT); |
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| 21 | state = (status & G1_REG_INTERRUPT_DEC_RDY_INT) ? |
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| 22 | VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR; |
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| 23 | |
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| 24 | vdpu_write(vpu, val: 0, G1_REG_INTERRUPT); |
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| 25 | vdpu_write(vpu, G1_REG_CONFIG_DEC_CLK_GATE_E, G1_REG_CONFIG); |
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| 26 | |
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| 27 | hantro_irq_done(vpu, result: state); |
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| 28 | |
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| 29 | return IRQ_HANDLED; |
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| 30 | } |
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| 31 | |
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| 32 | void hantro_g1_reset(struct hantro_ctx *ctx) |
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| 33 | { |
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| 34 | struct hantro_dev *vpu = ctx->dev; |
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| 35 | |
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| 36 | vdpu_write(vpu, G1_REG_INTERRUPT_DEC_IRQ_DIS, G1_REG_INTERRUPT); |
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| 37 | vdpu_write(vpu, G1_REG_CONFIG_DEC_CLK_GATE_E, G1_REG_CONFIG); |
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| 38 | vdpu_write(vpu, val: 1, G1_REG_SOFT_RESET); |
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| 39 | } |
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| 40 | |
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