1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* |
3 | * Xilinx Video IP Core |
4 | * |
5 | * Copyright (C) 2013-2015 Ideas on Board |
6 | * Copyright (C) 2013-2015 Xilinx, Inc. |
7 | * |
8 | * Contacts: Hyun Kwon <hyun.kwon@xilinx.com> |
9 | * Laurent Pinchart <laurent.pinchart@ideasonboard.com> |
10 | */ |
11 | |
12 | #ifndef __XILINX_VIP_H__ |
13 | #define __XILINX_VIP_H__ |
14 | |
15 | #include <linux/bitops.h> |
16 | #include <linux/io.h> |
17 | #include <media/v4l2-subdev.h> |
18 | |
19 | struct clk; |
20 | |
21 | /* |
22 | * Minimum and maximum width and height common to most video IP cores. IP |
23 | * cores with different requirements must define their own values. |
24 | */ |
25 | #define XVIP_MIN_WIDTH 32 |
26 | #define XVIP_MAX_WIDTH 7680 |
27 | #define XVIP_MIN_HEIGHT 32 |
28 | #define XVIP_MAX_HEIGHT 7680 |
29 | |
30 | /* |
31 | * Pad IDs. IP cores with multiple inputs or outputs should define their own |
32 | * values. |
33 | */ |
34 | #define XVIP_PAD_SINK 0 |
35 | #define XVIP_PAD_SOURCE 1 |
36 | |
37 | /* Xilinx Video IP Control Registers */ |
38 | #define XVIP_CTRL_CONTROL 0x0000 |
39 | #define XVIP_CTRL_CONTROL_SW_ENABLE BIT(0) |
40 | #define XVIP_CTRL_CONTROL_REG_UPDATE BIT(1) |
41 | #define XVIP_CTRL_CONTROL_BYPASS BIT(4) |
42 | #define XVIP_CTRL_CONTROL_TEST_PATTERN BIT(5) |
43 | #define XVIP_CTRL_CONTROL_FRAME_SYNC_RESET BIT(30) |
44 | #define XVIP_CTRL_CONTROL_SW_RESET BIT(31) |
45 | #define XVIP_CTRL_STATUS 0x0004 |
46 | #define XVIP_CTRL_STATUS_PROC_STARTED BIT(0) |
47 | #define XVIP_CTRL_STATUS_EOF BIT(1) |
48 | #define XVIP_CTRL_ERROR 0x0008 |
49 | #define XVIP_CTRL_ERROR_SLAVE_EOL_EARLY BIT(0) |
50 | #define XVIP_CTRL_ERROR_SLAVE_EOL_LATE BIT(1) |
51 | #define XVIP_CTRL_ERROR_SLAVE_SOF_EARLY BIT(2) |
52 | #define XVIP_CTRL_ERROR_SLAVE_SOF_LATE BIT(3) |
53 | #define XVIP_CTRL_IRQ_ENABLE 0x000c |
54 | #define XVIP_CTRL_IRQ_ENABLE_PROC_STARTED BIT(0) |
55 | #define XVIP_CTRL_IRQ_EOF BIT(1) |
56 | #define XVIP_CTRL_VERSION 0x0010 |
57 | #define XVIP_CTRL_VERSION_MAJOR_MASK (0xff << 24) |
58 | #define XVIP_CTRL_VERSION_MAJOR_SHIFT 24 |
59 | #define XVIP_CTRL_VERSION_MINOR_MASK (0xff << 16) |
60 | #define XVIP_CTRL_VERSION_MINOR_SHIFT 16 |
61 | #define XVIP_CTRL_VERSION_REVISION_MASK (0xf << 12) |
62 | #define XVIP_CTRL_VERSION_REVISION_SHIFT 12 |
63 | #define XVIP_CTRL_VERSION_PATCH_MASK (0xf << 8) |
64 | #define XVIP_CTRL_VERSION_PATCH_SHIFT 8 |
65 | #define XVIP_CTRL_VERSION_INTERNAL_MASK (0xff << 0) |
66 | #define XVIP_CTRL_VERSION_INTERNAL_SHIFT 0 |
67 | |
68 | /* Xilinx Video IP Timing Registers */ |
69 | #define XVIP_ACTIVE_SIZE 0x0020 |
70 | #define XVIP_ACTIVE_VSIZE_MASK (0x7ff << 16) |
71 | #define XVIP_ACTIVE_VSIZE_SHIFT 16 |
72 | #define XVIP_ACTIVE_HSIZE_MASK (0x7ff << 0) |
73 | #define XVIP_ACTIVE_HSIZE_SHIFT 0 |
74 | #define XVIP_ENCODING 0x0028 |
75 | #define XVIP_ENCODING_NBITS_8 (0 << 4) |
76 | #define XVIP_ENCODING_NBITS_10 (1 << 4) |
77 | #define XVIP_ENCODING_NBITS_12 (2 << 4) |
78 | #define XVIP_ENCODING_NBITS_16 (3 << 4) |
79 | #define XVIP_ENCODING_NBITS_MASK (3 << 4) |
80 | #define XVIP_ENCODING_NBITS_SHIFT 4 |
81 | #define XVIP_ENCODING_VIDEO_FORMAT_YUV422 (0 << 0) |
82 | #define XVIP_ENCODING_VIDEO_FORMAT_YUV444 (1 << 0) |
83 | #define XVIP_ENCODING_VIDEO_FORMAT_RGB (2 << 0) |
84 | #define XVIP_ENCODING_VIDEO_FORMAT_YUV420 (3 << 0) |
85 | #define XVIP_ENCODING_VIDEO_FORMAT_MASK (3 << 0) |
86 | #define XVIP_ENCODING_VIDEO_FORMAT_SHIFT 0 |
87 | |
88 | /** |
89 | * struct xvip_device - Xilinx Video IP device structure |
90 | * @subdev: V4L2 subdevice |
91 | * @dev: (OF) device |
92 | * @iomem: device I/O register space remapped to kernel virtual memory |
93 | * @clk: video core clock |
94 | * @saved_ctrl: saved control register for resume / suspend |
95 | */ |
96 | struct xvip_device { |
97 | struct v4l2_subdev subdev; |
98 | struct device *dev; |
99 | void __iomem *iomem; |
100 | struct clk *clk; |
101 | u32 saved_ctrl; |
102 | }; |
103 | |
104 | /** |
105 | * struct xvip_video_format - Xilinx Video IP video format description |
106 | * @vf_code: AXI4 video format code |
107 | * @width: AXI4 format width in bits per component |
108 | * @pattern: CFA pattern for Mono/Sensor formats |
109 | * @code: media bus format code |
110 | * @bpp: bytes per pixel (when stored in memory) |
111 | * @fourcc: V4L2 pixel format FCC identifier |
112 | */ |
113 | struct xvip_video_format { |
114 | unsigned int vf_code; |
115 | unsigned int width; |
116 | const char *pattern; |
117 | unsigned int code; |
118 | unsigned int bpp; |
119 | u32 fourcc; |
120 | }; |
121 | |
122 | const struct xvip_video_format *xvip_get_format_by_code(unsigned int code); |
123 | const struct xvip_video_format *xvip_get_format_by_fourcc(u32 fourcc); |
124 | const struct xvip_video_format *xvip_of_get_format(struct device_node *node); |
125 | void xvip_set_format_size(struct v4l2_mbus_framefmt *format, |
126 | const struct v4l2_subdev_format *fmt); |
127 | int xvip_enum_mbus_code(struct v4l2_subdev *subdev, |
128 | struct v4l2_subdev_state *sd_state, |
129 | struct v4l2_subdev_mbus_code_enum *code); |
130 | int xvip_enum_frame_size(struct v4l2_subdev *subdev, |
131 | struct v4l2_subdev_state *sd_state, |
132 | struct v4l2_subdev_frame_size_enum *fse); |
133 | |
134 | static inline u32 xvip_read(struct xvip_device *xvip, u32 addr) |
135 | { |
136 | return ioread32(xvip->iomem + addr); |
137 | } |
138 | |
139 | static inline void xvip_write(struct xvip_device *xvip, u32 addr, u32 value) |
140 | { |
141 | iowrite32(value, xvip->iomem + addr); |
142 | } |
143 | |
144 | static inline void xvip_clr(struct xvip_device *xvip, u32 addr, u32 clr) |
145 | { |
146 | xvip_write(xvip, addr, value: xvip_read(xvip, addr) & ~clr); |
147 | } |
148 | |
149 | static inline void xvip_set(struct xvip_device *xvip, u32 addr, u32 set) |
150 | { |
151 | xvip_write(xvip, addr, value: xvip_read(xvip, addr) | set); |
152 | } |
153 | |
154 | void xvip_clr_or_set(struct xvip_device *xvip, u32 addr, u32 mask, bool set); |
155 | void xvip_clr_and_set(struct xvip_device *xvip, u32 addr, u32 clr, u32 set); |
156 | |
157 | int xvip_init_resources(struct xvip_device *xvip); |
158 | void xvip_cleanup_resources(struct xvip_device *xvip); |
159 | |
160 | static inline void xvip_reset(struct xvip_device *xvip) |
161 | { |
162 | xvip_write(xvip, XVIP_CTRL_CONTROL, XVIP_CTRL_CONTROL_SW_RESET); |
163 | } |
164 | |
165 | static inline void xvip_start(struct xvip_device *xvip) |
166 | { |
167 | xvip_set(xvip, XVIP_CTRL_CONTROL, |
168 | XVIP_CTRL_CONTROL_SW_ENABLE | XVIP_CTRL_CONTROL_REG_UPDATE); |
169 | } |
170 | |
171 | static inline void xvip_stop(struct xvip_device *xvip) |
172 | { |
173 | xvip_clr(xvip, XVIP_CTRL_CONTROL, XVIP_CTRL_CONTROL_SW_ENABLE); |
174 | } |
175 | |
176 | static inline void xvip_resume(struct xvip_device *xvip) |
177 | { |
178 | xvip_write(xvip, XVIP_CTRL_CONTROL, |
179 | value: xvip->saved_ctrl | XVIP_CTRL_CONTROL_SW_ENABLE); |
180 | } |
181 | |
182 | static inline void xvip_suspend(struct xvip_device *xvip) |
183 | { |
184 | xvip->saved_ctrl = xvip_read(xvip, XVIP_CTRL_CONTROL); |
185 | xvip_write(xvip, XVIP_CTRL_CONTROL, |
186 | value: xvip->saved_ctrl & ~XVIP_CTRL_CONTROL_SW_ENABLE); |
187 | } |
188 | |
189 | static inline void xvip_set_frame_size(struct xvip_device *xvip, |
190 | const struct v4l2_mbus_framefmt *format) |
191 | { |
192 | xvip_write(xvip, XVIP_ACTIVE_SIZE, |
193 | value: (format->height << XVIP_ACTIVE_VSIZE_SHIFT) | |
194 | (format->width << XVIP_ACTIVE_HSIZE_SHIFT)); |
195 | } |
196 | |
197 | static inline void xvip_get_frame_size(struct xvip_device *xvip, |
198 | struct v4l2_mbus_framefmt *format) |
199 | { |
200 | u32 reg; |
201 | |
202 | reg = xvip_read(xvip, XVIP_ACTIVE_SIZE); |
203 | format->width = (reg & XVIP_ACTIVE_HSIZE_MASK) >> |
204 | XVIP_ACTIVE_HSIZE_SHIFT; |
205 | format->height = (reg & XVIP_ACTIVE_VSIZE_MASK) >> |
206 | XVIP_ACTIVE_VSIZE_SHIFT; |
207 | } |
208 | |
209 | static inline void xvip_enable_reg_update(struct xvip_device *xvip) |
210 | { |
211 | xvip_set(xvip, XVIP_CTRL_CONTROL, XVIP_CTRL_CONTROL_REG_UPDATE); |
212 | } |
213 | |
214 | static inline void xvip_disable_reg_update(struct xvip_device *xvip) |
215 | { |
216 | xvip_clr(xvip, XVIP_CTRL_CONTROL, XVIP_CTRL_CONTROL_REG_UPDATE); |
217 | } |
218 | |
219 | static inline void xvip_print_version(struct xvip_device *xvip) |
220 | { |
221 | u32 version; |
222 | |
223 | version = xvip_read(xvip, XVIP_CTRL_VERSION); |
224 | |
225 | dev_info(xvip->dev, "device found, version %u.%02x%x\n" , |
226 | ((version & XVIP_CTRL_VERSION_MAJOR_MASK) >> |
227 | XVIP_CTRL_VERSION_MAJOR_SHIFT), |
228 | ((version & XVIP_CTRL_VERSION_MINOR_MASK) >> |
229 | XVIP_CTRL_VERSION_MINOR_SHIFT), |
230 | ((version & XVIP_CTRL_VERSION_REVISION_MASK) >> |
231 | XVIP_CTRL_VERSION_REVISION_SHIFT)); |
232 | } |
233 | |
234 | #endif /* __XILINX_VIP_H__ */ |
235 | |