| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * Copyright (C) STMicroelectronics 2009 |
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| 4 | * Copyright (C) ST-Ericsson SA 2010 |
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| 5 | * |
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| 6 | * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com> |
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| 7 | * Author: Sundar Iyer <sundar.iyer@stericsson.com> |
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| 8 | * |
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| 9 | * PRCM Unit registers |
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| 10 | */ |
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| 11 | |
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| 12 | #ifndef __DB8500_PRCMU_REGS_H |
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| 13 | #define __DB8500_PRCMU_REGS_H |
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| 14 | |
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| 15 | #define BITS(_start, _end) ((BIT(_end) - BIT(_start)) + BIT(_end)) |
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| 16 | |
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| 17 | #define PRCM_ACLK_MGT (0x004) |
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| 18 | #define PRCM_SVAMMCSPCLK_MGT (0x008) |
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| 19 | #define PRCM_SIAMMDSPCLK_MGT (0x00C) |
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| 20 | #define PRCM_SGACLK_MGT (0x014) |
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| 21 | #define PRCM_UARTCLK_MGT (0x018) |
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| 22 | #define PRCM_MSP02CLK_MGT (0x01C) |
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| 23 | #define PRCM_I2CCLK_MGT (0x020) |
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| 24 | #define PRCM_SDMMCCLK_MGT (0x024) |
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| 25 | #define PRCM_SLIMCLK_MGT (0x028) |
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| 26 | #define PRCM_PER1CLK_MGT (0x02C) |
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| 27 | #define PRCM_PER2CLK_MGT (0x030) |
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| 28 | #define PRCM_PER3CLK_MGT (0x034) |
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| 29 | #define PRCM_PER5CLK_MGT (0x038) |
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| 30 | #define PRCM_PER6CLK_MGT (0x03C) |
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| 31 | #define PRCM_PER7CLK_MGT (0x040) |
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| 32 | #define PRCM_LCDCLK_MGT (0x044) |
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| 33 | #define PRCM_BMLCLK_MGT (0x04C) |
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| 34 | #define PRCM_HSITXCLK_MGT (0x050) |
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| 35 | #define PRCM_HSIRXCLK_MGT (0x054) |
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| 36 | #define PRCM_HDMICLK_MGT (0x058) |
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| 37 | #define PRCM_APEATCLK_MGT (0x05C) |
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| 38 | #define PRCM_APETRACECLK_MGT (0x060) |
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| 39 | #define PRCM_MCDECLK_MGT (0x064) |
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| 40 | #define PRCM_IPI2CCLK_MGT (0x068) |
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| 41 | #define PRCM_DSIALTCLK_MGT (0x06C) |
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| 42 | #define PRCM_DMACLK_MGT (0x074) |
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| 43 | #define PRCM_B2R2CLK_MGT (0x078) |
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| 44 | #define PRCM_TVCLK_MGT (0x07C) |
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| 45 | #define PRCM_UNIPROCLK_MGT (0x278) |
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| 46 | #define PRCM_SSPCLK_MGT (0x280) |
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| 47 | #define PRCM_RNGCLK_MGT (0x284) |
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| 48 | #define PRCM_UICCCLK_MGT (0x27C) |
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| 49 | #define PRCM_MSP1CLK_MGT (0x288) |
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| 50 | |
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| 51 | #define PRCM_ARM_PLLDIVPS (prcmu_base + 0x118) |
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| 52 | #define PRCM_ARM_PLLDIVPS_ARM_BRM_RATE 0x3f |
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| 53 | #define PRCM_ARM_PLLDIVPS_MAX_MASK 0xf |
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| 54 | |
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| 55 | #define PRCM_PLLARM_LOCKP (prcmu_base + 0x0a8) |
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| 56 | #define PRCM_PLLARM_LOCKP_PRCM_PLLARM_LOCKP3 0x2 |
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| 57 | |
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| 58 | #define PRCM_ARM_CHGCLKREQ (prcmu_base + 0x114) |
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| 59 | #define PRCM_ARM_CHGCLKREQ_PRCM_ARM_CHGCLKREQ BIT(0) |
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| 60 | #define PRCM_ARM_CHGCLKREQ_PRCM_ARM_DIVSEL BIT(16) |
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| 61 | |
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| 62 | #define PRCM_PLLARM_ENABLE (prcmu_base + 0x98) |
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| 63 | #define PRCM_PLLARM_ENABLE_PRCM_PLLARM_ENABLE 0x1 |
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| 64 | #define PRCM_PLLARM_ENABLE_PRCM_PLLARM_COUNTON 0x100 |
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| 65 | |
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| 66 | #define PRCM_ARMCLKFIX_MGT (prcmu_base + 0x0) |
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| 67 | #define PRCM_A9PL_FORCE_CLKEN (prcmu_base + 0x19C) |
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| 68 | #define PRCM_A9_RESETN_CLR (prcmu_base + 0x1f4) |
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| 69 | #define PRCM_A9_RESETN_SET (prcmu_base + 0x1f0) |
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| 70 | #define PRCM_ARM_LS_CLAMP (prcmu_base + 0x30c) |
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| 71 | #define PRCM_SRAM_A9 (prcmu_base + 0x308) |
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| 72 | |
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| 73 | #define PRCM_A9PL_FORCE_CLKEN_PRCM_A9PL_FORCE_CLKEN BIT(0) |
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| 74 | #define PRCM_A9PL_FORCE_CLKEN_PRCM_A9AXI_FORCE_CLKEN BIT(1) |
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| 75 | |
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| 76 | /* CPU mailbox registers */ |
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| 77 | #define PRCM_MBOX_CPU_VAL (prcmu_base + 0x0fc) |
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| 78 | #define PRCM_MBOX_CPU_SET (prcmu_base + 0x100) |
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| 79 | #define PRCM_MBOX_CPU_CLR (prcmu_base + 0x104) |
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| 80 | |
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| 81 | #define PRCM_HOSTACCESS_REQ (prcmu_base + 0x334) |
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| 82 | #define PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ 0x1 |
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| 83 | #define PRCM_HOSTACCESS_REQ_WAKE_REQ BIT(16) |
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| 84 | #define ARM_WAKEUP_MODEM 0x1 |
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| 85 | |
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| 86 | #define PRCM_ARM_IT1_CLR (prcmu_base + 0x48C) |
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| 87 | #define PRCM_ARM_IT1_VAL (prcmu_base + 0x494) |
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| 88 | #define PRCM_HOLD_EVT (prcmu_base + 0x174) |
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| 89 | |
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| 90 | #define PRCM_MOD_AWAKE_STATUS (prcmu_base + 0x4A0) |
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| 91 | #define PRCM_MOD_AWAKE_STATUS_PRCM_MOD_COREPD_AWAKE BIT(0) |
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| 92 | #define PRCM_MOD_AWAKE_STATUS_PRCM_MOD_AAPD_AWAKE BIT(1) |
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| 93 | #define PRCM_MOD_AWAKE_STATUS_PRCM_MOD_VMODEM_OFF_ISO BIT(2) |
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| 94 | |
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| 95 | #define PRCM_ITSTATUS0 (prcmu_base + 0x148) |
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| 96 | #define PRCM_ITSTATUS1 (prcmu_base + 0x150) |
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| 97 | #define PRCM_ITSTATUS2 (prcmu_base + 0x158) |
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| 98 | #define PRCM_ITSTATUS3 (prcmu_base + 0x160) |
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| 99 | #define PRCM_ITSTATUS4 (prcmu_base + 0x168) |
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| 100 | #define PRCM_ITSTATUS5 (prcmu_base + 0x484) |
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| 101 | #define PRCM_ITCLEAR5 (prcmu_base + 0x488) |
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| 102 | #define PRCM_ARMIT_MASKXP70_IT (prcmu_base + 0x1018) |
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| 103 | |
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| 104 | /* System reset register */ |
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| 105 | #define PRCM_APE_SOFTRST (prcmu_base + 0x228) |
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| 106 | |
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| 107 | /* Level shifter and clamp control registers */ |
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| 108 | #define PRCM_MMIP_LS_CLAMP_SET (prcmu_base + 0x420) |
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| 109 | #define PRCM_MMIP_LS_CLAMP_CLR (prcmu_base + 0x424) |
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| 110 | |
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| 111 | #define PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP BIT(11) |
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| 112 | #define PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI BIT(22) |
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| 113 | |
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| 114 | /* PRCMU clock/PLL/reset registers */ |
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| 115 | #define PRCM_PLLSOC0_FREQ (prcmu_base + 0x080) |
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| 116 | #define PRCM_PLLSOC1_FREQ (prcmu_base + 0x084) |
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| 117 | #define PRCM_PLLARM_FREQ (prcmu_base + 0x088) |
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| 118 | #define PRCM_PLLDDR_FREQ (prcmu_base + 0x08C) |
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| 119 | #define PRCM_PLL_FREQ_D_SHIFT 0 |
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| 120 | #define PRCM_PLL_FREQ_D_MASK BITS(0, 7) |
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| 121 | #define PRCM_PLL_FREQ_N_SHIFT 8 |
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| 122 | #define PRCM_PLL_FREQ_N_MASK BITS(8, 13) |
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| 123 | #define PRCM_PLL_FREQ_R_SHIFT 16 |
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| 124 | #define PRCM_PLL_FREQ_R_MASK BITS(16, 18) |
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| 125 | #define PRCM_PLL_FREQ_SELDIV2 BIT(24) |
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| 126 | #define PRCM_PLL_FREQ_DIV2EN BIT(25) |
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| 127 | |
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| 128 | #define PRCM_PLLDSI_FREQ (prcmu_base + 0x500) |
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| 129 | #define PRCM_PLLDSI_ENABLE (prcmu_base + 0x504) |
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| 130 | #define PRCM_PLLDSI_LOCKP (prcmu_base + 0x508) |
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| 131 | #define PRCM_DSI_PLLOUT_SEL (prcmu_base + 0x530) |
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| 132 | #define PRCM_DSITVCLK_DIV (prcmu_base + 0x52C) |
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| 133 | #define PRCM_PLLDSI_LOCKP (prcmu_base + 0x508) |
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| 134 | #define PRCM_APE_RESETN_SET (prcmu_base + 0x1E4) |
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| 135 | #define PRCM_APE_RESETN_CLR (prcmu_base + 0x1E8) |
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| 136 | |
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| 137 | #define PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE BIT(0) |
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| 138 | |
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| 139 | #define PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 BIT(0) |
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| 140 | #define PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3 BIT(1) |
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| 141 | |
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| 142 | #define PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_SHIFT 0 |
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| 143 | #define PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_MASK BITS(0, 2) |
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| 144 | #define PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_SHIFT 8 |
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| 145 | #define PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_MASK BITS(8, 10) |
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| 146 | |
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| 147 | #define PRCM_DSI_PLLOUT_SEL_OFF 0 |
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| 148 | #define PRCM_DSI_PLLOUT_SEL_PHI 1 |
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| 149 | #define PRCM_DSI_PLLOUT_SEL_PHI_2 2 |
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| 150 | #define PRCM_DSI_PLLOUT_SEL_PHI_4 3 |
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| 151 | |
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| 152 | #define PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_SHIFT 0 |
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| 153 | #define PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_MASK BITS(0, 7) |
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| 154 | #define PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_SHIFT 8 |
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| 155 | #define PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_MASK BITS(8, 15) |
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| 156 | #define PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_SHIFT 16 |
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| 157 | #define PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_MASK BITS(16, 23) |
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| 158 | #define PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_EN BIT(24) |
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| 159 | #define PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_EN BIT(25) |
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| 160 | #define PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_EN BIT(26) |
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| 161 | |
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| 162 | #define PRCM_APE_RESETN_DSIPLL_RESETN BIT(14) |
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| 163 | |
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| 164 | #define PRCM_CLKOCR (prcmu_base + 0x1CC) |
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| 165 | #define PRCM_CLKOCR_CLKOUT0_REF_CLK (1 << 0) |
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| 166 | #define PRCM_CLKOCR_CLKOUT0_MASK BITS(0, 13) |
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| 167 | #define PRCM_CLKOCR_CLKOUT1_REF_CLK (1 << 16) |
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| 168 | #define PRCM_CLKOCR_CLKOUT1_MASK BITS(16, 29) |
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| 169 | |
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| 170 | /* ePOD and memory power signal control registers */ |
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| 171 | #define PRCM_EPOD_C_SET (prcmu_base + 0x410) |
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| 172 | #define PRCM_SRAM_LS_SLEEP (prcmu_base + 0x304) |
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| 173 | |
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| 174 | /* Debug power control unit registers */ |
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| 175 | #define PRCM_POWER_STATE_SET (prcmu_base + 0x254) |
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| 176 | |
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| 177 | /* Miscellaneous unit registers */ |
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| 178 | #define PRCM_DSI_SW_RESET (prcmu_base + 0x324) |
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| 179 | #define PRCM_GPIOCR (prcmu_base + 0x138) |
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| 180 | #define PRCM_GPIOCR_DBG_STM_MOD_CMD1 0x800 |
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| 181 | #define PRCM_GPIOCR_DBG_UARTMOD_CMD0 0x1 |
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| 182 | |
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| 183 | /* PRCMU HW semaphore */ |
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| 184 | #define PRCM_SEM (prcmu_base + 0x400) |
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| 185 | #define PRCM_SEM_PRCM_SEM BIT(0) |
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| 186 | |
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| 187 | #define PRCM_TCR (prcmu_base + 0x1C8) |
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| 188 | #define PRCM_TCR_TENSEL_MASK BITS(0, 7) |
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| 189 | #define PRCM_TCR_STOP_TIMERS BIT(16) |
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| 190 | #define PRCM_TCR_DOZE_MODE BIT(17) |
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| 191 | |
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| 192 | #define PRCM_CLKOCR_CLKODIV0_SHIFT 0 |
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| 193 | #define PRCM_CLKOCR_CLKODIV0_MASK BITS(0, 5) |
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| 194 | #define PRCM_CLKOCR_CLKOSEL0_SHIFT 6 |
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| 195 | #define PRCM_CLKOCR_CLKOSEL0_MASK BITS(6, 8) |
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| 196 | #define PRCM_CLKOCR_CLKODIV1_SHIFT 16 |
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| 197 | #define PRCM_CLKOCR_CLKODIV1_MASK BITS(16, 21) |
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| 198 | #define PRCM_CLKOCR_CLKOSEL1_SHIFT 22 |
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| 199 | #define PRCM_CLKOCR_CLKOSEL1_MASK BITS(22, 24) |
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| 200 | #define PRCM_CLKOCR_CLK1TYPE BIT(28) |
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| 201 | |
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| 202 | #define PRCM_CLK_MGT_CLKPLLDIV_MASK BITS(0, 4) |
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| 203 | #define PRCM_CLK_MGT_CLKPLLSW_SOC0 BIT(5) |
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| 204 | #define PRCM_CLK_MGT_CLKPLLSW_SOC1 BIT(6) |
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| 205 | #define PRCM_CLK_MGT_CLKPLLSW_DDR BIT(7) |
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| 206 | #define PRCM_CLK_MGT_CLKPLLSW_MASK BITS(5, 7) |
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| 207 | #define PRCM_CLK_MGT_CLKEN BIT(8) |
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| 208 | #define PRCM_CLK_MGT_CLK38 BIT(9) |
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| 209 | #define PRCM_CLK_MGT_CLK38DIV BIT(11) |
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| 210 | #define PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN BIT(12) |
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| 211 | |
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| 212 | /* GPIOCR register */ |
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| 213 | #define PRCM_GPIOCR_SPI2_SELECT BIT(23) |
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| 214 | |
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| 215 | #define PRCM_DDR_SUBSYS_APE_MINBW (prcmu_base + 0x438) |
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| 216 | #define PRCM_CGATING_BYPASS (prcmu_base + 0x134) |
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| 217 | #define PRCM_CGATING_BYPASS_ICN2 BIT(6) |
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| 218 | |
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| 219 | /* Miscellaneous unit registers */ |
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| 220 | #define PRCM_RESOUTN_SET (prcmu_base + 0x214) |
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| 221 | #define PRCM_RESOUTN_CLR (prcmu_base + 0x218) |
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| 222 | |
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| 223 | /* System reset register */ |
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| 224 | #define PRCM_APE_SOFTRST (prcmu_base + 0x228) |
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| 225 | |
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| 226 | #endif /* __DB8500_PRCMU_REGS_H */ |
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| 227 | |
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