1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * MFD core driver for Intel Broxton Whiskey Cove PMIC |
4 | * |
5 | * Copyright (C) 2015-2017, 2022 Intel Corporation. All rights reserved. |
6 | */ |
7 | |
8 | #include <linux/acpi.h> |
9 | #include <linux/bits.h> |
10 | #include <linux/delay.h> |
11 | #include <linux/err.h> |
12 | #include <linux/interrupt.h> |
13 | #include <linux/kernel.h> |
14 | #include <linux/mfd/core.h> |
15 | #include <linux/mfd/intel_soc_pmic.h> |
16 | #include <linux/mfd/intel_soc_pmic_bxtwc.h> |
17 | #include <linux/module.h> |
18 | |
19 | #include <asm/intel_scu_ipc.h> |
20 | |
21 | /* PMIC device registers */ |
22 | #define REG_ADDR_MASK GENMASK(15, 8) |
23 | #define REG_ADDR_SHIFT 8 |
24 | #define REG_OFFSET_MASK GENMASK(7, 0) |
25 | |
26 | /* Interrupt Status Registers */ |
27 | #define BXTWC_IRQLVL1 0x4E02 |
28 | |
29 | #define BXTWC_PWRBTNIRQ 0x4E03 |
30 | #define BXTWC_THRM0IRQ 0x4E04 |
31 | #define BXTWC_THRM1IRQ 0x4E05 |
32 | #define BXTWC_THRM2IRQ 0x4E06 |
33 | #define BXTWC_BCUIRQ 0x4E07 |
34 | #define BXTWC_ADCIRQ 0x4E08 |
35 | #define BXTWC_CHGR0IRQ 0x4E09 |
36 | #define BXTWC_CHGR1IRQ 0x4E0A |
37 | #define BXTWC_GPIOIRQ0 0x4E0B |
38 | #define BXTWC_GPIOIRQ1 0x4E0C |
39 | #define BXTWC_CRITIRQ 0x4E0D |
40 | #define BXTWC_TMUIRQ 0x4FB6 |
41 | |
42 | /* Interrupt MASK Registers */ |
43 | #define BXTWC_MIRQLVL1 0x4E0E |
44 | #define BXTWC_MIRQLVL1_MCHGR BIT(5) |
45 | |
46 | #define BXTWC_MPWRBTNIRQ 0x4E0F |
47 | #define BXTWC_MTHRM0IRQ 0x4E12 |
48 | #define BXTWC_MTHRM1IRQ 0x4E13 |
49 | #define BXTWC_MTHRM2IRQ 0x4E14 |
50 | #define BXTWC_MBCUIRQ 0x4E15 |
51 | #define BXTWC_MADCIRQ 0x4E16 |
52 | #define BXTWC_MCHGR0IRQ 0x4E17 |
53 | #define BXTWC_MCHGR1IRQ 0x4E18 |
54 | #define BXTWC_MGPIO0IRQ 0x4E19 |
55 | #define BXTWC_MGPIO1IRQ 0x4E1A |
56 | #define BXTWC_MCRITIRQ 0x4E1B |
57 | #define BXTWC_MTMUIRQ 0x4FB7 |
58 | |
59 | /* Whiskey Cove PMIC share same ACPI ID between different platforms */ |
60 | #define BROXTON_PMIC_WC_HRV 4 |
61 | |
62 | #define PMC_PMIC_ACCESS 0xFF |
63 | #define PMC_PMIC_READ 0x0 |
64 | #define PMC_PMIC_WRITE 0x1 |
65 | |
66 | enum bxtwc_irqs { |
67 | BXTWC_PWRBTN_LVL1_IRQ = 0, |
68 | BXTWC_TMU_LVL1_IRQ, |
69 | BXTWC_THRM_LVL1_IRQ, |
70 | BXTWC_BCU_LVL1_IRQ, |
71 | BXTWC_ADC_LVL1_IRQ, |
72 | BXTWC_CHGR_LVL1_IRQ, |
73 | BXTWC_GPIO_LVL1_IRQ, |
74 | BXTWC_CRIT_LVL1_IRQ, |
75 | }; |
76 | |
77 | enum bxtwc_irqs_pwrbtn { |
78 | BXTWC_PWRBTN_IRQ = 0, |
79 | BXTWC_UIBTN_IRQ, |
80 | }; |
81 | |
82 | enum bxtwc_irqs_bcu { |
83 | BXTWC_BCU_IRQ = 0, |
84 | }; |
85 | |
86 | enum bxtwc_irqs_adc { |
87 | BXTWC_ADC_IRQ = 0, |
88 | }; |
89 | |
90 | enum bxtwc_irqs_chgr { |
91 | BXTWC_USBC_IRQ = 0, |
92 | BXTWC_CHGR0_IRQ, |
93 | BXTWC_CHGR1_IRQ, |
94 | }; |
95 | |
96 | enum bxtwc_irqs_tmu { |
97 | BXTWC_TMU_IRQ = 0, |
98 | }; |
99 | |
100 | enum bxtwc_irqs_crit { |
101 | BXTWC_CRIT_IRQ = 0, |
102 | }; |
103 | |
104 | static const struct regmap_irq bxtwc_regmap_irqs[] = { |
105 | REGMAP_IRQ_REG(BXTWC_PWRBTN_LVL1_IRQ, 0, BIT(0)), |
106 | REGMAP_IRQ_REG(BXTWC_TMU_LVL1_IRQ, 0, BIT(1)), |
107 | REGMAP_IRQ_REG(BXTWC_THRM_LVL1_IRQ, 0, BIT(2)), |
108 | REGMAP_IRQ_REG(BXTWC_BCU_LVL1_IRQ, 0, BIT(3)), |
109 | REGMAP_IRQ_REG(BXTWC_ADC_LVL1_IRQ, 0, BIT(4)), |
110 | REGMAP_IRQ_REG(BXTWC_CHGR_LVL1_IRQ, 0, BIT(5)), |
111 | REGMAP_IRQ_REG(BXTWC_GPIO_LVL1_IRQ, 0, BIT(6)), |
112 | REGMAP_IRQ_REG(BXTWC_CRIT_LVL1_IRQ, 0, BIT(7)), |
113 | }; |
114 | |
115 | static const struct regmap_irq bxtwc_regmap_irqs_pwrbtn[] = { |
116 | REGMAP_IRQ_REG(BXTWC_PWRBTN_IRQ, 0, BIT(0)), |
117 | }; |
118 | |
119 | static const struct regmap_irq bxtwc_regmap_irqs_bcu[] = { |
120 | REGMAP_IRQ_REG(BXTWC_BCU_IRQ, 0, GENMASK(4, 0)), |
121 | }; |
122 | |
123 | static const struct regmap_irq bxtwc_regmap_irqs_adc[] = { |
124 | REGMAP_IRQ_REG(BXTWC_ADC_IRQ, 0, GENMASK(7, 0)), |
125 | }; |
126 | |
127 | static const struct regmap_irq bxtwc_regmap_irqs_chgr[] = { |
128 | REGMAP_IRQ_REG(BXTWC_USBC_IRQ, 0, BIT(5)), |
129 | REGMAP_IRQ_REG(BXTWC_CHGR0_IRQ, 0, GENMASK(4, 0)), |
130 | REGMAP_IRQ_REG(BXTWC_CHGR1_IRQ, 1, GENMASK(4, 0)), |
131 | }; |
132 | |
133 | static const struct regmap_irq bxtwc_regmap_irqs_tmu[] = { |
134 | REGMAP_IRQ_REG(BXTWC_TMU_IRQ, 0, GENMASK(2, 1)), |
135 | }; |
136 | |
137 | static const struct regmap_irq bxtwc_regmap_irqs_crit[] = { |
138 | REGMAP_IRQ_REG(BXTWC_CRIT_IRQ, 0, GENMASK(1, 0)), |
139 | }; |
140 | |
141 | static struct regmap_irq_chip bxtwc_regmap_irq_chip = { |
142 | .name = "bxtwc_irq_chip" , |
143 | .status_base = BXTWC_IRQLVL1, |
144 | .mask_base = BXTWC_MIRQLVL1, |
145 | .irqs = bxtwc_regmap_irqs, |
146 | .num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs), |
147 | .num_regs = 1, |
148 | }; |
149 | |
150 | static struct regmap_irq_chip bxtwc_regmap_irq_chip_pwrbtn = { |
151 | .name = "bxtwc_irq_chip_pwrbtn" , |
152 | .status_base = BXTWC_PWRBTNIRQ, |
153 | .mask_base = BXTWC_MPWRBTNIRQ, |
154 | .irqs = bxtwc_regmap_irqs_pwrbtn, |
155 | .num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_pwrbtn), |
156 | .num_regs = 1, |
157 | }; |
158 | |
159 | static struct regmap_irq_chip bxtwc_regmap_irq_chip_tmu = { |
160 | .name = "bxtwc_irq_chip_tmu" , |
161 | .status_base = BXTWC_TMUIRQ, |
162 | .mask_base = BXTWC_MTMUIRQ, |
163 | .irqs = bxtwc_regmap_irqs_tmu, |
164 | .num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_tmu), |
165 | .num_regs = 1, |
166 | }; |
167 | |
168 | static struct regmap_irq_chip bxtwc_regmap_irq_chip_bcu = { |
169 | .name = "bxtwc_irq_chip_bcu" , |
170 | .status_base = BXTWC_BCUIRQ, |
171 | .mask_base = BXTWC_MBCUIRQ, |
172 | .irqs = bxtwc_regmap_irqs_bcu, |
173 | .num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_bcu), |
174 | .num_regs = 1, |
175 | }; |
176 | |
177 | static struct regmap_irq_chip bxtwc_regmap_irq_chip_adc = { |
178 | .name = "bxtwc_irq_chip_adc" , |
179 | .status_base = BXTWC_ADCIRQ, |
180 | .mask_base = BXTWC_MADCIRQ, |
181 | .irqs = bxtwc_regmap_irqs_adc, |
182 | .num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_adc), |
183 | .num_regs = 1, |
184 | }; |
185 | |
186 | static struct regmap_irq_chip bxtwc_regmap_irq_chip_chgr = { |
187 | .name = "bxtwc_irq_chip_chgr" , |
188 | .status_base = BXTWC_CHGR0IRQ, |
189 | .mask_base = BXTWC_MCHGR0IRQ, |
190 | .irqs = bxtwc_regmap_irqs_chgr, |
191 | .num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_chgr), |
192 | .num_regs = 2, |
193 | }; |
194 | |
195 | static struct regmap_irq_chip bxtwc_regmap_irq_chip_crit = { |
196 | .name = "bxtwc_irq_chip_crit" , |
197 | .status_base = BXTWC_CRITIRQ, |
198 | .mask_base = BXTWC_MCRITIRQ, |
199 | .irqs = bxtwc_regmap_irqs_crit, |
200 | .num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_crit), |
201 | .num_regs = 1, |
202 | }; |
203 | |
204 | static const struct resource gpio_resources[] = { |
205 | DEFINE_RES_IRQ_NAMED(BXTWC_GPIO_LVL1_IRQ, "GPIO" ), |
206 | }; |
207 | |
208 | static const struct resource adc_resources[] = { |
209 | DEFINE_RES_IRQ_NAMED(BXTWC_ADC_IRQ, "ADC" ), |
210 | }; |
211 | |
212 | static const struct resource usbc_resources[] = { |
213 | DEFINE_RES_IRQ(BXTWC_USBC_IRQ), |
214 | }; |
215 | |
216 | static const struct resource charger_resources[] = { |
217 | DEFINE_RES_IRQ_NAMED(BXTWC_CHGR0_IRQ, "CHARGER" ), |
218 | DEFINE_RES_IRQ_NAMED(BXTWC_CHGR1_IRQ, "CHARGER1" ), |
219 | }; |
220 | |
221 | static const struct resource thermal_resources[] = { |
222 | DEFINE_RES_IRQ(BXTWC_THRM_LVL1_IRQ), |
223 | }; |
224 | |
225 | static const struct resource bcu_resources[] = { |
226 | DEFINE_RES_IRQ_NAMED(BXTWC_BCU_IRQ, "BCU" ), |
227 | }; |
228 | |
229 | static const struct resource tmu_resources[] = { |
230 | DEFINE_RES_IRQ_NAMED(BXTWC_TMU_IRQ, "TMU" ), |
231 | }; |
232 | |
233 | static struct mfd_cell bxt_wc_dev[] = { |
234 | { |
235 | .name = "bxt_wcove_gpadc" , |
236 | .num_resources = ARRAY_SIZE(adc_resources), |
237 | .resources = adc_resources, |
238 | }, |
239 | { |
240 | .name = "bxt_wcove_thermal" , |
241 | .num_resources = ARRAY_SIZE(thermal_resources), |
242 | .resources = thermal_resources, |
243 | }, |
244 | { |
245 | .name = "bxt_wcove_usbc" , |
246 | .num_resources = ARRAY_SIZE(usbc_resources), |
247 | .resources = usbc_resources, |
248 | }, |
249 | { |
250 | .name = "bxt_wcove_ext_charger" , |
251 | .num_resources = ARRAY_SIZE(charger_resources), |
252 | .resources = charger_resources, |
253 | }, |
254 | { |
255 | .name = "bxt_wcove_bcu" , |
256 | .num_resources = ARRAY_SIZE(bcu_resources), |
257 | .resources = bcu_resources, |
258 | }, |
259 | { |
260 | .name = "bxt_wcove_tmu" , |
261 | .num_resources = ARRAY_SIZE(tmu_resources), |
262 | .resources = tmu_resources, |
263 | }, |
264 | |
265 | { |
266 | .name = "bxt_wcove_gpio" , |
267 | .num_resources = ARRAY_SIZE(gpio_resources), |
268 | .resources = gpio_resources, |
269 | }, |
270 | { |
271 | .name = "bxt_wcove_region" , |
272 | }, |
273 | }; |
274 | |
275 | static int regmap_ipc_byte_reg_read(void *context, unsigned int reg, |
276 | unsigned int *val) |
277 | { |
278 | int ret; |
279 | int i2c_addr; |
280 | u8 ipc_in[2]; |
281 | u8 ipc_out[4]; |
282 | struct intel_soc_pmic *pmic = context; |
283 | |
284 | if (!pmic) |
285 | return -EINVAL; |
286 | |
287 | if (reg & REG_ADDR_MASK) |
288 | i2c_addr = (reg & REG_ADDR_MASK) >> REG_ADDR_SHIFT; |
289 | else |
290 | i2c_addr = BXTWC_DEVICE1_ADDR; |
291 | |
292 | reg &= REG_OFFSET_MASK; |
293 | |
294 | ipc_in[0] = reg; |
295 | ipc_in[1] = i2c_addr; |
296 | ret = intel_scu_ipc_dev_command(scu: pmic->scu, PMC_PMIC_ACCESS, |
297 | PMC_PMIC_READ, in: ipc_in, inlen: sizeof(ipc_in), |
298 | out: ipc_out, outlen: sizeof(ipc_out)); |
299 | if (ret) |
300 | return ret; |
301 | |
302 | *val = ipc_out[0]; |
303 | |
304 | return 0; |
305 | } |
306 | |
307 | static int regmap_ipc_byte_reg_write(void *context, unsigned int reg, |
308 | unsigned int val) |
309 | { |
310 | int i2c_addr; |
311 | u8 ipc_in[3]; |
312 | struct intel_soc_pmic *pmic = context; |
313 | |
314 | if (!pmic) |
315 | return -EINVAL; |
316 | |
317 | if (reg & REG_ADDR_MASK) |
318 | i2c_addr = (reg & REG_ADDR_MASK) >> REG_ADDR_SHIFT; |
319 | else |
320 | i2c_addr = BXTWC_DEVICE1_ADDR; |
321 | |
322 | reg &= REG_OFFSET_MASK; |
323 | |
324 | ipc_in[0] = reg; |
325 | ipc_in[1] = i2c_addr; |
326 | ipc_in[2] = val; |
327 | return intel_scu_ipc_dev_command(scu: pmic->scu, PMC_PMIC_ACCESS, |
328 | PMC_PMIC_WRITE, in: ipc_in, inlen: sizeof(ipc_in), |
329 | NULL, outlen: 0); |
330 | } |
331 | |
332 | /* sysfs interfaces to r/w PMIC registers, required by initial script */ |
333 | static unsigned long bxtwc_reg_addr; |
334 | static ssize_t addr_show(struct device *dev, |
335 | struct device_attribute *attr, char *buf) |
336 | { |
337 | return sysfs_emit(buf, fmt: "0x%lx\n" , bxtwc_reg_addr); |
338 | } |
339 | |
340 | static ssize_t addr_store(struct device *dev, |
341 | struct device_attribute *attr, const char *buf, size_t count) |
342 | { |
343 | int ret; |
344 | |
345 | ret = kstrtoul(s: buf, base: 0, res: &bxtwc_reg_addr); |
346 | if (ret) |
347 | return ret; |
348 | |
349 | return count; |
350 | } |
351 | |
352 | static ssize_t val_show(struct device *dev, |
353 | struct device_attribute *attr, char *buf) |
354 | { |
355 | int ret; |
356 | unsigned int val; |
357 | struct intel_soc_pmic *pmic = dev_get_drvdata(dev); |
358 | |
359 | ret = regmap_read(map: pmic->regmap, reg: bxtwc_reg_addr, val: &val); |
360 | if (ret) { |
361 | dev_err(dev, "Failed to read 0x%lx\n" , bxtwc_reg_addr); |
362 | return ret; |
363 | } |
364 | |
365 | return sysfs_emit(buf, fmt: "0x%02x\n" , val); |
366 | } |
367 | |
368 | static ssize_t val_store(struct device *dev, |
369 | struct device_attribute *attr, const char *buf, size_t count) |
370 | { |
371 | int ret; |
372 | unsigned int val; |
373 | struct intel_soc_pmic *pmic = dev_get_drvdata(dev); |
374 | |
375 | ret = kstrtouint(s: buf, base: 0, res: &val); |
376 | if (ret) |
377 | return ret; |
378 | |
379 | ret = regmap_write(map: pmic->regmap, reg: bxtwc_reg_addr, val); |
380 | if (ret) { |
381 | dev_err(dev, "Failed to write value 0x%02x to address 0x%lx" , |
382 | val, bxtwc_reg_addr); |
383 | return ret; |
384 | } |
385 | return count; |
386 | } |
387 | |
388 | static DEVICE_ATTR_ADMIN_RW(addr); |
389 | static DEVICE_ATTR_ADMIN_RW(val); |
390 | static struct attribute *bxtwc_attrs[] = { |
391 | &dev_attr_addr.attr, |
392 | &dev_attr_val.attr, |
393 | NULL |
394 | }; |
395 | |
396 | static const struct attribute_group bxtwc_group = { |
397 | .attrs = bxtwc_attrs, |
398 | }; |
399 | |
400 | static const struct attribute_group *bxtwc_groups[] = { |
401 | &bxtwc_group, |
402 | NULL |
403 | }; |
404 | |
405 | static const struct regmap_config bxtwc_regmap_config = { |
406 | .reg_bits = 16, |
407 | .val_bits = 8, |
408 | .reg_write = regmap_ipc_byte_reg_write, |
409 | .reg_read = regmap_ipc_byte_reg_read, |
410 | }; |
411 | |
412 | static int bxtwc_add_chained_irq_chip(struct intel_soc_pmic *pmic, |
413 | struct regmap_irq_chip_data *pdata, |
414 | int pirq, int irq_flags, |
415 | const struct regmap_irq_chip *chip, |
416 | struct regmap_irq_chip_data **data) |
417 | { |
418 | int irq; |
419 | |
420 | irq = regmap_irq_get_virq(data: pdata, irq: pirq); |
421 | if (irq < 0) |
422 | return dev_err_probe(dev: pmic->dev, err: irq, fmt: "Failed to get parent vIRQ(%d) for chip %s\n" , |
423 | pirq, chip->name); |
424 | |
425 | return devm_regmap_add_irq_chip(dev: pmic->dev, map: pmic->regmap, irq, irq_flags, |
426 | irq_base: 0, chip, data); |
427 | } |
428 | |
429 | static int bxtwc_probe(struct platform_device *pdev) |
430 | { |
431 | struct device *dev = &pdev->dev; |
432 | int ret; |
433 | acpi_status status; |
434 | unsigned long long hrv; |
435 | struct intel_soc_pmic *pmic; |
436 | |
437 | status = acpi_evaluate_integer(ACPI_HANDLE(dev), pathname: "_HRV" , NULL, data: &hrv); |
438 | if (ACPI_FAILURE(status)) |
439 | return dev_err_probe(dev, err: -ENODEV, fmt: "Failed to get PMIC hardware revision\n" ); |
440 | if (hrv != BROXTON_PMIC_WC_HRV) |
441 | return dev_err_probe(dev, err: -ENODEV, fmt: "Invalid PMIC hardware revision: %llu\n" , hrv); |
442 | |
443 | pmic = devm_kzalloc(dev, size: sizeof(*pmic), GFP_KERNEL); |
444 | if (!pmic) |
445 | return -ENOMEM; |
446 | |
447 | ret = platform_get_irq(pdev, 0); |
448 | if (ret < 0) |
449 | return ret; |
450 | pmic->irq = ret; |
451 | |
452 | platform_set_drvdata(pdev, data: pmic); |
453 | pmic->dev = dev; |
454 | |
455 | pmic->scu = devm_intel_scu_ipc_dev_get(dev); |
456 | if (!pmic->scu) |
457 | return -EPROBE_DEFER; |
458 | |
459 | pmic->regmap = devm_regmap_init(dev, NULL, pmic, &bxtwc_regmap_config); |
460 | if (IS_ERR(ptr: pmic->regmap)) |
461 | return dev_err_probe(dev, err: PTR_ERR(ptr: pmic->regmap), fmt: "Failed to initialise regmap\n" ); |
462 | |
463 | ret = devm_regmap_add_irq_chip(dev, map: pmic->regmap, irq: pmic->irq, |
464 | IRQF_ONESHOT | IRQF_SHARED, |
465 | irq_base: 0, chip: &bxtwc_regmap_irq_chip, |
466 | data: &pmic->irq_chip_data); |
467 | if (ret) |
468 | return dev_err_probe(dev, err: ret, fmt: "Failed to add IRQ chip\n" ); |
469 | |
470 | ret = bxtwc_add_chained_irq_chip(pmic, pdata: pmic->irq_chip_data, |
471 | pirq: BXTWC_PWRBTN_LVL1_IRQ, |
472 | IRQF_ONESHOT, |
473 | chip: &bxtwc_regmap_irq_chip_pwrbtn, |
474 | data: &pmic->irq_chip_data_pwrbtn); |
475 | if (ret) |
476 | return dev_err_probe(dev, err: ret, fmt: "Failed to add PWRBTN IRQ chip\n" ); |
477 | |
478 | ret = bxtwc_add_chained_irq_chip(pmic, pdata: pmic->irq_chip_data, |
479 | pirq: BXTWC_TMU_LVL1_IRQ, |
480 | IRQF_ONESHOT, |
481 | chip: &bxtwc_regmap_irq_chip_tmu, |
482 | data: &pmic->irq_chip_data_tmu); |
483 | if (ret) |
484 | return dev_err_probe(dev, err: ret, fmt: "Failed to add TMU IRQ chip\n" ); |
485 | |
486 | /* Add chained IRQ handler for BCU IRQs */ |
487 | ret = bxtwc_add_chained_irq_chip(pmic, pdata: pmic->irq_chip_data, |
488 | pirq: BXTWC_BCU_LVL1_IRQ, |
489 | IRQF_ONESHOT, |
490 | chip: &bxtwc_regmap_irq_chip_bcu, |
491 | data: &pmic->irq_chip_data_bcu); |
492 | if (ret) |
493 | return dev_err_probe(dev, err: ret, fmt: "Failed to add BUC IRQ chip\n" ); |
494 | |
495 | /* Add chained IRQ handler for ADC IRQs */ |
496 | ret = bxtwc_add_chained_irq_chip(pmic, pdata: pmic->irq_chip_data, |
497 | pirq: BXTWC_ADC_LVL1_IRQ, |
498 | IRQF_ONESHOT, |
499 | chip: &bxtwc_regmap_irq_chip_adc, |
500 | data: &pmic->irq_chip_data_adc); |
501 | if (ret) |
502 | return dev_err_probe(dev, err: ret, fmt: "Failed to add ADC IRQ chip\n" ); |
503 | |
504 | /* Add chained IRQ handler for CHGR IRQs */ |
505 | ret = bxtwc_add_chained_irq_chip(pmic, pdata: pmic->irq_chip_data, |
506 | pirq: BXTWC_CHGR_LVL1_IRQ, |
507 | IRQF_ONESHOT, |
508 | chip: &bxtwc_regmap_irq_chip_chgr, |
509 | data: &pmic->irq_chip_data_chgr); |
510 | if (ret) |
511 | return dev_err_probe(dev, err: ret, fmt: "Failed to add CHGR IRQ chip\n" ); |
512 | |
513 | /* Add chained IRQ handler for CRIT IRQs */ |
514 | ret = bxtwc_add_chained_irq_chip(pmic, pdata: pmic->irq_chip_data, |
515 | pirq: BXTWC_CRIT_LVL1_IRQ, |
516 | IRQF_ONESHOT, |
517 | chip: &bxtwc_regmap_irq_chip_crit, |
518 | data: &pmic->irq_chip_data_crit); |
519 | if (ret) |
520 | return dev_err_probe(dev, err: ret, fmt: "Failed to add CRIT IRQ chip\n" ); |
521 | |
522 | ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE, cells: bxt_wc_dev, ARRAY_SIZE(bxt_wc_dev), |
523 | NULL, irq_base: 0, NULL); |
524 | if (ret) |
525 | return dev_err_probe(dev, err: ret, fmt: "Failed to add devices\n" ); |
526 | |
527 | /* |
528 | * There is a known H/W bug. Upon reset, BIT 5 of register |
529 | * BXTWC_CHGR_LVL1_IRQ is 0 which is the expected value. However, |
530 | * later it's set to 1(masked) automatically by hardware. So we |
531 | * place the software workaround here to unmask it again in order |
532 | * to re-enable the charger interrupt. |
533 | */ |
534 | regmap_update_bits(map: pmic->regmap, BXTWC_MIRQLVL1, BXTWC_MIRQLVL1_MCHGR, val: 0); |
535 | |
536 | return 0; |
537 | } |
538 | |
539 | static void bxtwc_shutdown(struct platform_device *pdev) |
540 | { |
541 | struct intel_soc_pmic *pmic = platform_get_drvdata(pdev); |
542 | |
543 | disable_irq(irq: pmic->irq); |
544 | } |
545 | |
546 | static int bxtwc_suspend(struct device *dev) |
547 | { |
548 | struct intel_soc_pmic *pmic = dev_get_drvdata(dev); |
549 | |
550 | disable_irq(irq: pmic->irq); |
551 | |
552 | return 0; |
553 | } |
554 | |
555 | static int bxtwc_resume(struct device *dev) |
556 | { |
557 | struct intel_soc_pmic *pmic = dev_get_drvdata(dev); |
558 | |
559 | enable_irq(irq: pmic->irq); |
560 | return 0; |
561 | } |
562 | |
563 | static DEFINE_SIMPLE_DEV_PM_OPS(bxtwc_pm_ops, bxtwc_suspend, bxtwc_resume); |
564 | |
565 | static const struct acpi_device_id bxtwc_acpi_ids[] = { |
566 | { "INT34D3" , }, |
567 | { } |
568 | }; |
569 | MODULE_DEVICE_TABLE(acpi, bxtwc_acpi_ids); |
570 | |
571 | static struct platform_driver bxtwc_driver = { |
572 | .probe = bxtwc_probe, |
573 | .shutdown = bxtwc_shutdown, |
574 | .driver = { |
575 | .name = "BXTWC PMIC" , |
576 | .pm = pm_sleep_ptr(&bxtwc_pm_ops), |
577 | .acpi_match_table = bxtwc_acpi_ids, |
578 | .dev_groups = bxtwc_groups, |
579 | }, |
580 | }; |
581 | |
582 | module_platform_driver(bxtwc_driver); |
583 | |
584 | MODULE_LICENSE("GPL v2" ); |
585 | MODULE_AUTHOR("Qipeng Zha <qipeng.zha@intel.com>" ); |
586 | |