1/*
2 * tps65910.c -- TI TPS6591x chip family multi-function driver
3 *
4 * Copyright 2010 Texas Instruments Inc.
5 *
6 * Author: Graeme Gregory <gg@slimlogic.co.uk>
7 * Author: Jorge Eduardo Candelaria <jedu@slimlogic.co.uk>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 */
15
16#include <linux/init.h>
17#include <linux/err.h>
18#include <linux/slab.h>
19#include <linux/i2c.h>
20#include <linux/interrupt.h>
21#include <linux/irq.h>
22#include <linux/irqdomain.h>
23#include <linux/mfd/core.h>
24#include <linux/regmap.h>
25#include <linux/mfd/tps65910.h>
26#include <linux/of.h>
27#include <linux/of_device.h>
28
29static struct resource rtc_resources[] = {
30 {
31 .start = TPS65910_IRQ_RTC_ALARM,
32 .end = TPS65910_IRQ_RTC_ALARM,
33 .flags = IORESOURCE_IRQ,
34 }
35};
36
37static const struct mfd_cell tps65910s[] = {
38 {
39 .name = "tps65910-gpio",
40 },
41 {
42 .name = "tps65910-pmic",
43 },
44 {
45 .name = "tps65910-rtc",
46 .num_resources = ARRAY_SIZE(rtc_resources),
47 .resources = &rtc_resources[0],
48 },
49 {
50 .name = "tps65910-power",
51 },
52};
53
54
55static const struct regmap_irq tps65911_irqs[] = {
56 /* INT_STS */
57 [TPS65911_IRQ_PWRHOLD_F] = {
58 .mask = INT_MSK_PWRHOLD_F_IT_MSK_MASK,
59 .reg_offset = 0,
60 },
61 [TPS65911_IRQ_VBAT_VMHI] = {
62 .mask = INT_MSK_VMBHI_IT_MSK_MASK,
63 .reg_offset = 0,
64 },
65 [TPS65911_IRQ_PWRON] = {
66 .mask = INT_MSK_PWRON_IT_MSK_MASK,
67 .reg_offset = 0,
68 },
69 [TPS65911_IRQ_PWRON_LP] = {
70 .mask = INT_MSK_PWRON_LP_IT_MSK_MASK,
71 .reg_offset = 0,
72 },
73 [TPS65911_IRQ_PWRHOLD_R] = {
74 .mask = INT_MSK_PWRHOLD_R_IT_MSK_MASK,
75 .reg_offset = 0,
76 },
77 [TPS65911_IRQ_HOTDIE] = {
78 .mask = INT_MSK_HOTDIE_IT_MSK_MASK,
79 .reg_offset = 0,
80 },
81 [TPS65911_IRQ_RTC_ALARM] = {
82 .mask = INT_MSK_RTC_ALARM_IT_MSK_MASK,
83 .reg_offset = 0,
84 },
85 [TPS65911_IRQ_RTC_PERIOD] = {
86 .mask = INT_MSK_RTC_PERIOD_IT_MSK_MASK,
87 .reg_offset = 0,
88 },
89
90 /* INT_STS2 */
91 [TPS65911_IRQ_GPIO0_R] = {
92 .mask = INT_MSK2_GPIO0_R_IT_MSK_MASK,
93 .reg_offset = 1,
94 },
95 [TPS65911_IRQ_GPIO0_F] = {
96 .mask = INT_MSK2_GPIO0_F_IT_MSK_MASK,
97 .reg_offset = 1,
98 },
99 [TPS65911_IRQ_GPIO1_R] = {
100 .mask = INT_MSK2_GPIO1_R_IT_MSK_MASK,
101 .reg_offset = 1,
102 },
103 [TPS65911_IRQ_GPIO1_F] = {
104 .mask = INT_MSK2_GPIO1_F_IT_MSK_MASK,
105 .reg_offset = 1,
106 },
107 [TPS65911_IRQ_GPIO2_R] = {
108 .mask = INT_MSK2_GPIO2_R_IT_MSK_MASK,
109 .reg_offset = 1,
110 },
111 [TPS65911_IRQ_GPIO2_F] = {
112 .mask = INT_MSK2_GPIO2_F_IT_MSK_MASK,
113 .reg_offset = 1,
114 },
115 [TPS65911_IRQ_GPIO3_R] = {
116 .mask = INT_MSK2_GPIO3_R_IT_MSK_MASK,
117 .reg_offset = 1,
118 },
119 [TPS65911_IRQ_GPIO3_F] = {
120 .mask = INT_MSK2_GPIO3_F_IT_MSK_MASK,
121 .reg_offset = 1,
122 },
123
124 /* INT_STS2 */
125 [TPS65911_IRQ_GPIO4_R] = {
126 .mask = INT_MSK3_GPIO4_R_IT_MSK_MASK,
127 .reg_offset = 2,
128 },
129 [TPS65911_IRQ_GPIO4_F] = {
130 .mask = INT_MSK3_GPIO4_F_IT_MSK_MASK,
131 .reg_offset = 2,
132 },
133 [TPS65911_IRQ_GPIO5_R] = {
134 .mask = INT_MSK3_GPIO5_R_IT_MSK_MASK,
135 .reg_offset = 2,
136 },
137 [TPS65911_IRQ_GPIO5_F] = {
138 .mask = INT_MSK3_GPIO5_F_IT_MSK_MASK,
139 .reg_offset = 2,
140 },
141 [TPS65911_IRQ_WTCHDG] = {
142 .mask = INT_MSK3_WTCHDG_IT_MSK_MASK,
143 .reg_offset = 2,
144 },
145 [TPS65911_IRQ_VMBCH2_H] = {
146 .mask = INT_MSK3_VMBCH2_H_IT_MSK_MASK,
147 .reg_offset = 2,
148 },
149 [TPS65911_IRQ_VMBCH2_L] = {
150 .mask = INT_MSK3_VMBCH2_L_IT_MSK_MASK,
151 .reg_offset = 2,
152 },
153 [TPS65911_IRQ_PWRDN] = {
154 .mask = INT_MSK3_PWRDN_IT_MSK_MASK,
155 .reg_offset = 2,
156 },
157};
158
159static const struct regmap_irq tps65910_irqs[] = {
160 /* INT_STS */
161 [TPS65910_IRQ_VBAT_VMBDCH] = {
162 .mask = TPS65910_INT_MSK_VMBDCH_IT_MSK_MASK,
163 .reg_offset = 0,
164 },
165 [TPS65910_IRQ_VBAT_VMHI] = {
166 .mask = TPS65910_INT_MSK_VMBHI_IT_MSK_MASK,
167 .reg_offset = 0,
168 },
169 [TPS65910_IRQ_PWRON] = {
170 .mask = TPS65910_INT_MSK_PWRON_IT_MSK_MASK,
171 .reg_offset = 0,
172 },
173 [TPS65910_IRQ_PWRON_LP] = {
174 .mask = TPS65910_INT_MSK_PWRON_LP_IT_MSK_MASK,
175 .reg_offset = 0,
176 },
177 [TPS65910_IRQ_PWRHOLD] = {
178 .mask = TPS65910_INT_MSK_PWRHOLD_IT_MSK_MASK,
179 .reg_offset = 0,
180 },
181 [TPS65910_IRQ_HOTDIE] = {
182 .mask = TPS65910_INT_MSK_HOTDIE_IT_MSK_MASK,
183 .reg_offset = 0,
184 },
185 [TPS65910_IRQ_RTC_ALARM] = {
186 .mask = TPS65910_INT_MSK_RTC_ALARM_IT_MSK_MASK,
187 .reg_offset = 0,
188 },
189 [TPS65910_IRQ_RTC_PERIOD] = {
190 .mask = TPS65910_INT_MSK_RTC_PERIOD_IT_MSK_MASK,
191 .reg_offset = 0,
192 },
193
194 /* INT_STS2 */
195 [TPS65910_IRQ_GPIO_R] = {
196 .mask = TPS65910_INT_MSK2_GPIO0_F_IT_MSK_MASK,
197 .reg_offset = 1,
198 },
199 [TPS65910_IRQ_GPIO_F] = {
200 .mask = TPS65910_INT_MSK2_GPIO0_R_IT_MSK_MASK,
201 .reg_offset = 1,
202 },
203};
204
205static struct regmap_irq_chip tps65911_irq_chip = {
206 .name = "tps65910",
207 .irqs = tps65911_irqs,
208 .num_irqs = ARRAY_SIZE(tps65911_irqs),
209 .num_regs = 3,
210 .irq_reg_stride = 2,
211 .status_base = TPS65910_INT_STS,
212 .mask_base = TPS65910_INT_MSK,
213 .ack_base = TPS65910_INT_STS,
214};
215
216static struct regmap_irq_chip tps65910_irq_chip = {
217 .name = "tps65910",
218 .irqs = tps65910_irqs,
219 .num_irqs = ARRAY_SIZE(tps65910_irqs),
220 .num_regs = 2,
221 .irq_reg_stride = 2,
222 .status_base = TPS65910_INT_STS,
223 .mask_base = TPS65910_INT_MSK,
224 .ack_base = TPS65910_INT_STS,
225};
226
227static int tps65910_irq_init(struct tps65910 *tps65910, int irq,
228 struct tps65910_platform_data *pdata)
229{
230 int ret;
231 static struct regmap_irq_chip *tps6591x_irqs_chip;
232
233 if (!irq) {
234 dev_warn(tps65910->dev, "No interrupt support, no core IRQ\n");
235 return -EINVAL;
236 }
237
238 if (!pdata) {
239 dev_warn(tps65910->dev, "No interrupt support, no pdata\n");
240 return -EINVAL;
241 }
242
243 switch (tps65910_chip_id(tps65910)) {
244 case TPS65910:
245 tps6591x_irqs_chip = &tps65910_irq_chip;
246 break;
247 case TPS65911:
248 tps6591x_irqs_chip = &tps65911_irq_chip;
249 break;
250 }
251
252 tps65910->chip_irq = irq;
253 ret = devm_regmap_add_irq_chip(tps65910->dev, tps65910->regmap,
254 tps65910->chip_irq,
255 IRQF_ONESHOT, pdata->irq_base,
256 tps6591x_irqs_chip, &tps65910->irq_data);
257 if (ret < 0) {
258 dev_warn(tps65910->dev, "Failed to add irq_chip %d\n", ret);
259 tps65910->chip_irq = 0;
260 }
261 return ret;
262}
263
264static bool is_volatile_reg(struct device *dev, unsigned int reg)
265{
266 struct tps65910 *tps65910 = dev_get_drvdata(dev);
267
268 /*
269 * Caching all regulator registers.
270 * All regualator register address range is same for
271 * TPS65910 and TPS65911
272 */
273 if ((reg >= TPS65910_VIO) && (reg <= TPS65910_VDAC)) {
274 /* Check for non-existing register */
275 if (tps65910_chip_id(tps65910) == TPS65910)
276 if ((reg == TPS65911_VDDCTRL_OP) ||
277 (reg == TPS65911_VDDCTRL_SR))
278 return true;
279 return false;
280 }
281 return true;
282}
283
284static const struct regmap_config tps65910_regmap_config = {
285 .reg_bits = 8,
286 .val_bits = 8,
287 .volatile_reg = is_volatile_reg,
288 .max_register = TPS65910_MAX_REGISTER - 1,
289 .cache_type = REGCACHE_RBTREE,
290};
291
292static int tps65910_ck32k_init(struct tps65910 *tps65910,
293 struct tps65910_board *pmic_pdata)
294{
295 int ret;
296
297 if (!pmic_pdata->en_ck32k_xtal)
298 return 0;
299
300 ret = tps65910_reg_clear_bits(tps65910, TPS65910_DEVCTRL,
301 DEVCTRL_CK32K_CTRL_MASK);
302 if (ret < 0) {
303 dev_err(tps65910->dev, "clear ck32k_ctrl failed: %d\n", ret);
304 return ret;
305 }
306
307 return 0;
308}
309
310static int tps65910_sleepinit(struct tps65910 *tps65910,
311 struct tps65910_board *pmic_pdata)
312{
313 struct device *dev;
314 int ret;
315
316 if (!pmic_pdata->en_dev_slp)
317 return 0;
318
319 dev = tps65910->dev;
320
321 /* enabling SLEEP device state */
322 ret = tps65910_reg_set_bits(tps65910, TPS65910_DEVCTRL,
323 DEVCTRL_DEV_SLP_MASK);
324 if (ret < 0) {
325 dev_err(dev, "set dev_slp failed: %d\n", ret);
326 goto err_sleep_init;
327 }
328
329 if (pmic_pdata->slp_keepon.therm_keepon) {
330 ret = tps65910_reg_set_bits(tps65910,
331 TPS65910_SLEEP_KEEP_RES_ON,
332 SLEEP_KEEP_RES_ON_THERM_KEEPON_MASK);
333 if (ret < 0) {
334 dev_err(dev, "set therm_keepon failed: %d\n", ret);
335 goto disable_dev_slp;
336 }
337 }
338
339 if (pmic_pdata->slp_keepon.clkout32k_keepon) {
340 ret = tps65910_reg_set_bits(tps65910,
341 TPS65910_SLEEP_KEEP_RES_ON,
342 SLEEP_KEEP_RES_ON_CLKOUT32K_KEEPON_MASK);
343 if (ret < 0) {
344 dev_err(dev, "set clkout32k_keepon failed: %d\n", ret);
345 goto disable_dev_slp;
346 }
347 }
348
349 if (pmic_pdata->slp_keepon.i2chs_keepon) {
350 ret = tps65910_reg_set_bits(tps65910,
351 TPS65910_SLEEP_KEEP_RES_ON,
352 SLEEP_KEEP_RES_ON_I2CHS_KEEPON_MASK);
353 if (ret < 0) {
354 dev_err(dev, "set i2chs_keepon failed: %d\n", ret);
355 goto disable_dev_slp;
356 }
357 }
358
359 return 0;
360
361disable_dev_slp:
362 tps65910_reg_clear_bits(tps65910, TPS65910_DEVCTRL,
363 DEVCTRL_DEV_SLP_MASK);
364
365err_sleep_init:
366 return ret;
367}
368
369#ifdef CONFIG_OF
370static const struct of_device_id tps65910_of_match[] = {
371 { .compatible = "ti,tps65910", .data = (void *)TPS65910},
372 { .compatible = "ti,tps65911", .data = (void *)TPS65911},
373 { },
374};
375
376static struct tps65910_board *tps65910_parse_dt(struct i2c_client *client,
377 unsigned long *chip_id)
378{
379 struct device_node *np = client->dev.of_node;
380 struct tps65910_board *board_info;
381 unsigned int prop;
382 const struct of_device_id *match;
383 int ret;
384
385 match = of_match_device(tps65910_of_match, &client->dev);
386 if (!match) {
387 dev_err(&client->dev, "Failed to find matching dt id\n");
388 return NULL;
389 }
390
391 *chip_id = (unsigned long)match->data;
392
393 board_info = devm_kzalloc(&client->dev, sizeof(*board_info),
394 GFP_KERNEL);
395 if (!board_info)
396 return NULL;
397
398 ret = of_property_read_u32(np, "ti,vmbch-threshold", &prop);
399 if (!ret)
400 board_info->vmbch_threshold = prop;
401
402 ret = of_property_read_u32(np, "ti,vmbch2-threshold", &prop);
403 if (!ret)
404 board_info->vmbch2_threshold = prop;
405
406 prop = of_property_read_bool(np, "ti,en-ck32k-xtal");
407 board_info->en_ck32k_xtal = prop;
408
409 prop = of_property_read_bool(np, "ti,sleep-enable");
410 board_info->en_dev_slp = prop;
411
412 prop = of_property_read_bool(np, "ti,sleep-keep-therm");
413 board_info->slp_keepon.therm_keepon = prop;
414
415 prop = of_property_read_bool(np, "ti,sleep-keep-ck32k");
416 board_info->slp_keepon.clkout32k_keepon = prop;
417
418 prop = of_property_read_bool(np, "ti,sleep-keep-hsclk");
419 board_info->slp_keepon.i2chs_keepon = prop;
420
421 board_info->irq = client->irq;
422 board_info->irq_base = -1;
423 board_info->pm_off = of_property_read_bool(np,
424 "ti,system-power-controller");
425
426 return board_info;
427}
428#else
429static inline
430struct tps65910_board *tps65910_parse_dt(struct i2c_client *client,
431 unsigned long *chip_id)
432{
433 return NULL;
434}
435#endif
436
437static struct i2c_client *tps65910_i2c_client;
438static void tps65910_power_off(void)
439{
440 struct tps65910 *tps65910;
441
442 tps65910 = dev_get_drvdata(&tps65910_i2c_client->dev);
443
444 if (tps65910_reg_set_bits(tps65910, TPS65910_DEVCTRL,
445 DEVCTRL_PWR_OFF_MASK) < 0)
446 return;
447
448 tps65910_reg_clear_bits(tps65910, TPS65910_DEVCTRL,
449 DEVCTRL_DEV_ON_MASK);
450}
451
452static int tps65910_i2c_probe(struct i2c_client *i2c,
453 const struct i2c_device_id *id)
454{
455 struct tps65910 *tps65910;
456 struct tps65910_board *pmic_plat_data;
457 struct tps65910_board *of_pmic_plat_data = NULL;
458 struct tps65910_platform_data *init_data;
459 unsigned long chip_id = id->driver_data;
460 int ret;
461
462 pmic_plat_data = dev_get_platdata(&i2c->dev);
463
464 if (!pmic_plat_data && i2c->dev.of_node) {
465 pmic_plat_data = tps65910_parse_dt(i2c, &chip_id);
466 of_pmic_plat_data = pmic_plat_data;
467 }
468
469 if (!pmic_plat_data)
470 return -EINVAL;
471
472 init_data = devm_kzalloc(&i2c->dev, sizeof(*init_data), GFP_KERNEL);
473 if (init_data == NULL)
474 return -ENOMEM;
475
476 tps65910 = devm_kzalloc(&i2c->dev, sizeof(*tps65910), GFP_KERNEL);
477 if (tps65910 == NULL)
478 return -ENOMEM;
479
480 tps65910->of_plat_data = of_pmic_plat_data;
481 i2c_set_clientdata(i2c, tps65910);
482 tps65910->dev = &i2c->dev;
483 tps65910->i2c_client = i2c;
484 tps65910->id = chip_id;
485
486 /* Work around silicon erratum SWCZ010: the tps65910 may miss the
487 * first I2C transfer. So issue a dummy transfer before the first
488 * real transfer.
489 */
490 i2c_master_send(i2c, "", 1);
491 tps65910->regmap = devm_regmap_init_i2c(i2c, &tps65910_regmap_config);
492 if (IS_ERR(tps65910->regmap)) {
493 ret = PTR_ERR(tps65910->regmap);
494 dev_err(&i2c->dev, "regmap initialization failed: %d\n", ret);
495 return ret;
496 }
497
498 init_data->irq = pmic_plat_data->irq;
499 init_data->irq_base = pmic_plat_data->irq_base;
500
501 tps65910_irq_init(tps65910, init_data->irq, init_data);
502 tps65910_ck32k_init(tps65910, pmic_plat_data);
503 tps65910_sleepinit(tps65910, pmic_plat_data);
504
505 if (pmic_plat_data->pm_off && !pm_power_off) {
506 tps65910_i2c_client = i2c;
507 pm_power_off = tps65910_power_off;
508 }
509
510 ret = devm_mfd_add_devices(tps65910->dev, -1,
511 tps65910s, ARRAY_SIZE(tps65910s),
512 NULL, 0,
513 regmap_irq_get_domain(tps65910->irq_data));
514 if (ret < 0) {
515 dev_err(&i2c->dev, "mfd_add_devices failed: %d\n", ret);
516 return ret;
517 }
518
519 return ret;
520}
521
522static const struct i2c_device_id tps65910_i2c_id[] = {
523 { "tps65910", TPS65910 },
524 { "tps65911", TPS65911 },
525 { }
526};
527
528static struct i2c_driver tps65910_i2c_driver = {
529 .driver = {
530 .name = "tps65910",
531 .of_match_table = of_match_ptr(tps65910_of_match),
532 },
533 .probe = tps65910_i2c_probe,
534 .id_table = tps65910_i2c_id,
535};
536
537static int __init tps65910_i2c_init(void)
538{
539 return i2c_add_driver(&tps65910_i2c_driver);
540}
541/* init early so consumer devices can complete system boot */
542subsys_initcall(tps65910_i2c_init);
543