| 1 | #ifndef __RTS5260_H__ |
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| 2 | #define __RTS5260_H__ |
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| 3 | |
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| 4 | #define RTS5260_DVCC_CTRL 0xFF73 |
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| 5 | #define RTS5260_DVCC_OCP_EN (0x01 << 7) |
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| 6 | #define RTS5260_DVCC_OCP_THD_MASK (0x07 << 4) |
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| 7 | #define RTS5260_DVCC_POWERON (0x01 << 3) |
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| 8 | #define RTS5260_DVCC_OCP_CL_EN (0x01 << 2) |
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| 9 | |
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| 10 | #define RTS5260_DVIO_CTRL 0xFF75 |
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| 11 | #define RTS5260_DVIO_OCP_EN (0x01 << 7) |
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| 12 | #define RTS5260_DVIO_OCP_THD_MASK (0x07 << 4) |
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| 13 | #define RTS5260_DVIO_POWERON (0x01 << 3) |
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| 14 | #define RTS5260_DVIO_OCP_CL_EN (0x01 << 2) |
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| 15 | |
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| 16 | #define RTS5260_DV331812_CFG 0xFF71 |
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| 17 | #define RTS5260_DV331812_OCP_EN (0x01 << 7) |
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| 18 | #define RTS5260_DV331812_OCP_THD_MASK (0x07 << 4) |
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| 19 | #define RTS5260_DV331812_POWERON (0x01 << 3) |
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| 20 | #define RTS5260_DV331812_SEL (0x01 << 2) |
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| 21 | #define RTS5260_DV331812_VDD1 (0x01 << 2) |
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| 22 | #define RTS5260_DV331812_VDD2 (0x00 << 2) |
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| 23 | |
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| 24 | #define RTS5260_DV331812_OCP_THD_120 (0x00 << 4) |
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| 25 | #define RTS5260_DV331812_OCP_THD_140 (0x01 << 4) |
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| 26 | #define RTS5260_DV331812_OCP_THD_160 (0x02 << 4) |
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| 27 | #define RTS5260_DV331812_OCP_THD_180 (0x03 << 4) |
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| 28 | #define RTS5260_DV331812_OCP_THD_210 (0x04 << 4) |
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| 29 | #define RTS5260_DV331812_OCP_THD_240 (0x05 << 4) |
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| 30 | #define RTS5260_DV331812_OCP_THD_270 (0x06 << 4) |
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| 31 | #define RTS5260_DV331812_OCP_THD_300 (0x07 << 4) |
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| 32 | |
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| 33 | #define RTS5260_DVIO_OCP_THD_250 (0x00 << 4) |
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| 34 | #define RTS5260_DVIO_OCP_THD_300 (0x01 << 4) |
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| 35 | #define RTS5260_DVIO_OCP_THD_350 (0x02 << 4) |
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| 36 | #define RTS5260_DVIO_OCP_THD_400 (0x03 << 4) |
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| 37 | #define RTS5260_DVIO_OCP_THD_450 (0x04 << 4) |
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| 38 | #define RTS5260_DVIO_OCP_THD_500 (0x05 << 4) |
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| 39 | #define RTS5260_DVIO_OCP_THD_550 (0x06 << 4) |
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| 40 | #define RTS5260_DVIO_OCP_THD_600 (0x07 << 4) |
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| 41 | |
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| 42 | #define RTS5260_DVCC_OCP_THD_550 (0x00 << 4) |
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| 43 | #define RTS5260_DVCC_OCP_THD_970 (0x05 << 4) |
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| 44 | |
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| 45 | #endif |
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| 46 | |
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