| 1 | /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ |
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| 2 | /* |
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| 3 | * Copyright (c) 2003-2022, Intel Corporation. All rights reserved. |
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| 4 | * Intel Management Engine Interface (Intel MEI) Linux driver |
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| 5 | */ |
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| 6 | #ifndef _MEI_HW_MEI_REGS_H_ |
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| 7 | #define _MEI_HW_MEI_REGS_H_ |
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| 8 | |
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| 9 | /* |
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| 10 | * MEI device IDs |
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| 11 | */ |
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| 12 | #define MEI_DEV_ID_82946GZ 0x2974 /* 82946GZ/GL */ |
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| 13 | #define MEI_DEV_ID_82G35 0x2984 /* 82G35 Express */ |
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| 14 | #define MEI_DEV_ID_82Q965 0x2994 /* 82Q963/Q965 */ |
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| 15 | #define MEI_DEV_ID_82G965 0x29A4 /* 82P965/G965 */ |
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| 16 | |
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| 17 | #define MEI_DEV_ID_82GM965 0x2A04 /* Mobile PM965/GM965 */ |
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| 18 | #define MEI_DEV_ID_82GME965 0x2A14 /* Mobile GME965/GLE960 */ |
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| 19 | |
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| 20 | #define MEI_DEV_ID_ICH9_82Q35 0x29B4 /* 82Q35 Express */ |
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| 21 | #define MEI_DEV_ID_ICH9_82G33 0x29C4 /* 82G33/G31/P35/P31 Express */ |
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| 22 | #define MEI_DEV_ID_ICH9_82Q33 0x29D4 /* 82Q33 Express */ |
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| 23 | #define MEI_DEV_ID_ICH9_82X38 0x29E4 /* 82X38/X48 Express */ |
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| 24 | #define MEI_DEV_ID_ICH9_3200 0x29F4 /* 3200/3210 Server */ |
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| 25 | |
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| 26 | #define MEI_DEV_ID_ICH9_6 0x28B4 /* Bearlake */ |
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| 27 | #define MEI_DEV_ID_ICH9_7 0x28C4 /* Bearlake */ |
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| 28 | #define MEI_DEV_ID_ICH9_8 0x28D4 /* Bearlake */ |
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| 29 | #define MEI_DEV_ID_ICH9_9 0x28E4 /* Bearlake */ |
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| 30 | #define MEI_DEV_ID_ICH9_10 0x28F4 /* Bearlake */ |
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| 31 | |
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| 32 | #define MEI_DEV_ID_ICH9M_1 0x2A44 /* Cantiga */ |
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| 33 | #define MEI_DEV_ID_ICH9M_2 0x2A54 /* Cantiga */ |
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| 34 | #define MEI_DEV_ID_ICH9M_3 0x2A64 /* Cantiga */ |
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| 35 | #define MEI_DEV_ID_ICH9M_4 0x2A74 /* Cantiga */ |
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| 36 | |
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| 37 | #define MEI_DEV_ID_ICH10_1 0x2E04 /* Eaglelake */ |
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| 38 | #define MEI_DEV_ID_ICH10_2 0x2E14 /* Eaglelake */ |
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| 39 | #define MEI_DEV_ID_ICH10_3 0x2E24 /* Eaglelake */ |
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| 40 | #define MEI_DEV_ID_ICH10_4 0x2E34 /* Eaglelake */ |
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| 41 | |
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| 42 | #define MEI_DEV_ID_IBXPK_1 0x3B64 /* Calpella */ |
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| 43 | #define MEI_DEV_ID_IBXPK_2 0x3B65 /* Calpella */ |
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| 44 | |
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| 45 | #define MEI_DEV_ID_CPT_1 0x1C3A /* Couger Point */ |
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| 46 | #define MEI_DEV_ID_PBG_1 0x1D3A /* C600/X79 Patsburg */ |
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| 47 | |
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| 48 | #define MEI_DEV_ID_PPT_1 0x1E3A /* Panther Point */ |
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| 49 | #define MEI_DEV_ID_PPT_2 0x1CBA /* Panther Point */ |
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| 50 | #define MEI_DEV_ID_PPT_3 0x1DBA /* Panther Point */ |
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| 51 | |
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| 52 | #define MEI_DEV_ID_LPT_H 0x8C3A /* Lynx Point H */ |
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| 53 | #define MEI_DEV_ID_LPT_W 0x8D3A /* Lynx Point - Wellsburg */ |
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| 54 | #define MEI_DEV_ID_LPT_LP 0x9C3A /* Lynx Point LP */ |
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| 55 | #define MEI_DEV_ID_LPT_HR 0x8CBA /* Lynx Point H Refresh */ |
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| 56 | |
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| 57 | #define MEI_DEV_ID_WPT_LP 0x9CBA /* Wildcat Point LP */ |
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| 58 | #define MEI_DEV_ID_WPT_LP_2 0x9CBB /* Wildcat Point LP 2 */ |
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| 59 | |
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| 60 | #define MEI_DEV_ID_SPT 0x9D3A /* Sunrise Point */ |
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| 61 | #define MEI_DEV_ID_SPT_2 0x9D3B /* Sunrise Point 2 */ |
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| 62 | #define MEI_DEV_ID_SPT_3 0x9D3E /* Sunrise Point 3 (iToutch) */ |
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| 63 | #define MEI_DEV_ID_SPT_H 0xA13A /* Sunrise Point H */ |
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| 64 | #define MEI_DEV_ID_SPT_H_2 0xA13B /* Sunrise Point H 2 */ |
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| 65 | |
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| 66 | #define MEI_DEV_ID_LBG 0xA1BA /* Lewisburg (SPT) */ |
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| 67 | |
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| 68 | #define MEI_DEV_ID_BXT_M 0x1A9A /* Broxton M */ |
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| 69 | #define MEI_DEV_ID_APL_I 0x5A9A /* Apollo Lake I */ |
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| 70 | |
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| 71 | #define MEI_DEV_ID_DNV_IE 0x19E5 /* Denverton IE */ |
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| 72 | |
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| 73 | #define MEI_DEV_ID_GLK 0x319A /* Gemini Lake */ |
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| 74 | |
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| 75 | #define MEI_DEV_ID_KBP 0xA2BA /* Kaby Point */ |
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| 76 | #define MEI_DEV_ID_KBP_2 0xA2BB /* Kaby Point 2 */ |
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| 77 | #define MEI_DEV_ID_KBP_3 0xA2BE /* Kaby Point 3 (iTouch) */ |
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| 78 | |
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| 79 | #define MEI_DEV_ID_CNP_LP 0x9DE0 /* Cannon Point LP */ |
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| 80 | #define MEI_DEV_ID_CNP_LP_3 0x9DE4 /* Cannon Point LP 3 (iTouch) */ |
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| 81 | #define MEI_DEV_ID_CNP_H 0xA360 /* Cannon Point H */ |
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| 82 | #define MEI_DEV_ID_CNP_H_3 0xA364 /* Cannon Point H 3 (iTouch) */ |
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| 83 | |
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| 84 | #define MEI_DEV_ID_CMP_LP 0x02e0 /* Comet Point LP */ |
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| 85 | #define MEI_DEV_ID_CMP_LP_3 0x02e4 /* Comet Point LP 3 (iTouch) */ |
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| 86 | |
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| 87 | #define MEI_DEV_ID_CMP_V 0xA3BA /* Comet Point Lake V */ |
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| 88 | |
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| 89 | #define MEI_DEV_ID_CMP_H 0x06e0 /* Comet Lake H */ |
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| 90 | #define MEI_DEV_ID_CMP_H_3 0x06e4 /* Comet Lake H 3 (iTouch) */ |
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| 91 | |
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| 92 | #define MEI_DEV_ID_CDF 0x18D3 /* Cedar Fork */ |
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| 93 | |
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| 94 | #define MEI_DEV_ID_ICP_LP 0x34E0 /* Ice Lake Point LP */ |
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| 95 | #define MEI_DEV_ID_ICP_N 0x38E0 /* Ice Lake Point N */ |
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| 96 | |
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| 97 | #define MEI_DEV_ID_JSP_N 0x4DE0 /* Jasper Lake Point N */ |
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| 98 | |
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| 99 | #define MEI_DEV_ID_TGP_LP 0xA0E0 /* Tiger Lake Point LP */ |
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| 100 | #define MEI_DEV_ID_TGP_H 0x43E0 /* Tiger Lake Point H */ |
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| 101 | |
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| 102 | #define MEI_DEV_ID_MCC 0x4B70 /* Mule Creek Canyon (EHL) */ |
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| 103 | #define MEI_DEV_ID_MCC_4 0x4B75 /* Mule Creek Canyon 4 (EHL) */ |
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| 104 | |
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| 105 | #define MEI_DEV_ID_EBG 0x1BE0 /* Emmitsburg WS */ |
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| 106 | |
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| 107 | #define MEI_DEV_ID_ADP_S 0x7AE8 /* Alder Lake Point S */ |
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| 108 | #define MEI_DEV_ID_ADP_LP 0x7A60 /* Alder Lake Point LP */ |
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| 109 | #define MEI_DEV_ID_ADP_P 0x51E0 /* Alder Lake Point P */ |
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| 110 | #define MEI_DEV_ID_ADP_N 0x54E0 /* Alder Lake Point N */ |
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| 111 | |
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| 112 | #define MEI_DEV_ID_RPL_S 0x7A68 /* Raptor Lake Point S */ |
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| 113 | |
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| 114 | #define MEI_DEV_ID_MTL_M 0x7E70 /* Meteor Lake Point M */ |
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| 115 | #define MEI_DEV_ID_ARL_S 0x7F68 /* Arrow Lake Point S */ |
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| 116 | #define MEI_DEV_ID_ARL_H 0x7770 /* Arrow Lake Point H */ |
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| 117 | |
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| 118 | /* |
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| 119 | * MEI HW Section |
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| 120 | */ |
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| 121 | |
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| 122 | /* Host Firmware Status Registers in PCI Config Space */ |
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| 123 | #define PCI_CFG_HFS_1 0x40 |
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| 124 | # define PCI_CFG_HFS_1_D0I3_MSK 0x80000000 |
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| 125 | # define PCI_CFG_HFS_1_OPMODE_MSK 0xf0000 /* OP MODE Mask: SPS <= 4.0 */ |
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| 126 | # define PCI_CFG_HFS_1_OPMODE_SPS 0xf0000 /* SPS SKU : SPS <= 4.0 */ |
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| 127 | #define PCI_CFG_HFS_2 0x48 |
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| 128 | # define PCI_CFG_HFS_2_PM_CMOFF_TO_CMX_ERROR 0x1000000 /* CMoff->CMx wake after an error */ |
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| 129 | # define PCI_CFG_HFS_2_PM_CM_RESET_ERROR 0x5000000 /* CME reset due to exception */ |
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| 130 | # define PCI_CFG_HFS_2_PM_EVENT_MASK 0xf000000 |
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| 131 | #define PCI_CFG_HFS_3 0x60 |
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| 132 | # define PCI_CFG_HFS_3_FW_SKU_MSK 0x00000070 |
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| 133 | # define PCI_CFG_HFS_3_FW_SKU_IGN 0x00000000 |
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| 134 | # define PCI_CFG_HFS_3_FW_SKU_SPS 0x00000060 |
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| 135 | #define PCI_CFG_HFS_4 0x64 |
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| 136 | #define PCI_CFG_HFS_5 0x68 |
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| 137 | # define GSC_CFG_HFS_5_BOOT_TYPE_MSK 0x00000003 |
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| 138 | # define GSC_CFG_HFS_5_BOOT_TYPE_PXP 3 |
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| 139 | #define PCI_CFG_HFS_6 0x6C |
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| 140 | |
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| 141 | /* MEI registers */ |
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| 142 | /* H_CB_WW - Host Circular Buffer (CB) Write Window register */ |
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| 143 | #define H_CB_WW 0 |
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| 144 | /* H_CSR - Host Control Status register */ |
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| 145 | #define H_CSR 4 |
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| 146 | /* ME_CB_RW - ME Circular Buffer Read Window register (read only) */ |
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| 147 | #define ME_CB_RW 8 |
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| 148 | /* ME_CSR_HA - ME Control Status Host Access register (read only) */ |
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| 149 | #define ME_CSR_HA 0xC |
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| 150 | /* H_HGC_CSR - PGI register */ |
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| 151 | #define H_HPG_CSR 0x10 |
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| 152 | /* H_D0I3C - D0I3 Control */ |
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| 153 | #define H_D0I3C 0x800 |
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| 154 | |
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| 155 | #define H_GSC_EXT_OP_MEM_BASE_ADDR_LO_REG 0x100 |
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| 156 | #define H_GSC_EXT_OP_MEM_BASE_ADDR_HI_REG 0x104 |
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| 157 | #define H_GSC_EXT_OP_MEM_LIMIT_REG 0x108 |
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| 158 | #define GSC_EXT_OP_MEM_VALID BIT(31) |
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| 159 | |
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| 160 | /* register bits of H_CSR (Host Control Status register) */ |
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| 161 | /* Host Circular Buffer Depth - maximum number of 32-bit entries in CB */ |
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| 162 | #define H_CBD 0xFF000000 |
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| 163 | /* Host Circular Buffer Write Pointer */ |
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| 164 | #define H_CBWP 0x00FF0000 |
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| 165 | /* Host Circular Buffer Read Pointer */ |
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| 166 | #define H_CBRP 0x0000FF00 |
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| 167 | /* Host Reset */ |
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| 168 | #define H_RST 0x00000010 |
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| 169 | /* Host Ready */ |
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| 170 | #define H_RDY 0x00000008 |
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| 171 | /* Host Interrupt Generate */ |
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| 172 | #define H_IG 0x00000004 |
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| 173 | /* Host Interrupt Status */ |
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| 174 | #define H_IS 0x00000002 |
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| 175 | /* Host Interrupt Enable */ |
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| 176 | #define H_IE 0x00000001 |
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| 177 | /* Host D0I3 Interrupt Enable */ |
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| 178 | #define H_D0I3C_IE 0x00000020 |
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| 179 | /* Host D0I3 Interrupt Status */ |
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| 180 | #define H_D0I3C_IS 0x00000040 |
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| 181 | |
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| 182 | /* H_CSR masks */ |
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| 183 | #define H_CSR_IE_MASK (H_IE | H_D0I3C_IE) |
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| 184 | #define H_CSR_IS_MASK (H_IS | H_D0I3C_IS) |
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| 185 | |
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| 186 | /* register bits of ME_CSR_HA (ME Control Status Host Access register) */ |
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| 187 | /* ME CB (Circular Buffer) Depth HRA (Host Read Access) - host read only |
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| 188 | access to ME_CBD */ |
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| 189 | #define ME_CBD_HRA 0xFF000000 |
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| 190 | /* ME CB Write Pointer HRA - host read only access to ME_CBWP */ |
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| 191 | #define ME_CBWP_HRA 0x00FF0000 |
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| 192 | /* ME CB Read Pointer HRA - host read only access to ME_CBRP */ |
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| 193 | #define ME_CBRP_HRA 0x0000FF00 |
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| 194 | /* ME Power Gate Isolation Capability HRA - host ready only access */ |
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| 195 | #define ME_PGIC_HRA 0x00000040 |
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| 196 | /* ME Reset HRA - host read only access to ME_RST */ |
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| 197 | #define ME_RST_HRA 0x00000010 |
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| 198 | /* ME Ready HRA - host read only access to ME_RDY */ |
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| 199 | #define ME_RDY_HRA 0x00000008 |
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| 200 | /* ME Interrupt Generate HRA - host read only access to ME_IG */ |
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| 201 | #define ME_IG_HRA 0x00000004 |
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| 202 | /* ME Interrupt Status HRA - host read only access to ME_IS */ |
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| 203 | #define ME_IS_HRA 0x00000002 |
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| 204 | /* ME Interrupt Enable HRA - host read only access to ME_IE */ |
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| 205 | #define ME_IE_HRA 0x00000001 |
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| 206 | /* TRC control shadow register */ |
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| 207 | #define ME_TRC 0x00000030 |
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| 208 | |
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| 209 | /* H_HPG_CSR register bits */ |
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| 210 | #define H_HPG_CSR_PGIHEXR 0x00000001 |
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| 211 | #define H_HPG_CSR_PGI 0x00000002 |
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| 212 | |
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| 213 | /* H_D0I3C register bits */ |
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| 214 | #define H_D0I3C_CIP 0x00000001 |
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| 215 | #define H_D0I3C_IR 0x00000002 |
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| 216 | #define H_D0I3C_I3 0x00000004 |
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| 217 | #define H_D0I3C_RR 0x00000008 |
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| 218 | |
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| 219 | #endif /* _MEI_HW_MEI_REGS_H_ */ |
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| 220 | |
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