1 | /* |
2 | * Copyright (c) 2008 Silicon Graphics, Inc. All Rights Reserved. |
3 | * |
4 | * This program is free software; you can redistribute it and/or modify |
5 | * it under the terms of the GNU Lesser General Public License as published by |
6 | * the Free Software Foundation; either version 2.1 of the License, or |
7 | * (at your option) any later version. |
8 | * |
9 | * This program is distributed in the hope that it will be useful, |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
12 | * GNU Lesser General Public License for more details. |
13 | * |
14 | * You should have received a copy of the GNU Lesser General Public License |
15 | * along with this program; if not, write to the Free Software |
16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
17 | */ |
18 | |
19 | #ifndef __GRU_INSTRUCTIONS_H__ |
20 | #define __GRU_INSTRUCTIONS_H__ |
21 | |
22 | extern int gru_check_status_proc(void *cb); |
23 | extern int gru_wait_proc(void *cb); |
24 | extern void gru_wait_abort_proc(void *cb); |
25 | |
26 | |
27 | |
28 | /* |
29 | * Architecture dependent functions |
30 | */ |
31 | |
32 | #if defined(CONFIG_X86_64) |
33 | #include <asm/cacheflush.h> |
34 | #define __flush_cache(p) clflush(p) |
35 | #define gru_ordered_store_ulong(p, v) \ |
36 | do { \ |
37 | barrier(); \ |
38 | *(unsigned long *)p = v; \ |
39 | } while (0) |
40 | #else |
41 | #error "Unsupported architecture" |
42 | #endif |
43 | |
44 | /* |
45 | * Control block status and exception codes |
46 | */ |
47 | #define CBS_IDLE 0 |
48 | #define CBS_EXCEPTION 1 |
49 | #define CBS_ACTIVE 2 |
50 | #define CBS_CALL_OS 3 |
51 | |
52 | /* CB substatus bitmasks */ |
53 | #define CBSS_MSG_QUEUE_MASK 7 |
54 | #define CBSS_IMPLICIT_ABORT_ACTIVE_MASK 8 |
55 | |
56 | /* CB substatus message queue values (low 3 bits of substatus) */ |
57 | #define CBSS_NO_ERROR 0 |
58 | #define CBSS_LB_OVERFLOWED 1 |
59 | #define CBSS_QLIMIT_REACHED 2 |
60 | #define CBSS_PAGE_OVERFLOW 3 |
61 | #define CBSS_AMO_NACKED 4 |
62 | #define CBSS_PUT_NACKED 5 |
63 | |
64 | /* |
65 | * Structure used to fetch exception detail for CBs that terminate with |
66 | * CBS_EXCEPTION |
67 | */ |
68 | struct control_block_extended_exc_detail { |
69 | unsigned long cb; |
70 | int opc; |
71 | int ecause; |
72 | int exopc; |
73 | long exceptdet0; |
74 | int exceptdet1; |
75 | int cbrstate; |
76 | int cbrexecstatus; |
77 | }; |
78 | |
79 | /* |
80 | * Instruction formats |
81 | */ |
82 | |
83 | /* |
84 | * Generic instruction format. |
85 | * This definition has precise bit field definitions. |
86 | */ |
87 | struct gru_instruction_bits { |
88 | /* DW 0 - low */ |
89 | unsigned int icmd: 1; |
90 | unsigned char ima: 3; /* CB_DelRep, unmapped mode */ |
91 | unsigned char reserved0: 4; |
92 | unsigned int xtype: 3; |
93 | unsigned int iaa0: 2; |
94 | unsigned int iaa1: 2; |
95 | unsigned char reserved1: 1; |
96 | unsigned char opc: 8; /* opcode */ |
97 | unsigned char exopc: 8; /* extended opcode */ |
98 | /* DW 0 - high */ |
99 | unsigned int idef2: 22; /* TRi0 */ |
100 | unsigned char reserved2: 2; |
101 | unsigned char istatus: 2; |
102 | unsigned char isubstatus:4; |
103 | unsigned char reserved3: 1; |
104 | unsigned char tlb_fault_color: 1; |
105 | /* DW 1 */ |
106 | unsigned long idef4; /* 42 bits: TRi1, BufSize */ |
107 | /* DW 2-6 */ |
108 | unsigned long idef1; /* BAddr0 */ |
109 | unsigned long idef5; /* Nelem */ |
110 | unsigned long idef6; /* Stride, Operand1 */ |
111 | unsigned long idef3; /* BAddr1, Value, Operand2 */ |
112 | unsigned long reserved4; |
113 | /* DW 7 */ |
114 | unsigned long avalue; /* AValue */ |
115 | }; |
116 | |
117 | /* |
118 | * Generic instruction with friendlier names. This format is used |
119 | * for inline instructions. |
120 | */ |
121 | struct gru_instruction { |
122 | /* DW 0 */ |
123 | union { |
124 | unsigned long op64; /* icmd,xtype,iaa0,ima,opc,tri0 */ |
125 | struct { |
126 | unsigned int op32; |
127 | unsigned int tri0; |
128 | }; |
129 | }; |
130 | unsigned long tri1_bufsize; /* DW 1 */ |
131 | unsigned long baddr0; /* DW 2 */ |
132 | unsigned long nelem; /* DW 3 */ |
133 | unsigned long op1_stride; /* DW 4 */ |
134 | unsigned long op2_value_baddr1; /* DW 5 */ |
135 | unsigned long reserved0; /* DW 6 */ |
136 | unsigned long avalue; /* DW 7 */ |
137 | }; |
138 | |
139 | /* Some shifts and masks for the low 64 bits of a GRU command */ |
140 | #define GRU_CB_ICMD_SHFT 0 |
141 | #define GRU_CB_ICMD_MASK 0x1 |
142 | #define GRU_CB_XTYPE_SHFT 8 |
143 | #define GRU_CB_XTYPE_MASK 0x7 |
144 | #define GRU_CB_IAA0_SHFT 11 |
145 | #define GRU_CB_IAA0_MASK 0x3 |
146 | #define GRU_CB_IAA1_SHFT 13 |
147 | #define GRU_CB_IAA1_MASK 0x3 |
148 | #define GRU_CB_IMA_SHFT 1 |
149 | #define GRU_CB_IMA_MASK 0x3 |
150 | #define GRU_CB_OPC_SHFT 16 |
151 | #define GRU_CB_OPC_MASK 0xff |
152 | #define GRU_CB_EXOPC_SHFT 24 |
153 | #define GRU_CB_EXOPC_MASK 0xff |
154 | #define GRU_IDEF2_SHFT 32 |
155 | #define GRU_IDEF2_MASK 0x3ffff |
156 | #define GRU_ISTATUS_SHFT 56 |
157 | #define GRU_ISTATUS_MASK 0x3 |
158 | |
159 | /* GRU instruction opcodes (opc field) */ |
160 | #define OP_NOP 0x00 |
161 | #define OP_BCOPY 0x01 |
162 | #define OP_VLOAD 0x02 |
163 | #define OP_IVLOAD 0x03 |
164 | #define OP_VSTORE 0x04 |
165 | #define OP_IVSTORE 0x05 |
166 | #define OP_VSET 0x06 |
167 | #define OP_IVSET 0x07 |
168 | #define OP_MESQ 0x08 |
169 | #define OP_GAMXR 0x09 |
170 | #define OP_GAMIR 0x0a |
171 | #define OP_GAMIRR 0x0b |
172 | #define OP_GAMER 0x0c |
173 | #define OP_GAMERR 0x0d |
174 | #define OP_BSTORE 0x0e |
175 | #define OP_VFLUSH 0x0f |
176 | |
177 | |
178 | /* Extended opcodes values (exopc field) */ |
179 | |
180 | /* GAMIR - AMOs with implicit operands */ |
181 | #define EOP_IR_FETCH 0x01 /* Plain fetch of memory */ |
182 | #define EOP_IR_CLR 0x02 /* Fetch and clear */ |
183 | #define EOP_IR_INC 0x05 /* Fetch and increment */ |
184 | #define EOP_IR_DEC 0x07 /* Fetch and decrement */ |
185 | #define EOP_IR_QCHK1 0x0d /* Queue check, 64 byte msg */ |
186 | #define EOP_IR_QCHK2 0x0e /* Queue check, 128 byte msg */ |
187 | |
188 | /* GAMIRR - Registered AMOs with implicit operands */ |
189 | #define EOP_IRR_FETCH 0x01 /* Registered fetch of memory */ |
190 | #define EOP_IRR_CLR 0x02 /* Registered fetch and clear */ |
191 | #define EOP_IRR_INC 0x05 /* Registered fetch and increment */ |
192 | #define EOP_IRR_DEC 0x07 /* Registered fetch and decrement */ |
193 | #define EOP_IRR_DECZ 0x0f /* Registered fetch and decrement, update on zero*/ |
194 | |
195 | /* GAMER - AMOs with explicit operands */ |
196 | #define EOP_ER_SWAP 0x00 /* Exchange argument and memory */ |
197 | #define EOP_ER_OR 0x01 /* Logical OR with memory */ |
198 | #define EOP_ER_AND 0x02 /* Logical AND with memory */ |
199 | #define EOP_ER_XOR 0x03 /* Logical XOR with memory */ |
200 | #define EOP_ER_ADD 0x04 /* Add value to memory */ |
201 | #define EOP_ER_CSWAP 0x08 /* Compare with operand2, write operand1 if match*/ |
202 | #define EOP_ER_CADD 0x0c /* Queue check, operand1*64 byte msg */ |
203 | |
204 | /* GAMERR - Registered AMOs with explicit operands */ |
205 | #define EOP_ERR_SWAP 0x00 /* Exchange argument and memory */ |
206 | #define EOP_ERR_OR 0x01 /* Logical OR with memory */ |
207 | #define EOP_ERR_AND 0x02 /* Logical AND with memory */ |
208 | #define EOP_ERR_XOR 0x03 /* Logical XOR with memory */ |
209 | #define EOP_ERR_ADD 0x04 /* Add value to memory */ |
210 | #define EOP_ERR_CSWAP 0x08 /* Compare with operand2, write operand1 if match*/ |
211 | #define EOP_ERR_EPOLL 0x09 /* Poll for equality */ |
212 | #define EOP_ERR_NPOLL 0x0a /* Poll for inequality */ |
213 | |
214 | /* GAMXR - SGI Arithmetic unit */ |
215 | #define EOP_XR_CSWAP 0x0b /* Masked compare exchange */ |
216 | |
217 | |
218 | /* Transfer types (xtype field) */ |
219 | #define XTYPE_B 0x0 /* byte */ |
220 | #define XTYPE_S 0x1 /* short (2-byte) */ |
221 | #define XTYPE_W 0x2 /* word (4-byte) */ |
222 | #define XTYPE_DW 0x3 /* doubleword (8-byte) */ |
223 | #define XTYPE_CL 0x6 /* cacheline (64-byte) */ |
224 | |
225 | |
226 | /* Instruction access attributes (iaa0, iaa1 fields) */ |
227 | #define IAA_RAM 0x0 /* normal cached RAM access */ |
228 | #define IAA_NCRAM 0x2 /* noncoherent RAM access */ |
229 | #define IAA_MMIO 0x1 /* noncoherent memory-mapped I/O space */ |
230 | #define IAA_REGISTER 0x3 /* memory-mapped registers, etc. */ |
231 | |
232 | |
233 | /* Instruction mode attributes (ima field) */ |
234 | #define IMA_MAPPED 0x0 /* Virtual mode */ |
235 | #define IMA_CB_DELAY 0x1 /* hold read responses until status changes */ |
236 | #define IMA_UNMAPPED 0x2 /* bypass the TLBs (OS only) */ |
237 | #define IMA_INTERRUPT 0x4 /* Interrupt when instruction completes */ |
238 | |
239 | /* CBE ecause bits */ |
240 | #define CBE_CAUSE_RI (1 << 0) |
241 | #define CBE_CAUSE_INVALID_INSTRUCTION (1 << 1) |
242 | #define CBE_CAUSE_UNMAPPED_MODE_FORBIDDEN (1 << 2) |
243 | #define CBE_CAUSE_PE_CHECK_DATA_ERROR (1 << 3) |
244 | #define CBE_CAUSE_IAA_GAA_MISMATCH (1 << 4) |
245 | #define CBE_CAUSE_DATA_SEGMENT_LIMIT_EXCEPTION (1 << 5) |
246 | #define CBE_CAUSE_OS_FATAL_TLB_FAULT (1 << 6) |
247 | #define CBE_CAUSE_EXECUTION_HW_ERROR (1 << 7) |
248 | #define CBE_CAUSE_TLBHW_ERROR (1 << 8) |
249 | #define CBE_CAUSE_RA_REQUEST_TIMEOUT (1 << 9) |
250 | #define CBE_CAUSE_HA_REQUEST_TIMEOUT (1 << 10) |
251 | #define CBE_CAUSE_RA_RESPONSE_FATAL (1 << 11) |
252 | #define CBE_CAUSE_RA_RESPONSE_NON_FATAL (1 << 12) |
253 | #define CBE_CAUSE_HA_RESPONSE_FATAL (1 << 13) |
254 | #define CBE_CAUSE_HA_RESPONSE_NON_FATAL (1 << 14) |
255 | #define CBE_CAUSE_ADDRESS_SPACE_DECODE_ERROR (1 << 15) |
256 | #define CBE_CAUSE_PROTOCOL_STATE_DATA_ERROR (1 << 16) |
257 | #define CBE_CAUSE_RA_RESPONSE_DATA_ERROR (1 << 17) |
258 | #define CBE_CAUSE_HA_RESPONSE_DATA_ERROR (1 << 18) |
259 | #define CBE_CAUSE_FORCED_ERROR (1 << 19) |
260 | |
261 | /* CBE cbrexecstatus bits */ |
262 | #define CBR_EXS_ABORT_OCC_BIT 0 |
263 | #define CBR_EXS_INT_OCC_BIT 1 |
264 | #define CBR_EXS_PENDING_BIT 2 |
265 | #define CBR_EXS_QUEUED_BIT 3 |
266 | #define CBR_EXS_TLB_INVAL_BIT 4 |
267 | #define CBR_EXS_EXCEPTION_BIT 5 |
268 | #define CBR_EXS_CB_INT_PENDING_BIT 6 |
269 | |
270 | #define CBR_EXS_ABORT_OCC (1 << CBR_EXS_ABORT_OCC_BIT) |
271 | #define CBR_EXS_INT_OCC (1 << CBR_EXS_INT_OCC_BIT) |
272 | #define CBR_EXS_PENDING (1 << CBR_EXS_PENDING_BIT) |
273 | #define CBR_EXS_QUEUED (1 << CBR_EXS_QUEUED_BIT) |
274 | #define CBR_EXS_TLB_INVAL (1 << CBR_EXS_TLB_INVAL_BIT) |
275 | #define CBR_EXS_EXCEPTION (1 << CBR_EXS_EXCEPTION_BIT) |
276 | #define CBR_EXS_CB_INT_PENDING (1 << CBR_EXS_CB_INT_PENDING_BIT) |
277 | |
278 | /* |
279 | * Exceptions are retried for the following cases. If any OTHER bits are set |
280 | * in ecause, the exception is not retryable. |
281 | */ |
282 | #define EXCEPTION_RETRY_BITS (CBE_CAUSE_EXECUTION_HW_ERROR | \ |
283 | CBE_CAUSE_TLBHW_ERROR | \ |
284 | CBE_CAUSE_RA_REQUEST_TIMEOUT | \ |
285 | CBE_CAUSE_RA_RESPONSE_NON_FATAL | \ |
286 | CBE_CAUSE_HA_RESPONSE_NON_FATAL | \ |
287 | CBE_CAUSE_RA_RESPONSE_DATA_ERROR | \ |
288 | CBE_CAUSE_HA_RESPONSE_DATA_ERROR \ |
289 | ) |
290 | |
291 | /* Message queue head structure */ |
292 | union gru_mesqhead { |
293 | unsigned long val; |
294 | struct { |
295 | unsigned int head; |
296 | unsigned int limit; |
297 | }; |
298 | }; |
299 | |
300 | |
301 | /* Generate the low word of a GRU instruction */ |
302 | static inline unsigned long |
303 | __opdword(unsigned char opcode, unsigned char exopc, unsigned char xtype, |
304 | unsigned char iaa0, unsigned char iaa1, |
305 | unsigned long idef2, unsigned char ima) |
306 | { |
307 | return (1 << GRU_CB_ICMD_SHFT) | |
308 | ((unsigned long)CBS_ACTIVE << GRU_ISTATUS_SHFT) | |
309 | (idef2<< GRU_IDEF2_SHFT) | |
310 | (iaa0 << GRU_CB_IAA0_SHFT) | |
311 | (iaa1 << GRU_CB_IAA1_SHFT) | |
312 | (ima << GRU_CB_IMA_SHFT) | |
313 | (xtype << GRU_CB_XTYPE_SHFT) | |
314 | (opcode << GRU_CB_OPC_SHFT) | |
315 | (exopc << GRU_CB_EXOPC_SHFT); |
316 | } |
317 | |
318 | /* |
319 | * Architecture specific intrinsics |
320 | */ |
321 | static inline void gru_flush_cache(void *p) |
322 | { |
323 | __flush_cache(p); |
324 | } |
325 | |
326 | /* |
327 | * Store the lower 64 bits of the command including the "start" bit. Then |
328 | * start the instruction executing. |
329 | */ |
330 | static inline void gru_start_instruction(struct gru_instruction *ins, unsigned long op64) |
331 | { |
332 | gru_ordered_store_ulong(ins, op64); |
333 | mb(); |
334 | gru_flush_cache(p: ins); |
335 | } |
336 | |
337 | |
338 | /* Convert "hints" to IMA */ |
339 | #define CB_IMA(h) ((h) | IMA_UNMAPPED) |
340 | |
341 | /* Convert data segment cache line index into TRI0 / TRI1 value */ |
342 | #define GRU_DINDEX(i) ((i) * GRU_CACHE_LINE_BYTES) |
343 | |
344 | /* Inline functions for GRU instructions. |
345 | * Note: |
346 | * - nelem and stride are in elements |
347 | * - tri0/tri1 is in bytes for the beginning of the data segment. |
348 | */ |
349 | static inline void gru_vload_phys(void *cb, unsigned long gpa, |
350 | unsigned int tri0, int iaa, unsigned long hints) |
351 | { |
352 | struct gru_instruction *ins = (struct gru_instruction *)cb; |
353 | |
354 | ins->baddr0 = (long)gpa | ((unsigned long)iaa << 62); |
355 | ins->nelem = 1; |
356 | ins->op1_stride = 1; |
357 | gru_start_instruction(ins, op64: __opdword(OP_VLOAD, exopc: 0, XTYPE_DW, iaa0: iaa, iaa1: 0, |
358 | idef2: (unsigned long)tri0, CB_IMA(hints))); |
359 | } |
360 | |
361 | static inline void gru_vstore_phys(void *cb, unsigned long gpa, |
362 | unsigned int tri0, int iaa, unsigned long hints) |
363 | { |
364 | struct gru_instruction *ins = (struct gru_instruction *)cb; |
365 | |
366 | ins->baddr0 = (long)gpa | ((unsigned long)iaa << 62); |
367 | ins->nelem = 1; |
368 | ins->op1_stride = 1; |
369 | gru_start_instruction(ins, op64: __opdword(OP_VSTORE, exopc: 0, XTYPE_DW, iaa0: iaa, iaa1: 0, |
370 | idef2: (unsigned long)tri0, CB_IMA(hints))); |
371 | } |
372 | |
373 | static inline void gru_vload(void *cb, unsigned long mem_addr, |
374 | unsigned int tri0, unsigned char xtype, unsigned long nelem, |
375 | unsigned long stride, unsigned long hints) |
376 | { |
377 | struct gru_instruction *ins = (struct gru_instruction *)cb; |
378 | |
379 | ins->baddr0 = (long)mem_addr; |
380 | ins->nelem = nelem; |
381 | ins->op1_stride = stride; |
382 | gru_start_instruction(ins, op64: __opdword(OP_VLOAD, exopc: 0, xtype, IAA_RAM, iaa1: 0, |
383 | idef2: (unsigned long)tri0, CB_IMA(hints))); |
384 | } |
385 | |
386 | static inline void gru_vstore(void *cb, unsigned long mem_addr, |
387 | unsigned int tri0, unsigned char xtype, unsigned long nelem, |
388 | unsigned long stride, unsigned long hints) |
389 | { |
390 | struct gru_instruction *ins = (void *)cb; |
391 | |
392 | ins->baddr0 = (long)mem_addr; |
393 | ins->nelem = nelem; |
394 | ins->op1_stride = stride; |
395 | gru_start_instruction(ins, op64: __opdword(OP_VSTORE, exopc: 0, xtype, IAA_RAM, iaa1: 0, |
396 | idef2: tri0, CB_IMA(hints))); |
397 | } |
398 | |
399 | static inline void gru_ivload(void *cb, unsigned long mem_addr, |
400 | unsigned int tri0, unsigned int tri1, unsigned char xtype, |
401 | unsigned long nelem, unsigned long hints) |
402 | { |
403 | struct gru_instruction *ins = (void *)cb; |
404 | |
405 | ins->baddr0 = (long)mem_addr; |
406 | ins->nelem = nelem; |
407 | ins->tri1_bufsize = tri1; |
408 | gru_start_instruction(ins, op64: __opdword(OP_IVLOAD, exopc: 0, xtype, IAA_RAM, iaa1: 0, |
409 | idef2: tri0, CB_IMA(hints))); |
410 | } |
411 | |
412 | static inline void gru_ivstore(void *cb, unsigned long mem_addr, |
413 | unsigned int tri0, unsigned int tri1, |
414 | unsigned char xtype, unsigned long nelem, unsigned long hints) |
415 | { |
416 | struct gru_instruction *ins = (void *)cb; |
417 | |
418 | ins->baddr0 = (long)mem_addr; |
419 | ins->nelem = nelem; |
420 | ins->tri1_bufsize = tri1; |
421 | gru_start_instruction(ins, op64: __opdword(OP_IVSTORE, exopc: 0, xtype, IAA_RAM, iaa1: 0, |
422 | idef2: tri0, CB_IMA(hints))); |
423 | } |
424 | |
425 | static inline void gru_vset(void *cb, unsigned long mem_addr, |
426 | unsigned long value, unsigned char xtype, unsigned long nelem, |
427 | unsigned long stride, unsigned long hints) |
428 | { |
429 | struct gru_instruction *ins = (void *)cb; |
430 | |
431 | ins->baddr0 = (long)mem_addr; |
432 | ins->op2_value_baddr1 = value; |
433 | ins->nelem = nelem; |
434 | ins->op1_stride = stride; |
435 | gru_start_instruction(ins, op64: __opdword(OP_VSET, exopc: 0, xtype, IAA_RAM, iaa1: 0, |
436 | idef2: 0, CB_IMA(hints))); |
437 | } |
438 | |
439 | static inline void gru_ivset(void *cb, unsigned long mem_addr, |
440 | unsigned int tri1, unsigned long value, unsigned char xtype, |
441 | unsigned long nelem, unsigned long hints) |
442 | { |
443 | struct gru_instruction *ins = (void *)cb; |
444 | |
445 | ins->baddr0 = (long)mem_addr; |
446 | ins->op2_value_baddr1 = value; |
447 | ins->nelem = nelem; |
448 | ins->tri1_bufsize = tri1; |
449 | gru_start_instruction(ins, op64: __opdword(OP_IVSET, exopc: 0, xtype, IAA_RAM, iaa1: 0, |
450 | idef2: 0, CB_IMA(hints))); |
451 | } |
452 | |
453 | static inline void gru_vflush(void *cb, unsigned long mem_addr, |
454 | unsigned long nelem, unsigned char xtype, unsigned long stride, |
455 | unsigned long hints) |
456 | { |
457 | struct gru_instruction *ins = (void *)cb; |
458 | |
459 | ins->baddr0 = (long)mem_addr; |
460 | ins->op1_stride = stride; |
461 | ins->nelem = nelem; |
462 | gru_start_instruction(ins, op64: __opdword(OP_VFLUSH, exopc: 0, xtype, IAA_RAM, iaa1: 0, |
463 | idef2: 0, CB_IMA(hints))); |
464 | } |
465 | |
466 | static inline void gru_nop(void *cb, int hints) |
467 | { |
468 | struct gru_instruction *ins = (void *)cb; |
469 | |
470 | gru_start_instruction(ins, op64: __opdword(OP_NOP, exopc: 0, xtype: 0, iaa0: 0, iaa1: 0, idef2: 0, CB_IMA(hints))); |
471 | } |
472 | |
473 | |
474 | static inline void gru_bcopy(void *cb, const unsigned long src, |
475 | unsigned long dest, |
476 | unsigned int tri0, unsigned int xtype, unsigned long nelem, |
477 | unsigned int bufsize, unsigned long hints) |
478 | { |
479 | struct gru_instruction *ins = (void *)cb; |
480 | |
481 | ins->baddr0 = (long)src; |
482 | ins->op2_value_baddr1 = (long)dest; |
483 | ins->nelem = nelem; |
484 | ins->tri1_bufsize = bufsize; |
485 | gru_start_instruction(ins, op64: __opdword(OP_BCOPY, exopc: 0, xtype, IAA_RAM, |
486 | IAA_RAM, idef2: tri0, CB_IMA(hints))); |
487 | } |
488 | |
489 | static inline void gru_bstore(void *cb, const unsigned long src, |
490 | unsigned long dest, unsigned int tri0, unsigned int xtype, |
491 | unsigned long nelem, unsigned long hints) |
492 | { |
493 | struct gru_instruction *ins = (void *)cb; |
494 | |
495 | ins->baddr0 = (long)src; |
496 | ins->op2_value_baddr1 = (long)dest; |
497 | ins->nelem = nelem; |
498 | gru_start_instruction(ins, op64: __opdword(OP_BSTORE, exopc: 0, xtype, iaa0: 0, IAA_RAM, |
499 | idef2: tri0, CB_IMA(hints))); |
500 | } |
501 | |
502 | static inline void gru_gamir(void *cb, int exopc, unsigned long src, |
503 | unsigned int xtype, unsigned long hints) |
504 | { |
505 | struct gru_instruction *ins = (void *)cb; |
506 | |
507 | ins->baddr0 = (long)src; |
508 | gru_start_instruction(ins, op64: __opdword(OP_GAMIR, exopc, xtype, IAA_RAM, iaa1: 0, |
509 | idef2: 0, CB_IMA(hints))); |
510 | } |
511 | |
512 | static inline void gru_gamirr(void *cb, int exopc, unsigned long src, |
513 | unsigned int xtype, unsigned long hints) |
514 | { |
515 | struct gru_instruction *ins = (void *)cb; |
516 | |
517 | ins->baddr0 = (long)src; |
518 | gru_start_instruction(ins, op64: __opdword(OP_GAMIRR, exopc, xtype, IAA_RAM, iaa1: 0, |
519 | idef2: 0, CB_IMA(hints))); |
520 | } |
521 | |
522 | static inline void gru_gamer(void *cb, int exopc, unsigned long src, |
523 | unsigned int xtype, |
524 | unsigned long operand1, unsigned long operand2, |
525 | unsigned long hints) |
526 | { |
527 | struct gru_instruction *ins = (void *)cb; |
528 | |
529 | ins->baddr0 = (long)src; |
530 | ins->op1_stride = operand1; |
531 | ins->op2_value_baddr1 = operand2; |
532 | gru_start_instruction(ins, op64: __opdword(OP_GAMER, exopc, xtype, IAA_RAM, iaa1: 0, |
533 | idef2: 0, CB_IMA(hints))); |
534 | } |
535 | |
536 | static inline void gru_gamerr(void *cb, int exopc, unsigned long src, |
537 | unsigned int xtype, unsigned long operand1, |
538 | unsigned long operand2, unsigned long hints) |
539 | { |
540 | struct gru_instruction *ins = (void *)cb; |
541 | |
542 | ins->baddr0 = (long)src; |
543 | ins->op1_stride = operand1; |
544 | ins->op2_value_baddr1 = operand2; |
545 | gru_start_instruction(ins, op64: __opdword(OP_GAMERR, exopc, xtype, IAA_RAM, iaa1: 0, |
546 | idef2: 0, CB_IMA(hints))); |
547 | } |
548 | |
549 | static inline void gru_gamxr(void *cb, unsigned long src, |
550 | unsigned int tri0, unsigned long hints) |
551 | { |
552 | struct gru_instruction *ins = (void *)cb; |
553 | |
554 | ins->baddr0 = (long)src; |
555 | ins->nelem = 4; |
556 | gru_start_instruction(ins, op64: __opdword(OP_GAMXR, EOP_XR_CSWAP, XTYPE_DW, |
557 | IAA_RAM, iaa1: 0, idef2: 0, CB_IMA(hints))); |
558 | } |
559 | |
560 | static inline void gru_mesq(void *cb, unsigned long queue, |
561 | unsigned long tri0, unsigned long nelem, |
562 | unsigned long hints) |
563 | { |
564 | struct gru_instruction *ins = (void *)cb; |
565 | |
566 | ins->baddr0 = (long)queue; |
567 | ins->nelem = nelem; |
568 | gru_start_instruction(ins, op64: __opdword(OP_MESQ, exopc: 0, XTYPE_CL, IAA_RAM, iaa1: 0, |
569 | idef2: tri0, CB_IMA(hints))); |
570 | } |
571 | |
572 | static inline unsigned long gru_get_amo_value(void *cb) |
573 | { |
574 | struct gru_instruction *ins = (void *)cb; |
575 | |
576 | return ins->avalue; |
577 | } |
578 | |
579 | static inline int gru_get_amo_value_head(void *cb) |
580 | { |
581 | struct gru_instruction *ins = (void *)cb; |
582 | |
583 | return ins->avalue & 0xffffffff; |
584 | } |
585 | |
586 | static inline int gru_get_amo_value_limit(void *cb) |
587 | { |
588 | struct gru_instruction *ins = (void *)cb; |
589 | |
590 | return ins->avalue >> 32; |
591 | } |
592 | |
593 | static inline union gru_mesqhead gru_mesq_head(int head, int limit) |
594 | { |
595 | union gru_mesqhead mqh; |
596 | |
597 | mqh.head = head; |
598 | mqh.limit = limit; |
599 | return mqh; |
600 | } |
601 | |
602 | /* |
603 | * Get struct control_block_extended_exc_detail for CB. |
604 | */ |
605 | extern int gru_get_cb_exception_detail(void *cb, |
606 | struct control_block_extended_exc_detail *excdet); |
607 | |
608 | #define GRU_EXC_STR_SIZE 256 |
609 | |
610 | |
611 | /* |
612 | * Control block definition for checking status |
613 | */ |
614 | struct gru_control_block_status { |
615 | unsigned int icmd :1; |
616 | unsigned int ima :3; |
617 | unsigned int reserved0 :4; |
618 | unsigned int unused1 :24; |
619 | unsigned int unused2 :24; |
620 | unsigned int istatus :2; |
621 | unsigned int isubstatus :4; |
622 | unsigned int unused3 :2; |
623 | }; |
624 | |
625 | /* Get CB status */ |
626 | static inline int gru_get_cb_status(void *cb) |
627 | { |
628 | struct gru_control_block_status *cbs = (void *)cb; |
629 | |
630 | return cbs->istatus; |
631 | } |
632 | |
633 | /* Get CB message queue substatus */ |
634 | static inline int gru_get_cb_message_queue_substatus(void *cb) |
635 | { |
636 | struct gru_control_block_status *cbs = (void *)cb; |
637 | |
638 | return cbs->isubstatus & CBSS_MSG_QUEUE_MASK; |
639 | } |
640 | |
641 | /* Get CB substatus */ |
642 | static inline int gru_get_cb_substatus(void *cb) |
643 | { |
644 | struct gru_control_block_status *cbs = (void *)cb; |
645 | |
646 | return cbs->isubstatus; |
647 | } |
648 | |
649 | /* |
650 | * User interface to check an instruction status. UPM and exceptions |
651 | * are handled automatically. However, this function does NOT wait |
652 | * for an active instruction to complete. |
653 | * |
654 | */ |
655 | static inline int gru_check_status(void *cb) |
656 | { |
657 | struct gru_control_block_status *cbs = (void *)cb; |
658 | int ret; |
659 | |
660 | ret = cbs->istatus; |
661 | if (ret != CBS_ACTIVE) |
662 | ret = gru_check_status_proc(cb); |
663 | return ret; |
664 | } |
665 | |
666 | /* |
667 | * User interface (via inline function) to wait for an instruction |
668 | * to complete. Completion status (IDLE or EXCEPTION is returned |
669 | * to the user. Exception due to hardware errors are automatically |
670 | * retried before returning an exception. |
671 | * |
672 | */ |
673 | static inline int gru_wait(void *cb) |
674 | { |
675 | return gru_wait_proc(cb); |
676 | } |
677 | |
678 | /* |
679 | * Wait for CB to complete. Aborts program if error. (Note: error does NOT |
680 | * mean TLB mis - only fatal errors such as memory parity error or user |
681 | * bugs will cause termination. |
682 | */ |
683 | static inline void gru_wait_abort(void *cb) |
684 | { |
685 | gru_wait_abort_proc(cb); |
686 | } |
687 | |
688 | /* |
689 | * Get a pointer to the start of a gseg |
690 | * p - Any valid pointer within the gseg |
691 | */ |
692 | static inline void *gru_get_gseg_pointer (void *p) |
693 | { |
694 | return (void *)((unsigned long)p & ~(GRU_GSEG_PAGESIZE - 1)); |
695 | } |
696 | |
697 | /* |
698 | * Get a pointer to a control block |
699 | * gseg - GSeg address returned from gru_get_thread_gru_segment() |
700 | * index - index of desired CB |
701 | */ |
702 | static inline void *gru_get_cb_pointer(void *gseg, |
703 | int index) |
704 | { |
705 | return gseg + GRU_CB_BASE + index * GRU_HANDLE_STRIDE; |
706 | } |
707 | |
708 | /* |
709 | * Get a pointer to a cacheline in the data segment portion of a GSeg |
710 | * gseg - GSeg address returned from gru_get_thread_gru_segment() |
711 | * index - index of desired cache line |
712 | */ |
713 | static inline void *gru_get_data_pointer(void *gseg, int index) |
714 | { |
715 | return gseg + GRU_DS_BASE + index * GRU_CACHE_LINE_BYTES; |
716 | } |
717 | |
718 | /* |
719 | * Convert a vaddr into the tri index within the GSEG |
720 | * vaddr - virtual address of within gseg |
721 | */ |
722 | static inline int gru_get_tri(void *vaddr) |
723 | { |
724 | return ((unsigned long)vaddr & (GRU_GSEG_PAGESIZE - 1)) - GRU_DS_BASE; |
725 | } |
726 | #endif /* __GRU_INSTRUCTIONS_H__ */ |
727 | |