1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | /* |
3 | * Amlogic Meson6/Meson8/Meson8b/Meson8m2 SDHC MMC host controller driver. |
4 | * |
5 | * Copyright (C) 2020 Martin Blumenstingl <martin.blumenstingl@googlemail.com> |
6 | */ |
7 | |
8 | #include <linux/clk.h> |
9 | #include <linux/device.h> |
10 | #include <linux/dma-mapping.h> |
11 | #include <linux/interrupt.h> |
12 | #include <linux/iopoll.h> |
13 | #include <linux/module.h> |
14 | #include <linux/of.h> |
15 | #include <linux/platform_device.h> |
16 | #include <linux/property.h> |
17 | #include <linux/regmap.h> |
18 | #include <linux/regulator/consumer.h> |
19 | #include <linux/types.h> |
20 | |
21 | #include <linux/mmc/host.h> |
22 | #include <linux/mmc/mmc.h> |
23 | #include <linux/mmc/sdio.h> |
24 | #include <linux/mmc/slot-gpio.h> |
25 | |
26 | #include "meson-mx-sdhc.h" |
27 | |
28 | #define MESON_SDHC_NUM_BULK_CLKS 4 |
29 | #define MESON_SDHC_MAX_BLK_SIZE 512 |
30 | #define MESON_SDHC_NUM_TUNING_TRIES 10 |
31 | |
32 | #define MESON_SDHC_WAIT_CMD_READY_SLEEP_US 1 |
33 | #define MESON_SDHC_WAIT_CMD_READY_TIMEOUT_US 100000 |
34 | #define MESON_SDHC_WAIT_BEFORE_SEND_SLEEP_US 1 |
35 | #define MESON_SDHC_WAIT_BEFORE_SEND_TIMEOUT_US 200 |
36 | |
37 | struct meson_mx_sdhc_data { |
38 | void (*init_hw)(struct mmc_host *mmc); |
39 | void (*set_pdma)(struct mmc_host *mmc); |
40 | void (*wait_before_send)(struct mmc_host *mmc); |
41 | bool hardware_flush_all_cmds; |
42 | }; |
43 | |
44 | struct meson_mx_sdhc_host { |
45 | struct mmc_host *mmc; |
46 | |
47 | struct mmc_request *mrq; |
48 | struct mmc_command *cmd; |
49 | int error; |
50 | |
51 | struct regmap *regmap; |
52 | |
53 | struct clk *pclk; |
54 | struct clk *sd_clk; |
55 | struct clk_bulk_data bulk_clks[MESON_SDHC_NUM_BULK_CLKS]; |
56 | bool bulk_clks_enabled; |
57 | |
58 | const struct meson_mx_sdhc_data *platform; |
59 | }; |
60 | |
61 | static const struct regmap_config meson_mx_sdhc_regmap_config = { |
62 | .reg_bits = 8, |
63 | .val_bits = 32, |
64 | .reg_stride = 4, |
65 | .max_register = MESON_SDHC_CLK2, |
66 | }; |
67 | |
68 | static void meson_mx_sdhc_reset(struct meson_mx_sdhc_host *host) |
69 | { |
70 | regmap_write(map: host->regmap, MESON_SDHC_SRST, MESON_SDHC_SRST_MAIN_CTRL | |
71 | MESON_SDHC_SRST_RXFIFO | MESON_SDHC_SRST_TXFIFO | |
72 | MESON_SDHC_SRST_DPHY_RX | MESON_SDHC_SRST_DPHY_TX | |
73 | MESON_SDHC_SRST_DMA_IF); |
74 | usleep_range(min: 10, max: 100); |
75 | |
76 | regmap_write(map: host->regmap, MESON_SDHC_SRST, val: 0); |
77 | usleep_range(min: 10, max: 100); |
78 | } |
79 | |
80 | static void meson_mx_sdhc_clear_fifo(struct mmc_host *mmc) |
81 | { |
82 | struct meson_mx_sdhc_host *host = mmc_priv(host: mmc); |
83 | u32 stat; |
84 | |
85 | regmap_read(map: host->regmap, MESON_SDHC_STAT, val: &stat); |
86 | if (!FIELD_GET(MESON_SDHC_STAT_RXFIFO_CNT, stat) && |
87 | !FIELD_GET(MESON_SDHC_STAT_TXFIFO_CNT, stat)) |
88 | return; |
89 | |
90 | regmap_write(map: host->regmap, MESON_SDHC_SRST, MESON_SDHC_SRST_RXFIFO | |
91 | MESON_SDHC_SRST_TXFIFO | MESON_SDHC_SRST_MAIN_CTRL); |
92 | udelay(5); |
93 | |
94 | regmap_read(map: host->regmap, MESON_SDHC_STAT, val: &stat); |
95 | if (FIELD_GET(MESON_SDHC_STAT_RXFIFO_CNT, stat) || |
96 | FIELD_GET(MESON_SDHC_STAT_TXFIFO_CNT, stat)) |
97 | dev_warn(mmc_dev(host->mmc), |
98 | "Failed to clear FIFOs, RX: %lu, TX: %lu\n" , |
99 | FIELD_GET(MESON_SDHC_STAT_RXFIFO_CNT, stat), |
100 | FIELD_GET(MESON_SDHC_STAT_TXFIFO_CNT, stat)); |
101 | } |
102 | |
103 | static void meson_mx_sdhc_wait_cmd_ready(struct mmc_host *mmc) |
104 | { |
105 | struct meson_mx_sdhc_host *host = mmc_priv(host: mmc); |
106 | u32 stat, esta; |
107 | int ret; |
108 | |
109 | ret = regmap_read_poll_timeout(host->regmap, MESON_SDHC_STAT, stat, |
110 | !(stat & MESON_SDHC_STAT_CMD_BUSY), |
111 | MESON_SDHC_WAIT_CMD_READY_SLEEP_US, |
112 | MESON_SDHC_WAIT_CMD_READY_TIMEOUT_US); |
113 | if (ret) { |
114 | dev_warn(mmc_dev(mmc), |
115 | "Failed to poll for CMD_BUSY while processing CMD%d\n" , |
116 | host->cmd->opcode); |
117 | meson_mx_sdhc_reset(host); |
118 | } |
119 | |
120 | ret = regmap_read_poll_timeout(host->regmap, MESON_SDHC_ESTA, esta, |
121 | !(esta & MESON_SDHC_ESTA_11_13), |
122 | MESON_SDHC_WAIT_CMD_READY_SLEEP_US, |
123 | MESON_SDHC_WAIT_CMD_READY_TIMEOUT_US); |
124 | if (ret) { |
125 | dev_warn(mmc_dev(mmc), |
126 | "Failed to poll for ESTA[13:11] while processing CMD%d\n" , |
127 | host->cmd->opcode); |
128 | meson_mx_sdhc_reset(host); |
129 | } |
130 | } |
131 | |
132 | static void meson_mx_sdhc_start_cmd(struct mmc_host *mmc, |
133 | struct mmc_command *cmd) |
134 | { |
135 | struct meson_mx_sdhc_host *host = mmc_priv(host: mmc); |
136 | bool manual_stop = false; |
137 | u32 ictl, send; |
138 | int pack_len; |
139 | |
140 | host->cmd = cmd; |
141 | |
142 | ictl = MESON_SDHC_ICTL_DATA_TIMEOUT | MESON_SDHC_ICTL_DATA_ERR_CRC | |
143 | MESON_SDHC_ICTL_RXFIFO_FULL | MESON_SDHC_ICTL_TXFIFO_EMPTY | |
144 | MESON_SDHC_ICTL_RESP_TIMEOUT | MESON_SDHC_ICTL_RESP_ERR_CRC; |
145 | |
146 | send = FIELD_PREP(MESON_SDHC_SEND_CMD_INDEX, cmd->opcode); |
147 | |
148 | if (cmd->data) { |
149 | send |= MESON_SDHC_SEND_CMD_HAS_DATA; |
150 | send |= FIELD_PREP(MESON_SDHC_SEND_TOTAL_PACK, |
151 | cmd->data->blocks - 1); |
152 | |
153 | if (cmd->data->blksz < MESON_SDHC_MAX_BLK_SIZE) |
154 | pack_len = cmd->data->blksz; |
155 | else |
156 | pack_len = 0; |
157 | |
158 | if (cmd->data->flags & MMC_DATA_WRITE) |
159 | send |= MESON_SDHC_SEND_DATA_DIR; |
160 | |
161 | /* |
162 | * If command with no data, just wait response done |
163 | * interrupt(int[0]), and if command with data transfer, just |
164 | * wait dma done interrupt(int[11]), don't need care about |
165 | * dat0 busy or not. |
166 | */ |
167 | if (host->platform->hardware_flush_all_cmds || |
168 | cmd->data->flags & MMC_DATA_WRITE) |
169 | /* hardware flush: */ |
170 | ictl |= MESON_SDHC_ICTL_DMA_DONE; |
171 | else |
172 | /* software flush: */ |
173 | ictl |= MESON_SDHC_ICTL_DATA_XFER_OK; |
174 | |
175 | /* |
176 | * Mimic the logic from the vendor driver where (only) |
177 | * SD_IO_RW_EXTENDED commands with more than one block set the |
178 | * MESON_SDHC_MISC_MANUAL_STOP bit. This fixes the firmware |
179 | * download in the brcmfmac driver for a BCM43362/1 card. |
180 | * Without this sdio_memcpy_toio() (with a size of 219557 |
181 | * bytes) times out if MESON_SDHC_MISC_MANUAL_STOP is not set. |
182 | */ |
183 | manual_stop = cmd->data->blocks > 1 && |
184 | cmd->opcode == SD_IO_RW_EXTENDED; |
185 | } else { |
186 | pack_len = 0; |
187 | |
188 | ictl |= MESON_SDHC_ICTL_RESP_OK; |
189 | } |
190 | |
191 | regmap_update_bits(map: host->regmap, MESON_SDHC_MISC, |
192 | MESON_SDHC_MISC_MANUAL_STOP, |
193 | val: manual_stop ? MESON_SDHC_MISC_MANUAL_STOP : 0); |
194 | |
195 | if (cmd->opcode == MMC_STOP_TRANSMISSION) |
196 | send |= MESON_SDHC_SEND_DATA_STOP; |
197 | |
198 | if (cmd->flags & MMC_RSP_PRESENT) |
199 | send |= MESON_SDHC_SEND_CMD_HAS_RESP; |
200 | |
201 | if (cmd->flags & MMC_RSP_136) { |
202 | send |= MESON_SDHC_SEND_RESP_LEN; |
203 | send |= MESON_SDHC_SEND_RESP_NO_CRC; |
204 | } |
205 | |
206 | if (!(cmd->flags & MMC_RSP_CRC)) |
207 | send |= MESON_SDHC_SEND_RESP_NO_CRC; |
208 | |
209 | if (cmd->flags & MMC_RSP_BUSY) |
210 | send |= MESON_SDHC_SEND_R1B; |
211 | |
212 | /* enable the new IRQs and mask all pending ones */ |
213 | regmap_write(map: host->regmap, MESON_SDHC_ICTL, val: ictl); |
214 | regmap_write(map: host->regmap, MESON_SDHC_ISTA, MESON_SDHC_ISTA_ALL_IRQS); |
215 | |
216 | regmap_write(map: host->regmap, MESON_SDHC_ARGU, val: cmd->arg); |
217 | |
218 | regmap_update_bits(map: host->regmap, MESON_SDHC_CTRL, |
219 | MESON_SDHC_CTRL_PACK_LEN, |
220 | FIELD_PREP(MESON_SDHC_CTRL_PACK_LEN, pack_len)); |
221 | |
222 | if (cmd->data) |
223 | regmap_write(map: host->regmap, MESON_SDHC_ADDR, |
224 | sg_dma_address(cmd->data->sg)); |
225 | |
226 | meson_mx_sdhc_wait_cmd_ready(mmc); |
227 | |
228 | if (cmd->data) |
229 | host->platform->set_pdma(mmc); |
230 | |
231 | if (host->platform->wait_before_send) |
232 | host->platform->wait_before_send(mmc); |
233 | |
234 | regmap_write(map: host->regmap, MESON_SDHC_SEND, val: send); |
235 | } |
236 | |
237 | static void meson_mx_sdhc_disable_clks(struct mmc_host *mmc) |
238 | { |
239 | struct meson_mx_sdhc_host *host = mmc_priv(host: mmc); |
240 | |
241 | if (!host->bulk_clks_enabled) |
242 | return; |
243 | |
244 | clk_bulk_disable_unprepare(MESON_SDHC_NUM_BULK_CLKS, clks: host->bulk_clks); |
245 | |
246 | host->bulk_clks_enabled = false; |
247 | } |
248 | |
249 | static int meson_mx_sdhc_enable_clks(struct mmc_host *mmc) |
250 | { |
251 | struct meson_mx_sdhc_host *host = mmc_priv(host: mmc); |
252 | int ret; |
253 | |
254 | if (host->bulk_clks_enabled) |
255 | return 0; |
256 | |
257 | ret = clk_bulk_prepare_enable(MESON_SDHC_NUM_BULK_CLKS, |
258 | clks: host->bulk_clks); |
259 | if (ret) |
260 | return ret; |
261 | |
262 | host->bulk_clks_enabled = true; |
263 | |
264 | return 0; |
265 | } |
266 | |
267 | static int meson_mx_sdhc_set_clk(struct mmc_host *mmc, struct mmc_ios *ios) |
268 | { |
269 | struct meson_mx_sdhc_host *host = mmc_priv(host: mmc); |
270 | u32 val, rx_clk_phase; |
271 | int ret; |
272 | |
273 | meson_mx_sdhc_disable_clks(mmc); |
274 | |
275 | if (ios->clock) { |
276 | ret = clk_set_rate(clk: host->sd_clk, rate: ios->clock); |
277 | if (ret) { |
278 | dev_warn(mmc_dev(mmc), |
279 | "Failed to set MMC clock to %uHz: %d\n" , |
280 | ios->clock, host->error); |
281 | return ret; |
282 | } |
283 | |
284 | ret = meson_mx_sdhc_enable_clks(mmc); |
285 | if (ret) |
286 | return ret; |
287 | |
288 | mmc->actual_clock = clk_get_rate(clk: host->sd_clk); |
289 | |
290 | /* |
291 | * Phase 90 should work in most cases. For data transmission, |
292 | * meson_mx_sdhc_execute_tuning() will find a accurate value |
293 | */ |
294 | regmap_read(map: host->regmap, MESON_SDHC_CLKC, val: &val); |
295 | rx_clk_phase = FIELD_GET(MESON_SDHC_CLKC_CLK_DIV, val) / 4; |
296 | regmap_update_bits(map: host->regmap, MESON_SDHC_CLK2, |
297 | MESON_SDHC_CLK2_RX_CLK_PHASE, |
298 | FIELD_PREP(MESON_SDHC_CLK2_RX_CLK_PHASE, |
299 | rx_clk_phase)); |
300 | } else { |
301 | mmc->actual_clock = 0; |
302 | } |
303 | |
304 | return 0; |
305 | } |
306 | |
307 | static void meson_mx_sdhc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) |
308 | { |
309 | struct meson_mx_sdhc_host *host = mmc_priv(host: mmc); |
310 | unsigned short vdd = ios->vdd; |
311 | |
312 | switch (ios->power_mode) { |
313 | case MMC_POWER_OFF: |
314 | vdd = 0; |
315 | fallthrough; |
316 | |
317 | case MMC_POWER_UP: |
318 | if (!IS_ERR(ptr: mmc->supply.vmmc)) { |
319 | host->error = mmc_regulator_set_ocr(mmc, |
320 | supply: mmc->supply.vmmc, |
321 | vdd_bit: vdd); |
322 | if (host->error) |
323 | return; |
324 | } |
325 | |
326 | break; |
327 | |
328 | case MMC_POWER_ON: |
329 | break; |
330 | } |
331 | |
332 | host->error = meson_mx_sdhc_set_clk(mmc, ios); |
333 | if (host->error) |
334 | return; |
335 | |
336 | switch (ios->bus_width) { |
337 | case MMC_BUS_WIDTH_1: |
338 | regmap_update_bits(map: host->regmap, MESON_SDHC_CTRL, |
339 | MESON_SDHC_CTRL_DAT_TYPE, |
340 | FIELD_PREP(MESON_SDHC_CTRL_DAT_TYPE, 0)); |
341 | break; |
342 | |
343 | case MMC_BUS_WIDTH_4: |
344 | regmap_update_bits(map: host->regmap, MESON_SDHC_CTRL, |
345 | MESON_SDHC_CTRL_DAT_TYPE, |
346 | FIELD_PREP(MESON_SDHC_CTRL_DAT_TYPE, 1)); |
347 | break; |
348 | |
349 | case MMC_BUS_WIDTH_8: |
350 | regmap_update_bits(map: host->regmap, MESON_SDHC_CTRL, |
351 | MESON_SDHC_CTRL_DAT_TYPE, |
352 | FIELD_PREP(MESON_SDHC_CTRL_DAT_TYPE, 2)); |
353 | break; |
354 | |
355 | default: |
356 | dev_err(mmc_dev(mmc), "unsupported bus width: %d\n" , |
357 | ios->bus_width); |
358 | host->error = -EINVAL; |
359 | return; |
360 | } |
361 | } |
362 | |
363 | static int meson_mx_sdhc_map_dma(struct mmc_host *mmc, struct mmc_request *mrq) |
364 | { |
365 | struct mmc_data *data = mrq->data; |
366 | unsigned int dma_len; |
367 | |
368 | if (!data) |
369 | return 0; |
370 | |
371 | dma_len = dma_map_sg(mmc_dev(mmc), data->sg, data->sg_len, |
372 | mmc_get_dma_dir(data)); |
373 | if (!dma_len) { |
374 | dev_err(mmc_dev(mmc), "dma_map_sg failed\n" ); |
375 | return -ENOMEM; |
376 | } |
377 | |
378 | return 0; |
379 | } |
380 | |
381 | static void meson_mx_sdhc_request(struct mmc_host *mmc, struct mmc_request *mrq) |
382 | { |
383 | struct meson_mx_sdhc_host *host = mmc_priv(host: mmc); |
384 | struct mmc_command *cmd = mrq->cmd; |
385 | |
386 | if (!host->error) |
387 | host->error = meson_mx_sdhc_map_dma(mmc, mrq); |
388 | |
389 | if (host->error) { |
390 | cmd->error = host->error; |
391 | mmc_request_done(mmc, mrq); |
392 | return; |
393 | } |
394 | |
395 | host->mrq = mrq; |
396 | |
397 | meson_mx_sdhc_start_cmd(mmc, cmd: mrq->cmd); |
398 | } |
399 | |
400 | static int meson_mx_sdhc_card_busy(struct mmc_host *mmc) |
401 | { |
402 | struct meson_mx_sdhc_host *host = mmc_priv(host: mmc); |
403 | u32 stat; |
404 | |
405 | regmap_read(map: host->regmap, MESON_SDHC_STAT, val: &stat); |
406 | return FIELD_GET(MESON_SDHC_STAT_DAT3_0, stat) == 0; |
407 | } |
408 | |
409 | static bool meson_mx_sdhc_tuning_point_matches(struct mmc_host *mmc, |
410 | u32 opcode) |
411 | { |
412 | unsigned int i, num_matches = 0; |
413 | int ret; |
414 | |
415 | for (i = 0; i < MESON_SDHC_NUM_TUNING_TRIES; i++) { |
416 | ret = mmc_send_tuning(host: mmc, opcode, NULL); |
417 | if (!ret) |
418 | num_matches++; |
419 | } |
420 | |
421 | return num_matches == MESON_SDHC_NUM_TUNING_TRIES; |
422 | } |
423 | |
424 | static int meson_mx_sdhc_execute_tuning(struct mmc_host *mmc, u32 opcode) |
425 | { |
426 | struct meson_mx_sdhc_host *host = mmc_priv(host: mmc); |
427 | int div, start, len, best_start, best_len; |
428 | int curr_phase, old_phase, new_phase; |
429 | u32 val; |
430 | |
431 | len = 0; |
432 | start = 0; |
433 | best_len = 0; |
434 | |
435 | regmap_read(map: host->regmap, MESON_SDHC_CLK2, val: &val); |
436 | old_phase = FIELD_GET(MESON_SDHC_CLK2_RX_CLK_PHASE, val); |
437 | |
438 | regmap_read(map: host->regmap, MESON_SDHC_CLKC, val: &val); |
439 | div = FIELD_GET(MESON_SDHC_CLKC_CLK_DIV, val); |
440 | |
441 | for (curr_phase = 0; curr_phase <= div; curr_phase++) { |
442 | regmap_update_bits(map: host->regmap, MESON_SDHC_CLK2, |
443 | MESON_SDHC_CLK2_RX_CLK_PHASE, |
444 | FIELD_PREP(MESON_SDHC_CLK2_RX_CLK_PHASE, |
445 | curr_phase)); |
446 | |
447 | if (meson_mx_sdhc_tuning_point_matches(mmc, opcode)) { |
448 | if (!len) { |
449 | start = curr_phase; |
450 | |
451 | dev_dbg(mmc_dev(mmc), |
452 | "New RX phase window starts at %u\n" , |
453 | start); |
454 | } |
455 | |
456 | len++; |
457 | } else { |
458 | if (len > best_len) { |
459 | best_start = start; |
460 | best_len = len; |
461 | |
462 | dev_dbg(mmc_dev(mmc), |
463 | "New best RX phase window: %u - %u\n" , |
464 | best_start, best_start + best_len); |
465 | } |
466 | |
467 | /* reset the current window */ |
468 | len = 0; |
469 | } |
470 | } |
471 | |
472 | if (len > best_len) |
473 | /* the last window is the best (or possibly only) window */ |
474 | new_phase = start + (len / 2); |
475 | else if (best_len) |
476 | /* there was a better window than the last */ |
477 | new_phase = best_start + (best_len / 2); |
478 | else |
479 | /* no window was found at all, reset to the original phase */ |
480 | new_phase = old_phase; |
481 | |
482 | regmap_update_bits(map: host->regmap, MESON_SDHC_CLK2, |
483 | MESON_SDHC_CLK2_RX_CLK_PHASE, |
484 | FIELD_PREP(MESON_SDHC_CLK2_RX_CLK_PHASE, |
485 | new_phase)); |
486 | |
487 | if (!len && !best_len) |
488 | return -EIO; |
489 | |
490 | dev_dbg(mmc_dev(mmc), "Tuned RX clock phase to %u\n" , new_phase); |
491 | |
492 | return 0; |
493 | } |
494 | |
495 | static const struct mmc_host_ops meson_mx_sdhc_ops = { |
496 | .request = meson_mx_sdhc_request, |
497 | .set_ios = meson_mx_sdhc_set_ios, |
498 | .card_busy = meson_mx_sdhc_card_busy, |
499 | .execute_tuning = meson_mx_sdhc_execute_tuning, |
500 | .get_cd = mmc_gpio_get_cd, |
501 | .get_ro = mmc_gpio_get_ro, |
502 | }; |
503 | |
504 | static void meson_mx_sdhc_request_done(struct meson_mx_sdhc_host *host) |
505 | { |
506 | struct mmc_request *mrq = host->mrq; |
507 | struct mmc_host *mmc = host->mmc; |
508 | |
509 | /* disable interrupts and mask all pending ones */ |
510 | regmap_update_bits(map: host->regmap, MESON_SDHC_ICTL, |
511 | MESON_SDHC_ICTL_ALL_IRQS, val: 0); |
512 | regmap_update_bits(map: host->regmap, MESON_SDHC_ISTA, |
513 | MESON_SDHC_ISTA_ALL_IRQS, MESON_SDHC_ISTA_ALL_IRQS); |
514 | |
515 | host->mrq = NULL; |
516 | host->cmd = NULL; |
517 | |
518 | mmc_request_done(mmc, mrq); |
519 | } |
520 | |
521 | static u32 meson_mx_sdhc_read_response(struct meson_mx_sdhc_host *host, u8 idx) |
522 | { |
523 | u32 val; |
524 | |
525 | regmap_update_bits(map: host->regmap, MESON_SDHC_PDMA, |
526 | MESON_SDHC_PDMA_DMA_MODE, val: 0); |
527 | |
528 | regmap_update_bits(map: host->regmap, MESON_SDHC_PDMA, |
529 | MESON_SDHC_PDMA_PIO_RDRESP, |
530 | FIELD_PREP(MESON_SDHC_PDMA_PIO_RDRESP, idx)); |
531 | |
532 | regmap_read(map: host->regmap, MESON_SDHC_ARGU, val: &val); |
533 | |
534 | return val; |
535 | } |
536 | |
537 | static irqreturn_t meson_mx_sdhc_irq(int irq, void *data) |
538 | { |
539 | struct meson_mx_sdhc_host *host = data; |
540 | struct mmc_command *cmd = host->cmd; |
541 | u32 ictl, ista; |
542 | |
543 | regmap_read(map: host->regmap, MESON_SDHC_ICTL, val: &ictl); |
544 | regmap_read(map: host->regmap, MESON_SDHC_ISTA, val: &ista); |
545 | |
546 | if (!(ictl & ista)) |
547 | return IRQ_NONE; |
548 | |
549 | if (ista & MESON_SDHC_ISTA_RXFIFO_FULL || |
550 | ista & MESON_SDHC_ISTA_TXFIFO_EMPTY) |
551 | cmd->error = -EIO; |
552 | else if (ista & MESON_SDHC_ISTA_RESP_ERR_CRC) |
553 | cmd->error = -EILSEQ; |
554 | else if (ista & MESON_SDHC_ISTA_RESP_TIMEOUT) |
555 | cmd->error = -ETIMEDOUT; |
556 | |
557 | if (cmd->data) { |
558 | if (ista & MESON_SDHC_ISTA_DATA_ERR_CRC) |
559 | cmd->data->error = -EILSEQ; |
560 | else if (ista & MESON_SDHC_ISTA_DATA_TIMEOUT) |
561 | cmd->data->error = -ETIMEDOUT; |
562 | } |
563 | |
564 | if (cmd->error || (cmd->data && cmd->data->error)) |
565 | dev_dbg(mmc_dev(host->mmc), "CMD%d error, ISTA: 0x%08x\n" , |
566 | cmd->opcode, ista); |
567 | |
568 | return IRQ_WAKE_THREAD; |
569 | } |
570 | |
571 | static irqreturn_t meson_mx_sdhc_irq_thread(int irq, void *irq_data) |
572 | { |
573 | struct meson_mx_sdhc_host *host = irq_data; |
574 | struct mmc_command *cmd; |
575 | u32 val; |
576 | |
577 | cmd = host->cmd; |
578 | if (WARN_ON(!cmd)) |
579 | return IRQ_HANDLED; |
580 | |
581 | if (cmd->data && !cmd->data->error) { |
582 | if (!host->platform->hardware_flush_all_cmds && |
583 | cmd->data->flags & MMC_DATA_READ) { |
584 | meson_mx_sdhc_wait_cmd_ready(mmc: host->mmc); |
585 | |
586 | /* |
587 | * If MESON_SDHC_PDMA_RXFIFO_MANUAL_FLUSH was |
588 | * previously 0x1 then it has to be set to 0x3. If it |
589 | * was 0x0 before then it has to be set to 0x2. Without |
590 | * this reading SD cards sometimes transfers garbage, |
591 | * which results in cards not being detected due to: |
592 | * unrecognised SCR structure version <random number> |
593 | */ |
594 | val = FIELD_PREP(MESON_SDHC_PDMA_RXFIFO_MANUAL_FLUSH, |
595 | 2); |
596 | regmap_update_bits(map: host->regmap, MESON_SDHC_PDMA, mask: val, |
597 | val); |
598 | } |
599 | |
600 | dma_unmap_sg(mmc_dev(host->mmc), cmd->data->sg, |
601 | cmd->data->sg_len, mmc_get_dma_dir(cmd->data)); |
602 | |
603 | cmd->data->bytes_xfered = cmd->data->blksz * cmd->data->blocks; |
604 | } |
605 | |
606 | meson_mx_sdhc_wait_cmd_ready(mmc: host->mmc); |
607 | |
608 | if (cmd->flags & MMC_RSP_136) { |
609 | cmd->resp[0] = meson_mx_sdhc_read_response(host, idx: 4); |
610 | cmd->resp[1] = meson_mx_sdhc_read_response(host, idx: 3); |
611 | cmd->resp[2] = meson_mx_sdhc_read_response(host, idx: 2); |
612 | cmd->resp[3] = meson_mx_sdhc_read_response(host, idx: 1); |
613 | } else { |
614 | cmd->resp[0] = meson_mx_sdhc_read_response(host, idx: 0); |
615 | } |
616 | |
617 | if (cmd->error == -EIO || cmd->error == -ETIMEDOUT) |
618 | meson_mx_sdhc_reset(host); |
619 | else if (cmd->data) |
620 | /* |
621 | * Clear the FIFOs after completing data transfers to prevent |
622 | * corrupting data on write access. It's not clear why this is |
623 | * needed (for reads and writes), but it mimics what the BSP |
624 | * kernel did. |
625 | */ |
626 | meson_mx_sdhc_clear_fifo(mmc: host->mmc); |
627 | |
628 | meson_mx_sdhc_request_done(host); |
629 | |
630 | return IRQ_HANDLED; |
631 | } |
632 | |
633 | static void meson_mx_sdhc_init_hw_meson8(struct mmc_host *mmc) |
634 | { |
635 | struct meson_mx_sdhc_host *host = mmc_priv(host: mmc); |
636 | |
637 | regmap_write(map: host->regmap, MESON_SDHC_MISC, |
638 | FIELD_PREP(MESON_SDHC_MISC_TXSTART_THRES, 7) | |
639 | FIELD_PREP(MESON_SDHC_MISC_WCRC_ERR_PATT, 5) | |
640 | FIELD_PREP(MESON_SDHC_MISC_WCRC_OK_PATT, 2)); |
641 | |
642 | regmap_write(map: host->regmap, MESON_SDHC_ENHC, |
643 | FIELD_PREP(MESON_SDHC_ENHC_RXFIFO_TH, 63) | |
644 | MESON_SDHC_ENHC_MESON6_DMA_WR_RESP | |
645 | FIELD_PREP(MESON_SDHC_ENHC_MESON6_RX_TIMEOUT, 255) | |
646 | FIELD_PREP(MESON_SDHC_ENHC_SDIO_IRQ_PERIOD, 12)); |
647 | }; |
648 | |
649 | static void meson_mx_sdhc_set_pdma_meson8(struct mmc_host *mmc) |
650 | { |
651 | struct meson_mx_sdhc_host *host = mmc_priv(host: mmc); |
652 | |
653 | if (host->cmd->data->flags & MMC_DATA_WRITE) |
654 | regmap_update_bits(map: host->regmap, MESON_SDHC_PDMA, |
655 | MESON_SDHC_PDMA_DMA_MODE | |
656 | MESON_SDHC_PDMA_RD_BURST | |
657 | MESON_SDHC_PDMA_TXFIFO_FILL, |
658 | MESON_SDHC_PDMA_DMA_MODE | |
659 | FIELD_PREP(MESON_SDHC_PDMA_RD_BURST, 31) | |
660 | MESON_SDHC_PDMA_TXFIFO_FILL); |
661 | else |
662 | regmap_update_bits(map: host->regmap, MESON_SDHC_PDMA, |
663 | MESON_SDHC_PDMA_DMA_MODE | |
664 | MESON_SDHC_PDMA_RXFIFO_MANUAL_FLUSH, |
665 | MESON_SDHC_PDMA_DMA_MODE | |
666 | FIELD_PREP(MESON_SDHC_PDMA_RXFIFO_MANUAL_FLUSH, |
667 | 1)); |
668 | |
669 | if (host->cmd->data->flags & MMC_DATA_WRITE) |
670 | regmap_update_bits(map: host->regmap, MESON_SDHC_PDMA, |
671 | MESON_SDHC_PDMA_RD_BURST, |
672 | FIELD_PREP(MESON_SDHC_PDMA_RD_BURST, 15)); |
673 | } |
674 | |
675 | static void meson_mx_sdhc_wait_before_send_meson8(struct mmc_host *mmc) |
676 | { |
677 | struct meson_mx_sdhc_host *host = mmc_priv(host: mmc); |
678 | u32 val; |
679 | int ret; |
680 | |
681 | ret = regmap_read_poll_timeout(host->regmap, MESON_SDHC_ESTA, val, |
682 | val == 0, |
683 | MESON_SDHC_WAIT_BEFORE_SEND_SLEEP_US, |
684 | MESON_SDHC_WAIT_BEFORE_SEND_TIMEOUT_US); |
685 | if (ret) |
686 | dev_warn(mmc_dev(mmc), |
687 | "Failed to wait for ESTA to clear: 0x%08x\n" , val); |
688 | |
689 | if (host->cmd->data && host->cmd->data->flags & MMC_DATA_WRITE) { |
690 | ret = regmap_read_poll_timeout(host->regmap, MESON_SDHC_STAT, |
691 | val, val & MESON_SDHC_STAT_TXFIFO_CNT, |
692 | MESON_SDHC_WAIT_BEFORE_SEND_SLEEP_US, |
693 | MESON_SDHC_WAIT_BEFORE_SEND_TIMEOUT_US); |
694 | if (ret) |
695 | dev_warn(mmc_dev(mmc), |
696 | "Failed to wait for TX FIFO to fill\n" ); |
697 | } |
698 | } |
699 | |
700 | static void meson_mx_sdhc_init_hw_meson8m2(struct mmc_host *mmc) |
701 | { |
702 | struct meson_mx_sdhc_host *host = mmc_priv(host: mmc); |
703 | |
704 | regmap_write(map: host->regmap, MESON_SDHC_MISC, |
705 | FIELD_PREP(MESON_SDHC_MISC_TXSTART_THRES, 6) | |
706 | FIELD_PREP(MESON_SDHC_MISC_WCRC_ERR_PATT, 5) | |
707 | FIELD_PREP(MESON_SDHC_MISC_WCRC_OK_PATT, 2)); |
708 | |
709 | regmap_write(map: host->regmap, MESON_SDHC_ENHC, |
710 | FIELD_PREP(MESON_SDHC_ENHC_RXFIFO_TH, 64) | |
711 | FIELD_PREP(MESON_SDHC_ENHC_MESON8M2_DEBUG, 1) | |
712 | MESON_SDHC_ENHC_MESON8M2_WRRSP_MODE | |
713 | FIELD_PREP(MESON_SDHC_ENHC_SDIO_IRQ_PERIOD, 12)); |
714 | } |
715 | |
716 | static void meson_mx_sdhc_set_pdma_meson8m2(struct mmc_host *mmc) |
717 | { |
718 | struct meson_mx_sdhc_host *host = mmc_priv(host: mmc); |
719 | |
720 | regmap_update_bits(map: host->regmap, MESON_SDHC_PDMA, |
721 | MESON_SDHC_PDMA_DMA_MODE, MESON_SDHC_PDMA_DMA_MODE); |
722 | } |
723 | |
724 | static void meson_mx_sdhc_init_hw(struct mmc_host *mmc) |
725 | { |
726 | struct meson_mx_sdhc_host *host = mmc_priv(host: mmc); |
727 | |
728 | meson_mx_sdhc_reset(host); |
729 | |
730 | regmap_write(map: host->regmap, MESON_SDHC_CTRL, |
731 | FIELD_PREP(MESON_SDHC_CTRL_RX_PERIOD, 0xf) | |
732 | FIELD_PREP(MESON_SDHC_CTRL_RX_TIMEOUT, 0x7f) | |
733 | FIELD_PREP(MESON_SDHC_CTRL_RX_ENDIAN, 0x7) | |
734 | FIELD_PREP(MESON_SDHC_CTRL_TX_ENDIAN, 0x7)); |
735 | |
736 | /* |
737 | * start with a valid divider and enable the memory (un-setting |
738 | * MESON_SDHC_CLKC_MEM_PWR_OFF). |
739 | */ |
740 | regmap_write(map: host->regmap, MESON_SDHC_CLKC, MESON_SDHC_CLKC_CLK_DIV); |
741 | |
742 | regmap_write(map: host->regmap, MESON_SDHC_CLK2, |
743 | FIELD_PREP(MESON_SDHC_CLK2_SD_CLK_PHASE, 1)); |
744 | |
745 | regmap_write(map: host->regmap, MESON_SDHC_PDMA, |
746 | MESON_SDHC_PDMA_DMA_URGENT | |
747 | FIELD_PREP(MESON_SDHC_PDMA_WR_BURST, 7) | |
748 | FIELD_PREP(MESON_SDHC_PDMA_TXFIFO_TH, 49) | |
749 | FIELD_PREP(MESON_SDHC_PDMA_RD_BURST, 15) | |
750 | FIELD_PREP(MESON_SDHC_PDMA_RXFIFO_TH, 7)); |
751 | |
752 | /* some initialization bits depend on the SoC: */ |
753 | host->platform->init_hw(mmc); |
754 | |
755 | /* disable and mask all interrupts: */ |
756 | regmap_write(map: host->regmap, MESON_SDHC_ICTL, val: 0); |
757 | regmap_write(map: host->regmap, MESON_SDHC_ISTA, MESON_SDHC_ISTA_ALL_IRQS); |
758 | } |
759 | |
760 | static void meason_mx_mmc_free_host(void *data) |
761 | { |
762 | mmc_free_host(data); |
763 | } |
764 | |
765 | static int meson_mx_sdhc_probe(struct platform_device *pdev) |
766 | { |
767 | struct device *dev = &pdev->dev; |
768 | struct meson_mx_sdhc_host *host; |
769 | struct mmc_host *mmc; |
770 | void __iomem *base; |
771 | int ret, irq; |
772 | |
773 | mmc = mmc_alloc_host(extra: sizeof(*host), dev); |
774 | if (!mmc) |
775 | return -ENOMEM; |
776 | |
777 | ret = devm_add_action_or_reset(dev, meason_mx_mmc_free_host, mmc); |
778 | if (ret) { |
779 | dev_err(dev, "Failed to register mmc_free_host action\n" ); |
780 | return ret; |
781 | } |
782 | |
783 | host = mmc_priv(host: mmc); |
784 | host->mmc = mmc; |
785 | |
786 | platform_set_drvdata(pdev, data: host); |
787 | |
788 | host->platform = device_get_match_data(dev); |
789 | if (!host->platform) |
790 | return -EINVAL; |
791 | |
792 | base = devm_platform_ioremap_resource(pdev, index: 0); |
793 | if (IS_ERR(ptr: base)) |
794 | return PTR_ERR(ptr: base); |
795 | |
796 | host->regmap = devm_regmap_init_mmio(dev, base, |
797 | &meson_mx_sdhc_regmap_config); |
798 | if (IS_ERR(ptr: host->regmap)) |
799 | return PTR_ERR(ptr: host->regmap); |
800 | |
801 | host->pclk = devm_clk_get(dev, id: "pclk" ); |
802 | if (IS_ERR(ptr: host->pclk)) |
803 | return PTR_ERR(ptr: host->pclk); |
804 | |
805 | /* accessing any register requires the module clock to be enabled: */ |
806 | ret = clk_prepare_enable(clk: host->pclk); |
807 | if (ret) { |
808 | dev_err(dev, "Failed to enable 'pclk' clock\n" ); |
809 | return ret; |
810 | } |
811 | |
812 | meson_mx_sdhc_init_hw(mmc); |
813 | |
814 | ret = meson_mx_sdhc_register_clkc(dev, base, clk_bulk_data: host->bulk_clks); |
815 | if (ret) |
816 | goto err_disable_pclk; |
817 | |
818 | host->sd_clk = host->bulk_clks[1].clk; |
819 | |
820 | /* Get regulators and the supported OCR mask */ |
821 | ret = mmc_regulator_get_supply(mmc); |
822 | if (ret) |
823 | goto err_disable_pclk; |
824 | |
825 | mmc->max_req_size = SZ_128K; |
826 | mmc->max_seg_size = mmc->max_req_size; |
827 | mmc->max_blk_count = FIELD_GET(MESON_SDHC_SEND_TOTAL_PACK, ~0); |
828 | mmc->max_blk_size = MESON_SDHC_MAX_BLK_SIZE; |
829 | mmc->max_busy_timeout = 30 * MSEC_PER_SEC; |
830 | mmc->f_min = clk_round_rate(clk: host->sd_clk, rate: 1); |
831 | mmc->f_max = clk_round_rate(clk: host->sd_clk, ULONG_MAX); |
832 | mmc->max_current_180 = 300; |
833 | mmc->max_current_330 = 300; |
834 | mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_HW_RESET; |
835 | mmc->ops = &meson_mx_sdhc_ops; |
836 | |
837 | ret = mmc_of_parse(host: mmc); |
838 | if (ret) |
839 | goto err_disable_pclk; |
840 | |
841 | irq = platform_get_irq(pdev, 0); |
842 | if (irq < 0) { |
843 | ret = irq; |
844 | goto err_disable_pclk; |
845 | } |
846 | |
847 | ret = devm_request_threaded_irq(dev, irq, handler: meson_mx_sdhc_irq, |
848 | thread_fn: meson_mx_sdhc_irq_thread, IRQF_ONESHOT, |
849 | NULL, dev_id: host); |
850 | if (ret) |
851 | goto err_disable_pclk; |
852 | |
853 | ret = mmc_add_host(mmc); |
854 | if (ret) |
855 | goto err_disable_pclk; |
856 | |
857 | return 0; |
858 | |
859 | err_disable_pclk: |
860 | clk_disable_unprepare(clk: host->pclk); |
861 | return ret; |
862 | } |
863 | |
864 | static void meson_mx_sdhc_remove(struct platform_device *pdev) |
865 | { |
866 | struct meson_mx_sdhc_host *host = platform_get_drvdata(pdev); |
867 | |
868 | mmc_remove_host(host->mmc); |
869 | |
870 | meson_mx_sdhc_disable_clks(mmc: host->mmc); |
871 | |
872 | clk_disable_unprepare(clk: host->pclk); |
873 | } |
874 | |
875 | static const struct meson_mx_sdhc_data meson_mx_sdhc_data_meson8 = { |
876 | .init_hw = meson_mx_sdhc_init_hw_meson8, |
877 | .set_pdma = meson_mx_sdhc_set_pdma_meson8, |
878 | .wait_before_send = meson_mx_sdhc_wait_before_send_meson8, |
879 | .hardware_flush_all_cmds = false, |
880 | }; |
881 | |
882 | static const struct meson_mx_sdhc_data meson_mx_sdhc_data_meson8m2 = { |
883 | .init_hw = meson_mx_sdhc_init_hw_meson8m2, |
884 | .set_pdma = meson_mx_sdhc_set_pdma_meson8m2, |
885 | .hardware_flush_all_cmds = true, |
886 | }; |
887 | |
888 | static const struct of_device_id meson_mx_sdhc_of_match[] = { |
889 | { |
890 | .compatible = "amlogic,meson8-sdhc" , |
891 | .data = &meson_mx_sdhc_data_meson8 |
892 | }, |
893 | { |
894 | .compatible = "amlogic,meson8b-sdhc" , |
895 | .data = &meson_mx_sdhc_data_meson8 |
896 | }, |
897 | { |
898 | .compatible = "amlogic,meson8m2-sdhc" , |
899 | .data = &meson_mx_sdhc_data_meson8m2 |
900 | }, |
901 | { /* sentinel */ } |
902 | }; |
903 | MODULE_DEVICE_TABLE(of, meson_mx_sdhc_of_match); |
904 | |
905 | static struct platform_driver meson_mx_sdhc_driver = { |
906 | .probe = meson_mx_sdhc_probe, |
907 | .remove_new = meson_mx_sdhc_remove, |
908 | .driver = { |
909 | .name = "meson-mx-sdhc" , |
910 | .probe_type = PROBE_PREFER_ASYNCHRONOUS, |
911 | .of_match_table = of_match_ptr(meson_mx_sdhc_of_match), |
912 | }, |
913 | }; |
914 | |
915 | module_platform_driver(meson_mx_sdhc_driver); |
916 | |
917 | MODULE_DESCRIPTION("Meson6, Meson8, Meson8b and Meson8m2 SDHC Host Driver" ); |
918 | MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>" ); |
919 | MODULE_LICENSE("GPL v2" ); |
920 | |