1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* |
3 | * Copyright (C) 2005, Intec Automation Inc. |
4 | * Copyright (C) 2014, Freescale Semiconductor, Inc. |
5 | */ |
6 | |
7 | #ifndef __LINUX_MTD_SFDP_H |
8 | #define __LINUX_MTD_SFDP_H |
9 | |
10 | /* SFDP revisions */ |
11 | #define SFDP_JESD216_MAJOR 1 |
12 | #define SFDP_JESD216_MINOR 0 |
13 | #define SFDP_JESD216A_MINOR 5 |
14 | #define SFDP_JESD216B_MINOR 6 |
15 | |
16 | /* SFDP DWORDS are indexed from 1 but C arrays are indexed from 0. */ |
17 | #define SFDP_DWORD(i) ((i) - 1) |
18 | #define SFDP_MASK_CHECK(dword, mask) (((dword) & (mask)) == (mask)) |
19 | |
20 | /* Basic Flash Parameter Table */ |
21 | |
22 | /* JESD216 rev D defines a Basic Flash Parameter Table of 20 DWORDs. */ |
23 | #define BFPT_DWORD_MAX 20 |
24 | |
25 | struct sfdp_bfpt { |
26 | u32 dwords[BFPT_DWORD_MAX]; |
27 | }; |
28 | |
29 | /* The first version of JESD216 defined only 9 DWORDs. */ |
30 | #define BFPT_DWORD_MAX_JESD216 9 |
31 | #define BFPT_DWORD_MAX_JESD216B 16 |
32 | |
33 | /* 1st DWORD. */ |
34 | #define BFPT_DWORD1_FAST_READ_1_1_2 BIT(16) |
35 | #define BFPT_DWORD1_ADDRESS_BYTES_MASK GENMASK(18, 17) |
36 | #define BFPT_DWORD1_ADDRESS_BYTES_3_ONLY (0x0UL << 17) |
37 | #define BFPT_DWORD1_ADDRESS_BYTES_3_OR_4 (0x1UL << 17) |
38 | #define BFPT_DWORD1_ADDRESS_BYTES_4_ONLY (0x2UL << 17) |
39 | #define BFPT_DWORD1_DTR BIT(19) |
40 | #define BFPT_DWORD1_FAST_READ_1_2_2 BIT(20) |
41 | #define BFPT_DWORD1_FAST_READ_1_4_4 BIT(21) |
42 | #define BFPT_DWORD1_FAST_READ_1_1_4 BIT(22) |
43 | |
44 | /* 5th DWORD. */ |
45 | #define BFPT_DWORD5_FAST_READ_2_2_2 BIT(0) |
46 | #define BFPT_DWORD5_FAST_READ_4_4_4 BIT(4) |
47 | |
48 | /* 11th DWORD. */ |
49 | #define BFPT_DWORD11_PAGE_SIZE_SHIFT 4 |
50 | #define BFPT_DWORD11_PAGE_SIZE_MASK GENMASK(7, 4) |
51 | |
52 | /* 15th DWORD. */ |
53 | |
54 | /* |
55 | * (from JESD216 rev B) |
56 | * Quad Enable Requirements (QER): |
57 | * - 000b: Device does not have a QE bit. Device detects 1-1-4 and 1-4-4 |
58 | * reads based on instruction. DQ3/HOLD# functions are hold during |
59 | * instruction phase. |
60 | * - 001b: QE is bit 1 of status register 2. It is set via Write Status with |
61 | * two data bytes where bit 1 of the second byte is one. |
62 | * [...] |
63 | * Writing only one byte to the status register has the side-effect of |
64 | * clearing status register 2, including the QE bit. The 100b code is |
65 | * used if writing one byte to the status register does not modify |
66 | * status register 2. |
67 | * - 010b: QE is bit 6 of status register 1. It is set via Write Status with |
68 | * one data byte where bit 6 is one. |
69 | * [...] |
70 | * - 011b: QE is bit 7 of status register 2. It is set via Write status |
71 | * register 2 instruction 3Eh with one data byte where bit 7 is one. |
72 | * [...] |
73 | * The status register 2 is read using instruction 3Fh. |
74 | * - 100b: QE is bit 1 of status register 2. It is set via Write Status with |
75 | * two data bytes where bit 1 of the second byte is one. |
76 | * [...] |
77 | * In contrast to the 001b code, writing one byte to the status |
78 | * register does not modify status register 2. |
79 | * - 101b: QE is bit 1 of status register 2. Status register 1 is read using |
80 | * Read Status instruction 05h. Status register2 is read using |
81 | * instruction 35h. QE is set via Write Status instruction 01h with |
82 | * two data bytes where bit 1 of the second byte is one. |
83 | * [...] |
84 | */ |
85 | #define BFPT_DWORD15_QER_MASK GENMASK(22, 20) |
86 | #define BFPT_DWORD15_QER_NONE (0x0UL << 20) /* Micron */ |
87 | #define BFPT_DWORD15_QER_SR2_BIT1_BUGGY (0x1UL << 20) |
88 | #define BFPT_DWORD15_QER_SR1_BIT6 (0x2UL << 20) /* Macronix */ |
89 | #define BFPT_DWORD15_QER_SR2_BIT7 (0x3UL << 20) |
90 | #define BFPT_DWORD15_QER_SR2_BIT1_NO_RD (0x4UL << 20) |
91 | #define BFPT_DWORD15_QER_SR2_BIT1 (0x5UL << 20) /* Spansion */ |
92 | |
93 | #define BFPT_DWORD16_EN4B_MASK GENMASK(31, 24) |
94 | #define BFPT_DWORD16_EN4B_ALWAYS_4B BIT(30) |
95 | #define BFPT_DWORD16_EN4B_4B_OPCODES BIT(29) |
96 | #define BFPT_DWORD16_EN4B_16BIT_NV_CR BIT(28) |
97 | #define BFPT_DWORD16_EN4B_BRWR BIT(27) |
98 | #define BFPT_DWORD16_EN4B_WREAR BIT(26) |
99 | #define BFPT_DWORD16_EN4B_WREN_EN4B BIT(25) |
100 | #define BFPT_DWORD16_EN4B_EN4B BIT(24) |
101 | #define BFPT_DWORD16_EX4B_MASK GENMASK(18, 14) |
102 | #define BFPT_DWORD16_EX4B_16BIT_NV_CR BIT(18) |
103 | #define BFPT_DWORD16_EX4B_BRWR BIT(17) |
104 | #define BFPT_DWORD16_EX4B_WREAR BIT(16) |
105 | #define BFPT_DWORD16_EX4B_WREN_EX4B BIT(15) |
106 | #define BFPT_DWORD16_EX4B_EX4B BIT(14) |
107 | #define BFPT_DWORD16_4B_ADDR_MODE_MASK \ |
108 | (BFPT_DWORD16_EN4B_MASK | BFPT_DWORD16_EX4B_MASK) |
109 | #define BFPT_DWORD16_4B_ADDR_MODE_16BIT_NV_CR \ |
110 | (BFPT_DWORD16_EN4B_16BIT_NV_CR | BFPT_DWORD16_EX4B_16BIT_NV_CR) |
111 | #define BFPT_DWORD16_4B_ADDR_MODE_BRWR \ |
112 | (BFPT_DWORD16_EN4B_BRWR | BFPT_DWORD16_EX4B_BRWR) |
113 | #define BFPT_DWORD16_4B_ADDR_MODE_WREAR \ |
114 | (BFPT_DWORD16_EN4B_WREAR | BFPT_DWORD16_EX4B_WREAR) |
115 | #define BFPT_DWORD16_4B_ADDR_MODE_WREN_EN4B_EX4B \ |
116 | (BFPT_DWORD16_EN4B_WREN_EN4B | BFPT_DWORD16_EX4B_WREN_EX4B) |
117 | #define BFPT_DWORD16_4B_ADDR_MODE_EN4B_EX4B \ |
118 | (BFPT_DWORD16_EN4B_EN4B | BFPT_DWORD16_EX4B_EX4B) |
119 | #define BFPT_DWORD16_SWRST_EN_RST BIT(12) |
120 | |
121 | #define BFPT_DWORD18_CMD_EXT_MASK GENMASK(30, 29) |
122 | #define BFPT_DWORD18_CMD_EXT_REP (0x0UL << 29) /* Repeat */ |
123 | #define BFPT_DWORD18_CMD_EXT_INV (0x1UL << 29) /* Invert */ |
124 | #define BFPT_DWORD18_CMD_EXT_RES (0x2UL << 29) /* Reserved */ |
125 | #define BFPT_DWORD18_CMD_EXT_16B (0x3UL << 29) /* 16-bit opcode */ |
126 | |
127 | struct { |
128 | u8 ; |
129 | u8 ; |
130 | u8 ; |
131 | u8 ; /* in double words */ |
132 | u8 [3]; /* byte address */ |
133 | u8 ; |
134 | }; |
135 | |
136 | #endif /* __LINUX_MTD_SFDP_H */ |
137 | |