1 | /* |
2 | * CAN bus driver for Bosch C_CAN controller |
3 | * |
4 | * Copyright (C) 2010 ST Microelectronics |
5 | * Bhupesh Sharma <bhupesh.sharma@st.com> |
6 | * |
7 | * Borrowed heavily from the C_CAN driver originally written by: |
8 | * Copyright (C) 2007 |
9 | * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de> |
10 | * - Simon Kallweit, intefo AG <simon.kallweit@intefo.ch> |
11 | * |
12 | * Bosch C_CAN controller is compliant to CAN protocol version 2.0 part A and B. |
13 | * Bosch C_CAN user manual can be obtained from: |
14 | * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/c_can/ |
15 | * users_manual_c_can.pdf |
16 | * |
17 | * This file is licensed under the terms of the GNU General Public |
18 | * License version 2. This program is licensed "as is" without any |
19 | * warranty of any kind, whether express or implied. |
20 | */ |
21 | |
22 | #ifndef C_CAN_H |
23 | #define C_CAN_H |
24 | |
25 | enum reg { |
26 | C_CAN_CTRL_REG = 0, |
27 | C_CAN_CTRL_EX_REG, |
28 | C_CAN_STS_REG, |
29 | C_CAN_ERR_CNT_REG, |
30 | C_CAN_BTR_REG, |
31 | C_CAN_INT_REG, |
32 | C_CAN_TEST_REG, |
33 | C_CAN_BRPEXT_REG, |
34 | C_CAN_IF1_COMREQ_REG, |
35 | C_CAN_IF1_COMMSK_REG, |
36 | C_CAN_IF1_MASK1_REG, |
37 | C_CAN_IF1_MASK2_REG, |
38 | C_CAN_IF1_ARB1_REG, |
39 | C_CAN_IF1_ARB2_REG, |
40 | C_CAN_IF1_MSGCTRL_REG, |
41 | C_CAN_IF1_DATA1_REG, |
42 | C_CAN_IF1_DATA2_REG, |
43 | C_CAN_IF1_DATA3_REG, |
44 | C_CAN_IF1_DATA4_REG, |
45 | C_CAN_IF2_COMREQ_REG, |
46 | C_CAN_IF2_COMMSK_REG, |
47 | C_CAN_IF2_MASK1_REG, |
48 | C_CAN_IF2_MASK2_REG, |
49 | C_CAN_IF2_ARB1_REG, |
50 | C_CAN_IF2_ARB2_REG, |
51 | C_CAN_IF2_MSGCTRL_REG, |
52 | C_CAN_IF2_DATA1_REG, |
53 | C_CAN_IF2_DATA2_REG, |
54 | C_CAN_IF2_DATA3_REG, |
55 | C_CAN_IF2_DATA4_REG, |
56 | C_CAN_TXRQST1_REG, |
57 | C_CAN_TXRQST2_REG, |
58 | C_CAN_NEWDAT1_REG, |
59 | C_CAN_NEWDAT2_REG, |
60 | C_CAN_INTPND1_REG, |
61 | C_CAN_INTPND2_REG, |
62 | C_CAN_INTPND3_REG, |
63 | C_CAN_MSGVAL1_REG, |
64 | C_CAN_MSGVAL2_REG, |
65 | C_CAN_FUNCTION_REG, |
66 | }; |
67 | |
68 | static const u16 __maybe_unused reg_map_c_can[] = { |
69 | [C_CAN_CTRL_REG] = 0x00, |
70 | [C_CAN_STS_REG] = 0x02, |
71 | [C_CAN_ERR_CNT_REG] = 0x04, |
72 | [C_CAN_BTR_REG] = 0x06, |
73 | [C_CAN_INT_REG] = 0x08, |
74 | [C_CAN_TEST_REG] = 0x0A, |
75 | [C_CAN_BRPEXT_REG] = 0x0C, |
76 | [C_CAN_IF1_COMREQ_REG] = 0x10, |
77 | [C_CAN_IF1_COMMSK_REG] = 0x12, |
78 | [C_CAN_IF1_MASK1_REG] = 0x14, |
79 | [C_CAN_IF1_MASK2_REG] = 0x16, |
80 | [C_CAN_IF1_ARB1_REG] = 0x18, |
81 | [C_CAN_IF1_ARB2_REG] = 0x1A, |
82 | [C_CAN_IF1_MSGCTRL_REG] = 0x1C, |
83 | [C_CAN_IF1_DATA1_REG] = 0x1E, |
84 | [C_CAN_IF1_DATA2_REG] = 0x20, |
85 | [C_CAN_IF1_DATA3_REG] = 0x22, |
86 | [C_CAN_IF1_DATA4_REG] = 0x24, |
87 | [C_CAN_IF2_COMREQ_REG] = 0x40, |
88 | [C_CAN_IF2_COMMSK_REG] = 0x42, |
89 | [C_CAN_IF2_MASK1_REG] = 0x44, |
90 | [C_CAN_IF2_MASK2_REG] = 0x46, |
91 | [C_CAN_IF2_ARB1_REG] = 0x48, |
92 | [C_CAN_IF2_ARB2_REG] = 0x4A, |
93 | [C_CAN_IF2_MSGCTRL_REG] = 0x4C, |
94 | [C_CAN_IF2_DATA1_REG] = 0x4E, |
95 | [C_CAN_IF2_DATA2_REG] = 0x50, |
96 | [C_CAN_IF2_DATA3_REG] = 0x52, |
97 | [C_CAN_IF2_DATA4_REG] = 0x54, |
98 | [C_CAN_TXRQST1_REG] = 0x80, |
99 | [C_CAN_TXRQST2_REG] = 0x82, |
100 | [C_CAN_NEWDAT1_REG] = 0x90, |
101 | [C_CAN_NEWDAT2_REG] = 0x92, |
102 | [C_CAN_INTPND1_REG] = 0xA0, |
103 | [C_CAN_INTPND2_REG] = 0xA2, |
104 | [C_CAN_MSGVAL1_REG] = 0xB0, |
105 | [C_CAN_MSGVAL2_REG] = 0xB2, |
106 | }; |
107 | |
108 | static const u16 __maybe_unused reg_map_d_can[] = { |
109 | [C_CAN_CTRL_REG] = 0x00, |
110 | [C_CAN_CTRL_EX_REG] = 0x02, |
111 | [C_CAN_STS_REG] = 0x04, |
112 | [C_CAN_ERR_CNT_REG] = 0x08, |
113 | [C_CAN_BTR_REG] = 0x0C, |
114 | [C_CAN_BRPEXT_REG] = 0x0E, |
115 | [C_CAN_INT_REG] = 0x10, |
116 | [C_CAN_TEST_REG] = 0x14, |
117 | [C_CAN_FUNCTION_REG] = 0x18, |
118 | [C_CAN_TXRQST1_REG] = 0x88, |
119 | [C_CAN_TXRQST2_REG] = 0x8A, |
120 | [C_CAN_NEWDAT1_REG] = 0x9C, |
121 | [C_CAN_NEWDAT2_REG] = 0x9E, |
122 | [C_CAN_INTPND1_REG] = 0xB0, |
123 | [C_CAN_INTPND2_REG] = 0xB2, |
124 | [C_CAN_INTPND3_REG] = 0xB4, |
125 | [C_CAN_MSGVAL1_REG] = 0xC4, |
126 | [C_CAN_MSGVAL2_REG] = 0xC6, |
127 | [C_CAN_IF1_COMREQ_REG] = 0x100, |
128 | [C_CAN_IF1_COMMSK_REG] = 0x102, |
129 | [C_CAN_IF1_MASK1_REG] = 0x104, |
130 | [C_CAN_IF1_MASK2_REG] = 0x106, |
131 | [C_CAN_IF1_ARB1_REG] = 0x108, |
132 | [C_CAN_IF1_ARB2_REG] = 0x10A, |
133 | [C_CAN_IF1_MSGCTRL_REG] = 0x10C, |
134 | [C_CAN_IF1_DATA1_REG] = 0x110, |
135 | [C_CAN_IF1_DATA2_REG] = 0x112, |
136 | [C_CAN_IF1_DATA3_REG] = 0x114, |
137 | [C_CAN_IF1_DATA4_REG] = 0x116, |
138 | [C_CAN_IF2_COMREQ_REG] = 0x120, |
139 | [C_CAN_IF2_COMMSK_REG] = 0x122, |
140 | [C_CAN_IF2_MASK1_REG] = 0x124, |
141 | [C_CAN_IF2_MASK2_REG] = 0x126, |
142 | [C_CAN_IF2_ARB1_REG] = 0x128, |
143 | [C_CAN_IF2_ARB2_REG] = 0x12A, |
144 | [C_CAN_IF2_MSGCTRL_REG] = 0x12C, |
145 | [C_CAN_IF2_DATA1_REG] = 0x130, |
146 | [C_CAN_IF2_DATA2_REG] = 0x132, |
147 | [C_CAN_IF2_DATA3_REG] = 0x134, |
148 | [C_CAN_IF2_DATA4_REG] = 0x136, |
149 | }; |
150 | |
151 | enum c_can_dev_id { |
152 | BOSCH_C_CAN, |
153 | BOSCH_D_CAN, |
154 | }; |
155 | |
156 | struct raminit_bits { |
157 | u8 start; |
158 | u8 done; |
159 | }; |
160 | |
161 | struct c_can_driver_data { |
162 | enum c_can_dev_id id; |
163 | unsigned int msg_obj_num; |
164 | |
165 | /* RAMINIT register description. Optional. */ |
166 | const struct raminit_bits *raminit_bits; /* Array of START/DONE bit positions */ |
167 | u8 raminit_num; /* Number of CAN instances on the SoC */ |
168 | bool raminit_pulse; /* If set, sets and clears START bit (pulse) */ |
169 | }; |
170 | |
171 | /* Out of band RAMINIT register access via syscon regmap */ |
172 | struct c_can_raminit { |
173 | struct regmap *syscon; /* for raminit ctrl. reg. access */ |
174 | unsigned int reg; /* register index within syscon */ |
175 | struct raminit_bits bits; |
176 | bool needs_pulse; |
177 | }; |
178 | |
179 | /* c_can tx ring structure */ |
180 | struct c_can_tx_ring { |
181 | unsigned int head; |
182 | unsigned int tail; |
183 | unsigned int obj_num; |
184 | }; |
185 | |
186 | /* c_can private data structure */ |
187 | struct c_can_priv { |
188 | struct can_priv can; /* must be the first member */ |
189 | struct napi_struct napi; |
190 | struct net_device *dev; |
191 | struct device *device; |
192 | unsigned int msg_obj_num; |
193 | unsigned int msg_obj_rx_num; |
194 | unsigned int msg_obj_tx_num; |
195 | unsigned int msg_obj_rx_first; |
196 | unsigned int msg_obj_rx_last; |
197 | unsigned int msg_obj_tx_first; |
198 | unsigned int msg_obj_tx_last; |
199 | u32 msg_obj_rx_mask; |
200 | atomic_t sie_pending; |
201 | unsigned long tx_dir; |
202 | int last_status; |
203 | struct c_can_tx_ring tx; |
204 | u16 (*read_reg)(const struct c_can_priv *priv, enum reg index); |
205 | void (*write_reg)(const struct c_can_priv *priv, enum reg index, u16 val); |
206 | u32 (*read_reg32)(const struct c_can_priv *priv, enum reg index); |
207 | void (*write_reg32)(const struct c_can_priv *priv, enum reg index, u32 val); |
208 | void __iomem *base; |
209 | const u16 *regs; |
210 | enum c_can_dev_id type; |
211 | struct c_can_raminit raminit_sys; /* RAMINIT via syscon regmap */ |
212 | void (*raminit)(const struct c_can_priv *priv, bool enable); |
213 | u32 comm_rcv_high; |
214 | }; |
215 | |
216 | struct net_device *alloc_c_can_dev(int msg_obj_num); |
217 | void free_c_can_dev(struct net_device *dev); |
218 | int register_c_can_dev(struct net_device *dev); |
219 | void unregister_c_can_dev(struct net_device *dev); |
220 | |
221 | #ifdef CONFIG_PM |
222 | int c_can_power_up(struct net_device *dev); |
223 | int c_can_power_down(struct net_device *dev); |
224 | #endif |
225 | |
226 | extern const struct ethtool_ops c_can_ethtool_ops; |
227 | |
228 | static inline u8 c_can_get_tx_head(const struct c_can_tx_ring *ring) |
229 | { |
230 | return ring->head & (ring->obj_num - 1); |
231 | } |
232 | |
233 | static inline u8 c_can_get_tx_tail(const struct c_can_tx_ring *ring) |
234 | { |
235 | return ring->tail & (ring->obj_num - 1); |
236 | } |
237 | |
238 | static inline u8 c_can_get_tx_free(const struct c_can_priv *priv, |
239 | const struct c_can_tx_ring *ring) |
240 | { |
241 | u8 head = c_can_get_tx_head(ring); |
242 | u8 tail = c_can_get_tx_tail(ring); |
243 | |
244 | if (priv->type == BOSCH_D_CAN) |
245 | return ring->obj_num - (ring->head - ring->tail); |
246 | |
247 | /* This is not a FIFO. C/D_CAN sends out the buffers |
248 | * prioritized. The lowest buffer number wins. |
249 | */ |
250 | if (head < tail) |
251 | return 0; |
252 | |
253 | return ring->obj_num - head; |
254 | } |
255 | |
256 | #endif /* C_CAN_H */ |
257 | |