1	// SPDX-License-Identifier: GPL-2.0
2	// CAN bus driver for Bosch M_CAN controller
3	// Copyright (C) 2014 Freescale Semiconductor, Inc.
4	// Dong Aisheng <b29396@freescale.com>
5	// Copyright (C) 2018-19 Texas Instruments Incorporated - http://www.ti.com/
6
7	/* Bosch M_CAN user manual can be obtained from:
8	* https://github.com/linux-can/can-doc/tree/master/m_can
9	*/
10
11	#include <linux/bitfield.h>
12	#include <linux/can/dev.h>
13	#include <linux/ethtool.h>
14	#include <linux/hrtimer.h>
15	#include <linux/interrupt.h>
16	#include <linux/io.h>
17	#include <linux/iopoll.h>
18	#include <linux/kernel.h>
19	#include <linux/module.h>
20	#include <linux/netdevice.h>
21	#include <linux/of.h>
22	#include <linux/phy/phy.h>
23	#include <linux/pinctrl/consumer.h>
24	#include <linux/platform_device.h>
25	#include <linux/pm_runtime.h>
26
27	#include "m_can.h"
28
29	/* registers definition */
30	enum m_can_reg {
31	M_CAN_CREL = 0x0,
32	M_CAN_ENDN = 0x4,
33	M_CAN_CUST = 0x8,
34	M_CAN_DBTP = 0xc,
35	M_CAN_TEST = 0x10,
36	M_CAN_RWD = 0x14,
37	M_CAN_CCCR = 0x18,
38	M_CAN_NBTP = 0x1c,
39	M_CAN_TSCC = 0x20,
40	M_CAN_TSCV = 0x24,
41	M_CAN_TOCC = 0x28,
42	M_CAN_TOCV = 0x2c,
43	M_CAN_ECR = 0x40,
44	M_CAN_PSR = 0x44,
45	/* TDCR Register only available for version >=3.1.x */
46	M_CAN_TDCR = 0x48,
47	M_CAN_IR = 0x50,
48	M_CAN_IE = 0x54,
49	M_CAN_ILS = 0x58,
50	M_CAN_ILE = 0x5c,
51	M_CAN_GFC = 0x80,
52	M_CAN_SIDFC = 0x84,
53	M_CAN_XIDFC = 0x88,
54	M_CAN_XIDAM = 0x90,
55	M_CAN_HPMS = 0x94,
56	M_CAN_NDAT1 = 0x98,
57	M_CAN_NDAT2 = 0x9c,
58	M_CAN_RXF0C = 0xa0,
59	M_CAN_RXF0S = 0xa4,
60	M_CAN_RXF0A = 0xa8,
61	M_CAN_RXBC = 0xac,
62	M_CAN_RXF1C = 0xb0,
63	M_CAN_RXF1S = 0xb4,
64	M_CAN_RXF1A = 0xb8,
65	M_CAN_RXESC = 0xbc,
66	M_CAN_TXBC = 0xc0,
67	M_CAN_TXFQS = 0xc4,
68	M_CAN_TXESC = 0xc8,
69	M_CAN_TXBRP = 0xcc,
70	M_CAN_TXBAR = 0xd0,
71	M_CAN_TXBCR = 0xd4,
72	M_CAN_TXBTO = 0xd8,
73	M_CAN_TXBCF = 0xdc,
74	M_CAN_TXBTIE = 0xe0,
75	M_CAN_TXBCIE = 0xe4,
76	M_CAN_TXEFC = 0xf0,
77	M_CAN_TXEFS = 0xf4,
78	M_CAN_TXEFA = 0xf8,
79	};
80
81	/* message ram configuration data length */
82	#define MRAM_CFG_LEN 8
83
84	/* Core Release Register (CREL) */
85	#define CREL_REL_MASK GENMASK(31, 28)
86	#define CREL_STEP_MASK GENMASK(27, 24)
87	#define CREL_SUBSTEP_MASK GENMASK(23, 20)
88
89	/* Data Bit Timing & Prescaler Register (DBTP) */
90	#define DBTP_TDC BIT(23)
91	#define DBTP_DBRP_MASK GENMASK(20, 16)
92	#define DBTP_DTSEG1_MASK GENMASK(12, 8)
93	#define DBTP_DTSEG2_MASK GENMASK(7, 4)
94	#define DBTP_DSJW_MASK GENMASK(3, 0)
95
96	/* Transmitter Delay Compensation Register (TDCR) */
97	#define TDCR_TDCO_MASK GENMASK(14, 8)
98	#define TDCR_TDCF_MASK GENMASK(6, 0)
99
100	/* Test Register (TEST) */
101	#define TEST_LBCK BIT(4)
102
103	/* CC Control Register (CCCR) */
104	#define CCCR_TXP BIT(14)
105	#define CCCR_TEST BIT(7)
106	#define CCCR_DAR BIT(6)
107	#define CCCR_MON BIT(5)
108	#define CCCR_CSR BIT(4)
109	#define CCCR_CSA BIT(3)
110	#define CCCR_ASM BIT(2)
111	#define CCCR_CCE BIT(1)
112	#define CCCR_INIT BIT(0)
113	/* for version 3.0.x */
114	#define CCCR_CMR_MASK GENMASK(11, 10)
115	#define CCCR_CMR_CANFD 0x1
116	#define CCCR_CMR_CANFD_BRS 0x2
117	#define CCCR_CMR_CAN 0x3
118	#define CCCR_CME_MASK GENMASK(9, 8)
119	#define CCCR_CME_CAN 0
120	#define CCCR_CME_CANFD 0x1
121	#define CCCR_CME_CANFD_BRS 0x2
122	/* for version >=3.1.x */
123	#define CCCR_EFBI BIT(13)
124	#define CCCR_PXHD BIT(12)
125	#define CCCR_BRSE BIT(9)
126	#define CCCR_FDOE BIT(8)
127	/* for version >=3.2.x */
128	#define CCCR_NISO BIT(15)
129	/* for version >=3.3.x */
130	#define CCCR_WMM BIT(11)
131	#define CCCR_UTSU BIT(10)
132
133	/* Nominal Bit Timing & Prescaler Register (NBTP) */
134	#define NBTP_NSJW_MASK GENMASK(31, 25)
135	#define NBTP_NBRP_MASK GENMASK(24, 16)
136	#define NBTP_NTSEG1_MASK GENMASK(15, 8)
137	#define NBTP_NTSEG2_MASK GENMASK(6, 0)
138
139	/* Timestamp Counter Configuration Register (TSCC) */
140	#define TSCC_TCP_MASK GENMASK(19, 16)
141	#define TSCC_TSS_MASK GENMASK(1, 0)
142	#define TSCC_TSS_DISABLE 0x0
143	#define TSCC_TSS_INTERNAL 0x1
144	#define TSCC_TSS_EXTERNAL 0x2
145
146	/* Timestamp Counter Value Register (TSCV) */
147	#define TSCV_TSC_MASK GENMASK(15, 0)
148
149	/* Error Counter Register (ECR) */
150	#define ECR_RP BIT(15)
151	#define ECR_REC_MASK GENMASK(14, 8)
152	#define ECR_TEC_MASK GENMASK(7, 0)
153
154	/* Protocol Status Register (PSR) */
155	#define PSR_BO BIT(7)
156	#define PSR_EW BIT(6)
157	#define PSR_EP BIT(5)
158	#define PSR_LEC_MASK GENMASK(2, 0)
159	#define PSR_DLEC_MASK GENMASK(10, 8)
160
161	/* Interrupt Register (IR) */
162	#define IR_ALL_INT 0xffffffff
163
164	/* Renamed bits for versions > 3.1.x */
165	#define IR_ARA BIT(29)
166	#define IR_PED BIT(28)
167	#define IR_PEA BIT(27)
168
169	/* Bits for version 3.0.x */
170	#define IR_STE BIT(31)
171	#define IR_FOE BIT(30)
172	#define IR_ACKE BIT(29)
173	#define IR_BE BIT(28)
174	#define IR_CRCE BIT(27)
175	#define IR_WDI BIT(26)
176	#define IR_BO BIT(25)
177	#define IR_EW BIT(24)
178	#define IR_EP BIT(23)
179	#define IR_ELO BIT(22)
180	#define IR_BEU BIT(21)
181	#define IR_BEC BIT(20)
182	#define IR_DRX BIT(19)
183	#define IR_TOO BIT(18)
184	#define IR_MRAF BIT(17)
185	#define IR_TSW BIT(16)
186	#define IR_TEFL BIT(15)
187	#define IR_TEFF BIT(14)
188	#define IR_TEFW BIT(13)
189	#define IR_TEFN BIT(12)
190	#define IR_TFE BIT(11)
191	#define IR_TCF BIT(10)
192	#define IR_TC BIT(9)
193	#define IR_HPM BIT(8)
194	#define IR_RF1L BIT(7)
195	#define IR_RF1F BIT(6)
196	#define IR_RF1W BIT(5)
197	#define IR_RF1N BIT(4)
198	#define IR_RF0L BIT(3)
199	#define IR_RF0F BIT(2)
200	#define IR_RF0W BIT(1)
201	#define IR_RF0N BIT(0)
202	#define IR_ERR_STATE (IR_BO | IR_EW | IR_EP)
203
204	/* Interrupts for version 3.0.x */
205	#define IR_ERR_LEC_30X (IR_STE | IR_FOE | IR_ACKE | IR_BE | IR_CRCE)
206	#define IR_ERR_BUS_30X (IR_ERR_LEC_30X | IR_WDI | IR_BEU | IR_BEC | \
207	IR_TOO | IR_MRAF | IR_TSW | IR_TEFL | IR_RF1L | \
208	IR_RF0L)
209	#define IR_ERR_ALL_30X (IR_ERR_STATE | IR_ERR_BUS_30X)
210
211	/* Interrupts for version >= 3.1.x */
212	#define IR_ERR_LEC_31X (IR_PED | IR_PEA)
213	#define IR_ERR_BUS_31X (IR_ERR_LEC_31X | IR_WDI | IR_BEU | IR_BEC | \
214	IR_TOO | IR_MRAF | IR_TSW | IR_TEFL | IR_RF1L | \
215	IR_RF0L)
216	#define IR_ERR_ALL_31X (IR_ERR_STATE | IR_ERR_BUS_31X)
217
218	/* Interrupt Line Select (ILS) */
219	#define ILS_ALL_INT0 0x0
220	#define ILS_ALL_INT1 0xFFFFFFFF
221
222	/* Interrupt Line Enable (ILE) */
223	#define ILE_EINT1 BIT(1)
224	#define ILE_EINT0 BIT(0)
225
226	/* Rx FIFO 0/1 Configuration (RXF0C/RXF1C) */
227	#define RXFC_FWM_MASK GENMASK(30, 24)
228	#define RXFC_FS_MASK GENMASK(22, 16)
229
230	/* Rx FIFO 0/1 Status (RXF0S/RXF1S) */
231	#define RXFS_RFL BIT(25)
232	#define RXFS_FF BIT(24)
233	#define RXFS_FPI_MASK GENMASK(21, 16)
234	#define RXFS_FGI_MASK GENMASK(13, 8)
235	#define RXFS_FFL_MASK GENMASK(6, 0)
236
237	/* Rx Buffer / FIFO Element Size Configuration (RXESC) */
238	#define RXESC_RBDS_MASK GENMASK(10, 8)
239	#define RXESC_F1DS_MASK GENMASK(6, 4)
240	#define RXESC_F0DS_MASK GENMASK(2, 0)
241	#define RXESC_64B 0x7
242
243	/* Tx Buffer Configuration (TXBC) */
244	#define TXBC_TFQS_MASK GENMASK(29, 24)
245	#define TXBC_NDTB_MASK GENMASK(21, 16)
246
247	/* Tx FIFO/Queue Status (TXFQS) */
248	#define TXFQS_TFQF BIT(21)
249	#define TXFQS_TFQPI_MASK GENMASK(20, 16)
250	#define TXFQS_TFGI_MASK GENMASK(12, 8)
251	#define TXFQS_TFFL_MASK GENMASK(5, 0)
252
253	/* Tx Buffer Element Size Configuration (TXESC) */
254	#define TXESC_TBDS_MASK GENMASK(2, 0)
255	#define TXESC_TBDS_64B 0x7
256
257	/* Tx Event FIFO Configuration (TXEFC) */
258	#define TXEFC_EFWM_MASK GENMASK(29, 24)
259	#define TXEFC_EFS_MASK GENMASK(21, 16)
260
261	/* Tx Event FIFO Status (TXEFS) */
262	#define TXEFS_TEFL BIT(25)
263	#define TXEFS_EFF BIT(24)
264	#define TXEFS_EFGI_MASK GENMASK(12, 8)
265	#define TXEFS_EFFL_MASK GENMASK(5, 0)
266
267	/* Tx Event FIFO Acknowledge (TXEFA) */
268	#define TXEFA_EFAI_MASK GENMASK(4, 0)
269
270	/* Message RAM Configuration (in bytes) */
271	#define SIDF_ELEMENT_SIZE 4
272	#define XIDF_ELEMENT_SIZE 8
273	#define RXF0_ELEMENT_SIZE 72
274	#define RXF1_ELEMENT_SIZE 72
275	#define RXB_ELEMENT_SIZE 72
276	#define TXE_ELEMENT_SIZE 8
277	#define TXB_ELEMENT_SIZE 72
278
279	/* Message RAM Elements */
280	#define M_CAN_FIFO_ID 0x0
281	#define M_CAN_FIFO_DLC 0x4
282	#define M_CAN_FIFO_DATA 0x8
283
284	/* Rx Buffer Element */
285	/* R0 */
286	#define RX_BUF_ESI BIT(31)
287	#define RX_BUF_XTD BIT(30)
288	#define RX_BUF_RTR BIT(29)
289	/* R1 */
290	#define RX_BUF_ANMF BIT(31)
291	#define RX_BUF_FDF BIT(21)
292	#define RX_BUF_BRS BIT(20)
293	#define RX_BUF_RXTS_MASK GENMASK(15, 0)
294
295	/* Tx Buffer Element */
296	/* T0 */
297	#define TX_BUF_ESI BIT(31)
298	#define TX_BUF_XTD BIT(30)
299	#define TX_BUF_RTR BIT(29)
300	/* T1 */
301	#define TX_BUF_EFC BIT(23)
302	#define TX_BUF_FDF BIT(21)
303	#define TX_BUF_BRS BIT(20)
304	#define TX_BUF_MM_MASK GENMASK(31, 24)
305	#define TX_BUF_DLC_MASK GENMASK(19, 16)
306
307	/* Tx event FIFO Element */
308	/* E1 */
309	#define TX_EVENT_MM_MASK GENMASK(31, 24)
310	#define TX_EVENT_TXTS_MASK GENMASK(15, 0)
311
312	/* Hrtimer polling interval */
313	#define HRTIMER_POLL_INTERVAL_MS 1
314
315	/* The ID and DLC registers are adjacent in M_CAN FIFO memory,
316	* and we can save a (potentially slow) bus round trip by combining
317	* reads and writes to them.
318	*/
319	struct id_and_dlc {
320	u32 id;
321	u32 dlc;
322	};
323
324	struct m_can_fifo_element {
325	u32 id;
326	u32 dlc;
327	u8 data[CANFD_MAX_DLEN];
328	};
329
330	static inline u32 m_can_read(struct m_can_classdev *cdev, enum m_can_reg reg)
331	{
332	return cdev->ops->read_reg(cdev, reg);
333	}
334
335	static inline void m_can_write(struct m_can_classdev *cdev, enum m_can_reg reg,
336	u32 val)
337	{
338	cdev->ops->write_reg(cdev, reg, val);
339	}
340
341	static int
342	m_can_fifo_read(struct m_can_classdev *cdev,
343	u32 fgi, unsigned int offset, void *val, size_t val_count)
344	{
345	u32 addr_offset = cdev->mcfg[MRAM_RXF0].off + fgi * RXF0_ELEMENT_SIZE +
346	offset;
347
348	if (val_count == 0)
349	return 0;
350
351	return cdev->ops->read_fifo(cdev, addr_offset, val, val_count);
352	}
353
354	static int
355	m_can_fifo_write(struct m_can_classdev *cdev,
356	u32 fpi, unsigned int offset, const void *val, size_t val_count)
357	{
358	u32 addr_offset = cdev->mcfg[MRAM_TXB].off + fpi * TXB_ELEMENT_SIZE +
359	offset;
360
361	if (val_count == 0)
362	return 0;
363
364	return cdev->ops->write_fifo(cdev, addr_offset, val, val_count);
365	}
366
367	static inline int m_can_fifo_write_no_off(struct m_can_classdev *cdev,
368	u32 fpi, u32 val)
369	{
370	return cdev->ops->write_fifo(cdev, fpi, &val, 1);
371	}
372
373	static int
374	m_can_txe_fifo_read(struct m_can_classdev *cdev, u32 fgi, u32 offset, u32 *val)
375	{
376	u32 addr_offset = cdev->mcfg[MRAM_TXE].off + fgi * TXE_ELEMENT_SIZE +
377	offset;
378
379	return cdev->ops->read_fifo(cdev, addr_offset, val, 1);
380	}
381
382	static void m_can_config_endisable(struct m_can_classdev *cdev, bool enable)
383	{
384	u32 cccr = m_can_read(cdev, reg: M_CAN_CCCR);
385	u32 timeout = 10;
386	u32 val = 0;
387
388	/* Clear the Clock stop request if it was set */
389	if (cccr & CCCR_CSR)
390	cccr &= ~CCCR_CSR;
391
392	if (enable) {
393	/* enable m_can configuration */
394	m_can_write(cdev, reg: M_CAN_CCCR, val: cccr | CCCR_INIT);
395	udelay(5);
396	/* CCCR.CCE can only be set/reset while CCCR.INIT = '1' */
397	m_can_write(cdev, reg: M_CAN_CCCR, val: cccr | CCCR_INIT | CCCR_CCE);
398	} else {
399	m_can_write(cdev, reg: M_CAN_CCCR, val: cccr & ~(CCCR_INIT | CCCR_CCE));
400	}
401
402	/* there's a delay for module initialization */
403	if (enable)
404	val = CCCR_INIT | CCCR_CCE;
405
406	while ((m_can_read(cdev, reg: M_CAN_CCCR) & (CCCR_INIT | CCCR_CCE)) != val) {
407	if (timeout == 0) {
408	netdev_warn(dev: cdev->net, format: "Failed to init module\n");
409	return;
410	}
411	timeout--;
412	udelay(1);
413	}
414	}
415
416	static void m_can_interrupt_enable(struct m_can_classdev *cdev, u32 interrupts)
417	{
418	if (cdev->active_interrupts == interrupts)
419	return;
420	cdev->ops->write_reg(cdev, M_CAN_IE, interrupts);
421	cdev->active_interrupts = interrupts;
422	}
423
424	static void m_can_coalescing_disable(struct m_can_classdev *cdev)
425	{
426	u32 new_interrupts = cdev->active_interrupts | IR_RF0N | IR_TEFN;
427
428	if (!cdev->net->irq)
429	return;
430
431	hrtimer_cancel(timer: &cdev->hrtimer);
432	m_can_interrupt_enable(cdev, interrupts: new_interrupts);
433	}
434
435	static inline void m_can_enable_all_interrupts(struct m_can_classdev *cdev)
436	{
437	if (!cdev->net->irq) {
438	dev_dbg(cdev->dev, "Start hrtimer\n");
439	hrtimer_start(timer: &cdev->hrtimer,
440	tim: ms_to_ktime(HRTIMER_POLL_INTERVAL_MS),
441	mode: HRTIMER_MODE_REL_PINNED);
442	}
443
444	/* Only interrupt line 0 is used in this driver */
445	m_can_write(cdev, reg: M_CAN_ILE, ILE_EINT0);
446	}
447
448	static inline void m_can_disable_all_interrupts(struct m_can_classdev *cdev)
449	{
450	m_can_coalescing_disable(cdev);
451	m_can_write(cdev, reg: M_CAN_ILE, val: 0x0);
452	cdev->active_interrupts = 0x0;
453
454	if (!cdev->net->irq) {
455	dev_dbg(cdev->dev, "Stop hrtimer\n");
456	hrtimer_cancel(timer: &cdev->hrtimer);
457	}
458	}
459
460	/* Retrieve internal timestamp counter from TSCV.TSC, and shift it to 32-bit
461	* width.
462	*/
463	static u32 m_can_get_timestamp(struct m_can_classdev *cdev)
464	{
465	u32 tscv;
466	u32 tsc;
467
468	tscv = m_can_read(cdev, reg: M_CAN_TSCV);
469	tsc = FIELD_GET(TSCV_TSC_MASK, tscv);
470
471	return (tsc << 16);
472	}
473
474	static void m_can_clean(struct net_device *net)
475	{
476	struct m_can_classdev *cdev = netdev_priv(dev: net);
477	unsigned long irqflags;
478
479	if (cdev->tx_ops) {
480	for (int i = 0; i != cdev->tx_fifo_size; ++i) {
481	if (!cdev->tx_ops[i].skb)
482	continue;
483
484	net->stats.tx_errors++;
485	cdev->tx_ops[i].skb = NULL;
486	}
487	}
488
489	for (int i = 0; i != cdev->can.echo_skb_max; ++i)
490	can_free_echo_skb(dev: cdev->net, idx: i, NULL);
491
492	netdev_reset_queue(dev_queue: cdev->net);
493
494	spin_lock_irqsave(&cdev->tx_handling_spinlock, irqflags);
495	cdev->tx_fifo_in_flight = 0;
496	spin_unlock_irqrestore(lock: &cdev->tx_handling_spinlock, flags: irqflags);
497	}
498
499	/* For peripherals, pass skb to rx-offload, which will push skb from
500	* napi. For non-peripherals, RX is done in napi already, so push
501	* directly. timestamp is used to ensure good skb ordering in
502	* rx-offload and is ignored for non-peripherals.
503	*/
504	static void m_can_receive_skb(struct m_can_classdev *cdev,
505	struct sk_buff *skb,
506	u32 timestamp)
507	{
508	if (cdev->is_peripheral) {
509	struct net_device_stats *stats = &cdev->net->stats;
510	int err;
511
512	err = can_rx_offload_queue_timestamp(offload: &cdev->offload, skb,
513	timestamp);
514	if (err)
515	stats->rx_fifo_errors++;
516	} else {
517	netif_receive_skb(skb);
518	}
519	}
520
521	static int m_can_read_fifo(struct net_device *dev, u32 fgi)
522	{
523	struct net_device_stats *stats = &dev->stats;
524	struct m_can_classdev *cdev = netdev_priv(dev);
525	struct canfd_frame *cf;
526	struct sk_buff *skb;
527	struct id_and_dlc fifo_header;
528	u32 timestamp = 0;
529	int err;
530
531	err = m_can_fifo_read(cdev, fgi, M_CAN_FIFO_ID, val: &fifo_header, val_count: 2);
532	if (err)
533	goto out_fail;
534
535	if (fifo_header.dlc & RX_BUF_FDF)
536	skb = alloc_canfd_skb(dev, cfd: &cf);
537	else
538	skb = alloc_can_skb(dev, cf: (struct can_frame **)&cf);
539	if (!skb) {
540	stats->rx_dropped++;
541	return 0;
542	}
543
544	if (fifo_header.dlc & RX_BUF_FDF)
545	cf->len = can_fd_dlc2len(dlc: (fifo_header.dlc >> 16) & 0x0F);
546	else
547	cf->len = can_cc_dlc2len((fifo_header.dlc >> 16) & 0x0F);
548
549	if (fifo_header.id & RX_BUF_XTD)
550	cf->can_id = (fifo_header.id & CAN_EFF_MASK) | CAN_EFF_FLAG;
551	else
552	cf->can_id = (fifo_header.id >> 18) & CAN_SFF_MASK;
553
554	if (fifo_header.id & RX_BUF_ESI) {
555	cf->flags |= CANFD_ESI;
556	netdev_dbg(dev, "ESI Error\n");
557	}
558
559	if (!(fifo_header.dlc & RX_BUF_FDF) && (fifo_header.id & RX_BUF_RTR)) {
560	cf->can_id |= CAN_RTR_FLAG;
561	} else {
562	if (fifo_header.dlc & RX_BUF_BRS)
563	cf->flags |= CANFD_BRS;
564
565	err = m_can_fifo_read(cdev, fgi, M_CAN_FIFO_DATA,
566	val: cf->data, DIV_ROUND_UP(cf->len, 4));
567	if (err)
568	goto out_free_skb;
569
570	stats->rx_bytes += cf->len;
571	}
572	stats->rx_packets++;
573
574	timestamp = FIELD_GET(RX_BUF_RXTS_MASK, fifo_header.dlc) << 16;
575
576	m_can_receive_skb(cdev, skb, timestamp);
577
578	return 0;
579
580	out_free_skb:
581	kfree_skb(skb);
582	out_fail:
583	netdev_err(dev, format: "FIFO read returned %d\n", err);
584	return err;
585	}
586
587	static int m_can_do_rx_poll(struct net_device *dev, int quota)
588	{
589	struct m_can_classdev *cdev = netdev_priv(dev);
590	u32 pkts = 0;
591	u32 rxfs;
592	u32 rx_count;
593	u32 fgi;
594	int ack_fgi = -1;
595	int i;
596	int err = 0;
597
598	rxfs = m_can_read(cdev, reg: M_CAN_RXF0S);
599	if (!(rxfs & RXFS_FFL_MASK)) {
600	netdev_dbg(dev, "no messages in fifo0\n");
601	return 0;
602	}
603
604	rx_count = FIELD_GET(RXFS_FFL_MASK, rxfs);
605	fgi = FIELD_GET(RXFS_FGI_MASK, rxfs);
606
607	for (i = 0; i < rx_count && quota > 0; ++i) {
608	err = m_can_read_fifo(dev, fgi);
609	if (err)
610	break;
611
612	quota--;
613	pkts++;
614	ack_fgi = fgi;
615	fgi = (++fgi >= cdev->mcfg[MRAM_RXF0].num ? 0 : fgi);
616	}
617
618	if (ack_fgi != -1)
619	m_can_write(cdev, reg: M_CAN_RXF0A, val: ack_fgi);
620
621	if (err)
622	return err;
623
624	return pkts;
625	}
626
627	static int m_can_handle_lost_msg(struct net_device *dev)
628	{
629	struct m_can_classdev *cdev = netdev_priv(dev);
630	struct net_device_stats *stats = &dev->stats;
631	struct sk_buff *skb;
632	struct can_frame *frame;
633	u32 timestamp = 0;
634
635	netdev_err(dev, format: "msg lost in rxf0\n");
636
637	stats->rx_errors++;
638	stats->rx_over_errors++;
639
640	skb = alloc_can_err_skb(dev, cf: &frame);
641	if (unlikely(!skb))
642	return 0;
643
644	frame->can_id |= CAN_ERR_CRTL;
645	frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
646
647	if (cdev->is_peripheral)
648	timestamp = m_can_get_timestamp(cdev);
649
650	m_can_receive_skb(cdev, skb, timestamp);
651
652	return 1;
653	}
654
655	static int m_can_handle_lec_err(struct net_device *dev,
656	enum m_can_lec_type lec_type)
657	{
658	struct m_can_classdev *cdev = netdev_priv(dev);
659	struct net_device_stats *stats = &dev->stats;
660	struct can_frame *cf;
661	struct sk_buff *skb;
662	u32 timestamp = 0;
663
664	cdev->can.can_stats.bus_error++;
665	stats->rx_errors++;
666
667	/* propagate the error condition to the CAN stack */
668	skb = alloc_can_err_skb(dev, cf: &cf);
669	if (unlikely(!skb))
670	return 0;
671
672	/* check for 'last error code' which tells us the
673	* type of the last error to occur on the CAN bus
674	*/
675	cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
676
677	switch (lec_type) {
678	case LEC_STUFF_ERROR:
679	netdev_dbg(dev, "stuff error\n");
680	cf->data[2] |= CAN_ERR_PROT_STUFF;
681	break;
682	case LEC_FORM_ERROR:
683	netdev_dbg(dev, "form error\n");
684	cf->data[2] |= CAN_ERR_PROT_FORM;
685	break;
686	case LEC_ACK_ERROR:
687	netdev_dbg(dev, "ack error\n");
688	cf->data[3] = CAN_ERR_PROT_LOC_ACK;
689	break;
690	case LEC_BIT1_ERROR:
691	netdev_dbg(dev, "bit1 error\n");
692	cf->data[2] |= CAN_ERR_PROT_BIT1;
693	break;
694	case LEC_BIT0_ERROR:
695	netdev_dbg(dev, "bit0 error\n");
696	cf->data[2] |= CAN_ERR_PROT_BIT0;
697	break;
698	case LEC_CRC_ERROR:
699	netdev_dbg(dev, "CRC error\n");
700	cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
701	break;
702	default:
703	break;
704	}
705
706	if (cdev->is_peripheral)
707	timestamp = m_can_get_timestamp(cdev);
708
709	m_can_receive_skb(cdev, skb, timestamp);
710
711	return 1;
712	}
713
714	static int __m_can_get_berr_counter(const struct net_device *dev,
715	struct can_berr_counter *bec)
716	{
717	struct m_can_classdev *cdev = netdev_priv(dev);
718	unsigned int ecr;
719
720	ecr = m_can_read(cdev, reg: M_CAN_ECR);
721	bec->rxerr = FIELD_GET(ECR_REC_MASK, ecr);
722	bec->txerr = FIELD_GET(ECR_TEC_MASK, ecr);
723
724	return 0;
725	}
726
727	static int m_can_clk_start(struct m_can_classdev *cdev)
728	{
729	if (cdev->pm_clock_support == 0)
730	return 0;
731
732	return pm_runtime_resume_and_get(dev: cdev->dev);
733	}
734
735	static void m_can_clk_stop(struct m_can_classdev *cdev)
736	{
737	if (cdev->pm_clock_support)
738	pm_runtime_put_sync(dev: cdev->dev);
739	}
740
741	static int m_can_get_berr_counter(const struct net_device *dev,
742	struct can_berr_counter *bec)
743	{
744	struct m_can_classdev *cdev = netdev_priv(dev);
745	int err;
746
747	err = m_can_clk_start(cdev);
748	if (err)
749	return err;
750
751	__m_can_get_berr_counter(dev, bec);
752
753	m_can_clk_stop(cdev);
754
755	return 0;
756	}
757
758	static int m_can_handle_state_change(struct net_device *dev,
759	enum can_state new_state)
760	{
761	struct m_can_classdev *cdev = netdev_priv(dev);
762	struct can_frame *cf;
763	struct sk_buff *skb;
764	struct can_berr_counter bec;
765	unsigned int ecr;
766	u32 timestamp = 0;
767
768	switch (new_state) {
769	case CAN_STATE_ERROR_WARNING:
770	/* error warning state */
771	cdev->can.can_stats.error_warning++;
772	cdev->can.state = CAN_STATE_ERROR_WARNING;
773	break;
774	case CAN_STATE_ERROR_PASSIVE:
775	/* error passive state */
776	cdev->can.can_stats.error_passive++;
777	cdev->can.state = CAN_STATE_ERROR_PASSIVE;
778	break;
779	case CAN_STATE_BUS_OFF:
780	/* bus-off state */
781	cdev->can.state = CAN_STATE_BUS_OFF;
782	m_can_disable_all_interrupts(cdev);
783	cdev->can.can_stats.bus_off++;
784	can_bus_off(dev);
785	break;
786	default:
787	break;
788	}
789
790	/* propagate the error condition to the CAN stack */
791	skb = alloc_can_err_skb(dev, cf: &cf);
792	if (unlikely(!skb))
793	return 0;
794
795	__m_can_get_berr_counter(dev, bec: &bec);
796
797	switch (new_state) {
798	case CAN_STATE_ERROR_WARNING:
799	/* error warning state */
800	cf->can_id |= CAN_ERR_CRTL | CAN_ERR_CNT;
801	cf->data[1] = (bec.txerr > bec.rxerr) ?
802	CAN_ERR_CRTL_TX_WARNING :
803	CAN_ERR_CRTL_RX_WARNING;
804	cf->data[6] = bec.txerr;
805	cf->data[7] = bec.rxerr;
806	break;
807	case CAN_STATE_ERROR_PASSIVE:
808	/* error passive state */
809	cf->can_id |= CAN_ERR_CRTL | CAN_ERR_CNT;
810	ecr = m_can_read(cdev, reg: M_CAN_ECR);
811	if (ecr & ECR_RP)
812	cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
813	if (bec.txerr > 127)
814	cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
815	cf->data[6] = bec.txerr;
816	cf->data[7] = bec.rxerr;
817	break;
818	case CAN_STATE_BUS_OFF:
819	/* bus-off state */
820	cf->can_id |= CAN_ERR_BUSOFF;
821	break;
822	default:
823	break;
824	}
825
826	if (cdev->is_peripheral)
827	timestamp = m_can_get_timestamp(cdev);
828
829	m_can_receive_skb(cdev, skb, timestamp);
830
831	return 1;
832	}
833
834	static int m_can_handle_state_errors(struct net_device *dev, u32 psr)
835	{
836	struct m_can_classdev *cdev = netdev_priv(dev);
837	int work_done = 0;
838
839	if (psr & PSR_EW && cdev->can.state != CAN_STATE_ERROR_WARNING) {
840	netdev_dbg(dev, "entered error warning state\n");
841	work_done += m_can_handle_state_change(dev,
842	new_state: CAN_STATE_ERROR_WARNING);
843	}
844
845	if (psr & PSR_EP && cdev->can.state != CAN_STATE_ERROR_PASSIVE) {
846	netdev_dbg(dev, "entered error passive state\n");
847	work_done += m_can_handle_state_change(dev,
848	new_state: CAN_STATE_ERROR_PASSIVE);
849	}
850
851	if (psr & PSR_BO && cdev->can.state != CAN_STATE_BUS_OFF) {
852	netdev_dbg(dev, "entered error bus off state\n");
853	work_done += m_can_handle_state_change(dev,
854	new_state: CAN_STATE_BUS_OFF);
855	}
856
857	return work_done;
858	}
859
860	static void m_can_handle_other_err(struct net_device *dev, u32 irqstatus)
861	{
862	if (irqstatus & IR_WDI)
863	netdev_err(dev, format: "Message RAM Watchdog event due to missing READY\n");
864	if (irqstatus & IR_BEU)
865	netdev_err(dev, format: "Bit Error Uncorrected\n");
866	if (irqstatus & IR_BEC)
867	netdev_err(dev, format: "Bit Error Corrected\n");
868	if (irqstatus & IR_TOO)
869	netdev_err(dev, format: "Timeout reached\n");
870	if (irqstatus & IR_MRAF)
871	netdev_err(dev, format: "Message RAM access failure occurred\n");
872	}
873
874	static inline bool is_lec_err(u8 lec)
875	{
876	return lec != LEC_NO_ERROR && lec != LEC_NO_CHANGE;
877	}
878
879	static inline bool m_can_is_protocol_err(u32 irqstatus)
880	{
881	return irqstatus & IR_ERR_LEC_31X;
882	}
883
884	static int m_can_handle_protocol_error(struct net_device *dev, u32 irqstatus)
885	{
886	struct net_device_stats *stats = &dev->stats;
887	struct m_can_classdev *cdev = netdev_priv(dev);
888	struct can_frame *cf;
889	struct sk_buff *skb;
890	u32 timestamp = 0;
891
892	/* propagate the error condition to the CAN stack */
893	skb = alloc_can_err_skb(dev, cf: &cf);
894
895	/* update tx error stats since there is protocol error */
896	stats->tx_errors++;
897
898	/* update arbitration lost status */
899	if (cdev->version >= 31 && (irqstatus & IR_PEA)) {
900	netdev_dbg(dev, "Protocol error in Arbitration fail\n");
901	cdev->can.can_stats.arbitration_lost++;
902	if (skb) {
903	cf->can_id |= CAN_ERR_LOSTARB;
904	cf->data[0] |= CAN_ERR_LOSTARB_UNSPEC;
905	}
906	}
907
908	if (unlikely(!skb)) {
909	netdev_dbg(dev, "allocation of skb failed\n");
910	return 0;
911	}
912
913	if (cdev->is_peripheral)
914	timestamp = m_can_get_timestamp(cdev);
915
916	m_can_receive_skb(cdev, skb, timestamp);
917
918	return 1;
919	}
920
921	static int m_can_handle_bus_errors(struct net_device *dev, u32 irqstatus,
922	u32 psr)
923	{
924	struct m_can_classdev *cdev = netdev_priv(dev);
925	int work_done = 0;
926
927	if (irqstatus & IR_RF0L)
928	work_done += m_can_handle_lost_msg(dev);
929
930	/* handle lec errors on the bus */
931	if (cdev->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) {
932	u8 lec = FIELD_GET(PSR_LEC_MASK, psr);
933	u8 dlec = FIELD_GET(PSR_DLEC_MASK, psr);
934
935	if (is_lec_err(lec)) {
936	netdev_dbg(dev, "Arbitration phase error detected\n");
937	work_done += m_can_handle_lec_err(dev, lec_type: lec);
938	}
939
940	if (is_lec_err(lec: dlec)) {
941	netdev_dbg(dev, "Data phase error detected\n");
942	work_done += m_can_handle_lec_err(dev, lec_type: dlec);
943	}
944	}
945
946	/* handle protocol errors in arbitration phase */
947	if ((cdev->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) &&
948	m_can_is_protocol_err(irqstatus))
949	work_done += m_can_handle_protocol_error(dev, irqstatus);
950
951	/* other unproccessed error interrupts */
952	m_can_handle_other_err(dev, irqstatus);
953
954	return work_done;
955	}
956
957	static int m_can_rx_handler(struct net_device *dev, int quota, u32 irqstatus)
958	{
959	struct m_can_classdev *cdev = netdev_priv(dev);
960	int rx_work_or_err;
961	int work_done = 0;
962
963	if (!irqstatus)
964	goto end;
965
966	/* Errata workaround for issue "Needless activation of MRAF irq"
967	* During frame reception while the MCAN is in Error Passive state
968	* and the Receive Error Counter has the value MCAN_ECR.REC = 127,
969	* it may happen that MCAN_IR.MRAF is set although there was no
970	* Message RAM access failure.
971	* If MCAN_IR.MRAF is enabled, an interrupt to the Host CPU is generated
972	* The Message RAM Access Failure interrupt routine needs to check
973	* whether MCAN_ECR.RP = ’1’ and MCAN_ECR.REC = 127.
974	* In this case, reset MCAN_IR.MRAF. No further action is required.
975	*/
976	if (cdev->version <= 31 && irqstatus & IR_MRAF &&
977	m_can_read(cdev, reg: M_CAN_ECR) & ECR_RP) {
978	struct can_berr_counter bec;
979
980	__m_can_get_berr_counter(dev, bec: &bec);
981	if (bec.rxerr == 127) {
982	m_can_write(cdev, reg: M_CAN_IR, IR_MRAF);
983	irqstatus &= ~IR_MRAF;
984	}
985	}
986
987	if (irqstatus & IR_ERR_STATE)
988	work_done += m_can_handle_state_errors(dev,
989	psr: m_can_read(cdev, reg: M_CAN_PSR));
990
991	if (irqstatus & IR_ERR_BUS_30X)
992	work_done += m_can_handle_bus_errors(dev, irqstatus,
993	psr: m_can_read(cdev, reg: M_CAN_PSR));
994
995	if (irqstatus & IR_RF0N) {
996	rx_work_or_err = m_can_do_rx_poll(dev, quota: (quota - work_done));
997	if (rx_work_or_err < 0)
998	return rx_work_or_err;
999
1000	work_done += rx_work_or_err;
1001	}
1002	end:
1003	return work_done;
1004	}
1005
1006	static int m_can_rx_peripheral(struct net_device *dev, u32 irqstatus)
1007	{
1008	struct m_can_classdev *cdev = netdev_priv(dev);
1009	int work_done;
1010
1011	work_done = m_can_rx_handler(dev, NAPI_POLL_WEIGHT, irqstatus);
1012
1013	/* Don't re-enable interrupts if the driver had a fatal error
1014	* (e.g., FIFO read failure).
1015	*/
1016	if (work_done < 0)
1017	m_can_disable_all_interrupts(cdev);
1018
1019	return work_done;
1020	}
1021
1022	static int m_can_poll(struct napi_struct *napi, int quota)
1023	{
1024	struct net_device *dev = napi->dev;
1025	struct m_can_classdev *cdev = netdev_priv(dev);
1026	int work_done;
1027	u32 irqstatus;
1028
1029	irqstatus = cdev->irqstatus | m_can_read(cdev, reg: M_CAN_IR);
1030
1031	work_done = m_can_rx_handler(dev, quota, irqstatus);
1032
1033	/* Don't re-enable interrupts if the driver had a fatal error
1034	* (e.g., FIFO read failure).
1035	*/
1036	if (work_done >= 0 && work_done < quota) {
1037	napi_complete_done(n: napi, work_done);
1038	m_can_enable_all_interrupts(cdev);
1039	}
1040
1041	return work_done;
1042	}
1043
1044	/* Echo tx skb and update net stats. Peripherals use rx-offload for
1045	* echo. timestamp is used for peripherals to ensure correct ordering
1046	* by rx-offload, and is ignored for non-peripherals.
1047	*/
1048	static unsigned int m_can_tx_update_stats(struct m_can_classdev *cdev,
1049	unsigned int msg_mark, u32 timestamp)
1050	{
1051	struct net_device *dev = cdev->net;
1052	struct net_device_stats *stats = &dev->stats;
1053	unsigned int frame_len;
1054
1055	if (cdev->is_peripheral)
1056	stats->tx_bytes +=
1057	can_rx_offload_get_echo_skb_queue_timestamp(offload: &cdev->offload,
1058	idx: msg_mark,
1059	timestamp,
1060	frame_len_ptr: &frame_len);
1061	else
1062	stats->tx_bytes += can_get_echo_skb(dev, idx: msg_mark, frame_len_ptr: &frame_len);
1063
1064	stats->tx_packets++;
1065
1066	return frame_len;
1067	}
1068
1069	static void m_can_finish_tx(struct m_can_classdev *cdev, int transmitted,
1070	unsigned int transmitted_frame_len)
1071	{
1072	unsigned long irqflags;
1073
1074	netdev_completed_queue(dev: cdev->net, pkts: transmitted, bytes: transmitted_frame_len);
1075
1076	spin_lock_irqsave(&cdev->tx_handling_spinlock, irqflags);
1077	if (cdev->tx_fifo_in_flight >= cdev->tx_fifo_size && transmitted > 0)
1078	netif_wake_queue(dev: cdev->net);
1079	cdev->tx_fifo_in_flight -= transmitted;
1080	spin_unlock_irqrestore(lock: &cdev->tx_handling_spinlock, flags: irqflags);
1081	}
1082
1083	static netdev_tx_t m_can_start_tx(struct m_can_classdev *cdev)
1084	{
1085	unsigned long irqflags;
1086	int tx_fifo_in_flight;
1087
1088	spin_lock_irqsave(&cdev->tx_handling_spinlock, irqflags);
1089	tx_fifo_in_flight = cdev->tx_fifo_in_flight + 1;
1090	if (tx_fifo_in_flight >= cdev->tx_fifo_size) {
1091	netif_stop_queue(dev: cdev->net);
1092	if (tx_fifo_in_flight > cdev->tx_fifo_size) {
1093	netdev_err_once(cdev->net, "hard_xmit called while TX FIFO full\n");
1094	spin_unlock_irqrestore(lock: &cdev->tx_handling_spinlock, flags: irqflags);
1095	return NETDEV_TX_BUSY;
1096	}
1097	}
1098	cdev->tx_fifo_in_flight = tx_fifo_in_flight;
1099	spin_unlock_irqrestore(lock: &cdev->tx_handling_spinlock, flags: irqflags);
1100
1101	return NETDEV_TX_OK;
1102	}
1103
1104	static int m_can_echo_tx_event(struct net_device *dev)
1105	{
1106	u32 txe_count = 0;
1107	u32 m_can_txefs;
1108	u32 fgi = 0;
1109	int ack_fgi = -1;
1110	int i = 0;
1111	int err = 0;
1112	unsigned int msg_mark;
1113	int processed = 0;
1114	unsigned int processed_frame_len = 0;
1115
1116	struct m_can_classdev *cdev = netdev_priv(dev);
1117
1118	/* read tx event fifo status */
1119	m_can_txefs = m_can_read(cdev, reg: M_CAN_TXEFS);
1120
1121	/* Get Tx Event fifo element count */
1122	txe_count = FIELD_GET(TXEFS_EFFL_MASK, m_can_txefs);
1123	fgi = FIELD_GET(TXEFS_EFGI_MASK, m_can_txefs);
1124
1125	/* Get and process all sent elements */
1126	for (i = 0; i < txe_count; i++) {
1127	u32 txe, timestamp = 0;
1128
1129	/* get message marker, timestamp */
1130	err = m_can_txe_fifo_read(cdev, fgi, offset: 4, val: &txe);
1131	if (err) {
1132	netdev_err(dev, format: "TXE FIFO read returned %d\n", err);
1133	break;
1134	}
1135
1136	msg_mark = FIELD_GET(TX_EVENT_MM_MASK, txe);
1137	timestamp = FIELD_GET(TX_EVENT_TXTS_MASK, txe) << 16;
1138
1139	ack_fgi = fgi;
1140	fgi = (++fgi >= cdev->mcfg[MRAM_TXE].num ? 0 : fgi);
1141
1142	/* update stats */
1143	processed_frame_len += m_can_tx_update_stats(cdev, msg_mark,
1144	timestamp);
1145
1146	++processed;
1147	}
1148
1149	if (ack_fgi != -1)
1150	m_can_write(cdev, reg: M_CAN_TXEFA, FIELD_PREP(TXEFA_EFAI_MASK,
1151	ack_fgi));
1152
1153	m_can_finish_tx(cdev, transmitted: processed, transmitted_frame_len: processed_frame_len);
1154
1155	return err;
1156	}
1157
1158	static void m_can_coalescing_update(struct m_can_classdev *cdev, u32 ir)
1159	{
1160	u32 new_interrupts = cdev->active_interrupts;
1161	bool enable_rx_timer = false;
1162	bool enable_tx_timer = false;
1163
1164	if (!cdev->net->irq)
1165	return;
1166
1167	if (cdev->rx_coalesce_usecs_irq > 0 && (ir & (IR_RF0N | IR_RF0W))) {
1168	enable_rx_timer = true;
1169	new_interrupts &= ~IR_RF0N;
1170	}
1171	if (cdev->tx_coalesce_usecs_irq > 0 && (ir & (IR_TEFN | IR_TEFW))) {
1172	enable_tx_timer = true;
1173	new_interrupts &= ~IR_TEFN;
1174	}
1175	if (!enable_rx_timer && !hrtimer_active(timer: &cdev->hrtimer))
1176	new_interrupts |= IR_RF0N;
1177	if (!enable_tx_timer && !hrtimer_active(timer: &cdev->hrtimer))
1178	new_interrupts |= IR_TEFN;
1179
1180	m_can_interrupt_enable(cdev, interrupts: new_interrupts);
1181	if (enable_rx_timer | enable_tx_timer)
1182	hrtimer_start(timer: &cdev->hrtimer, tim: cdev->irq_timer_wait,
1183	mode: HRTIMER_MODE_REL);
1184	}
1185
1186	static irqreturn_t m_can_isr(int irq, void *dev_id)
1187	{
1188	struct net_device *dev = (struct net_device *)dev_id;
1189	struct m_can_classdev *cdev = netdev_priv(dev);
1190	u32 ir;
1191
1192	if (pm_runtime_suspended(dev: cdev->dev)) {
1193	m_can_coalescing_disable(cdev);
1194	return IRQ_NONE;
1195	}
1196
1197	ir = m_can_read(cdev, reg: M_CAN_IR);
1198	m_can_coalescing_update(cdev, ir);
1199	if (!ir)
1200	return IRQ_NONE;
1201
1202	/* ACK all irqs */
1203	m_can_write(cdev, reg: M_CAN_IR, val: ir);
1204
1205	if (cdev->ops->clear_interrupts)
1206	cdev->ops->clear_interrupts(cdev);
1207
1208	/* schedule NAPI in case of
1209	* - rx IRQ
1210	* - state change IRQ
1211	* - bus error IRQ and bus error reporting
1212	*/
1213	if (ir & (IR_RF0N | IR_RF0W | IR_ERR_ALL_30X)) {
1214	cdev->irqstatus = ir;
1215	if (!cdev->is_peripheral) {
1216	m_can_disable_all_interrupts(cdev);
1217	napi_schedule(n: &cdev->napi);
1218	} else {
1219	int pkts;
1220
1221	pkts = m_can_rx_peripheral(dev, irqstatus: ir);
1222	if (pkts < 0)
1223	goto out_fail;
1224	}
1225	}
1226
1227	if (cdev->version == 30) {
1228	if (ir & IR_TC) {
1229	/* Transmission Complete Interrupt*/
1230	u32 timestamp = 0;
1231	unsigned int frame_len;
1232
1233	if (cdev->is_peripheral)
1234	timestamp = m_can_get_timestamp(cdev);
1235	frame_len = m_can_tx_update_stats(cdev, msg_mark: 0, timestamp);
1236	m_can_finish_tx(cdev, transmitted: 1, transmitted_frame_len: frame_len);
1237	}
1238	} else {
1239	if (ir & (IR_TEFN | IR_TEFW)) {
1240	/* New TX FIFO Element arrived */
1241	if (m_can_echo_tx_event(dev) != 0)
1242	goto out_fail;
1243	}
1244	}
1245
1246	if (cdev->is_peripheral)
1247	can_rx_offload_threaded_irq_finish(offload: &cdev->offload);
1248
1249	return IRQ_HANDLED;
1250
1251	out_fail:
1252	m_can_disable_all_interrupts(cdev);
1253	return IRQ_HANDLED;
1254	}
1255
1256	static enum hrtimer_restart m_can_coalescing_timer(struct hrtimer *timer)
1257	{
1258	struct m_can_classdev *cdev = container_of(timer, struct m_can_classdev, hrtimer);
1259
1260	irq_wake_thread(irq: cdev->net->irq, dev_id: cdev->net);
1261
1262	return HRTIMER_NORESTART;
1263	}
1264
1265	static const struct can_bittiming_const m_can_bittiming_const_30X = {
1266	.name = KBUILD_MODNAME,
1267	.tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */
1268	.tseg1_max = 64,
1269	.tseg2_min = 1, /* Time segment 2 = phase_seg2 */
1270	.tseg2_max = 16,
1271	.sjw_max = 16,
1272	.brp_min = 1,
1273	.brp_max = 1024,
1274	.brp_inc = 1,
1275	};
1276
1277	static const struct can_bittiming_const m_can_data_bittiming_const_30X = {
1278	.name = KBUILD_MODNAME,
1279	.tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */
1280	.tseg1_max = 16,
1281	.tseg2_min = 1, /* Time segment 2 = phase_seg2 */
1282	.tseg2_max = 8,
1283	.sjw_max = 4,
1284	.brp_min = 1,
1285	.brp_max = 32,
1286	.brp_inc = 1,
1287	};
1288
1289	static const struct can_bittiming_const m_can_bittiming_const_31X = {
1290	.name = KBUILD_MODNAME,
1291	.tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */
1292	.tseg1_max = 256,
1293	.tseg2_min = 2, /* Time segment 2 = phase_seg2 */
1294	.tseg2_max = 128,
1295	.sjw_max = 128,
1296	.brp_min = 1,
1297	.brp_max = 512,
1298	.brp_inc = 1,
1299	};
1300
1301	static const struct can_bittiming_const m_can_data_bittiming_const_31X = {
1302	.name = KBUILD_MODNAME,
1303	.tseg1_min = 1, /* Time segment 1 = prop_seg + phase_seg1 */
1304	.tseg1_max = 32,
1305	.tseg2_min = 1, /* Time segment 2 = phase_seg2 */
1306	.tseg2_max = 16,
1307	.sjw_max = 16,
1308	.brp_min = 1,
1309	.brp_max = 32,
1310	.brp_inc = 1,
1311	};
1312
1313	static int m_can_set_bittiming(struct net_device *dev)
1314	{
1315	struct m_can_classdev *cdev = netdev_priv(dev);
1316	const struct can_bittiming *bt = &cdev->can.bittiming;
1317	const struct can_bittiming *dbt = &cdev->can.data_bittiming;
1318	u16 brp, sjw, tseg1, tseg2;
1319	u32 reg_btp;
1320
1321	brp = bt->brp - 1;
1322	sjw = bt->sjw - 1;
1323	tseg1 = bt->prop_seg + bt->phase_seg1 - 1;
1324	tseg2 = bt->phase_seg2 - 1;
1325	reg_btp = FIELD_PREP(NBTP_NBRP_MASK, brp) |
1326	FIELD_PREP(NBTP_NSJW_MASK, sjw) |
1327	FIELD_PREP(NBTP_NTSEG1_MASK, tseg1) |
1328	FIELD_PREP(NBTP_NTSEG2_MASK, tseg2);
1329	m_can_write(cdev, reg: M_CAN_NBTP, val: reg_btp);
1330
1331	if (cdev->can.ctrlmode & CAN_CTRLMODE_FD) {
1332	reg_btp = 0;
1333	brp = dbt->brp - 1;
1334	sjw = dbt->sjw - 1;
1335	tseg1 = dbt->prop_seg + dbt->phase_seg1 - 1;
1336	tseg2 = dbt->phase_seg2 - 1;
1337
1338	/* TDC is only needed for bitrates beyond 2.5 MBit/s.
1339	* This is mentioned in the "Bit Time Requirements for CAN FD"
1340	* paper presented at the International CAN Conference 2013
1341	*/
1342	if (dbt->bitrate > 2500000) {
1343	u32 tdco, ssp;
1344
1345	/* Use the same value of secondary sampling point
1346	* as the data sampling point
1347	*/
1348	ssp = dbt->sample_point;
1349
1350	/* Equation based on Bosch's M_CAN User Manual's
1351	* Transmitter Delay Compensation Section
1352	*/
1353	tdco = (cdev->can.clock.freq / 1000) *
1354	ssp / dbt->bitrate;
1355
1356	/* Max valid TDCO value is 127 */
1357	if (tdco > 127) {
1358	netdev_warn(dev, format: "TDCO value of %u is beyond maximum. Using maximum possible value\n",
1359	tdco);
1360	tdco = 127;
1361	}
1362
1363	reg_btp |= DBTP_TDC;
1364	m_can_write(cdev, reg: M_CAN_TDCR,
1365	FIELD_PREP(TDCR_TDCO_MASK, tdco));
1366	}
1367
1368	reg_btp |= FIELD_PREP(DBTP_DBRP_MASK, brp) |
1369	FIELD_PREP(DBTP_DSJW_MASK, sjw) |
1370	FIELD_PREP(DBTP_DTSEG1_MASK, tseg1) |
1371	FIELD_PREP(DBTP_DTSEG2_MASK, tseg2);
1372
1373	m_can_write(cdev, reg: M_CAN_DBTP, val: reg_btp);
1374	}
1375
1376	return 0;
1377	}
1378
1379	/* Configure M_CAN chip:
1380	* - set rx buffer/fifo element size
1381	* - configure rx fifo
1382	* - accept non-matching frame into fifo 0
1383	* - configure tx buffer
1384	* - >= v3.1.x: TX FIFO is used
1385	* - configure mode
1386	* - setup bittiming
1387	* - configure timestamp generation
1388	*/
1389	static int m_can_chip_config(struct net_device *dev)
1390	{
1391	struct m_can_classdev *cdev = netdev_priv(dev);
1392	u32 interrupts = IR_ALL_INT;
1393	u32 cccr, test;
1394	int err;
1395
1396	err = m_can_init_ram(priv: cdev);
1397	if (err) {
1398	dev_err(cdev->dev, "Message RAM configuration failed\n");
1399	return err;
1400	}
1401
1402	/* Disable unused interrupts */
1403	interrupts &= ~(IR_ARA | IR_ELO | IR_DRX | IR_TEFF | IR_TFE | IR_TCF |
1404	IR_HPM | IR_RF1F | IR_RF1W | IR_RF1N | IR_RF0F);
1405
1406	m_can_config_endisable(cdev, enable: true);
1407
1408	/* RX Buffer/FIFO Element Size 64 bytes data field */
1409	m_can_write(cdev, reg: M_CAN_RXESC,
1410	FIELD_PREP(RXESC_RBDS_MASK, RXESC_64B) |
1411	FIELD_PREP(RXESC_F1DS_MASK, RXESC_64B) |
1412	FIELD_PREP(RXESC_F0DS_MASK, RXESC_64B));
1413
1414	/* Accept Non-matching Frames Into FIFO 0 */
1415	m_can_write(cdev, reg: M_CAN_GFC, val: 0x0);
1416
1417	if (cdev->version == 30) {
1418	/* only support one Tx Buffer currently */
1419	m_can_write(cdev, reg: M_CAN_TXBC, FIELD_PREP(TXBC_NDTB_MASK, 1) |
1420	cdev->mcfg[MRAM_TXB].off);
1421	} else {
1422	/* TX FIFO is used for newer IP Core versions */
1423	m_can_write(cdev, reg: M_CAN_TXBC,
1424	FIELD_PREP(TXBC_TFQS_MASK,
1425	cdev->mcfg[MRAM_TXB].num) |
1426	cdev->mcfg[MRAM_TXB].off);
1427	}
1428
1429	/* support 64 bytes payload */
1430	m_can_write(cdev, reg: M_CAN_TXESC,
1431	FIELD_PREP(TXESC_TBDS_MASK, TXESC_TBDS_64B));
1432
1433	/* TX Event FIFO */
1434	if (cdev->version == 30) {
1435	m_can_write(cdev, reg: M_CAN_TXEFC,
1436	FIELD_PREP(TXEFC_EFS_MASK, 1) |
1437	cdev->mcfg[MRAM_TXE].off);
1438	} else {
1439	/* Full TX Event FIFO is used */
1440	m_can_write(cdev, reg: M_CAN_TXEFC,
1441	FIELD_PREP(TXEFC_EFWM_MASK,
1442	cdev->tx_max_coalesced_frames_irq) |
1443	FIELD_PREP(TXEFC_EFS_MASK,
1444	cdev->mcfg[MRAM_TXE].num) |
1445	cdev->mcfg[MRAM_TXE].off);
1446	}
1447
1448	/* rx fifo configuration, blocking mode, fifo size 1 */
1449	m_can_write(cdev, reg: M_CAN_RXF0C,
1450	FIELD_PREP(RXFC_FWM_MASK, cdev->rx_max_coalesced_frames_irq) |
1451	FIELD_PREP(RXFC_FS_MASK, cdev->mcfg[MRAM_RXF0].num) |
1452	cdev->mcfg[MRAM_RXF0].off);
1453
1454	m_can_write(cdev, reg: M_CAN_RXF1C,
1455	FIELD_PREP(RXFC_FS_MASK, cdev->mcfg[MRAM_RXF1].num) |
1456	cdev->mcfg[MRAM_RXF1].off);
1457
1458	cccr = m_can_read(cdev, reg: M_CAN_CCCR);
1459	test = m_can_read(cdev, reg: M_CAN_TEST);
1460	test &= ~TEST_LBCK;
1461	if (cdev->version == 30) {
1462	/* Version 3.0.x */
1463
1464	cccr &= ~(CCCR_TEST | CCCR_MON | CCCR_DAR |
1465	FIELD_PREP(CCCR_CMR_MASK, FIELD_MAX(CCCR_CMR_MASK)) |
1466	FIELD_PREP(CCCR_CME_MASK, FIELD_MAX(CCCR_CME_MASK)));
1467
1468	if (cdev->can.ctrlmode & CAN_CTRLMODE_FD)
1469	cccr |= FIELD_PREP(CCCR_CME_MASK, CCCR_CME_CANFD_BRS);
1470
1471	} else {
1472	/* Version 3.1.x or 3.2.x */
1473	cccr &= ~(CCCR_TEST | CCCR_MON | CCCR_BRSE | CCCR_FDOE |
1474	CCCR_NISO | CCCR_DAR);
1475
1476	/* Only 3.2.x has NISO Bit implemented */
1477	if (cdev->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO)
1478	cccr |= CCCR_NISO;
1479
1480	if (cdev->can.ctrlmode & CAN_CTRLMODE_FD)
1481	cccr |= (CCCR_BRSE | CCCR_FDOE);
1482	}
1483
1484	/* Loopback Mode */
1485	if (cdev->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
1486	cccr |= CCCR_TEST | CCCR_MON;
1487	test |= TEST_LBCK;
1488	}
1489
1490	/* Enable Monitoring (all versions) */
1491	if (cdev->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
1492	cccr |= CCCR_MON;
1493
1494	/* Disable Auto Retransmission (all versions) */
1495	if (cdev->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT)
1496	cccr |= CCCR_DAR;
1497
1498	/* Write config */
1499	m_can_write(cdev, reg: M_CAN_CCCR, val: cccr);
1500	m_can_write(cdev, reg: M_CAN_TEST, val: test);
1501
1502	/* Enable interrupts */
1503	if (!(cdev->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) {
1504	if (cdev->version == 30)
1505	interrupts &= ~(IR_ERR_LEC_30X);
1506	else
1507	interrupts &= ~(IR_ERR_LEC_31X);
1508	}
1509	m_can_interrupt_enable(cdev, interrupts);
1510
1511	/* route all interrupts to INT0 */
1512	m_can_write(cdev, reg: M_CAN_ILS, ILS_ALL_INT0);
1513
1514	/* set bittiming params */
1515	m_can_set_bittiming(dev);
1516
1517	/* enable internal timestamp generation, with a prescaler of 16. The
1518	* prescaler is applied to the nominal bit timing
1519	*/
1520	m_can_write(cdev, reg: M_CAN_TSCC,
1521	FIELD_PREP(TSCC_TCP_MASK, 0xf) |
1522	FIELD_PREP(TSCC_TSS_MASK, TSCC_TSS_INTERNAL));
1523
1524	m_can_config_endisable(cdev, enable: false);
1525
1526	if (cdev->ops->init)
1527	cdev->ops->init(cdev);
1528
1529	return 0;
1530	}
1531
1532	static int m_can_start(struct net_device *dev)
1533	{
1534	struct m_can_classdev *cdev = netdev_priv(dev);
1535	int ret;
1536
1537	/* basic m_can configuration */
1538	ret = m_can_chip_config(dev);
1539	if (ret)
1540	return ret;
1541
1542	netdev_queue_set_dql_min_limit(dev_queue: netdev_get_tx_queue(dev: cdev->net, index: 0),
1543	min_limit: cdev->tx_max_coalesced_frames);
1544
1545	cdev->can.state = CAN_STATE_ERROR_ACTIVE;
1546
1547	m_can_enable_all_interrupts(cdev);
1548
1549	if (cdev->version > 30)
1550	cdev->tx_fifo_putidx = FIELD_GET(TXFQS_TFQPI_MASK,
1551	m_can_read(cdev, M_CAN_TXFQS));
1552
1553	return 0;
1554	}
1555
1556	static int m_can_set_mode(struct net_device *dev, enum can_mode mode)
1557	{
1558	switch (mode) {
1559	case CAN_MODE_START:
1560	m_can_clean(net: dev);
1561	m_can_start(dev);
1562	netif_wake_queue(dev);
1563	break;
1564	default:
1565	return -EOPNOTSUPP;
1566	}
1567
1568	return 0;
1569	}
1570
1571	/* Checks core release number of M_CAN
1572	* returns 0 if an unsupported device is detected
1573	* else it returns the release and step coded as:
1574	* return value = 10 * <release> + 1 * <step>
1575	*/
1576	static int m_can_check_core_release(struct m_can_classdev *cdev)
1577	{
1578	u32 crel_reg;
1579	u8 rel;
1580	u8 step;
1581	int res;
1582
1583	/* Read Core Release Version and split into version number
1584	* Example: Version 3.2.1 => rel = 3; step = 2; substep = 1;
1585	*/
1586	crel_reg = m_can_read(cdev, reg: M_CAN_CREL);
1587	rel = (u8)FIELD_GET(CREL_REL_MASK, crel_reg);
1588	step = (u8)FIELD_GET(CREL_STEP_MASK, crel_reg);
1589
1590	if (rel == 3) {
1591	/* M_CAN v3.x.y: create return value */
1592	res = 30 + step;
1593	} else {
1594	/* Unsupported M_CAN version */
1595	res = 0;
1596	}
1597
1598	return res;
1599	}
1600
1601	/* Selectable Non ISO support only in version 3.2.x
1602	* This function checks if the bit is writable.
1603	*/
1604	static bool m_can_niso_supported(struct m_can_classdev *cdev)
1605	{
1606	u32 cccr_reg, cccr_poll = 0;
1607	int niso_timeout = -ETIMEDOUT;
1608	int i;
1609
1610	m_can_config_endisable(cdev, enable: true);
1611	cccr_reg = m_can_read(cdev, reg: M_CAN_CCCR);
1612	cccr_reg |= CCCR_NISO;
1613	m_can_write(cdev, reg: M_CAN_CCCR, val: cccr_reg);
1614
1615	for (i = 0; i <= 10; i++) {
1616	cccr_poll = m_can_read(cdev, reg: M_CAN_CCCR);
1617	if (cccr_poll == cccr_reg) {
1618	niso_timeout = 0;
1619	break;
1620	}
1621
1622	usleep_range(min: 1, max: 5);
1623	}
1624
1625	/* Clear NISO */
1626	cccr_reg &= ~(CCCR_NISO);
1627	m_can_write(cdev, reg: M_CAN_CCCR, val: cccr_reg);
1628
1629	m_can_config_endisable(cdev, enable: false);
1630
1631	/* return false if time out (-ETIMEDOUT), else return true */
1632	return !niso_timeout;
1633	}
1634
1635	static int m_can_dev_setup(struct m_can_classdev *cdev)
1636	{
1637	struct net_device *dev = cdev->net;
1638	int m_can_version, err;
1639
1640	m_can_version = m_can_check_core_release(cdev);
1641	/* return if unsupported version */
1642	if (!m_can_version) {
1643	dev_err(cdev->dev, "Unsupported version number: %2d",
1644	m_can_version);
1645	return -EINVAL;
1646	}
1647
1648	if (!cdev->is_peripheral)
1649	netif_napi_add(dev, napi: &cdev->napi, poll: m_can_poll);
1650
1651	/* Shared properties of all M_CAN versions */
1652	cdev->version = m_can_version;
1653	cdev->can.do_set_mode = m_can_set_mode;
1654	cdev->can.do_get_berr_counter = m_can_get_berr_counter;
1655
1656	/* Set M_CAN supported operations */
1657	cdev->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
1658	CAN_CTRLMODE_LISTENONLY |
1659	CAN_CTRLMODE_BERR_REPORTING |
1660	CAN_CTRLMODE_FD |
1661	CAN_CTRLMODE_ONE_SHOT;
1662
1663	/* Set properties depending on M_CAN version */
1664	switch (cdev->version) {
1665	case 30:
1666	/* CAN_CTRLMODE_FD_NON_ISO is fixed with M_CAN IP v3.0.x */
1667	err = can_set_static_ctrlmode(dev, CAN_CTRLMODE_FD_NON_ISO);
1668	if (err)
1669	return err;
1670	cdev->can.bittiming_const = &m_can_bittiming_const_30X;
1671	cdev->can.data_bittiming_const = &m_can_data_bittiming_const_30X;
1672	break;
1673	case 31:
1674	/* CAN_CTRLMODE_FD_NON_ISO is fixed with M_CAN IP v3.1.x */
1675	err = can_set_static_ctrlmode(dev, CAN_CTRLMODE_FD_NON_ISO);
1676	if (err)
1677	return err;
1678	cdev->can.bittiming_const = &m_can_bittiming_const_31X;
1679	cdev->can.data_bittiming_const = &m_can_data_bittiming_const_31X;
1680	break;
1681	case 32:
1682	case 33:
1683	/* Support both MCAN version v3.2.x and v3.3.0 */
1684	cdev->can.bittiming_const = &m_can_bittiming_const_31X;
1685	cdev->can.data_bittiming_const = &m_can_data_bittiming_const_31X;
1686
1687	cdev->can.ctrlmode_supported |=
1688	(m_can_niso_supported(cdev) ?
1689	CAN_CTRLMODE_FD_NON_ISO : 0);
1690	break;
1691	default:
1692	dev_err(cdev->dev, "Unsupported version number: %2d",
1693	cdev->version);
1694	return -EINVAL;
1695	}
1696
1697	if (cdev->ops->init)
1698	cdev->ops->init(cdev);
1699
1700	return 0;
1701	}
1702
1703	static void m_can_stop(struct net_device *dev)
1704	{
1705	struct m_can_classdev *cdev = netdev_priv(dev);
1706
1707	/* disable all interrupts */
1708	m_can_disable_all_interrupts(cdev);
1709
1710	/* Set init mode to disengage from the network */
1711	m_can_config_endisable(cdev, enable: true);
1712
1713	/* set the state as STOPPED */
1714	cdev->can.state = CAN_STATE_STOPPED;
1715	}
1716
1717	static int m_can_close(struct net_device *dev)
1718	{
1719	struct m_can_classdev *cdev = netdev_priv(dev);
1720
1721	netif_stop_queue(dev);
1722
1723	if (!cdev->is_peripheral)
1724	napi_disable(n: &cdev->napi);
1725
1726	m_can_stop(dev);
1727	m_can_clk_stop(cdev);
1728	free_irq(dev->irq, dev);
1729
1730	m_can_clean(net: dev);
1731
1732	if (cdev->is_peripheral) {
1733	destroy_workqueue(wq: cdev->tx_wq);
1734	cdev->tx_wq = NULL;
1735	can_rx_offload_disable(offload: &cdev->offload);
1736	}
1737
1738	close_candev(dev);
1739
1740	phy_power_off(phy: cdev->transceiver);
1741
1742	return 0;
1743	}
1744
1745	static netdev_tx_t m_can_tx_handler(struct m_can_classdev *cdev,
1746	struct sk_buff *skb)
1747	{
1748	struct canfd_frame *cf = (struct canfd_frame *)skb->data;
1749	u8 len_padded = DIV_ROUND_UP(cf->len, 4);
1750	struct m_can_fifo_element fifo_element;
1751	struct net_device *dev = cdev->net;
1752	u32 cccr, fdflags;
1753	int err;
1754	u32 putidx;
1755	unsigned int frame_len = can_skb_get_frame_len(skb);
1756
1757	/* Generate ID field for TX buffer Element */
1758	/* Common to all supported M_CAN versions */
1759	if (cf->can_id & CAN_EFF_FLAG) {
1760	fifo_element.id = cf->can_id & CAN_EFF_MASK;
1761	fifo_element.id |= TX_BUF_XTD;
1762	} else {
1763	fifo_element.id = ((cf->can_id & CAN_SFF_MASK) << 18);
1764	}
1765
1766	if (cf->can_id & CAN_RTR_FLAG)
1767	fifo_element.id |= TX_BUF_RTR;
1768
1769	if (cdev->version == 30) {
1770	netif_stop_queue(dev);
1771
1772	fifo_element.dlc = can_fd_len2dlc(len: cf->len) << 16;
1773
1774	/* Write the frame ID, DLC, and payload to the FIFO element. */
1775	err = m_can_fifo_write(cdev, fpi: 0, M_CAN_FIFO_ID, val: &fifo_element, val_count: 2);
1776	if (err)
1777	goto out_fail;
1778
1779	err = m_can_fifo_write(cdev, fpi: 0, M_CAN_FIFO_DATA,
1780	val: cf->data, val_count: len_padded);
1781	if (err)
1782	goto out_fail;
1783
1784	if (cdev->can.ctrlmode & CAN_CTRLMODE_FD) {
1785	cccr = m_can_read(cdev, reg: M_CAN_CCCR);
1786	cccr &= ~CCCR_CMR_MASK;
1787	if (can_is_canfd_skb(skb)) {
1788	if (cf->flags & CANFD_BRS)
1789	cccr |= FIELD_PREP(CCCR_CMR_MASK,
1790	CCCR_CMR_CANFD_BRS);
1791	else
1792	cccr |= FIELD_PREP(CCCR_CMR_MASK,
1793	CCCR_CMR_CANFD);
1794	} else {
1795	cccr |= FIELD_PREP(CCCR_CMR_MASK, CCCR_CMR_CAN);
1796	}
1797	m_can_write(cdev, reg: M_CAN_CCCR, val: cccr);
1798	}
1799	m_can_write(cdev, reg: M_CAN_TXBTIE, val: 0x1);
1800
1801	can_put_echo_skb(skb, dev, idx: 0, frame_len);
1802
1803	m_can_write(cdev, reg: M_CAN_TXBAR, val: 0x1);
1804	/* End of xmit function for version 3.0.x */
1805	} else {
1806	/* Transmit routine for version >= v3.1.x */
1807
1808	/* get put index for frame */
1809	putidx = cdev->tx_fifo_putidx;
1810
1811	/* Construct DLC Field, with CAN-FD configuration.
1812	* Use the put index of the fifo as the message marker,
1813	* used in the TX interrupt for sending the correct echo frame.
1814	*/
1815
1816	/* get CAN FD configuration of frame */
1817	fdflags = 0;
1818	if (can_is_canfd_skb(skb)) {
1819	fdflags |= TX_BUF_FDF;
1820	if (cf->flags & CANFD_BRS)
1821	fdflags |= TX_BUF_BRS;
1822	}
1823
1824	fifo_element.dlc = FIELD_PREP(TX_BUF_MM_MASK, putidx) |
1825	FIELD_PREP(TX_BUF_DLC_MASK, can_fd_len2dlc(cf->len)) |
1826	fdflags | TX_BUF_EFC;
1827
1828	memcpy_and_pad(dest: fifo_element.data, CANFD_MAX_DLEN, src: &cf->data,
1829	count: cf->len, pad: 0);
1830
1831	err = m_can_fifo_write(cdev, fpi: putidx, M_CAN_FIFO_ID,
1832	val: &fifo_element, val_count: 2 + len_padded);
1833	if (err)
1834	goto out_fail;
1835
1836	/* Push loopback echo.
1837	* Will be looped back on TX interrupt based on message marker
1838	*/
1839	can_put_echo_skb(skb, dev, idx: putidx, frame_len);
1840
1841	if (cdev->is_peripheral) {
1842	/* Delay enabling TX FIFO element */
1843	cdev->tx_peripheral_submit |= BIT(putidx);
1844	} else {
1845	/* Enable TX FIFO element to start transfer */
1846	m_can_write(cdev, reg: M_CAN_TXBAR, BIT(putidx));
1847	}
1848	cdev->tx_fifo_putidx = (++cdev->tx_fifo_putidx >= cdev->can.echo_skb_max ?
1849	0 : cdev->tx_fifo_putidx);
1850	}
1851
1852	return NETDEV_TX_OK;
1853
1854	out_fail:
1855	netdev_err(dev, format: "FIFO write returned %d\n", err);
1856	m_can_disable_all_interrupts(cdev);
1857	return NETDEV_TX_BUSY;
1858	}
1859
1860	static void m_can_tx_submit(struct m_can_classdev *cdev)
1861	{
1862	if (cdev->version == 30)
1863	return;
1864	if (!cdev->is_peripheral)
1865	return;
1866
1867	m_can_write(cdev, reg: M_CAN_TXBAR, val: cdev->tx_peripheral_submit);
1868	cdev->tx_peripheral_submit = 0;
1869	}
1870
1871	static void m_can_tx_work_queue(struct work_struct *ws)
1872	{
1873	struct m_can_tx_op *op = container_of(ws, struct m_can_tx_op, work);
1874	struct m_can_classdev *cdev = op->cdev;
1875	struct sk_buff *skb = op->skb;
1876
1877	op->skb = NULL;
1878	m_can_tx_handler(cdev, skb);
1879	if (op->submit)
1880	m_can_tx_submit(cdev);
1881	}
1882
1883	static void m_can_tx_queue_skb(struct m_can_classdev *cdev, struct sk_buff *skb,
1884	bool submit)
1885	{
1886	cdev->tx_ops[cdev->next_tx_op].skb = skb;
1887	cdev->tx_ops[cdev->next_tx_op].submit = submit;
1888	queue_work(wq: cdev->tx_wq, work: &cdev->tx_ops[cdev->next_tx_op].work);
1889
1890	++cdev->next_tx_op;
1891	if (cdev->next_tx_op >= cdev->tx_fifo_size)
1892	cdev->next_tx_op = 0;
1893	}
1894
1895	static netdev_tx_t m_can_start_peripheral_xmit(struct m_can_classdev *cdev,
1896	struct sk_buff *skb)
1897	{
1898	bool submit;
1899
1900	++cdev->nr_txs_without_submit;
1901	if (cdev->nr_txs_without_submit >= cdev->tx_max_coalesced_frames ||
1902	!netdev_xmit_more()) {
1903	cdev->nr_txs_without_submit = 0;
1904	submit = true;
1905	} else {
1906	submit = false;
1907	}
1908	m_can_tx_queue_skb(cdev, skb, submit);
1909
1910	return NETDEV_TX_OK;
1911	}
1912
1913	static netdev_tx_t m_can_start_xmit(struct sk_buff *skb,
1914	struct net_device *dev)
1915	{
1916	struct m_can_classdev *cdev = netdev_priv(dev);
1917	unsigned int frame_len;
1918	netdev_tx_t ret;
1919
1920	if (can_dev_dropped_skb(dev, skb))
1921	return NETDEV_TX_OK;
1922
1923	frame_len = can_skb_get_frame_len(skb);
1924
1925	if (cdev->can.state == CAN_STATE_BUS_OFF) {
1926	m_can_clean(net: cdev->net);
1927	return NETDEV_TX_OK;
1928	}
1929
1930	ret = m_can_start_tx(cdev);
1931	if (ret != NETDEV_TX_OK)
1932	return ret;
1933
1934	netdev_sent_queue(dev, bytes: frame_len);
1935
1936	if (cdev->is_peripheral)
1937	ret = m_can_start_peripheral_xmit(cdev, skb);
1938	else
1939	ret = m_can_tx_handler(cdev, skb);
1940
1941	if (ret != NETDEV_TX_OK)
1942	netdev_completed_queue(dev, pkts: 1, bytes: frame_len);
1943
1944	return ret;
1945	}
1946
1947	static enum hrtimer_restart hrtimer_callback(struct hrtimer *timer)
1948	{
1949	struct m_can_classdev *cdev = container_of(timer, struct
1950	m_can_classdev, hrtimer);
1951
1952	m_can_isr(irq: 0, dev_id: cdev->net);
1953
1954	hrtimer_forward_now(timer, interval: ms_to_ktime(HRTIMER_POLL_INTERVAL_MS));
1955
1956	return HRTIMER_RESTART;
1957	}
1958
1959	static int m_can_open(struct net_device *dev)
1960	{
1961	struct m_can_classdev *cdev = netdev_priv(dev);
1962	int err;
1963
1964	err = phy_power_on(phy: cdev->transceiver);
1965	if (err)
1966	return err;
1967
1968	err = m_can_clk_start(cdev);
1969	if (err)
1970	goto out_phy_power_off;
1971
1972	/* open the can device */
1973	err = open_candev(dev);
1974	if (err) {
1975	netdev_err(dev, format: "failed to open can device\n");
1976	goto exit_disable_clks;
1977	}
1978
1979	if (cdev->is_peripheral)
1980	can_rx_offload_enable(offload: &cdev->offload);
1981
1982	/* register interrupt handler */
1983	if (cdev->is_peripheral) {
1984	cdev->tx_wq = alloc_ordered_workqueue("mcan_wq",
1985	WQ_FREEZABLE | WQ_MEM_RECLAIM);
1986	if (!cdev->tx_wq) {
1987	err = -ENOMEM;
1988	goto out_wq_fail;
1989	}
1990
1991	for (int i = 0; i != cdev->tx_fifo_size; ++i) {
1992	cdev->tx_ops[i].cdev = cdev;
1993	INIT_WORK(&cdev->tx_ops[i].work, m_can_tx_work_queue);
1994	}
1995
1996	err = request_threaded_irq(irq: dev->irq, NULL, thread_fn: m_can_isr,
1997	IRQF_ONESHOT,
1998	name: dev->name, dev);
1999	} else if (dev->irq) {
2000	err = request_irq(irq: dev->irq, handler: m_can_isr, IRQF_SHARED, name: dev->name,
2001	dev);
2002	}
2003
2004	if (err < 0) {
2005	netdev_err(dev, format: "failed to request interrupt\n");
2006	goto exit_irq_fail;
2007	}
2008
2009	/* start the m_can controller */
2010	err = m_can_start(dev);
2011	if (err)
2012	goto exit_irq_fail;
2013
2014	if (!cdev->is_peripheral)
2015	napi_enable(n: &cdev->napi);
2016
2017	netif_start_queue(dev);
2018
2019	return 0;
2020
2021	exit_irq_fail:
2022	if (cdev->is_peripheral)
2023	destroy_workqueue(wq: cdev->tx_wq);
2024	out_wq_fail:
2025	if (cdev->is_peripheral)
2026	can_rx_offload_disable(offload: &cdev->offload);
2027	close_candev(dev);
2028	exit_disable_clks:
2029	m_can_clk_stop(cdev);
2030	out_phy_power_off:
2031	phy_power_off(phy: cdev->transceiver);
2032	return err;
2033	}
2034
2035	static const struct net_device_ops m_can_netdev_ops = {
2036	.ndo_open = m_can_open,
2037	.ndo_stop = m_can_close,
2038	.ndo_start_xmit = m_can_start_xmit,
2039	.ndo_change_mtu = can_change_mtu,
2040	};
2041
2042	static int m_can_get_coalesce(struct net_device *dev,
2043	struct ethtool_coalesce *ec,
2044	struct kernel_ethtool_coalesce *kec,
2045	struct netlink_ext_ack *ext_ack)
2046	{
2047	struct m_can_classdev *cdev = netdev_priv(dev);
2048
2049	ec->rx_max_coalesced_frames_irq = cdev->rx_max_coalesced_frames_irq;
2050	ec->rx_coalesce_usecs_irq = cdev->rx_coalesce_usecs_irq;
2051	ec->tx_max_coalesced_frames = cdev->tx_max_coalesced_frames;
2052	ec->tx_max_coalesced_frames_irq = cdev->tx_max_coalesced_frames_irq;
2053	ec->tx_coalesce_usecs_irq = cdev->tx_coalesce_usecs_irq;
2054
2055	return 0;
2056	}
2057
2058	static int m_can_set_coalesce(struct net_device *dev,
2059	struct ethtool_coalesce *ec,
2060	struct kernel_ethtool_coalesce *kec,
2061	struct netlink_ext_ack *ext_ack)
2062	{
2063	struct m_can_classdev *cdev = netdev_priv(dev);
2064
2065	if (cdev->can.state != CAN_STATE_STOPPED) {
2066	netdev_err(dev, format: "Device is in use, please shut it down first\n");
2067	return -EBUSY;
2068	}
2069
2070	if (ec->rx_max_coalesced_frames_irq > cdev->mcfg[MRAM_RXF0].num) {
2071	netdev_err(dev, format: "rx-frames-irq %u greater than the RX FIFO %u\n",
2072	ec->rx_max_coalesced_frames_irq,
2073	cdev->mcfg[MRAM_RXF0].num);
2074	return -EINVAL;
2075	}
2076	if ((ec->rx_max_coalesced_frames_irq == 0) != (ec->rx_coalesce_usecs_irq == 0)) {
2077	netdev_err(dev, format: "rx-frames-irq and rx-usecs-irq can only be set together\n");
2078	return -EINVAL;
2079	}
2080	if (ec->tx_max_coalesced_frames_irq > cdev->mcfg[MRAM_TXE].num) {
2081	netdev_err(dev, format: "tx-frames-irq %u greater than the TX event FIFO %u\n",
2082	ec->tx_max_coalesced_frames_irq,
2083	cdev->mcfg[MRAM_TXE].num);
2084	return -EINVAL;
2085	}
2086	if (ec->tx_max_coalesced_frames_irq > cdev->mcfg[MRAM_TXB].num) {
2087	netdev_err(dev, format: "tx-frames-irq %u greater than the TX FIFO %u\n",
2088	ec->tx_max_coalesced_frames_irq,
2089	cdev->mcfg[MRAM_TXB].num);
2090	return -EINVAL;
2091	}
2092	if ((ec->tx_max_coalesced_frames_irq == 0) != (ec->tx_coalesce_usecs_irq == 0)) {
2093	netdev_err(dev, format: "tx-frames-irq and tx-usecs-irq can only be set together\n");
2094	return -EINVAL;
2095	}
2096	if (ec->tx_max_coalesced_frames > cdev->mcfg[MRAM_TXE].num) {
2097	netdev_err(dev, format: "tx-frames %u greater than the TX event FIFO %u\n",
2098	ec->tx_max_coalesced_frames,
2099	cdev->mcfg[MRAM_TXE].num);
2100	return -EINVAL;
2101	}
2102	if (ec->tx_max_coalesced_frames > cdev->mcfg[MRAM_TXB].num) {
2103	netdev_err(dev, format: "tx-frames %u greater than the TX FIFO %u\n",
2104	ec->tx_max_coalesced_frames,
2105	cdev->mcfg[MRAM_TXB].num);
2106	return -EINVAL;
2107	}
2108	if (ec->rx_coalesce_usecs_irq != 0 && ec->tx_coalesce_usecs_irq != 0 &&
2109	ec->rx_coalesce_usecs_irq != ec->tx_coalesce_usecs_irq) {
2110	netdev_err(dev, format: "rx-usecs-irq %u needs to be equal to tx-usecs-irq %u if both are enabled\n",
2111	ec->rx_coalesce_usecs_irq,
2112	ec->tx_coalesce_usecs_irq);
2113	return -EINVAL;
2114	}
2115
2116	cdev->rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
2117	cdev->rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
2118	cdev->tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
2119	cdev->tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
2120	cdev->tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
2121
2122	if (cdev->rx_coalesce_usecs_irq)
2123	cdev->irq_timer_wait =
2124	ns_to_ktime(ns: cdev->rx_coalesce_usecs_irq * NSEC_PER_USEC);
2125	else
2126	cdev->irq_timer_wait =
2127	ns_to_ktime(ns: cdev->tx_coalesce_usecs_irq * NSEC_PER_USEC);
2128
2129	return 0;
2130	}
2131
2132	static const struct ethtool_ops m_can_ethtool_ops = {
2133	.supported_coalesce_params = ETHTOOL_COALESCE_RX_USECS_IRQ |
2134	ETHTOOL_COALESCE_RX_MAX_FRAMES_IRQ |
2135	ETHTOOL_COALESCE_TX_USECS_IRQ |
2136	ETHTOOL_COALESCE_TX_MAX_FRAMES |
2137	ETHTOOL_COALESCE_TX_MAX_FRAMES_IRQ,
2138	.get_ts_info = ethtool_op_get_ts_info,
2139	.get_coalesce = m_can_get_coalesce,
2140	.set_coalesce = m_can_set_coalesce,
2141	};
2142
2143	static const struct ethtool_ops m_can_ethtool_ops_polling = {
2144	.get_ts_info = ethtool_op_get_ts_info,
2145	};
2146
2147	static int register_m_can_dev(struct net_device *dev)
2148	{
2149	dev->flags |= IFF_ECHO; /* we support local echo */
2150	dev->netdev_ops = &m_can_netdev_ops;
2151	if (dev->irq)
2152	dev->ethtool_ops = &m_can_ethtool_ops;
2153	else
2154	dev->ethtool_ops = &m_can_ethtool_ops_polling;
2155
2156	return register_candev(dev);
2157	}
2158
2159	int m_can_check_mram_cfg(struct m_can_classdev *cdev, u32 mram_max_size)
2160	{
2161	u32 total_size;
2162
2163	total_size = cdev->mcfg[MRAM_TXB].off - cdev->mcfg[MRAM_SIDF].off +
2164	cdev->mcfg[MRAM_TXB].num * TXB_ELEMENT_SIZE;
2165	if (total_size > mram_max_size) {
2166	dev_err(cdev->dev, "Total size of mram config(%u) exceeds mram(%u)\n",
2167	total_size, mram_max_size);
2168	return -EINVAL;
2169	}
2170
2171	return 0;
2172	}
2173	EXPORT_SYMBOL_GPL(m_can_check_mram_cfg);
2174
2175	static void m_can_of_parse_mram(struct m_can_classdev *cdev,
2176	const u32 *mram_config_vals)
2177	{
2178	cdev->mcfg[MRAM_SIDF].off = mram_config_vals[0];
2179	cdev->mcfg[MRAM_SIDF].num = mram_config_vals[1];
2180	cdev->mcfg[MRAM_XIDF].off = cdev->mcfg[MRAM_SIDF].off +
2181	cdev->mcfg[MRAM_SIDF].num * SIDF_ELEMENT_SIZE;
2182	cdev->mcfg[MRAM_XIDF].num = mram_config_vals[2];
2183	cdev->mcfg[MRAM_RXF0].off = cdev->mcfg[MRAM_XIDF].off +
2184	cdev->mcfg[MRAM_XIDF].num * XIDF_ELEMENT_SIZE;
2185	cdev->mcfg[MRAM_RXF0].num = mram_config_vals[3] &
2186	FIELD_MAX(RXFC_FS_MASK);
2187	cdev->mcfg[MRAM_RXF1].off = cdev->mcfg[MRAM_RXF0].off +
2188	cdev->mcfg[MRAM_RXF0].num * RXF0_ELEMENT_SIZE;
2189	cdev->mcfg[MRAM_RXF1].num = mram_config_vals[4] &
2190	FIELD_MAX(RXFC_FS_MASK);
2191	cdev->mcfg[MRAM_RXB].off = cdev->mcfg[MRAM_RXF1].off +
2192	cdev->mcfg[MRAM_RXF1].num * RXF1_ELEMENT_SIZE;
2193	cdev->mcfg[MRAM_RXB].num = mram_config_vals[5];
2194	cdev->mcfg[MRAM_TXE].off = cdev->mcfg[MRAM_RXB].off +
2195	cdev->mcfg[MRAM_RXB].num * RXB_ELEMENT_SIZE;
2196	cdev->mcfg[MRAM_TXE].num = mram_config_vals[6];
2197	cdev->mcfg[MRAM_TXB].off = cdev->mcfg[MRAM_TXE].off +
2198	cdev->mcfg[MRAM_TXE].num * TXE_ELEMENT_SIZE;
2199	cdev->mcfg[MRAM_TXB].num = mram_config_vals[7] &
2200	FIELD_MAX(TXBC_NDTB_MASK);
2201
2202	dev_dbg(cdev->dev,
2203	"sidf 0x%x %d xidf 0x%x %d rxf0 0x%x %d rxf1 0x%x %d rxb 0x%x %d txe 0x%x %d txb 0x%x %d\n",
2204	cdev->mcfg[MRAM_SIDF].off, cdev->mcfg[MRAM_SIDF].num,
2205	cdev->mcfg[MRAM_XIDF].off, cdev->mcfg[MRAM_XIDF].num,
2206	cdev->mcfg[MRAM_RXF0].off, cdev->mcfg[MRAM_RXF0].num,
2207	cdev->mcfg[MRAM_RXF1].off, cdev->mcfg[MRAM_RXF1].num,
2208	cdev->mcfg[MRAM_RXB].off, cdev->mcfg[MRAM_RXB].num,
2209	cdev->mcfg[MRAM_TXE].off, cdev->mcfg[MRAM_TXE].num,
2210	cdev->mcfg[MRAM_TXB].off, cdev->mcfg[MRAM_TXB].num);
2211	}
2212
2213	int m_can_init_ram(struct m_can_classdev *cdev)
2214	{
2215	int end, i, start;
2216	int err = 0;
2217
2218	/* initialize the entire Message RAM in use to avoid possible
2219	* ECC/parity checksum errors when reading an uninitialized buffer
2220	*/
2221	start = cdev->mcfg[MRAM_SIDF].off;
2222	end = cdev->mcfg[MRAM_TXB].off +
2223	cdev->mcfg[MRAM_TXB].num * TXB_ELEMENT_SIZE;
2224
2225	for (i = start; i < end; i += 4) {
2226	err = m_can_fifo_write_no_off(cdev, fpi: i, val: 0x0);
2227	if (err)
2228	break;
2229	}
2230
2231	return err;
2232	}
2233	EXPORT_SYMBOL_GPL(m_can_init_ram);
2234
2235	int m_can_class_get_clocks(struct m_can_classdev *cdev)
2236	{
2237	int ret = 0;
2238
2239	cdev->hclk = devm_clk_get(dev: cdev->dev, id: "hclk");
2240	cdev->cclk = devm_clk_get(dev: cdev->dev, id: "cclk");
2241
2242	if (IS_ERR(ptr: cdev->hclk) || IS_ERR(ptr: cdev->cclk)) {
2243	dev_err(cdev->dev, "no clock found\n");
2244	ret = -ENODEV;
2245	}
2246
2247	return ret;
2248	}
2249	EXPORT_SYMBOL_GPL(m_can_class_get_clocks);
2250
2251	struct m_can_classdev *m_can_class_allocate_dev(struct device *dev,
2252	int sizeof_priv)
2253	{
2254	struct m_can_classdev *class_dev = NULL;
2255	u32 mram_config_vals[MRAM_CFG_LEN];
2256	struct net_device *net_dev;
2257	u32 tx_fifo_size;
2258	int ret;
2259
2260	ret = fwnode_property_read_u32_array(dev_fwnode(dev),
2261	propname: "bosch,mram-cfg",
2262	val: mram_config_vals,
2263	nval: sizeof(mram_config_vals) / 4);
2264	if (ret) {
2265	dev_err(dev, "Could not get Message RAM configuration.");
2266	goto out;
2267	}
2268
2269	/* Get TX FIFO size
2270	* Defines the total amount of echo buffers for loopback
2271	*/
2272	tx_fifo_size = mram_config_vals[7];
2273
2274	/* allocate the m_can device */
2275	net_dev = alloc_candev(sizeof_priv, tx_fifo_size);
2276	if (!net_dev) {
2277	dev_err(dev, "Failed to allocate CAN device");
2278	goto out;
2279	}
2280
2281	class_dev = netdev_priv(dev: net_dev);
2282	class_dev->net = net_dev;
2283	class_dev->dev = dev;
2284	SET_NETDEV_DEV(net_dev, dev);
2285
2286	m_can_of_parse_mram(cdev: class_dev, mram_config_vals);
2287	out:
2288	return class_dev;
2289	}
2290	EXPORT_SYMBOL_GPL(m_can_class_allocate_dev);
2291
2292	void m_can_class_free_dev(struct net_device *net)
2293	{
2294	free_candev(dev: net);
2295	}
2296	EXPORT_SYMBOL_GPL(m_can_class_free_dev);
2297
2298	int m_can_class_register(struct m_can_classdev *cdev)
2299	{
2300	int ret;
2301
2302	cdev->tx_fifo_size = max(1, min(cdev->mcfg[MRAM_TXB].num,
2303	cdev->mcfg[MRAM_TXE].num));
2304	if (cdev->is_peripheral) {
2305	cdev->tx_ops =
2306	devm_kzalloc(dev: cdev->dev,
2307	size: cdev->tx_fifo_size * sizeof(*cdev->tx_ops),
2308	GFP_KERNEL);
2309	if (!cdev->tx_ops) {
2310	dev_err(cdev->dev, "Failed to allocate tx_ops for workqueue\n");
2311	return -ENOMEM;
2312	}
2313	}
2314
2315	ret = m_can_clk_start(cdev);
2316	if (ret)
2317	return ret;
2318
2319	if (cdev->is_peripheral) {
2320	ret = can_rx_offload_add_manual(dev: cdev->net, offload: &cdev->offload,
2321	NAPI_POLL_WEIGHT);
2322	if (ret)
2323	goto clk_disable;
2324	}
2325
2326	if (!cdev->net->irq) {
2327	dev_dbg(cdev->dev, "Polling enabled, initialize hrtimer");
2328	hrtimer_init(timer: &cdev->hrtimer, CLOCK_MONOTONIC,
2329	mode: HRTIMER_MODE_REL_PINNED);
2330	cdev->hrtimer.function = &hrtimer_callback;
2331	} else {
2332	hrtimer_init(timer: &cdev->hrtimer, CLOCK_MONOTONIC, mode: HRTIMER_MODE_REL);
2333	cdev->hrtimer.function = m_can_coalescing_timer;
2334	}
2335
2336	ret = m_can_dev_setup(cdev);
2337	if (ret)
2338	goto rx_offload_del;
2339
2340	ret = register_m_can_dev(dev: cdev->net);
2341	if (ret) {
2342	dev_err(cdev->dev, "registering %s failed (err=%d)\n",
2343	cdev->net->name, ret);
2344	goto rx_offload_del;
2345	}
2346
2347	of_can_transceiver(dev: cdev->net);
2348
2349	dev_info(cdev->dev, "%s device registered (irq=%d, version=%d)\n",
2350	KBUILD_MODNAME, cdev->net->irq, cdev->version);
2351
2352	/* Probe finished
2353	* Stop clocks. They will be reactivated once the M_CAN device is opened
2354	*/
2355	m_can_clk_stop(cdev);
2356
2357	return 0;
2358
2359	rx_offload_del:
2360	if (cdev->is_peripheral)
2361	can_rx_offload_del(offload: &cdev->offload);
2362	clk_disable:
2363	m_can_clk_stop(cdev);
2364
2365	return ret;
2366	}
2367	EXPORT_SYMBOL_GPL(m_can_class_register);
2368
2369	void m_can_class_unregister(struct m_can_classdev *cdev)
2370	{
2371	if (cdev->is_peripheral)
2372	can_rx_offload_del(offload: &cdev->offload);
2373	unregister_candev(dev: cdev->net);
2374	}
2375	EXPORT_SYMBOL_GPL(m_can_class_unregister);
2376
2377	int m_can_class_suspend(struct device *dev)
2378	{
2379	struct m_can_classdev *cdev = dev_get_drvdata(dev);
2380	struct net_device *ndev = cdev->net;
2381
2382	if (netif_running(dev: ndev)) {
2383	netif_stop_queue(dev: ndev);
2384	netif_device_detach(dev: ndev);
2385
2386	/* leave the chip running with rx interrupt enabled if it is
2387	* used as a wake-up source.
2388	*/
2389	if (cdev->pm_wake_source)
2390	m_can_write(cdev, reg: M_CAN_IE, IR_RF0N);
2391	else
2392	m_can_stop(dev: ndev);
2393
2394	m_can_clk_stop(cdev);
2395	}
2396
2397	pinctrl_pm_select_sleep_state(dev);
2398
2399	cdev->can.state = CAN_STATE_SLEEPING;
2400
2401	return 0;
2402	}
2403	EXPORT_SYMBOL_GPL(m_can_class_suspend);
2404
2405	int m_can_class_resume(struct device *dev)
2406	{
2407	struct m_can_classdev *cdev = dev_get_drvdata(dev);
2408	struct net_device *ndev = cdev->net;
2409
2410	pinctrl_pm_select_default_state(dev);
2411
2412	cdev->can.state = CAN_STATE_ERROR_ACTIVE;
2413
2414	if (netif_running(dev: ndev)) {
2415	int ret;
2416
2417	ret = m_can_clk_start(cdev);
2418	if (ret)
2419	return ret;
2420
2421	if (cdev->pm_wake_source) {
2422	m_can_write(cdev, reg: M_CAN_IE, val: cdev->active_interrupts);
2423	} else {
2424	ret = m_can_start(dev: ndev);
2425	if (ret) {
2426	m_can_clk_stop(cdev);
2427	return ret;
2428	}
2429	}
2430
2431	netif_device_attach(dev: ndev);
2432	netif_start_queue(dev: ndev);
2433	}
2434
2435	return 0;
2436	}
2437	EXPORT_SYMBOL_GPL(m_can_class_resume);
2438
2439	MODULE_AUTHOR("Dong Aisheng <b29396@freescale.com>");
2440	MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com>");
2441	MODULE_LICENSE("GPL v2");
2442	MODULE_DESCRIPTION("CAN bus driver for Bosch M_CAN controller");
2443