| 1 | /* |
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| 2 | * B53 register definitions |
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| 3 | * |
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| 4 | * Copyright (C) 2004 Broadcom Corporation |
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| 5 | * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org> |
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| 6 | * |
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| 7 | * Permission to use, copy, modify, and/or distribute this software for any |
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| 8 | * purpose with or without fee is hereby granted, provided that the above |
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| 9 | * copyright notice and this permission notice appear in all copies. |
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| 10 | * |
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| 11 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
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| 12 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
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| 13 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
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| 14 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
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| 15 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
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| 16 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
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| 17 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
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| 18 | */ |
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| 19 | |
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| 20 | #ifndef __B53_REGS_H |
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| 21 | #define __B53_REGS_H |
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| 22 | |
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| 23 | /* Management Port (SMP) Page offsets */ |
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| 24 | #define B53_CTRL_PAGE 0x00 /* Control */ |
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| 25 | #define B53_STAT_PAGE 0x01 /* Status */ |
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| 26 | #define B53_MGMT_PAGE 0x02 /* Management Mode */ |
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| 27 | #define B53_MIB_AC_PAGE 0x03 /* MIB Autocast */ |
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| 28 | #define B53_ARLCTRL_PAGE 0x04 /* ARL Control */ |
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| 29 | #define B53_ARLIO_PAGE 0x05 /* ARL Access */ |
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| 30 | #define B53_FRAMEBUF_PAGE 0x06 /* Management frame access */ |
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| 31 | #define B53_MEM_ACCESS_PAGE 0x08 /* Memory access */ |
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| 32 | |
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| 33 | /* PHY Registers */ |
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| 34 | #define B53_PORT_MII_PAGE(i) (0x10 + (i)) /* Port i MII Registers */ |
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| 35 | #define B53_IM_PORT_PAGE 0x18 /* Inverse MII Port (to EMAC) */ |
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| 36 | #define B53_ALL_PORT_PAGE 0x19 /* All ports MII (broadcast) */ |
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| 37 | |
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| 38 | /* MIB registers */ |
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| 39 | #define B53_MIB_PAGE(i) (0x20 + (i)) |
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| 40 | |
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| 41 | /* Quality of Service (QoS) Registers */ |
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| 42 | #define B53_QOS_PAGE 0x30 |
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| 43 | |
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| 44 | /* Port VLAN Page */ |
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| 45 | #define B53_PVLAN_PAGE 0x31 |
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| 46 | |
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| 47 | /* VLAN Registers */ |
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| 48 | #define B53_VLAN_PAGE 0x34 |
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| 49 | |
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| 50 | /* Jumbo Frame Registers */ |
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| 51 | #define B53_JUMBO_PAGE 0x40 |
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| 52 | |
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| 53 | /* EEE Control Registers Page */ |
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| 54 | #define B53_EEE_PAGE 0x92 |
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| 55 | |
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| 56 | /* CFP Configuration Registers Page */ |
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| 57 | #define B53_CFP_PAGE 0xa1 |
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| 58 | |
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| 59 | /************************************************************************* |
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| 60 | * Control Page registers |
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| 61 | *************************************************************************/ |
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| 62 | |
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| 63 | /* Port Control Register (8 bit) */ |
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| 64 | #define B53_PORT_CTRL(i) (0x00 + (i)) |
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| 65 | #define PORT_CTRL_RX_DISABLE BIT(0) |
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| 66 | #define PORT_CTRL_TX_DISABLE BIT(1) |
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| 67 | #define PORT_CTRL_RX_BCST_EN BIT(2) /* Broadcast RX (P8 only) */ |
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| 68 | #define PORT_CTRL_RX_MCST_EN BIT(3) /* Multicast RX (P8 only) */ |
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| 69 | #define PORT_CTRL_RX_UCST_EN BIT(4) /* Unicast RX (P8 only) */ |
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| 70 | #define PORT_CTRL_STP_STATE_S 5 |
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| 71 | #define PORT_CTRL_NO_STP (0 << PORT_CTRL_STP_STATE_S) |
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| 72 | #define PORT_CTRL_DIS_STATE (1 << PORT_CTRL_STP_STATE_S) |
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| 73 | #define PORT_CTRL_BLOCK_STATE (2 << PORT_CTRL_STP_STATE_S) |
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| 74 | #define PORT_CTRL_LISTEN_STATE (3 << PORT_CTRL_STP_STATE_S) |
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| 75 | #define PORT_CTRL_LEARN_STATE (4 << PORT_CTRL_STP_STATE_S) |
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| 76 | #define PORT_CTRL_FWD_STATE (5 << PORT_CTRL_STP_STATE_S) |
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| 77 | #define PORT_CTRL_STP_STATE_MASK (0x7 << PORT_CTRL_STP_STATE_S) |
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| 78 | |
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| 79 | /* SMP Control Register (8 bit) */ |
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| 80 | #define B53_SMP_CTRL 0x0a |
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| 81 | |
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| 82 | /* Switch Mode Control Register (8 bit) */ |
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| 83 | #define B53_SWITCH_MODE 0x0b |
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| 84 | #define SM_SW_FWD_MODE BIT(0) /* 1 = Managed Mode */ |
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| 85 | #define SM_SW_FWD_EN BIT(1) /* Forwarding Enable */ |
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| 86 | |
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| 87 | /* IMP Port state override register (8 bit) */ |
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| 88 | #define B53_PORT_OVERRIDE_CTRL 0x0e |
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| 89 | #define PORT_OVERRIDE_LINK BIT(0) |
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| 90 | #define PORT_OVERRIDE_FULL_DUPLEX BIT(1) /* 0 = Half Duplex */ |
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| 91 | #define PORT_OVERRIDE_SPEED_S 2 |
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| 92 | #define PORT_OVERRIDE_SPEED_10M (0 << PORT_OVERRIDE_SPEED_S) |
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| 93 | #define PORT_OVERRIDE_SPEED_100M (1 << PORT_OVERRIDE_SPEED_S) |
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| 94 | #define PORT_OVERRIDE_SPEED_1000M (2 << PORT_OVERRIDE_SPEED_S) |
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| 95 | #define PORT_OVERRIDE_RV_MII_25 BIT(4) /* BCM5325 only */ |
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| 96 | #define PORT_OVERRIDE_RX_FLOW BIT(4) |
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| 97 | #define PORT_OVERRIDE_TX_FLOW BIT(5) |
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| 98 | #define PORT_OVERRIDE_SPEED_2000M BIT(6) /* BCM5301X only, requires setting 1000M */ |
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| 99 | #define PORT_OVERRIDE_EN BIT(7) /* Use the register contents */ |
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| 100 | |
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| 101 | /* Power-down mode control */ |
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| 102 | #define B53_PD_MODE_CTRL_25 0x0f |
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| 103 | |
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| 104 | /* IP Multicast control (8 bit) */ |
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| 105 | #define B53_IP_MULTICAST_CTRL 0x21 |
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| 106 | #define B53_IPMC_FWD_EN BIT(1) |
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| 107 | #define B53_UC_FWD_EN BIT(6) |
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| 108 | #define B53_MC_FWD_EN BIT(7) |
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| 109 | |
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| 110 | /* Switch control (8 bit) */ |
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| 111 | #define B53_SWITCH_CTRL 0x22 |
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| 112 | #define B53_MII_DUMB_FWDG_EN BIT(6) |
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| 113 | |
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| 114 | /* (16 bit) */ |
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| 115 | #define B53_UC_FLOOD_MASK 0x32 |
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| 116 | #define B53_MC_FLOOD_MASK 0x34 |
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| 117 | #define B53_IPMC_FLOOD_MASK 0x36 |
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| 118 | #define B53_DIS_LEARNING 0x3c |
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| 119 | |
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| 120 | /* |
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| 121 | * Override Ports 0-7 State on devices with xMII interfaces (8 bit) |
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| 122 | * |
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| 123 | * For port 8 still use B53_PORT_OVERRIDE_CTRL |
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| 124 | * Please note that not all ports are available on every hardware, e.g. BCM5301X |
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| 125 | * don't include overriding port 6, BCM63xx also have some limitations. |
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| 126 | */ |
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| 127 | #define B53_GMII_PORT_OVERRIDE_CTRL(i) (0x58 + (i)) |
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| 128 | #define GMII_PO_LINK BIT(0) |
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| 129 | #define GMII_PO_FULL_DUPLEX BIT(1) /* 0 = Half Duplex */ |
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| 130 | #define GMII_PO_SPEED_S 2 |
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| 131 | #define GMII_PO_SPEED_10M (0 << GMII_PO_SPEED_S) |
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| 132 | #define GMII_PO_SPEED_100M (1 << GMII_PO_SPEED_S) |
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| 133 | #define GMII_PO_SPEED_1000M (2 << GMII_PO_SPEED_S) |
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| 134 | #define GMII_PO_RX_FLOW BIT(4) |
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| 135 | #define GMII_PO_TX_FLOW BIT(5) |
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| 136 | #define GMII_PO_EN BIT(6) /* Use the register contents */ |
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| 137 | #define GMII_PO_SPEED_2000M BIT(7) /* BCM5301X only, requires setting 1000M */ |
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| 138 | |
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| 139 | #define B53_RGMII_CTRL_IMP 0x60 |
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| 140 | #define RGMII_CTRL_ENABLE_GMII BIT(7) |
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| 141 | #define RGMII_CTRL_MII_OVERRIDE BIT(6) |
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| 142 | #define RGMII_CTRL_TIMING_SEL BIT(2) |
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| 143 | #define RGMII_CTRL_DLL_RXC BIT(1) |
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| 144 | #define RGMII_CTRL_DLL_TXC BIT(0) |
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| 145 | |
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| 146 | #define B53_RGMII_CTRL_P(i) (B53_RGMII_CTRL_IMP + (i)) |
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| 147 | |
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| 148 | /* Software reset register (8 bit) */ |
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| 149 | #define B53_SOFTRESET 0x79 |
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| 150 | #define SW_RST BIT(7) |
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| 151 | #define EN_CH_RST BIT(6) |
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| 152 | #define EN_SW_RST BIT(4) |
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| 153 | |
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| 154 | /* Fast Aging Control register (8 bit) */ |
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| 155 | #define B53_FAST_AGE_CTRL 0x88 |
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| 156 | #define FAST_AGE_STATIC BIT(0) |
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| 157 | #define FAST_AGE_DYNAMIC BIT(1) |
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| 158 | #define FAST_AGE_PORT BIT(2) |
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| 159 | #define FAST_AGE_VLAN BIT(3) |
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| 160 | #define FAST_AGE_STP BIT(4) |
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| 161 | #define FAST_AGE_MC BIT(5) |
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| 162 | #define FAST_AGE_DONE BIT(7) |
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| 163 | |
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| 164 | /* Fast Aging Port Control register (8 bit) */ |
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| 165 | #define B53_FAST_AGE_PORT_CTRL 0x89 |
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| 166 | |
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| 167 | /* Fast Aging VID Control register (16 bit) */ |
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| 168 | #define B53_FAST_AGE_VID_CTRL 0x8a |
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| 169 | |
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| 170 | /************************************************************************* |
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| 171 | * Status Page registers |
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| 172 | *************************************************************************/ |
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| 173 | |
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| 174 | /* Link Status Summary Register (16bit) */ |
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| 175 | #define B53_LINK_STAT 0x00 |
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| 176 | |
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| 177 | /* Link Status Change Register (16 bit) */ |
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| 178 | #define B53_LINK_STAT_CHANGE 0x02 |
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| 179 | |
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| 180 | /* Port Speed Summary Register (16 bit for FE, 32 bit for GE) */ |
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| 181 | #define B53_SPEED_STAT 0x04 |
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| 182 | #define SPEED_PORT_FE(reg, port) (((reg) >> (port)) & 1) |
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| 183 | #define SPEED_PORT_GE(reg, port) (((reg) >> 2 * (port)) & 3) |
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| 184 | #define SPEED_STAT_10M 0 |
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| 185 | #define SPEED_STAT_100M 1 |
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| 186 | #define SPEED_STAT_1000M 2 |
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| 187 | |
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| 188 | /* Duplex Status Summary (16 bit) */ |
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| 189 | #define B53_DUPLEX_STAT_FE 0x06 |
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| 190 | #define B53_DUPLEX_STAT_GE 0x08 |
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| 191 | #define B53_DUPLEX_STAT_63XX 0x0c |
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| 192 | |
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| 193 | /* Revision ID register for BCM5325 */ |
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| 194 | #define B53_REV_ID_25 0x50 |
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| 195 | |
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| 196 | /* Strap Value (48 bit) */ |
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| 197 | #define B53_STRAP_VALUE 0x70 |
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| 198 | #define SV_GMII_CTRL_115 BIT(27) |
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| 199 | |
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| 200 | /************************************************************************* |
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| 201 | * Management Mode Page Registers |
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| 202 | *************************************************************************/ |
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| 203 | |
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| 204 | /* Global Management Config Register (8 bit) */ |
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| 205 | #define B53_GLOBAL_CONFIG 0x00 |
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| 206 | #define GC_RESET_MIB 0x01 |
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| 207 | #define GC_RX_BPDU_EN 0x02 |
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| 208 | #define GC_MIB_AC_HDR_EN 0x10 |
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| 209 | #define GC_MIB_AC_EN 0x20 |
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| 210 | #define GC_FRM_MGMT_PORT_M 0xC0 |
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| 211 | #define GC_FRM_MGMT_PORT_04 0x00 |
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| 212 | #define GC_FRM_MGMT_PORT_MII 0x80 |
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| 213 | |
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| 214 | /* Broadcom Header control register (8 bit) */ |
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| 215 | #define B53_BRCM_HDR 0x03 |
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| 216 | #define BRCM_HDR_P8_EN BIT(0) /* Enable tagging on port 8 */ |
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| 217 | #define BRCM_HDR_P5_EN BIT(1) /* Enable tagging on port 5 */ |
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| 218 | #define BRCM_HDR_P7_EN BIT(2) /* Enable tagging on port 7 */ |
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| 219 | |
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| 220 | /* Mirror capture control register (16 bit) */ |
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| 221 | #define B53_MIR_CAP_CTL 0x10 |
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| 222 | #define CAP_PORT_MASK 0xf |
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| 223 | #define BLK_NOT_MIR BIT(14) |
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| 224 | #define MIRROR_EN BIT(15) |
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| 225 | |
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| 226 | /* Ingress mirror control register (16 bit) */ |
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| 227 | #define B53_IG_MIR_CTL 0x12 |
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| 228 | #define MIRROR_MASK 0x1ff |
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| 229 | #define DIV_EN BIT(13) |
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| 230 | #define MIRROR_FILTER_MASK 0x3 |
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| 231 | #define MIRROR_FILTER_SHIFT 14 |
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| 232 | #define MIRROR_ALL 0 |
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| 233 | #define MIRROR_DA 1 |
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| 234 | #define MIRROR_SA 2 |
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| 235 | |
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| 236 | /* Ingress mirror divider register (16 bit) */ |
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| 237 | #define B53_IG_MIR_DIV 0x14 |
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| 238 | #define IN_MIRROR_DIV_MASK 0x3ff |
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| 239 | |
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| 240 | /* Ingress mirror MAC address register (48 bit) */ |
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| 241 | #define B53_IG_MIR_MAC 0x16 |
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| 242 | |
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| 243 | /* Egress mirror control register (16 bit) */ |
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| 244 | #define B53_EG_MIR_CTL 0x1C |
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| 245 | |
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| 246 | /* Egress mirror divider register (16 bit) */ |
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| 247 | #define B53_EG_MIR_DIV 0x1E |
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| 248 | |
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| 249 | /* Egress mirror MAC address register (48 bit) */ |
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| 250 | #define B53_EG_MIR_MAC 0x20 |
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| 251 | |
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| 252 | /* Device ID register (8 or 32 bit) */ |
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| 253 | #define B53_DEVICE_ID 0x30 |
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| 254 | |
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| 255 | /* Revision ID register (8 bit) */ |
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| 256 | #define B53_REV_ID 0x40 |
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| 257 | |
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| 258 | /* Broadcom header RX control (16 bit) */ |
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| 259 | #define B53_BRCM_HDR_RX_DIS 0x60 |
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| 260 | |
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| 261 | /* Broadcom header TX control (16 bit) */ |
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| 262 | #define B53_BRCM_HDR_TX_DIS 0x62 |
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| 263 | |
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| 264 | /************************************************************************* |
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| 265 | * ARL Access Page Registers |
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| 266 | *************************************************************************/ |
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| 267 | |
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| 268 | /* VLAN Table Access Register (8 bit) */ |
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| 269 | #define B53_VT_ACCESS 0x80 |
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| 270 | #define B53_VT_ACCESS_9798 0x60 /* for BCM5397/BCM5398 */ |
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| 271 | #define B53_VT_ACCESS_63XX 0x60 /* for BCM6328/62/68 */ |
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| 272 | #define VTA_CMD_WRITE 0 |
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| 273 | #define VTA_CMD_READ 1 |
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| 274 | #define VTA_CMD_CLEAR 2 |
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| 275 | #define VTA_START_CMD BIT(7) |
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| 276 | |
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| 277 | /* VLAN Table Index Register (16 bit) */ |
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| 278 | #define B53_VT_INDEX 0x81 |
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| 279 | #define B53_VT_INDEX_9798 0x61 |
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| 280 | #define B53_VT_INDEX_63XX 0x62 |
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| 281 | |
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| 282 | /* VLAN Table Entry Register (32 bit) */ |
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| 283 | #define B53_VT_ENTRY 0x83 |
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| 284 | #define B53_VT_ENTRY_9798 0x63 |
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| 285 | #define B53_VT_ENTRY_63XX 0x64 |
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| 286 | #define VTE_MEMBERS 0x1ff |
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| 287 | #define VTE_UNTAG_S 9 |
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| 288 | #define VTE_UNTAG (0x1ff << 9) |
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| 289 | |
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| 290 | /************************************************************************* |
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| 291 | * ARL I/O Registers |
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| 292 | *************************************************************************/ |
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| 293 | |
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| 294 | /* ARL Table Read/Write Register (8 bit) */ |
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| 295 | #define B53_ARLTBL_RW_CTRL 0x00 |
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| 296 | #define ARLTBL_RW BIT(0) |
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| 297 | #define ARLTBL_IVL_SVL_SELECT BIT(6) |
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| 298 | #define ARLTBL_START_DONE BIT(7) |
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| 299 | |
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| 300 | /* MAC Address Index Register (48 bit) */ |
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| 301 | #define B53_MAC_ADDR_IDX 0x02 |
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| 302 | |
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| 303 | /* VLAN ID Index Register (16 bit) */ |
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| 304 | #define B53_VLAN_ID_IDX 0x08 |
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| 305 | |
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| 306 | /* ARL Table MAC/VID Entry N Registers (64 bit) |
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| 307 | * |
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| 308 | * BCM5325 and BCM5365 share most definitions below |
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| 309 | */ |
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| 310 | #define B53_ARLTBL_MAC_VID_ENTRY(n) ((0x10 * (n)) + 0x10) |
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| 311 | #define ARLTBL_MAC_MASK 0xffffffffffffULL |
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| 312 | #define ARLTBL_VID_S 48 |
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| 313 | #define ARLTBL_VID_MASK_25 0xff |
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| 314 | #define ARLTBL_VID_MASK 0xfff |
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| 315 | #define ARLTBL_DATA_PORT_ID_S_25 48 |
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| 316 | #define ARLTBL_DATA_PORT_ID_MASK_25 0xf |
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| 317 | #define ARLTBL_AGE_25 BIT(61) |
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| 318 | #define ARLTBL_STATIC_25 BIT(62) |
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| 319 | #define ARLTBL_VALID_25 BIT(63) |
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| 320 | |
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| 321 | /* ARL Table Data Entry N Registers (32 bit) */ |
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| 322 | #define B53_ARLTBL_DATA_ENTRY(n) ((0x10 * (n)) + 0x18) |
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| 323 | #define ARLTBL_DATA_PORT_ID_MASK 0x1ff |
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| 324 | #define ARLTBL_TC(tc) ((3 & tc) << 11) |
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| 325 | #define ARLTBL_AGE BIT(14) |
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| 326 | #define ARLTBL_STATIC BIT(15) |
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| 327 | #define ARLTBL_VALID BIT(16) |
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| 328 | |
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| 329 | /* Maximum number of bin entries in the ARL for all switches */ |
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| 330 | #define B53_ARLTBL_MAX_BIN_ENTRIES 4 |
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| 331 | |
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| 332 | /* ARL Search Control Register (8 bit) */ |
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| 333 | #define B53_ARL_SRCH_CTL 0x50 |
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| 334 | #define B53_ARL_SRCH_CTL_25 0x20 |
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| 335 | #define ARL_SRCH_VLID BIT(0) |
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| 336 | #define ARL_SRCH_STDN BIT(7) |
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| 337 | |
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| 338 | /* ARL Search Address Register (16 bit) */ |
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| 339 | #define B53_ARL_SRCH_ADDR 0x51 |
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| 340 | #define B53_ARL_SRCH_ADDR_25 0x22 |
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| 341 | #define B53_ARL_SRCH_ADDR_65 0x24 |
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| 342 | #define ARL_ADDR_MASK GENMASK(14, 0) |
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| 343 | |
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| 344 | /* ARL Search MAC/VID Result (64 bit) */ |
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| 345 | #define B53_ARL_SRCH_RSTL_0_MACVID 0x60 |
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| 346 | |
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| 347 | /* Single register search result on 5325 */ |
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| 348 | #define B53_ARL_SRCH_RSTL_0_MACVID_25 0x24 |
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| 349 | /* Single register search result on 5365 */ |
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| 350 | #define B53_ARL_SRCH_RSTL_0_MACVID_65 0x30 |
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| 351 | |
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| 352 | /* ARL Search Data Result (32 bit) */ |
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| 353 | #define B53_ARL_SRCH_RSTL_0 0x68 |
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| 354 | |
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| 355 | #define B53_ARL_SRCH_RSTL_MACVID(x) (B53_ARL_SRCH_RSTL_0_MACVID + ((x) * 0x10)) |
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| 356 | #define B53_ARL_SRCH_RSTL(x) (B53_ARL_SRCH_RSTL_0 + ((x) * 0x10)) |
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| 357 | |
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| 358 | /************************************************************************* |
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| 359 | * Port VLAN Registers |
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| 360 | *************************************************************************/ |
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| 361 | |
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| 362 | /* Port VLAN mask (16 bit) IMP port is always 8, also on 5325 & co */ |
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| 363 | #define B53_PVLAN_PORT_MASK(i) ((i) * 2) |
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| 364 | |
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| 365 | /* Join all VLANs register (16 bit) */ |
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| 366 | #define B53_JOIN_ALL_VLAN_EN 0x50 |
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| 367 | |
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| 368 | /************************************************************************* |
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| 369 | * 802.1Q Page Registers |
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| 370 | *************************************************************************/ |
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| 371 | |
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| 372 | /* Global QoS Control (8 bit) */ |
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| 373 | #define B53_QOS_GLOBAL_CTL 0x00 |
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| 374 | |
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| 375 | /* Enable 802.1Q for individual Ports (16 bit) */ |
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| 376 | #define B53_802_1P_EN 0x04 |
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| 377 | |
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| 378 | /************************************************************************* |
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| 379 | * VLAN Page Registers |
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| 380 | *************************************************************************/ |
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| 381 | |
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| 382 | /* VLAN Control 0 (8 bit) */ |
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| 383 | #define B53_VLAN_CTRL0 0x00 |
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| 384 | #define VC0_8021PF_CTRL_MASK 0x3 |
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| 385 | #define VC0_8021PF_CTRL_NONE 0x0 |
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| 386 | #define VC0_8021PF_CTRL_CHANGE_PRI 0x1 |
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| 387 | #define VC0_8021PF_CTRL_CHANGE_VID 0x2 |
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| 388 | #define VC0_8021PF_CTRL_CHANGE_BOTH 0x3 |
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| 389 | #define VC0_8021QF_CTRL_MASK 0xc |
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| 390 | #define VC0_8021QF_CTRL_CHANGE_PRI 0x1 |
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| 391 | #define VC0_8021QF_CTRL_CHANGE_VID 0x2 |
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| 392 | #define VC0_8021QF_CTRL_CHANGE_BOTH 0x3 |
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| 393 | #define VC0_RESERVED_1 BIT(1) |
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| 394 | #define VC0_DROP_VID_MISS BIT(4) |
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| 395 | #define VC0_VID_HASH_VID BIT(5) |
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| 396 | #define VC0_VID_CHK_EN BIT(6) /* Use VID,DA or VID,SA */ |
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| 397 | #define VC0_VLAN_EN BIT(7) /* 802.1Q VLAN Enabled */ |
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| 398 | |
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| 399 | /* VLAN Control 1 (8 bit) */ |
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| 400 | #define B53_VLAN_CTRL1 0x01 |
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| 401 | #define VC1_RX_MCST_TAG_EN BIT(1) |
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| 402 | #define VC1_RX_MCST_FWD_EN BIT(2) |
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| 403 | #define VC1_RX_MCST_UNTAG_EN BIT(3) |
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| 404 | |
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| 405 | /* VLAN Control 2 (8 bit) */ |
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| 406 | #define B53_VLAN_CTRL2 0x02 |
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| 407 | |
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| 408 | /* VLAN Control 3 (8 bit when BCM5325, 16 bit else) */ |
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| 409 | #define B53_VLAN_CTRL3 0x03 |
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| 410 | #define B53_VLAN_CTRL3_63XX 0x04 |
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| 411 | #define VC3_MAXSIZE_1532 BIT(6) /* 5325 only */ |
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| 412 | #define VC3_HIGH_8BIT_EN BIT(7) /* 5325 only */ |
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| 413 | |
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| 414 | /* VLAN Control 4 (8 bit) */ |
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| 415 | #define B53_VLAN_CTRL4 0x05 |
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| 416 | #define B53_VLAN_CTRL4_25 0x04 |
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| 417 | #define B53_VLAN_CTRL4_63XX 0x06 |
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| 418 | #define VC4_ING_VID_CHECK_S 6 |
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| 419 | #define VC4_ING_VID_CHECK_MASK (0x3 << VC4_ING_VID_CHECK_S) |
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| 420 | #define VC4_ING_VID_VIO_FWD 0 /* forward, but do not learn */ |
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| 421 | #define VC4_ING_VID_VIO_DROP 1 /* drop VID violations */ |
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| 422 | #define VC4_NO_ING_VID_CHK 2 /* do not check */ |
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| 423 | #define VC4_ING_VID_VIO_TO_IMP 3 /* redirect to MII port */ |
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| 424 | |
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| 425 | /* VLAN Control 5 (8 bit) */ |
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| 426 | #define B53_VLAN_CTRL5 0x06 |
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| 427 | #define B53_VLAN_CTRL5_25 0x05 |
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| 428 | #define B53_VLAN_CTRL5_63XX 0x07 |
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| 429 | #define VC5_VID_FFF_EN BIT(2) |
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| 430 | #define VC5_DROP_VTABLE_MISS BIT(3) |
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| 431 | |
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| 432 | /* VLAN Control 6 (8 bit) */ |
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| 433 | #define B53_VLAN_CTRL6 0x07 |
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| 434 | #define B53_VLAN_CTRL6_63XX 0x08 |
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| 435 | |
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| 436 | /* VLAN Table Access Register (16 bit) */ |
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| 437 | #define B53_VLAN_TABLE_ACCESS_25 0x06 /* BCM5325E/5350 */ |
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| 438 | #define B53_VLAN_TABLE_ACCESS_65 0x08 /* BCM5365 */ |
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| 439 | #define VTA_VID_LOW_MASK_25 0xf |
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| 440 | #define VTA_VID_LOW_MASK_65 0xff |
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| 441 | #define VTA_VID_HIGH_S_25 4 |
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| 442 | #define VTA_VID_HIGH_S_65 8 |
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| 443 | #define VTA_VID_HIGH_MASK_25 (0xff << VTA_VID_HIGH_S_25E) |
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| 444 | #define VTA_VID_HIGH_MASK_65 (0xf << VTA_VID_HIGH_S_65) |
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| 445 | #define VTA_RW_STATE BIT(12) |
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| 446 | #define VTA_RW_STATE_RD 0 |
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| 447 | #define VTA_RW_STATE_WR BIT(12) |
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| 448 | #define VTA_RW_OP_EN BIT(13) |
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| 449 | |
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| 450 | /* VLAN Read/Write Registers for (16/32 bit) */ |
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| 451 | #define B53_VLAN_WRITE_25 0x08 |
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| 452 | #define B53_VLAN_WRITE_65 0x0a |
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| 453 | #define B53_VLAN_READ 0x0c |
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| 454 | #define VA_MEMBER_MASK 0x3f |
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| 455 | #define VA_UNTAG_S_25 6 |
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| 456 | #define VA_UNTAG_MASK_25 0x3f |
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| 457 | #define VA_UNTAG_S_65 7 |
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| 458 | #define VA_UNTAG_MASK_65 0x1f |
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| 459 | #define VA_VID_HIGH_S 12 |
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| 460 | #define VA_VID_HIGH_MASK (0xffff << VA_VID_HIGH_S) |
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| 461 | #define VA_VALID_25 BIT(20) |
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| 462 | #define VA_VALID_25_R4 BIT(24) |
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| 463 | #define VA_VALID_65 BIT(14) |
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| 464 | |
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| 465 | /* VLAN Port Default Tag (16 bit) */ |
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| 466 | #define B53_VLAN_PORT_DEF_TAG(i) (0x10 + 2 * (i)) |
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| 467 | |
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| 468 | /************************************************************************* |
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| 469 | * Jumbo Frame Page Registers |
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| 470 | *************************************************************************/ |
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| 471 | |
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| 472 | /* Jumbo Enable Port Mask (bit i == port i enabled) (32 bit) */ |
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| 473 | #define B53_JUMBO_PORT_MASK 0x01 |
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| 474 | #define B53_JUMBO_PORT_MASK_63XX 0x04 |
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| 475 | #define JPM_10_100_JUMBO_EN BIT(24) /* GigE always enabled */ |
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| 476 | |
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| 477 | /* Good Frame Max Size without 802.1Q TAG (16 bit) */ |
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| 478 | #define B53_JUMBO_MAX_SIZE 0x05 |
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| 479 | #define B53_JUMBO_MAX_SIZE_63XX 0x08 |
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| 480 | #define JMS_MIN_SIZE 1518 |
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| 481 | #define JMS_MAX_SIZE 9724 |
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| 482 | |
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| 483 | /************************************************************************* |
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| 484 | * EEE Configuration Page Registers |
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| 485 | *************************************************************************/ |
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| 486 | |
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| 487 | /* EEE Enable control register (16 bit) */ |
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| 488 | #define B53_EEE_EN_CTRL 0x00 |
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| 489 | |
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| 490 | /* EEE LPI assert status register (16 bit) */ |
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| 491 | #define B53_EEE_LPI_ASSERT_STS 0x02 |
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| 492 | |
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| 493 | /* EEE LPI indicate status register (16 bit) */ |
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| 494 | #define B53_EEE_LPI_INDICATE 0x4 |
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| 495 | |
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| 496 | /* EEE Receiving idle symbols status register (16 bit) */ |
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| 497 | #define B53_EEE_RX_IDLE_SYM_STS 0x6 |
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| 498 | |
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| 499 | /* EEE Pipeline timer register (32 bit) */ |
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| 500 | #define B53_EEE_PIP_TIMER 0xC |
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| 501 | |
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| 502 | /* EEE Sleep timer Gig register (32 bit) */ |
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| 503 | #define B53_EEE_SLEEP_TIMER_GIG(i) (0x10 + 4 * (i)) |
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| 504 | |
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| 505 | /* EEE Sleep timer FE register (32 bit) */ |
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| 506 | #define B53_EEE_SLEEP_TIMER_FE(i) (0x34 + 4 * (i)) |
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| 507 | |
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| 508 | /* EEE Minimum LP timer Gig register (32 bit) */ |
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| 509 | #define B53_EEE_MIN_LP_TIMER_GIG(i) (0x58 + 4 * (i)) |
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| 510 | |
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| 511 | /* EEE Minimum LP timer FE register (32 bit) */ |
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| 512 | #define B53_EEE_MIN_LP_TIMER_FE(i) (0x7c + 4 * (i)) |
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| 513 | |
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| 514 | /* EEE Wake timer Gig register (16 bit) */ |
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| 515 | #define B53_EEE_WAKE_TIMER_GIG(i) (0xa0 + 2 * (i)) |
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| 516 | |
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| 517 | /* EEE Wake timer FE register (16 bit) */ |
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| 518 | #define B53_EEE_WAKE_TIMER_FE(i) (0xb2 + 2 * (i)) |
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| 519 | |
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| 520 | |
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| 521 | /************************************************************************* |
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| 522 | * CFP Configuration Page Registers |
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| 523 | *************************************************************************/ |
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| 524 | |
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| 525 | /* CFP Control Register with ports map (8 bit) */ |
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| 526 | #define B53_CFP_CTRL 0x00 |
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| 527 | |
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| 528 | #endif /* !__B53_REGS_H */ |
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| 529 | |
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