1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* Microchip KSZ PTP register definitions |
3 | * Copyright (C) 2022 Microchip Technology Inc. |
4 | */ |
5 | |
6 | #ifndef __KSZ_PTP_REGS_H |
7 | #define __KSZ_PTP_REGS_H |
8 | |
9 | #define REG_SW_GLOBAL_LED_OVR__4 0x0120 |
10 | #define LED_OVR_2 BIT(1) |
11 | #define LED_OVR_1 BIT(0) |
12 | |
13 | #define REG_SW_GLOBAL_LED_SRC__4 0x0128 |
14 | #define LED_SRC_PTP_GPIO_1 BIT(3) |
15 | #define LED_SRC_PTP_GPIO_2 BIT(2) |
16 | |
17 | /* 5 - PTP Clock */ |
18 | #define REG_PTP_CLK_CTRL 0x0500 |
19 | |
20 | #define PTP_STEP_ADJ BIT(6) |
21 | #define PTP_STEP_DIR BIT(5) |
22 | #define PTP_READ_TIME BIT(4) |
23 | #define PTP_LOAD_TIME BIT(3) |
24 | #define PTP_CLK_ADJ_ENABLE BIT(2) |
25 | #define PTP_CLK_ENABLE BIT(1) |
26 | #define PTP_CLK_RESET BIT(0) |
27 | |
28 | #define REG_PTP_RTC_SUB_NANOSEC__2 0x0502 |
29 | |
30 | #define PTP_RTC_SUB_NANOSEC_M 0x0007 |
31 | #define PTP_RTC_0NS 0x00 |
32 | |
33 | #define REG_PTP_RTC_NANOSEC 0x0504 |
34 | |
35 | #define REG_PTP_RTC_SEC 0x0508 |
36 | |
37 | #define REG_PTP_SUBNANOSEC_RATE 0x050C |
38 | |
39 | #define PTP_SUBNANOSEC_M 0x3FFFFFFF |
40 | #define PTP_RATE_DIR BIT(31) |
41 | #define PTP_TMP_RATE_ENABLE BIT(30) |
42 | |
43 | #define REG_PTP_SUBNANOSEC_RATE_L 0x050E |
44 | |
45 | #define REG_PTP_RATE_DURATION 0x0510 |
46 | #define REG_PTP_RATE_DURATION_H 0x0510 |
47 | #define REG_PTP_RATE_DURATION_L 0x0512 |
48 | |
49 | #define REG_PTP_MSG_CONF1 0x0514 |
50 | |
51 | #define PTP_802_1AS BIT(7) |
52 | #define PTP_ENABLE BIT(6) |
53 | #define PTP_ETH_ENABLE BIT(5) |
54 | #define PTP_IPV4_UDP_ENABLE BIT(4) |
55 | #define PTP_IPV6_UDP_ENABLE BIT(3) |
56 | #define PTP_TC_P2P BIT(2) |
57 | #define PTP_MASTER BIT(1) |
58 | #define PTP_1STEP BIT(0) |
59 | |
60 | #define REG_PTP_UNIT_INDEX__4 0x0520 |
61 | |
62 | #define PTP_GPIO_INDEX GENMASK(19, 16) |
63 | #define PTP_TSI_INDEX BIT(8) |
64 | #define PTP_TOU_INDEX GENMASK(1, 0) |
65 | |
66 | #define REG_PTP_TRIG_STATUS__4 0x0524 |
67 | |
68 | #define TRIG_ERROR_M GENMASK(18, 16) |
69 | #define TRIG_DONE_M GENMASK(2, 0) |
70 | |
71 | #define REG_PTP_INT_STATUS__4 0x0528 |
72 | |
73 | #define TRIG_INT_M GENMASK(18, 16) |
74 | #define TS_INT_M GENMASK(1, 0) |
75 | |
76 | #define REG_PTP_CTRL_STAT__4 0x052C |
77 | |
78 | #define GPIO_IN BIT(7) |
79 | #define GPIO_OUT BIT(6) |
80 | #define TS_INT_ENABLE BIT(5) |
81 | #define TRIG_ACTIVE BIT(4) |
82 | #define TRIG_ENABLE BIT(3) |
83 | #define TRIG_RESET BIT(2) |
84 | #define TS_ENABLE BIT(1) |
85 | #define TS_RESET BIT(0) |
86 | |
87 | #define REG_TRIG_TARGET_NANOSEC 0x0530 |
88 | #define REG_TRIG_TARGET_SEC 0x0534 |
89 | |
90 | #define REG_TRIG_CTRL__4 0x0538 |
91 | |
92 | #define TRIG_CASCADE_ENABLE BIT(31) |
93 | #define TRIG_CASCADE_TAIL BIT(30) |
94 | #define TRIG_CASCADE_UPS_M GENMASK(29, 26) |
95 | #define TRIG_NOW BIT(25) |
96 | #define TRIG_NOTIFY BIT(24) |
97 | #define TRIG_EDGE BIT(23) |
98 | #define TRIG_PATTERN_M GENMASK(22, 20) |
99 | #define TRIG_NEG_EDGE 0 |
100 | #define TRIG_POS_EDGE 1 |
101 | #define TRIG_NEG_PULSE 2 |
102 | #define TRIG_POS_PULSE 3 |
103 | #define TRIG_NEG_PERIOD 4 |
104 | #define TRIG_POS_PERIOD 5 |
105 | #define TRIG_REG_OUTPUT 6 |
106 | #define TRIG_GPO_M GENMASK(19, 16) |
107 | #define TRIG_CASCADE_ITERATE_CNT_M GENMASK(15, 0) |
108 | |
109 | #define REG_TRIG_CYCLE_WIDTH 0x053C |
110 | #define TRIG_CYCLE_WIDTH_M GENMASK(31, 0) |
111 | |
112 | #define REG_TRIG_CYCLE_CNT 0x0540 |
113 | |
114 | #define TRIG_CYCLE_CNT_M GENMASK(31, 16) |
115 | #define TRIG_BIT_PATTERN_M GENMASK(15, 0) |
116 | |
117 | #define REG_TRIG_ITERATE_TIME 0x0544 |
118 | |
119 | #define REG_TRIG_PULSE_WIDTH__4 0x0548 |
120 | |
121 | #define TRIG_PULSE_WIDTH_M GENMASK(23, 0) |
122 | |
123 | /* Port PTP Register */ |
124 | #define REG_PTP_PORT_RX_DELAY__2 0x0C00 |
125 | #define REG_PTP_PORT_TX_DELAY__2 0x0C02 |
126 | #define REG_PTP_PORT_ASYM_DELAY__2 0x0C04 |
127 | |
128 | #define REG_PTP_PORT_XDELAY_TS 0x0C08 |
129 | #define REG_PTP_PORT_SYNC_TS 0x0C0C |
130 | #define REG_PTP_PORT_PDRESP_TS 0x0C10 |
131 | |
132 | #define REG_PTP_PORT_TX_INT_STATUS__2 0x0C14 |
133 | #define REG_PTP_PORT_TX_INT_ENABLE__2 0x0C16 |
134 | |
135 | #define PTP_PORT_SYNC_INT BIT(15) |
136 | #define PTP_PORT_XDELAY_REQ_INT BIT(14) |
137 | #define PTP_PORT_PDELAY_RESP_INT BIT(13) |
138 | #define KSZ_SYNC_MSG 2 |
139 | #define KSZ_XDREQ_MSG 1 |
140 | #define KSZ_PDRES_MSG 0 |
141 | |
142 | #endif |
143 | |