1 | /* typhoon.h: chip info for the 3Com 3CR990 family of controllers */ |
2 | /* |
3 | Written 2002-2003 by David Dillow <dave@thedillows.org> |
4 | |
5 | This software may be used and distributed according to the terms of |
6 | the GNU General Public License (GPL), incorporated herein by reference. |
7 | Drivers based on or derived from this code fall under the GPL and must |
8 | retain the authorship, copyright and license notice. This file is not |
9 | a complete program and may only be used when the entire operating |
10 | system is licensed under the GPL. |
11 | |
12 | This software is available on a public web site. It may enable |
13 | cryptographic capabilities of the 3Com hardware, and may be |
14 | exported from the United States under License Exception "TSU" |
15 | pursuant to 15 C.F.R. Section 740.13(e). |
16 | |
17 | This work was funded by the National Library of Medicine under |
18 | the Department of Energy project number 0274DD06D1 and NLM project |
19 | number Y1-LM-2015-01. |
20 | */ |
21 | |
22 | /* All Typhoon ring positions are specificed in bytes, and point to the |
23 | * first "clean" entry in the ring -- ie the next entry we use for whatever |
24 | * purpose. |
25 | */ |
26 | |
27 | /* The Typhoon basic ring |
28 | * ringBase: where this ring lives (our virtual address) |
29 | * lastWrite: the next entry we'll use |
30 | */ |
31 | struct basic_ring { |
32 | u8 *ringBase; |
33 | u32 lastWrite; |
34 | }; |
35 | |
36 | /* The Typhoon transmit ring -- same as a basic ring, plus: |
37 | * lastRead: where we're at in regard to cleaning up the ring |
38 | * writeRegister: register to use for writing (different for Hi & Lo rings) |
39 | */ |
40 | struct transmit_ring { |
41 | u8 *ringBase; |
42 | u32 lastWrite; |
43 | u32 lastRead; |
44 | int writeRegister; |
45 | }; |
46 | |
47 | /* The host<->Typhoon ring index structure |
48 | * This indicates the current positions in the rings |
49 | * |
50 | * All values must be in little endian format for the 3XP |
51 | * |
52 | * rxHiCleared: entry we've cleared to in the Hi receive ring |
53 | * rxLoCleared: entry we've cleared to in the Lo receive ring |
54 | * rxBuffReady: next entry we'll put a free buffer in |
55 | * respCleared: entry we've cleared to in the response ring |
56 | * |
57 | * txLoCleared: entry the NIC has cleared to in the Lo transmit ring |
58 | * txHiCleared: entry the NIC has cleared to in the Hi transmit ring |
59 | * rxLoReady: entry the NIC has filled to in the Lo receive ring |
60 | * rxBuffCleared: entry the NIC has cleared in the free buffer ring |
61 | * cmdCleared: entry the NIC has cleared in the command ring |
62 | * respReady: entry the NIC has filled to in the response ring |
63 | * rxHiReady: entry the NIC has filled to in the Hi receive ring |
64 | */ |
65 | struct typhoon_indexes { |
66 | /* The first four are written by the host, and read by the NIC */ |
67 | volatile __le32 rxHiCleared; |
68 | volatile __le32 rxLoCleared; |
69 | volatile __le32 rxBuffReady; |
70 | volatile __le32 respCleared; |
71 | |
72 | /* The remaining are written by the NIC, and read by the host */ |
73 | volatile __le32 txLoCleared; |
74 | volatile __le32 txHiCleared; |
75 | volatile __le32 rxLoReady; |
76 | volatile __le32 rxBuffCleared; |
77 | volatile __le32 cmdCleared; |
78 | volatile __le32 respReady; |
79 | volatile __le32 rxHiReady; |
80 | } __packed; |
81 | |
82 | /* The host<->Typhoon interface |
83 | * Our means of communicating where things are |
84 | * |
85 | * All values must be in little endian format for the 3XP |
86 | * |
87 | * ringIndex: 64 bit bus address of the index structure |
88 | * txLoAddr: 64 bit bus address of the Lo transmit ring |
89 | * txLoSize: size (in bytes) of the Lo transmit ring |
90 | * txHi*: as above for the Hi priority transmit ring |
91 | * rxLo*: as above for the Lo priority receive ring |
92 | * rxBuff*: as above for the free buffer ring |
93 | * cmd*: as above for the command ring |
94 | * resp*: as above for the response ring |
95 | * zeroAddr: 64 bit bus address of a zero word (for DMA) |
96 | * rxHi*: as above for the Hi Priority receive ring |
97 | * |
98 | * While there is room for 64 bit addresses, current versions of the 3XP |
99 | * only do 32 bit addresses, so the *Hi for each of the above will always |
100 | * be zero. |
101 | */ |
102 | struct typhoon_interface { |
103 | __le32 ringIndex; |
104 | __le32 ringIndexHi; |
105 | __le32 txLoAddr; |
106 | __le32 txLoAddrHi; |
107 | __le32 txLoSize; |
108 | __le32 txHiAddr; |
109 | __le32 txHiAddrHi; |
110 | __le32 txHiSize; |
111 | __le32 rxLoAddr; |
112 | __le32 rxLoAddrHi; |
113 | __le32 rxLoSize; |
114 | __le32 rxBuffAddr; |
115 | __le32 rxBuffAddrHi; |
116 | __le32 rxBuffSize; |
117 | __le32 cmdAddr; |
118 | __le32 cmdAddrHi; |
119 | __le32 cmdSize; |
120 | __le32 respAddr; |
121 | __le32 respAddrHi; |
122 | __le32 respSize; |
123 | __le32 zeroAddr; |
124 | __le32 zeroAddrHi; |
125 | __le32 rxHiAddr; |
126 | __le32 rxHiAddrHi; |
127 | __le32 rxHiSize; |
128 | } __packed; |
129 | |
130 | /* The Typhoon transmit/fragment descriptor |
131 | * |
132 | * A packet is described by a packet descriptor, followed by option descriptors, |
133 | * if any, then one or more fragment descriptors. |
134 | * |
135 | * Packet descriptor: |
136 | * flags: Descriptor type |
137 | * len:i zero, or length of this packet |
138 | * addr*: 8 bytes of opaque data to the firmware -- for skb pointer |
139 | * processFlags: Determine offload tasks to perform on this packet. |
140 | * |
141 | * Fragment descriptor: |
142 | * flags: Descriptor type |
143 | * len:i length of this fragment |
144 | * addr: low bytes of DMA address for this part of the packet |
145 | * addrHi: hi bytes of DMA address for this part of the packet |
146 | * processFlags: must be zero |
147 | * |
148 | * TYPHOON_DESC_VALID is not mentioned in their docs, but their Linux |
149 | * driver uses it. |
150 | */ |
151 | struct tx_desc { |
152 | u8 flags; |
153 | #define TYPHOON_TYPE_MASK 0x07 |
154 | #define TYPHOON_FRAG_DESC 0x00 |
155 | #define TYPHOON_TX_DESC 0x01 |
156 | #define TYPHOON_CMD_DESC 0x02 |
157 | #define TYPHOON_OPT_DESC 0x03 |
158 | #define TYPHOON_RX_DESC 0x04 |
159 | #define TYPHOON_RESP_DESC 0x05 |
160 | #define TYPHOON_OPT_TYPE_MASK 0xf0 |
161 | #define TYPHOON_OPT_IPSEC 0x00 |
162 | #define TYPHOON_OPT_TCP_SEG 0x10 |
163 | #define TYPHOON_CMD_RESPOND 0x40 |
164 | #define TYPHOON_RESP_ERROR 0x40 |
165 | #define TYPHOON_RX_ERROR 0x40 |
166 | #define TYPHOON_DESC_VALID 0x80 |
167 | u8 numDesc; |
168 | __le16 len; |
169 | union { |
170 | struct { |
171 | __le32 addr; |
172 | __le32 addrHi; |
173 | } frag; |
174 | u64 tx_addr; /* opaque for hardware, for TX_DESC */ |
175 | }; |
176 | __le32 processFlags; |
177 | #define TYPHOON_TX_PF_NO_CRC cpu_to_le32(0x00000001) |
178 | #define TYPHOON_TX_PF_IP_CHKSUM cpu_to_le32(0x00000002) |
179 | #define TYPHOON_TX_PF_TCP_CHKSUM cpu_to_le32(0x00000004) |
180 | #define TYPHOON_TX_PF_TCP_SEGMENT cpu_to_le32(0x00000008) |
181 | #define TYPHOON_TX_PF_INSERT_VLAN cpu_to_le32(0x00000010) |
182 | #define TYPHOON_TX_PF_IPSEC cpu_to_le32(0x00000020) |
183 | #define TYPHOON_TX_PF_VLAN_PRIORITY cpu_to_le32(0x00000040) |
184 | #define TYPHOON_TX_PF_UDP_CHKSUM cpu_to_le32(0x00000080) |
185 | #define TYPHOON_TX_PF_PAD_FRAME cpu_to_le32(0x00000100) |
186 | #define TYPHOON_TX_PF_RESERVED cpu_to_le32(0x00000e00) |
187 | #define TYPHOON_TX_PF_VLAN_MASK cpu_to_le32(0x0ffff000) |
188 | #define TYPHOON_TX_PF_INTERNAL cpu_to_le32(0xf0000000) |
189 | #define TYPHOON_TX_PF_VLAN_TAG_SHIFT 12 |
190 | } __packed; |
191 | |
192 | /* The TCP Segmentation offload option descriptor |
193 | * |
194 | * flags: descriptor type |
195 | * numDesc: must be 1 |
196 | * mss_flags: bits 0-11 (little endian) are MSS, 12 is first TSO descriptor |
197 | * 13 is list TSO descriptor, set both if only one TSO |
198 | * respAddrLo: low bytes of address of the bytesTx field of this descriptor |
199 | * bytesTx: total number of bytes in this TSO request |
200 | * status: 0 on completion |
201 | */ |
202 | struct tcpopt_desc { |
203 | u8 flags; |
204 | u8 numDesc; |
205 | __le16 mss_flags; |
206 | #define TYPHOON_TSO_FIRST cpu_to_le16(0x1000) |
207 | #define TYPHOON_TSO_LAST cpu_to_le16(0x2000) |
208 | __le32 respAddrLo; |
209 | __le32 bytesTx; |
210 | __le32 status; |
211 | } __packed; |
212 | |
213 | /* The IPSEC Offload descriptor |
214 | * |
215 | * flags: descriptor type |
216 | * numDesc: must be 1 |
217 | * ipsecFlags: bit 0: 0 -- generate IV, 1 -- use supplied IV |
218 | * sa1, sa2: Security Association IDs for this packet |
219 | * reserved: set to 0 |
220 | */ |
221 | struct ipsec_desc { |
222 | u8 flags; |
223 | u8 numDesc; |
224 | __le16 ipsecFlags; |
225 | #define TYPHOON_IPSEC_GEN_IV cpu_to_le16(0x0000) |
226 | #define TYPHOON_IPSEC_USE_IV cpu_to_le16(0x0001) |
227 | __le32 sa1; |
228 | __le32 sa2; |
229 | __le32 reserved; |
230 | } __packed; |
231 | |
232 | /* The Typhoon receive descriptor (Updated by NIC) |
233 | * |
234 | * flags: Descriptor type, error indication |
235 | * numDesc: Always zero |
236 | * frameLen: the size of the packet received |
237 | * addr: low 32 bytes of the virtual addr passed in for this buffer |
238 | * addrHi: high 32 bytes of the virtual addr passed in for this buffer |
239 | * rxStatus: Error if set in flags, otherwise result of offload processing |
240 | * filterResults: results of filtering on packet, not used |
241 | * ipsecResults: Results of IPSEC processing |
242 | * vlanTag: the 801.2q TCI from the packet |
243 | */ |
244 | struct rx_desc { |
245 | u8 flags; |
246 | u8 numDesc; |
247 | __le16 frameLen; |
248 | u32 addr; /* opaque, comes from virtAddr */ |
249 | u32 addrHi; /* opaque, comes from virtAddrHi */ |
250 | __le32 rxStatus; |
251 | #define TYPHOON_RX_ERR_INTERNAL cpu_to_le32(0x00000000) |
252 | #define TYPHOON_RX_ERR_FIFO_UNDERRUN cpu_to_le32(0x00000001) |
253 | #define TYPHOON_RX_ERR_BAD_SSD cpu_to_le32(0x00000002) |
254 | #define TYPHOON_RX_ERR_RUNT cpu_to_le32(0x00000003) |
255 | #define TYPHOON_RX_ERR_CRC cpu_to_le32(0x00000004) |
256 | #define TYPHOON_RX_ERR_OVERSIZE cpu_to_le32(0x00000005) |
257 | #define TYPHOON_RX_ERR_ALIGN cpu_to_le32(0x00000006) |
258 | #define TYPHOON_RX_ERR_DRIBBLE cpu_to_le32(0x00000007) |
259 | #define TYPHOON_RX_PROTO_MASK cpu_to_le32(0x00000003) |
260 | #define TYPHOON_RX_PROTO_UNKNOWN cpu_to_le32(0x00000000) |
261 | #define TYPHOON_RX_PROTO_IP cpu_to_le32(0x00000001) |
262 | #define TYPHOON_RX_PROTO_IPX cpu_to_le32(0x00000002) |
263 | #define TYPHOON_RX_VLAN cpu_to_le32(0x00000004) |
264 | #define TYPHOON_RX_IP_FRAG cpu_to_le32(0x00000008) |
265 | #define TYPHOON_RX_IPSEC cpu_to_le32(0x00000010) |
266 | #define TYPHOON_RX_IP_CHK_FAIL cpu_to_le32(0x00000020) |
267 | #define TYPHOON_RX_TCP_CHK_FAIL cpu_to_le32(0x00000040) |
268 | #define TYPHOON_RX_UDP_CHK_FAIL cpu_to_le32(0x00000080) |
269 | #define TYPHOON_RX_IP_CHK_GOOD cpu_to_le32(0x00000100) |
270 | #define TYPHOON_RX_TCP_CHK_GOOD cpu_to_le32(0x00000200) |
271 | #define TYPHOON_RX_UDP_CHK_GOOD cpu_to_le32(0x00000400) |
272 | __le16 filterResults; |
273 | #define TYPHOON_RX_FILTER_MASK cpu_to_le16(0x7fff) |
274 | #define TYPHOON_RX_FILTERED cpu_to_le16(0x8000) |
275 | __le16 ipsecResults; |
276 | #define TYPHOON_RX_OUTER_AH_GOOD cpu_to_le16(0x0001) |
277 | #define TYPHOON_RX_OUTER_ESP_GOOD cpu_to_le16(0x0002) |
278 | #define TYPHOON_RX_INNER_AH_GOOD cpu_to_le16(0x0004) |
279 | #define TYPHOON_RX_INNER_ESP_GOOD cpu_to_le16(0x0008) |
280 | #define TYPHOON_RX_OUTER_AH_FAIL cpu_to_le16(0x0010) |
281 | #define TYPHOON_RX_OUTER_ESP_FAIL cpu_to_le16(0x0020) |
282 | #define TYPHOON_RX_INNER_AH_FAIL cpu_to_le16(0x0040) |
283 | #define TYPHOON_RX_INNER_ESP_FAIL cpu_to_le16(0x0080) |
284 | #define TYPHOON_RX_UNKNOWN_SA cpu_to_le16(0x0100) |
285 | #define TYPHOON_RX_ESP_FORMAT_ERR cpu_to_le16(0x0200) |
286 | __be32 vlanTag; |
287 | } __packed; |
288 | |
289 | /* The Typhoon free buffer descriptor, used to give a buffer to the NIC |
290 | * |
291 | * physAddr: low 32 bits of the bus address of the buffer |
292 | * physAddrHi: high 32 bits of the bus address of the buffer, always zero |
293 | * virtAddr: low 32 bits of the skb address |
294 | * virtAddrHi: high 32 bits of the skb address, always zero |
295 | * |
296 | * the virt* address is basically two 32 bit cookies, just passed back |
297 | * from the NIC |
298 | */ |
299 | struct rx_free { |
300 | __le32 physAddr; |
301 | __le32 physAddrHi; |
302 | u32 virtAddr; |
303 | u32 virtAddrHi; |
304 | } __packed; |
305 | |
306 | /* The Typhoon command descriptor, used for commands and responses |
307 | * |
308 | * flags: descriptor type |
309 | * numDesc: number of descriptors following in this command/response, |
310 | * ie, zero for a one descriptor command |
311 | * cmd: the command |
312 | * seqNo: sequence number (unused) |
313 | * parm1: use varies by command |
314 | * parm2: use varies by command |
315 | * parm3: use varies by command |
316 | */ |
317 | struct cmd_desc { |
318 | u8 flags; |
319 | u8 numDesc; |
320 | __le16 cmd; |
321 | #define TYPHOON_CMD_TX_ENABLE cpu_to_le16(0x0001) |
322 | #define TYPHOON_CMD_TX_DISABLE cpu_to_le16(0x0002) |
323 | #define TYPHOON_CMD_RX_ENABLE cpu_to_le16(0x0003) |
324 | #define TYPHOON_CMD_RX_DISABLE cpu_to_le16(0x0004) |
325 | #define TYPHOON_CMD_SET_RX_FILTER cpu_to_le16(0x0005) |
326 | #define TYPHOON_CMD_READ_STATS cpu_to_le16(0x0007) |
327 | #define TYPHOON_CMD_XCVR_SELECT cpu_to_le16(0x0013) |
328 | #define TYPHOON_CMD_SET_MAX_PKT_SIZE cpu_to_le16(0x001a) |
329 | #define TYPHOON_CMD_READ_MEDIA_STATUS cpu_to_le16(0x001b) |
330 | #define TYPHOON_CMD_GOTO_SLEEP cpu_to_le16(0x0023) |
331 | #define TYPHOON_CMD_SET_MULTICAST_HASH cpu_to_le16(0x0025) |
332 | #define TYPHOON_CMD_SET_MAC_ADDRESS cpu_to_le16(0x0026) |
333 | #define TYPHOON_CMD_READ_MAC_ADDRESS cpu_to_le16(0x0027) |
334 | #define TYPHOON_CMD_VLAN_TYPE_WRITE cpu_to_le16(0x002b) |
335 | #define TYPHOON_CMD_CREATE_SA cpu_to_le16(0x0034) |
336 | #define TYPHOON_CMD_DELETE_SA cpu_to_le16(0x0035) |
337 | #define TYPHOON_CMD_READ_VERSIONS cpu_to_le16(0x0043) |
338 | #define TYPHOON_CMD_IRQ_COALESCE_CTRL cpu_to_le16(0x0045) |
339 | #define TYPHOON_CMD_ENABLE_WAKE_EVENTS cpu_to_le16(0x0049) |
340 | #define TYPHOON_CMD_SET_OFFLOAD_TASKS cpu_to_le16(0x004f) |
341 | #define TYPHOON_CMD_HELLO_RESP cpu_to_le16(0x0057) |
342 | #define TYPHOON_CMD_HALT cpu_to_le16(0x005d) |
343 | #define TYPHOON_CMD_READ_IPSEC_INFO cpu_to_le16(0x005e) |
344 | #define TYPHOON_CMD_GET_IPSEC_ENABLE cpu_to_le16(0x0067) |
345 | #define TYPHOON_CMD_GET_CMD_LVL cpu_to_le16(0x0069) |
346 | u16 seqNo; |
347 | __le16 parm1; |
348 | __le32 parm2; |
349 | __le32 parm3; |
350 | } __packed; |
351 | |
352 | /* The Typhoon response descriptor, see command descriptor for details |
353 | */ |
354 | struct resp_desc { |
355 | u8 flags; |
356 | u8 numDesc; |
357 | __le16 cmd; |
358 | __le16 seqNo; |
359 | __le16 parm1; |
360 | __le32 parm2; |
361 | __le32 parm3; |
362 | } __packed; |
363 | |
364 | #define INIT_COMMAND_NO_RESPONSE(x, command) \ |
365 | do { struct cmd_desc *_ptr = (x); \ |
366 | memset(_ptr, 0, sizeof(struct cmd_desc)); \ |
367 | _ptr->flags = TYPHOON_CMD_DESC | TYPHOON_DESC_VALID; \ |
368 | _ptr->cmd = command; \ |
369 | } while (0) |
370 | |
371 | /* We set seqNo to 1 if we're expecting a response from this command */ |
372 | #define INIT_COMMAND_WITH_RESPONSE(x, command) \ |
373 | do { struct cmd_desc *_ptr = (x); \ |
374 | memset(_ptr, 0, sizeof(struct cmd_desc)); \ |
375 | _ptr->flags = TYPHOON_CMD_RESPOND | TYPHOON_CMD_DESC; \ |
376 | _ptr->flags |= TYPHOON_DESC_VALID; \ |
377 | _ptr->cmd = command; \ |
378 | _ptr->seqNo = 1; \ |
379 | } while (0) |
380 | |
381 | /* TYPHOON_CMD_SET_RX_FILTER filter bits (cmd.parm1) |
382 | */ |
383 | #define TYPHOON_RX_FILTER_DIRECTED cpu_to_le16(0x0001) |
384 | #define TYPHOON_RX_FILTER_ALL_MCAST cpu_to_le16(0x0002) |
385 | #define TYPHOON_RX_FILTER_BROADCAST cpu_to_le16(0x0004) |
386 | #define TYPHOON_RX_FILTER_PROMISCOUS cpu_to_le16(0x0008) |
387 | #define TYPHOON_RX_FILTER_MCAST_HASH cpu_to_le16(0x0010) |
388 | |
389 | /* TYPHOON_CMD_READ_STATS response format |
390 | */ |
391 | struct stats_resp { |
392 | u8 flags; |
393 | u8 numDesc; |
394 | __le16 cmd; |
395 | __le16 seqNo; |
396 | __le16 unused; |
397 | __le32 txPackets; |
398 | __le64 txBytes; |
399 | __le32 txDeferred; |
400 | __le32 txLateCollisions; |
401 | __le32 txCollisions; |
402 | __le32 txCarrierLost; |
403 | __le32 txMultipleCollisions; |
404 | __le32 txExcessiveCollisions; |
405 | __le32 txFifoUnderruns; |
406 | __le32 txMulticastTxOverflows; |
407 | __le32 txFiltered; |
408 | __le32 rxPacketsGood; |
409 | __le64 rxBytesGood; |
410 | __le32 rxFifoOverruns; |
411 | __le32 BadSSD; |
412 | __le32 rxCrcErrors; |
413 | __le32 rxOversized; |
414 | __le32 rxBroadcast; |
415 | __le32 rxMulticast; |
416 | __le32 rxOverflow; |
417 | __le32 rxFiltered; |
418 | __le32 linkStatus; |
419 | #define TYPHOON_LINK_STAT_MASK cpu_to_le32(0x00000001) |
420 | #define TYPHOON_LINK_GOOD cpu_to_le32(0x00000001) |
421 | #define TYPHOON_LINK_BAD cpu_to_le32(0x00000000) |
422 | #define TYPHOON_LINK_SPEED_MASK cpu_to_le32(0x00000002) |
423 | #define TYPHOON_LINK_100MBPS cpu_to_le32(0x00000002) |
424 | #define TYPHOON_LINK_10MBPS cpu_to_le32(0x00000000) |
425 | #define TYPHOON_LINK_DUPLEX_MASK cpu_to_le32(0x00000004) |
426 | #define TYPHOON_LINK_FULL_DUPLEX cpu_to_le32(0x00000004) |
427 | #define TYPHOON_LINK_HALF_DUPLEX cpu_to_le32(0x00000000) |
428 | __le32 unused2; |
429 | __le32 unused3; |
430 | } __packed; |
431 | |
432 | /* TYPHOON_CMD_XCVR_SELECT xcvr values (resp.parm1) |
433 | */ |
434 | #define TYPHOON_XCVR_10HALF cpu_to_le16(0x0000) |
435 | #define TYPHOON_XCVR_10FULL cpu_to_le16(0x0001) |
436 | #define TYPHOON_XCVR_100HALF cpu_to_le16(0x0002) |
437 | #define TYPHOON_XCVR_100FULL cpu_to_le16(0x0003) |
438 | #define TYPHOON_XCVR_AUTONEG cpu_to_le16(0x0004) |
439 | |
440 | /* TYPHOON_CMD_READ_MEDIA_STATUS (resp.parm1) |
441 | */ |
442 | #define TYPHOON_MEDIA_STAT_CRC_STRIP_DISABLE cpu_to_le16(0x0004) |
443 | #define TYPHOON_MEDIA_STAT_COLLISION_DETECT cpu_to_le16(0x0010) |
444 | #define TYPHOON_MEDIA_STAT_CARRIER_SENSE cpu_to_le16(0x0020) |
445 | #define TYPHOON_MEDIA_STAT_POLARITY_REV cpu_to_le16(0x0400) |
446 | #define TYPHOON_MEDIA_STAT_NO_LINK cpu_to_le16(0x0800) |
447 | |
448 | /* TYPHOON_CMD_SET_MULTICAST_HASH enable values (cmd.parm1) |
449 | */ |
450 | #define TYPHOON_MCAST_HASH_DISABLE cpu_to_le16(0x0000) |
451 | #define TYPHOON_MCAST_HASH_ENABLE cpu_to_le16(0x0001) |
452 | #define TYPHOON_MCAST_HASH_SET cpu_to_le16(0x0002) |
453 | |
454 | /* TYPHOON_CMD_CREATE_SA descriptor and settings |
455 | */ |
456 | struct sa_descriptor { |
457 | u8 flags; |
458 | u8 numDesc; |
459 | u16 cmd; |
460 | u16 seqNo; |
461 | u16 mode; |
462 | #define TYPHOON_SA_MODE_NULL cpu_to_le16(0x0000) |
463 | #define TYPHOON_SA_MODE_AH cpu_to_le16(0x0001) |
464 | #define TYPHOON_SA_MODE_ESP cpu_to_le16(0x0002) |
465 | u8 hashFlags; |
466 | #define TYPHOON_SA_HASH_ENABLE 0x01 |
467 | #define TYPHOON_SA_HASH_SHA1 0x02 |
468 | #define TYPHOON_SA_HASH_MD5 0x04 |
469 | u8 direction; |
470 | #define TYPHOON_SA_DIR_RX 0x00 |
471 | #define TYPHOON_SA_DIR_TX 0x01 |
472 | u8 encryptionFlags; |
473 | #define TYPHOON_SA_ENCRYPT_ENABLE 0x01 |
474 | #define TYPHOON_SA_ENCRYPT_DES 0x02 |
475 | #define TYPHOON_SA_ENCRYPT_3DES 0x00 |
476 | #define TYPHOON_SA_ENCRYPT_3DES_2KEY 0x00 |
477 | #define TYPHOON_SA_ENCRYPT_3DES_3KEY 0x04 |
478 | #define TYPHOON_SA_ENCRYPT_CBC 0x08 |
479 | #define TYPHOON_SA_ENCRYPT_ECB 0x00 |
480 | u8 specifyIndex; |
481 | #define TYPHOON_SA_SPECIFY_INDEX 0x01 |
482 | #define TYPHOON_SA_GENERATE_INDEX 0x00 |
483 | u32 SPI; |
484 | u32 destAddr; |
485 | u32 destMask; |
486 | u8 integKey[20]; |
487 | u8 confKey[24]; |
488 | u32 index; |
489 | u32 unused; |
490 | u32 unused2; |
491 | } __packed; |
492 | |
493 | /* TYPHOON_CMD_SET_OFFLOAD_TASKS bits (cmd.parm2 (Tx) & cmd.parm3 (Rx)) |
494 | * This is all for IPv4. |
495 | */ |
496 | #define TYPHOON_OFFLOAD_TCP_CHKSUM cpu_to_le32(0x00000002) |
497 | #define TYPHOON_OFFLOAD_UDP_CHKSUM cpu_to_le32(0x00000004) |
498 | #define TYPHOON_OFFLOAD_IP_CHKSUM cpu_to_le32(0x00000008) |
499 | #define TYPHOON_OFFLOAD_IPSEC cpu_to_le32(0x00000010) |
500 | #define TYPHOON_OFFLOAD_BCAST_THROTTLE cpu_to_le32(0x00000020) |
501 | #define TYPHOON_OFFLOAD_DHCP_PREVENT cpu_to_le32(0x00000040) |
502 | #define TYPHOON_OFFLOAD_VLAN cpu_to_le32(0x00000080) |
503 | #define TYPHOON_OFFLOAD_FILTERING cpu_to_le32(0x00000100) |
504 | #define TYPHOON_OFFLOAD_TCP_SEGMENT cpu_to_le32(0x00000200) |
505 | |
506 | /* TYPHOON_CMD_ENABLE_WAKE_EVENTS bits (cmd.parm1) |
507 | */ |
508 | #define TYPHOON_WAKE_MAGIC_PKT cpu_to_le16(0x01) |
509 | #define TYPHOON_WAKE_LINK_EVENT cpu_to_le16(0x02) |
510 | #define TYPHOON_WAKE_ICMP_ECHO cpu_to_le16(0x04) |
511 | #define TYPHOON_WAKE_ARP cpu_to_le16(0x08) |
512 | |
513 | /* These are used to load the firmware image on the NIC |
514 | */ |
515 | struct { |
516 | u8 [8]; |
517 | __le32 ; |
518 | __le32 ; |
519 | __le32 ; |
520 | __le32 [5]; |
521 | } __packed; |
522 | |
523 | struct { |
524 | __le32 ; |
525 | u16 ; |
526 | u16 ; |
527 | __le32 ; |
528 | } __packed; |
529 | |
530 | /* The Typhoon Register offsets |
531 | */ |
532 | #define TYPHOON_REG_SOFT_RESET 0x00 |
533 | #define TYPHOON_REG_INTR_STATUS 0x04 |
534 | #define TYPHOON_REG_INTR_ENABLE 0x08 |
535 | #define TYPHOON_REG_INTR_MASK 0x0c |
536 | #define TYPHOON_REG_SELF_INTERRUPT 0x10 |
537 | #define TYPHOON_REG_HOST2ARM7 0x14 |
538 | #define TYPHOON_REG_HOST2ARM6 0x18 |
539 | #define TYPHOON_REG_HOST2ARM5 0x1c |
540 | #define TYPHOON_REG_HOST2ARM4 0x20 |
541 | #define TYPHOON_REG_HOST2ARM3 0x24 |
542 | #define TYPHOON_REG_HOST2ARM2 0x28 |
543 | #define TYPHOON_REG_HOST2ARM1 0x2c |
544 | #define TYPHOON_REG_HOST2ARM0 0x30 |
545 | #define TYPHOON_REG_ARM2HOST3 0x34 |
546 | #define TYPHOON_REG_ARM2HOST2 0x38 |
547 | #define TYPHOON_REG_ARM2HOST1 0x3c |
548 | #define TYPHOON_REG_ARM2HOST0 0x40 |
549 | |
550 | #define TYPHOON_REG_BOOT_DATA_LO TYPHOON_REG_HOST2ARM5 |
551 | #define TYPHOON_REG_BOOT_DATA_HI TYPHOON_REG_HOST2ARM4 |
552 | #define TYPHOON_REG_BOOT_DEST_ADDR TYPHOON_REG_HOST2ARM3 |
553 | #define TYPHOON_REG_BOOT_CHECKSUM TYPHOON_REG_HOST2ARM2 |
554 | #define TYPHOON_REG_BOOT_LENGTH TYPHOON_REG_HOST2ARM1 |
555 | |
556 | #define TYPHOON_REG_DOWNLOAD_BOOT_ADDR TYPHOON_REG_HOST2ARM1 |
557 | #define TYPHOON_REG_DOWNLOAD_HMAC_0 TYPHOON_REG_HOST2ARM2 |
558 | #define TYPHOON_REG_DOWNLOAD_HMAC_1 TYPHOON_REG_HOST2ARM3 |
559 | #define TYPHOON_REG_DOWNLOAD_HMAC_2 TYPHOON_REG_HOST2ARM4 |
560 | #define TYPHOON_REG_DOWNLOAD_HMAC_3 TYPHOON_REG_HOST2ARM5 |
561 | #define TYPHOON_REG_DOWNLOAD_HMAC_4 TYPHOON_REG_HOST2ARM6 |
562 | |
563 | #define TYPHOON_REG_BOOT_RECORD_ADDR_HI TYPHOON_REG_HOST2ARM2 |
564 | #define TYPHOON_REG_BOOT_RECORD_ADDR_LO TYPHOON_REG_HOST2ARM1 |
565 | |
566 | #define TYPHOON_REG_TX_LO_READY TYPHOON_REG_HOST2ARM3 |
567 | #define TYPHOON_REG_CMD_READY TYPHOON_REG_HOST2ARM2 |
568 | #define TYPHOON_REG_TX_HI_READY TYPHOON_REG_HOST2ARM1 |
569 | |
570 | #define TYPHOON_REG_COMMAND TYPHOON_REG_HOST2ARM0 |
571 | #define TYPHOON_REG_HEARTBEAT TYPHOON_REG_ARM2HOST3 |
572 | #define TYPHOON_REG_STATUS TYPHOON_REG_ARM2HOST0 |
573 | |
574 | /* 3XP Reset values (TYPHOON_REG_SOFT_RESET) |
575 | */ |
576 | #define TYPHOON_RESET_ALL 0x7f |
577 | #define TYPHOON_RESET_NONE 0x00 |
578 | |
579 | /* 3XP irq bits (TYPHOON_REG_INTR{STATUS,ENABLE,MASK}) |
580 | * |
581 | * Some of these came from OpenBSD, as the 3Com docs have it wrong |
582 | * (INTR_SELF) or don't list it at all (INTR_*_ABORT) |
583 | * |
584 | * Enabling irqs on the Heartbeat reg (ArmToHost3) gets you an irq |
585 | * about every 8ms, so don't do it. |
586 | */ |
587 | #define TYPHOON_INTR_HOST_INT 0x00000001 |
588 | #define TYPHOON_INTR_ARM2HOST0 0x00000002 |
589 | #define TYPHOON_INTR_ARM2HOST1 0x00000004 |
590 | #define TYPHOON_INTR_ARM2HOST2 0x00000008 |
591 | #define TYPHOON_INTR_ARM2HOST3 0x00000010 |
592 | #define TYPHOON_INTR_DMA0 0x00000020 |
593 | #define TYPHOON_INTR_DMA1 0x00000040 |
594 | #define TYPHOON_INTR_DMA2 0x00000080 |
595 | #define TYPHOON_INTR_DMA3 0x00000100 |
596 | #define TYPHOON_INTR_MASTER_ABORT 0x00000200 |
597 | #define TYPHOON_INTR_TARGET_ABORT 0x00000400 |
598 | #define TYPHOON_INTR_SELF 0x00000800 |
599 | #define TYPHOON_INTR_RESERVED 0xfffff000 |
600 | |
601 | #define TYPHOON_INTR_BOOTCMD TYPHOON_INTR_ARM2HOST0 |
602 | |
603 | #define TYPHOON_INTR_ENABLE_ALL 0xffffffef |
604 | #define TYPHOON_INTR_ALL 0xffffffff |
605 | #define TYPHOON_INTR_NONE 0x00000000 |
606 | |
607 | /* The commands for the 3XP chip (TYPHOON_REG_COMMAND) |
608 | */ |
609 | #define TYPHOON_BOOTCMD_BOOT 0x00 |
610 | #define TYPHOON_BOOTCMD_WAKEUP 0xfa |
611 | #define TYPHOON_BOOTCMD_DNLD_COMPLETE 0xfb |
612 | #define TYPHOON_BOOTCMD_SEG_AVAILABLE 0xfc |
613 | #define TYPHOON_BOOTCMD_RUNTIME_IMAGE 0xfd |
614 | #define TYPHOON_BOOTCMD_REG_BOOT_RECORD 0xff |
615 | |
616 | /* 3XP Status values (TYPHOON_REG_STATUS) |
617 | */ |
618 | #define TYPHOON_STATUS_WAITING_FOR_BOOT 0x07 |
619 | #define TYPHOON_STATUS_SECOND_INIT 0x08 |
620 | #define TYPHOON_STATUS_RUNNING 0x09 |
621 | #define TYPHOON_STATUS_WAITING_FOR_HOST 0x0d |
622 | #define TYPHOON_STATUS_WAITING_FOR_SEGMENT 0x10 |
623 | #define TYPHOON_STATUS_SLEEPING 0x11 |
624 | #define TYPHOON_STATUS_HALTED 0x14 |
625 | |