1 | /* ---------------------------------------------------------------------------- |
2 | Linux PCMCIA ethernet adapter driver for the New Media Ethernet LAN. |
3 | nmclan_cs.c,v 0.16 1995/07/01 06:42:17 rpao Exp rpao |
4 | |
5 | The Ethernet LAN uses the Advanced Micro Devices (AMD) Am79C940 Media |
6 | Access Controller for Ethernet (MACE). It is essentially the Am2150 |
7 | PCMCIA Ethernet card contained in the Am2150 Demo Kit. |
8 | |
9 | Written by Roger C. Pao <rpao@paonet.org> |
10 | Copyright 1995 Roger C. Pao |
11 | Linux 2.5 cleanups Copyright Red Hat 2003 |
12 | |
13 | This software may be used and distributed according to the terms of |
14 | the GNU General Public License. |
15 | |
16 | Ported to Linux 1.3.* network driver environment by |
17 | Matti Aarnio <mea@utu.fi> |
18 | |
19 | References |
20 | |
21 | Am2150 Technical Reference Manual, Revision 1.0, August 17, 1993 |
22 | Am79C940 (MACE) Data Sheet, 1994 |
23 | Am79C90 (C-LANCE) Data Sheet, 1994 |
24 | Linux PCMCIA Programmer's Guide v1.17 |
25 | /usr/src/linux/net/inet/dev.c, Linux kernel 1.2.8 |
26 | |
27 | Eric Mears, New Media Corporation |
28 | Tom Pollard, New Media Corporation |
29 | Dean Siasoyco, New Media Corporation |
30 | Ken Lesniak, Silicon Graphics, Inc. <lesniak@boston.sgi.com> |
31 | Donald Becker <becker@scyld.com> |
32 | David Hinds <dahinds@users.sourceforge.net> |
33 | |
34 | The Linux client driver is based on the 3c589_cs.c client driver by |
35 | David Hinds. |
36 | |
37 | The Linux network driver outline is based on the 3c589_cs.c driver, |
38 | the 8390.c driver, and the example skeleton.c kernel code, which are |
39 | by Donald Becker. |
40 | |
41 | The Am2150 network driver hardware interface code is based on the |
42 | OS/9000 driver for the New Media Ethernet LAN by Eric Mears. |
43 | |
44 | Special thanks for testing and help in debugging this driver goes |
45 | to Ken Lesniak. |
46 | |
47 | ------------------------------------------------------------------------------- |
48 | Driver Notes and Issues |
49 | ------------------------------------------------------------------------------- |
50 | |
51 | 1. Developed on a Dell 320SLi |
52 | PCMCIA Card Services 2.6.2 |
53 | Linux dell 1.2.10 #1 Thu Jun 29 20:23:41 PDT 1995 i386 |
54 | |
55 | 2. rc.pcmcia may require loading pcmcia_core with io_speed=300: |
56 | 'insmod pcmcia_core.o io_speed=300'. |
57 | This will avoid problems with fast systems which causes rx_framecnt |
58 | to return random values. |
59 | |
60 | 3. If hot extraction does not work for you, use 'ifconfig eth0 down' |
61 | before extraction. |
62 | |
63 | 4. There is a bad slow-down problem in this driver. |
64 | |
65 | 5. Future: Multicast processing. In the meantime, do _not_ compile your |
66 | kernel with multicast ip enabled. |
67 | |
68 | ------------------------------------------------------------------------------- |
69 | History |
70 | ------------------------------------------------------------------------------- |
71 | Log: nmclan_cs.c,v |
72 | * 2.5.75-ac1 2003/07/11 Alan Cox <alan@lxorguk.ukuu.org.uk> |
73 | * Fixed hang on card eject as we probe it |
74 | * Cleaned up to use new style locking. |
75 | * |
76 | * Revision 0.16 1995/07/01 06:42:17 rpao |
77 | * Bug fix: nmclan_reset() called CardServices incorrectly. |
78 | * |
79 | * Revision 0.15 1995/05/24 08:09:47 rpao |
80 | * Re-implement MULTI_TX dev->tbusy handling. |
81 | * |
82 | * Revision 0.14 1995/05/23 03:19:30 rpao |
83 | * Added, in nmclan_config(), "tuple.Attributes = 0;". |
84 | * Modified MACE ID check to ignore chip revision level. |
85 | * Avoid tx_free_frames race condition between _start_xmit and _interrupt. |
86 | * |
87 | * Revision 0.13 1995/05/18 05:56:34 rpao |
88 | * Statistics changes. |
89 | * Bug fix: nmclan_reset did not enable TX and RX: call restore_multicast_list. |
90 | * Bug fix: mace_interrupt checks ~MACE_IMR_DEFAULT. Fixes driver lockup. |
91 | * |
92 | * Revision 0.12 1995/05/14 00:12:23 rpao |
93 | * Statistics overhaul. |
94 | * |
95 | |
96 | 95/05/13 rpao V0.10a |
97 | Bug fix: MACE statistics counters used wrong I/O ports. |
98 | Bug fix: mace_interrupt() needed to allow statistics to be |
99 | processed without RX or TX interrupts pending. |
100 | 95/05/11 rpao V0.10 |
101 | Multiple transmit request processing. |
102 | Modified statistics to use MACE counters where possible. |
103 | 95/05/10 rpao V0.09 Bug fix: Must use IO_DATA_PATH_WIDTH_AUTO. |
104 | *Released |
105 | 95/05/10 rpao V0.08 |
106 | Bug fix: Make all non-exported functions private by using |
107 | static keyword. |
108 | Bug fix: Test IntrCnt _before_ reading MACE_IR. |
109 | 95/05/10 rpao V0.07 Statistics. |
110 | 95/05/09 rpao V0.06 Fix rx_framecnt problem by addition of PCIC wait states. |
111 | |
112 | ---------------------------------------------------------------------------- */ |
113 | |
114 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
115 | |
116 | #define DRV_NAME "nmclan_cs" |
117 | |
118 | /* ---------------------------------------------------------------------------- |
119 | Conditional Compilation Options |
120 | ---------------------------------------------------------------------------- */ |
121 | |
122 | #define MULTI_TX 0 |
123 | #define RESET_ON_TIMEOUT 1 |
124 | #define TX_INTERRUPTABLE 1 |
125 | #define RESET_XILINX 0 |
126 | |
127 | /* ---------------------------------------------------------------------------- |
128 | Include Files |
129 | ---------------------------------------------------------------------------- */ |
130 | |
131 | #include <linux/module.h> |
132 | #include <linux/kernel.h> |
133 | #include <linux/ptrace.h> |
134 | #include <linux/slab.h> |
135 | #include <linux/string.h> |
136 | #include <linux/timer.h> |
137 | #include <linux/interrupt.h> |
138 | #include <linux/in.h> |
139 | #include <linux/delay.h> |
140 | #include <linux/ethtool.h> |
141 | #include <linux/netdevice.h> |
142 | #include <linux/etherdevice.h> |
143 | #include <linux/skbuff.h> |
144 | #include <linux/if_arp.h> |
145 | #include <linux/ioport.h> |
146 | #include <linux/bitops.h> |
147 | |
148 | #include <pcmcia/cisreg.h> |
149 | #include <pcmcia/cistpl.h> |
150 | #include <pcmcia/ds.h> |
151 | |
152 | #include <linux/uaccess.h> |
153 | #include <asm/io.h> |
154 | |
155 | /* ---------------------------------------------------------------------------- |
156 | Defines |
157 | ---------------------------------------------------------------------------- */ |
158 | |
159 | #define MACE_LADRF_LEN 8 |
160 | /* 8 bytes in Logical Address Filter */ |
161 | |
162 | /* Loop Control Defines */ |
163 | #define MACE_MAX_IR_ITERATIONS 10 |
164 | #define MACE_MAX_RX_ITERATIONS 12 |
165 | /* |
166 | TBD: Dean brought this up, and I assumed the hardware would |
167 | handle it: |
168 | |
169 | If MACE_MAX_RX_ITERATIONS is > 1, rx_framecnt may still be |
170 | non-zero when the isr exits. We may not get another interrupt |
171 | to process the remaining packets for some time. |
172 | */ |
173 | |
174 | /* |
175 | The Am2150 has a Xilinx XC3042 field programmable gate array (FPGA) |
176 | which manages the interface between the MACE and the PCMCIA bus. It |
177 | also includes buffer management for the 32K x 8 SRAM to control up to |
178 | four transmit and 12 receive frames at a time. |
179 | */ |
180 | #define AM2150_MAX_TX_FRAMES 4 |
181 | #define AM2150_MAX_RX_FRAMES 12 |
182 | |
183 | /* Am2150 Ethernet Card I/O Mapping */ |
184 | #define AM2150_RCV 0x00 |
185 | #define AM2150_XMT 0x04 |
186 | #define AM2150_XMT_SKIP 0x09 |
187 | #define AM2150_RCV_NEXT 0x0A |
188 | #define AM2150_RCV_FRAME_COUNT 0x0B |
189 | #define AM2150_MACE_BANK 0x0C |
190 | #define AM2150_MACE_BASE 0x10 |
191 | |
192 | /* MACE Registers */ |
193 | #define MACE_RCVFIFO 0 |
194 | #define MACE_XMTFIFO 1 |
195 | #define MACE_XMTFC 2 |
196 | #define MACE_XMTFS 3 |
197 | #define MACE_XMTRC 4 |
198 | #define MACE_RCVFC 5 |
199 | #define MACE_RCVFS 6 |
200 | #define MACE_FIFOFC 7 |
201 | #define MACE_IR 8 |
202 | #define MACE_IMR 9 |
203 | #define MACE_PR 10 |
204 | #define MACE_BIUCC 11 |
205 | #define MACE_FIFOCC 12 |
206 | #define MACE_MACCC 13 |
207 | #define MACE_PLSCC 14 |
208 | #define MACE_PHYCC 15 |
209 | #define MACE_CHIPIDL 16 |
210 | #define MACE_CHIPIDH 17 |
211 | #define MACE_IAC 18 |
212 | /* Reserved */ |
213 | #define MACE_LADRF 20 |
214 | #define MACE_PADR 21 |
215 | /* Reserved */ |
216 | /* Reserved */ |
217 | #define MACE_MPC 24 |
218 | /* Reserved */ |
219 | #define MACE_RNTPC 26 |
220 | #define MACE_RCVCC 27 |
221 | /* Reserved */ |
222 | #define MACE_UTR 29 |
223 | #define MACE_RTR1 30 |
224 | #define MACE_RTR2 31 |
225 | |
226 | /* MACE Bit Masks */ |
227 | #define MACE_XMTRC_EXDEF 0x80 |
228 | #define MACE_XMTRC_XMTRC 0x0F |
229 | |
230 | #define MACE_XMTFS_XMTSV 0x80 |
231 | #define MACE_XMTFS_UFLO 0x40 |
232 | #define MACE_XMTFS_LCOL 0x20 |
233 | #define MACE_XMTFS_MORE 0x10 |
234 | #define MACE_XMTFS_ONE 0x08 |
235 | #define MACE_XMTFS_DEFER 0x04 |
236 | #define MACE_XMTFS_LCAR 0x02 |
237 | #define MACE_XMTFS_RTRY 0x01 |
238 | |
239 | #define MACE_RCVFS_RCVSTS 0xF000 |
240 | #define MACE_RCVFS_OFLO 0x8000 |
241 | #define MACE_RCVFS_CLSN 0x4000 |
242 | #define MACE_RCVFS_FRAM 0x2000 |
243 | #define MACE_RCVFS_FCS 0x1000 |
244 | |
245 | #define MACE_FIFOFC_RCVFC 0xF0 |
246 | #define MACE_FIFOFC_XMTFC 0x0F |
247 | |
248 | #define MACE_IR_JAB 0x80 |
249 | #define MACE_IR_BABL 0x40 |
250 | #define MACE_IR_CERR 0x20 |
251 | #define MACE_IR_RCVCCO 0x10 |
252 | #define MACE_IR_RNTPCO 0x08 |
253 | #define MACE_IR_MPCO 0x04 |
254 | #define MACE_IR_RCVINT 0x02 |
255 | #define MACE_IR_XMTINT 0x01 |
256 | |
257 | #define MACE_MACCC_PROM 0x80 |
258 | #define MACE_MACCC_DXMT2PD 0x40 |
259 | #define MACE_MACCC_EMBA 0x20 |
260 | #define MACE_MACCC_RESERVED 0x10 |
261 | #define MACE_MACCC_DRCVPA 0x08 |
262 | #define MACE_MACCC_DRCVBC 0x04 |
263 | #define MACE_MACCC_ENXMT 0x02 |
264 | #define MACE_MACCC_ENRCV 0x01 |
265 | |
266 | #define MACE_PHYCC_LNKFL 0x80 |
267 | #define MACE_PHYCC_DLNKTST 0x40 |
268 | #define MACE_PHYCC_REVPOL 0x20 |
269 | #define MACE_PHYCC_DAPC 0x10 |
270 | #define MACE_PHYCC_LRT 0x08 |
271 | #define MACE_PHYCC_ASEL 0x04 |
272 | #define MACE_PHYCC_RWAKE 0x02 |
273 | #define MACE_PHYCC_AWAKE 0x01 |
274 | |
275 | #define MACE_IAC_ADDRCHG 0x80 |
276 | #define MACE_IAC_PHYADDR 0x04 |
277 | #define MACE_IAC_LOGADDR 0x02 |
278 | |
279 | #define MACE_UTR_RTRE 0x80 |
280 | #define MACE_UTR_RTRD 0x40 |
281 | #define MACE_UTR_RPA 0x20 |
282 | #define MACE_UTR_FCOLL 0x10 |
283 | #define MACE_UTR_RCVFCSE 0x08 |
284 | #define MACE_UTR_LOOP_INCL_MENDEC 0x06 |
285 | #define MACE_UTR_LOOP_NO_MENDEC 0x04 |
286 | #define MACE_UTR_LOOP_EXTERNAL 0x02 |
287 | #define MACE_UTR_LOOP_NONE 0x00 |
288 | #define MACE_UTR_RESERVED 0x01 |
289 | |
290 | /* Switch MACE register bank (only 0 and 1 are valid) */ |
291 | #define MACEBANK(win_num) outb((win_num), ioaddr + AM2150_MACE_BANK) |
292 | |
293 | #define MACE_IMR_DEFAULT \ |
294 | (0xFF - \ |
295 | ( \ |
296 | MACE_IR_CERR | \ |
297 | MACE_IR_RCVCCO | \ |
298 | MACE_IR_RNTPCO | \ |
299 | MACE_IR_MPCO | \ |
300 | MACE_IR_RCVINT | \ |
301 | MACE_IR_XMTINT \ |
302 | ) \ |
303 | ) |
304 | #undef MACE_IMR_DEFAULT |
305 | #define MACE_IMR_DEFAULT 0x00 /* New statistics handling: grab everything */ |
306 | |
307 | #define TX_TIMEOUT ((400*HZ)/1000) |
308 | |
309 | /* ---------------------------------------------------------------------------- |
310 | Type Definitions |
311 | ---------------------------------------------------------------------------- */ |
312 | |
313 | typedef struct _mace_statistics { |
314 | /* MACE_XMTFS */ |
315 | int xmtsv; |
316 | int uflo; |
317 | int lcol; |
318 | int more; |
319 | int one; |
320 | int defer; |
321 | int lcar; |
322 | int rtry; |
323 | |
324 | /* MACE_XMTRC */ |
325 | int exdef; |
326 | int xmtrc; |
327 | |
328 | /* RFS1--Receive Status (RCVSTS) */ |
329 | int oflo; |
330 | int clsn; |
331 | int fram; |
332 | int fcs; |
333 | |
334 | /* RFS2--Runt Packet Count (RNTPC) */ |
335 | int rfs_rntpc; |
336 | |
337 | /* RFS3--Receive Collision Count (RCVCC) */ |
338 | int rfs_rcvcc; |
339 | |
340 | /* MACE_IR */ |
341 | int jab; |
342 | int babl; |
343 | int cerr; |
344 | int rcvcco; |
345 | int rntpco; |
346 | int mpco; |
347 | |
348 | /* MACE_MPC */ |
349 | int mpc; |
350 | |
351 | /* MACE_RNTPC */ |
352 | int rntpc; |
353 | |
354 | /* MACE_RCVCC */ |
355 | int rcvcc; |
356 | } mace_statistics; |
357 | |
358 | typedef struct _mace_private { |
359 | struct pcmcia_device *p_dev; |
360 | mace_statistics mace_stats; /* MACE chip statistics counters */ |
361 | |
362 | /* restore_multicast_list() state variables */ |
363 | int multicast_ladrf[MACE_LADRF_LEN]; /* Logical address filter */ |
364 | int multicast_num_addrs; |
365 | |
366 | char tx_free_frames; /* Number of free transmit frame buffers */ |
367 | char tx_irq_disabled; /* MACE TX interrupt disabled */ |
368 | |
369 | spinlock_t bank_lock; /* Must be held if you step off bank 0 */ |
370 | } mace_private; |
371 | |
372 | /* ---------------------------------------------------------------------------- |
373 | Private Global Variables |
374 | ---------------------------------------------------------------------------- */ |
375 | |
376 | static const char *if_names[]={ |
377 | "Auto" , "10baseT" , "BNC" , |
378 | }; |
379 | |
380 | /* ---------------------------------------------------------------------------- |
381 | Parameters |
382 | These are the parameters that can be set during loading with |
383 | 'insmod'. |
384 | ---------------------------------------------------------------------------- */ |
385 | |
386 | MODULE_DESCRIPTION("New Media PCMCIA ethernet driver" ); |
387 | MODULE_LICENSE("GPL" ); |
388 | |
389 | #define INT_MODULE_PARM(n, v) static int n = v; module_param(n, int, 0) |
390 | |
391 | /* 0=auto, 1=10baseT, 2 = 10base2, default=auto */ |
392 | INT_MODULE_PARM(if_port, 0); |
393 | |
394 | |
395 | /* ---------------------------------------------------------------------------- |
396 | Function Prototypes |
397 | ---------------------------------------------------------------------------- */ |
398 | |
399 | static int nmclan_config(struct pcmcia_device *link); |
400 | static void nmclan_release(struct pcmcia_device *link); |
401 | |
402 | static void nmclan_reset(struct net_device *dev); |
403 | static int mace_config(struct net_device *dev, struct ifmap *map); |
404 | static int mace_open(struct net_device *dev); |
405 | static int mace_close(struct net_device *dev); |
406 | static netdev_tx_t mace_start_xmit(struct sk_buff *skb, |
407 | struct net_device *dev); |
408 | static void mace_tx_timeout(struct net_device *dev, unsigned int txqueue); |
409 | static irqreturn_t mace_interrupt(int irq, void *dev_id); |
410 | static struct net_device_stats *mace_get_stats(struct net_device *dev); |
411 | static int mace_rx(struct net_device *dev, unsigned char RxCnt); |
412 | static void restore_multicast_list(struct net_device *dev); |
413 | static void set_multicast_list(struct net_device *dev); |
414 | static const struct ethtool_ops netdev_ethtool_ops; |
415 | |
416 | |
417 | static void nmclan_detach(struct pcmcia_device *p_dev); |
418 | |
419 | static const struct net_device_ops mace_netdev_ops = { |
420 | .ndo_open = mace_open, |
421 | .ndo_stop = mace_close, |
422 | .ndo_start_xmit = mace_start_xmit, |
423 | .ndo_tx_timeout = mace_tx_timeout, |
424 | .ndo_set_config = mace_config, |
425 | .ndo_get_stats = mace_get_stats, |
426 | .ndo_set_rx_mode = set_multicast_list, |
427 | .ndo_set_mac_address = eth_mac_addr, |
428 | .ndo_validate_addr = eth_validate_addr, |
429 | }; |
430 | |
431 | static int nmclan_probe(struct pcmcia_device *link) |
432 | { |
433 | mace_private *lp; |
434 | struct net_device *dev; |
435 | |
436 | dev_dbg(&link->dev, "nmclan_attach()\n" ); |
437 | |
438 | /* Create new ethernet device */ |
439 | dev = alloc_etherdev(sizeof(mace_private)); |
440 | if (!dev) |
441 | return -ENOMEM; |
442 | lp = netdev_priv(dev); |
443 | lp->p_dev = link; |
444 | link->priv = dev; |
445 | |
446 | spin_lock_init(&lp->bank_lock); |
447 | link->resource[0]->end = 32; |
448 | link->resource[0]->flags |= IO_DATA_PATH_WIDTH_AUTO; |
449 | link->config_flags |= CONF_ENABLE_IRQ; |
450 | link->config_index = 1; |
451 | link->config_regs = PRESENT_OPTION; |
452 | |
453 | lp->tx_free_frames=AM2150_MAX_TX_FRAMES; |
454 | |
455 | dev->netdev_ops = &mace_netdev_ops; |
456 | dev->ethtool_ops = &netdev_ethtool_ops; |
457 | dev->watchdog_timeo = TX_TIMEOUT; |
458 | |
459 | return nmclan_config(link); |
460 | } /* nmclan_attach */ |
461 | |
462 | static void nmclan_detach(struct pcmcia_device *link) |
463 | { |
464 | struct net_device *dev = link->priv; |
465 | |
466 | dev_dbg(&link->dev, "nmclan_detach\n" ); |
467 | |
468 | unregister_netdev(dev); |
469 | |
470 | nmclan_release(link); |
471 | |
472 | free_netdev(dev); |
473 | } /* nmclan_detach */ |
474 | |
475 | /* ---------------------------------------------------------------------------- |
476 | mace_read |
477 | Reads a MACE register. This is bank independent; however, the |
478 | caller must ensure that this call is not interruptable. We are |
479 | assuming that during normal operation, the MACE is always in |
480 | bank 0. |
481 | ---------------------------------------------------------------------------- */ |
482 | static int mace_read(mace_private *lp, unsigned int ioaddr, int reg) |
483 | { |
484 | int data = 0xFF; |
485 | unsigned long flags; |
486 | |
487 | switch (reg >> 4) { |
488 | case 0: /* register 0-15 */ |
489 | data = inb(port: ioaddr + AM2150_MACE_BASE + reg); |
490 | break; |
491 | case 1: /* register 16-31 */ |
492 | spin_lock_irqsave(&lp->bank_lock, flags); |
493 | MACEBANK(1); |
494 | data = inb(port: ioaddr + AM2150_MACE_BASE + (reg & 0x0F)); |
495 | MACEBANK(0); |
496 | spin_unlock_irqrestore(lock: &lp->bank_lock, flags); |
497 | break; |
498 | } |
499 | return data & 0xFF; |
500 | } /* mace_read */ |
501 | |
502 | /* ---------------------------------------------------------------------------- |
503 | mace_write |
504 | Writes to a MACE register. This is bank independent; however, |
505 | the caller must ensure that this call is not interruptable. We |
506 | are assuming that during normal operation, the MACE is always in |
507 | bank 0. |
508 | ---------------------------------------------------------------------------- */ |
509 | static void mace_write(mace_private *lp, unsigned int ioaddr, int reg, |
510 | int data) |
511 | { |
512 | unsigned long flags; |
513 | |
514 | switch (reg >> 4) { |
515 | case 0: /* register 0-15 */ |
516 | outb(value: data & 0xFF, port: ioaddr + AM2150_MACE_BASE + reg); |
517 | break; |
518 | case 1: /* register 16-31 */ |
519 | spin_lock_irqsave(&lp->bank_lock, flags); |
520 | MACEBANK(1); |
521 | outb(value: data & 0xFF, port: ioaddr + AM2150_MACE_BASE + (reg & 0x0F)); |
522 | MACEBANK(0); |
523 | spin_unlock_irqrestore(lock: &lp->bank_lock, flags); |
524 | break; |
525 | } |
526 | } /* mace_write */ |
527 | |
528 | /* ---------------------------------------------------------------------------- |
529 | mace_init |
530 | Resets the MACE chip. |
531 | ---------------------------------------------------------------------------- */ |
532 | static int mace_init(mace_private *lp, unsigned int ioaddr, |
533 | const char *enet_addr) |
534 | { |
535 | int i; |
536 | int ct = 0; |
537 | |
538 | /* MACE Software reset */ |
539 | mace_write(lp, ioaddr, MACE_BIUCC, data: 1); |
540 | while (mace_read(lp, ioaddr, MACE_BIUCC) & 0x01) { |
541 | /* Wait for reset bit to be cleared automatically after <= 200ns */; |
542 | if(++ct > 500) |
543 | { |
544 | pr_err("reset failed, card removed?\n" ); |
545 | return -1; |
546 | } |
547 | udelay(1); |
548 | } |
549 | mace_write(lp, ioaddr, MACE_BIUCC, data: 0); |
550 | |
551 | /* The Am2150 requires that the MACE FIFOs operate in burst mode. */ |
552 | mace_write(lp, ioaddr, MACE_FIFOCC, data: 0x0F); |
553 | |
554 | mace_write(lp,ioaddr, MACE_RCVFC, data: 0); /* Disable Auto Strip Receive */ |
555 | mace_write(lp, ioaddr, MACE_IMR, data: 0xFF); /* Disable all interrupts until _open */ |
556 | |
557 | /* |
558 | * Bit 2-1 PORTSEL[1-0] Port Select. |
559 | * 00 AUI/10Base-2 |
560 | * 01 10Base-T |
561 | * 10 DAI Port (reserved in Am2150) |
562 | * 11 GPSI |
563 | * For this card, only the first two are valid. |
564 | * So, PLSCC should be set to |
565 | * 0x00 for 10Base-2 |
566 | * 0x02 for 10Base-T |
567 | * Or just set ASEL in PHYCC below! |
568 | */ |
569 | switch (if_port) { |
570 | case 1: |
571 | mace_write(lp, ioaddr, MACE_PLSCC, data: 0x02); |
572 | break; |
573 | case 2: |
574 | mace_write(lp, ioaddr, MACE_PLSCC, data: 0x00); |
575 | break; |
576 | default: |
577 | mace_write(lp, ioaddr, MACE_PHYCC, /* ASEL */ data: 4); |
578 | /* ASEL Auto Select. When set, the PORTSEL[1-0] bits are overridden, |
579 | and the MACE device will automatically select the operating media |
580 | interface port. */ |
581 | break; |
582 | } |
583 | |
584 | mace_write(lp, ioaddr, MACE_IAC, MACE_IAC_ADDRCHG | MACE_IAC_PHYADDR); |
585 | /* Poll ADDRCHG bit */ |
586 | ct = 0; |
587 | while (mace_read(lp, ioaddr, MACE_IAC) & MACE_IAC_ADDRCHG) |
588 | { |
589 | if(++ ct > 500) |
590 | { |
591 | pr_err("ADDRCHG timeout, card removed?\n" ); |
592 | return -1; |
593 | } |
594 | } |
595 | /* Set PADR register */ |
596 | for (i = 0; i < ETH_ALEN; i++) |
597 | mace_write(lp, ioaddr, MACE_PADR, data: enet_addr[i]); |
598 | |
599 | /* MAC Configuration Control Register should be written last */ |
600 | /* Let set_multicast_list set this. */ |
601 | /* mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV); */ |
602 | mace_write(lp, ioaddr, MACE_MACCC, data: 0x00); |
603 | return 0; |
604 | } /* mace_init */ |
605 | |
606 | static int nmclan_config(struct pcmcia_device *link) |
607 | { |
608 | struct net_device *dev = link->priv; |
609 | mace_private *lp = netdev_priv(dev); |
610 | u8 *buf; |
611 | size_t len; |
612 | int i, ret; |
613 | unsigned int ioaddr; |
614 | |
615 | dev_dbg(&link->dev, "nmclan_config\n" ); |
616 | |
617 | link->io_lines = 5; |
618 | ret = pcmcia_request_io(p_dev: link); |
619 | if (ret) |
620 | goto failed; |
621 | ret = pcmcia_request_irq(p_dev: link, handler: mace_interrupt); |
622 | if (ret) |
623 | goto failed; |
624 | ret = pcmcia_enable_device(p_dev: link); |
625 | if (ret) |
626 | goto failed; |
627 | |
628 | dev->irq = link->irq; |
629 | dev->base_addr = link->resource[0]->start; |
630 | |
631 | ioaddr = dev->base_addr; |
632 | |
633 | /* Read the ethernet address from the CIS. */ |
634 | len = pcmcia_get_tuple(p_dev: link, code: 0x80, buf: &buf); |
635 | if (!buf || len < ETH_ALEN) { |
636 | kfree(objp: buf); |
637 | goto failed; |
638 | } |
639 | eth_hw_addr_set(dev, addr: buf); |
640 | kfree(objp: buf); |
641 | |
642 | /* Verify configuration by reading the MACE ID. */ |
643 | { |
644 | char sig[2]; |
645 | |
646 | sig[0] = mace_read(lp, ioaddr, MACE_CHIPIDL); |
647 | sig[1] = mace_read(lp, ioaddr, MACE_CHIPIDH); |
648 | if ((sig[0] == 0x40) && ((sig[1] & 0x0F) == 0x09)) { |
649 | dev_dbg(&link->dev, "nmclan_cs configured: mace id=%x %x\n" , |
650 | sig[0], sig[1]); |
651 | } else { |
652 | pr_notice("mace id not found: %x %x should be 0x40 0x?9\n" , |
653 | sig[0], sig[1]); |
654 | goto failed; |
655 | } |
656 | } |
657 | |
658 | if(mace_init(lp, ioaddr, enet_addr: dev->dev_addr) == -1) |
659 | goto failed; |
660 | |
661 | /* The if_port symbol can be set when the module is loaded */ |
662 | if (if_port <= 2) |
663 | dev->if_port = if_port; |
664 | else |
665 | pr_notice("invalid if_port requested\n" ); |
666 | |
667 | SET_NETDEV_DEV(dev, &link->dev); |
668 | |
669 | i = register_netdev(dev); |
670 | if (i != 0) { |
671 | pr_notice("register_netdev() failed\n" ); |
672 | goto failed; |
673 | } |
674 | |
675 | netdev_info(dev, format: "nmclan: port %#3lx, irq %d, %s port, hw_addr %pM\n" , |
676 | dev->base_addr, dev->irq, if_names[dev->if_port], dev->dev_addr); |
677 | return 0; |
678 | |
679 | failed: |
680 | nmclan_release(link); |
681 | return -ENODEV; |
682 | } /* nmclan_config */ |
683 | |
684 | static void nmclan_release(struct pcmcia_device *link) |
685 | { |
686 | dev_dbg(&link->dev, "nmclan_release\n" ); |
687 | pcmcia_disable_device(p_dev: link); |
688 | } |
689 | |
690 | static int nmclan_suspend(struct pcmcia_device *link) |
691 | { |
692 | struct net_device *dev = link->priv; |
693 | |
694 | if (link->open) |
695 | netif_device_detach(dev); |
696 | |
697 | return 0; |
698 | } |
699 | |
700 | static int nmclan_resume(struct pcmcia_device *link) |
701 | { |
702 | struct net_device *dev = link->priv; |
703 | |
704 | if (link->open) { |
705 | nmclan_reset(dev); |
706 | netif_device_attach(dev); |
707 | } |
708 | |
709 | return 0; |
710 | } |
711 | |
712 | |
713 | /* ---------------------------------------------------------------------------- |
714 | nmclan_reset |
715 | Reset and restore all of the Xilinx and MACE registers. |
716 | ---------------------------------------------------------------------------- */ |
717 | static void nmclan_reset(struct net_device *dev) |
718 | { |
719 | mace_private *lp = netdev_priv(dev); |
720 | |
721 | #if RESET_XILINX |
722 | struct pcmcia_device *link = &lp->link; |
723 | u8 OrigCorValue; |
724 | |
725 | /* Save original COR value */ |
726 | pcmcia_read_config_byte(link, CISREG_COR, &OrigCorValue); |
727 | |
728 | /* Reset Xilinx */ |
729 | dev_dbg(&link->dev, "nmclan_reset: OrigCorValue=0x%x, resetting...\n" , |
730 | OrigCorValue); |
731 | pcmcia_write_config_byte(link, CISREG_COR, COR_SOFT_RESET); |
732 | /* Need to wait for 20 ms for PCMCIA to finish reset. */ |
733 | |
734 | /* Restore original COR configuration index */ |
735 | pcmcia_write_config_byte(link, CISREG_COR, |
736 | (COR_LEVEL_REQ | (OrigCorValue & COR_CONFIG_MASK))); |
737 | /* Xilinx is now completely reset along with the MACE chip. */ |
738 | lp->tx_free_frames=AM2150_MAX_TX_FRAMES; |
739 | |
740 | #endif /* #if RESET_XILINX */ |
741 | |
742 | /* Xilinx is now completely reset along with the MACE chip. */ |
743 | lp->tx_free_frames=AM2150_MAX_TX_FRAMES; |
744 | |
745 | /* Reinitialize the MACE chip for operation. */ |
746 | mace_init(lp, ioaddr: dev->base_addr, enet_addr: dev->dev_addr); |
747 | mace_write(lp, ioaddr: dev->base_addr, MACE_IMR, MACE_IMR_DEFAULT); |
748 | |
749 | /* Restore the multicast list and enable TX and RX. */ |
750 | restore_multicast_list(dev); |
751 | } /* nmclan_reset */ |
752 | |
753 | /* ---------------------------------------------------------------------------- |
754 | mace_config |
755 | [Someone tell me what this is supposed to do? Is if_port a defined |
756 | standard? If so, there should be defines to indicate 1=10Base-T, |
757 | 2=10Base-2, etc. including limited automatic detection.] |
758 | ---------------------------------------------------------------------------- */ |
759 | static int mace_config(struct net_device *dev, struct ifmap *map) |
760 | { |
761 | if ((map->port != (u_char)(-1)) && (map->port != dev->if_port)) { |
762 | if (map->port <= 2) { |
763 | dev->if_port = map->port; |
764 | netdev_info(dev, format: "switched to %s port\n" , if_names[dev->if_port]); |
765 | } else |
766 | return -EINVAL; |
767 | } |
768 | return 0; |
769 | } /* mace_config */ |
770 | |
771 | /* ---------------------------------------------------------------------------- |
772 | mace_open |
773 | Open device driver. |
774 | ---------------------------------------------------------------------------- */ |
775 | static int mace_open(struct net_device *dev) |
776 | { |
777 | unsigned int ioaddr = dev->base_addr; |
778 | mace_private *lp = netdev_priv(dev); |
779 | struct pcmcia_device *link = lp->p_dev; |
780 | |
781 | if (!pcmcia_dev_present(p_dev: link)) |
782 | return -ENODEV; |
783 | |
784 | link->open++; |
785 | |
786 | MACEBANK(0); |
787 | |
788 | netif_start_queue(dev); |
789 | nmclan_reset(dev); |
790 | |
791 | return 0; /* Always succeed */ |
792 | } /* mace_open */ |
793 | |
794 | /* ---------------------------------------------------------------------------- |
795 | mace_close |
796 | Closes device driver. |
797 | ---------------------------------------------------------------------------- */ |
798 | static int mace_close(struct net_device *dev) |
799 | { |
800 | unsigned int ioaddr = dev->base_addr; |
801 | mace_private *lp = netdev_priv(dev); |
802 | struct pcmcia_device *link = lp->p_dev; |
803 | |
804 | dev_dbg(&link->dev, "%s: shutting down ethercard.\n" , dev->name); |
805 | |
806 | /* Mask off all interrupts from the MACE chip. */ |
807 | outb(value: 0xFF, port: ioaddr + AM2150_MACE_BASE + MACE_IMR); |
808 | |
809 | link->open--; |
810 | netif_stop_queue(dev); |
811 | |
812 | return 0; |
813 | } /* mace_close */ |
814 | |
815 | static void netdev_get_drvinfo(struct net_device *dev, |
816 | struct ethtool_drvinfo *info) |
817 | { |
818 | strscpy(p: info->driver, DRV_NAME, size: sizeof(info->driver)); |
819 | snprintf(buf: info->bus_info, size: sizeof(info->bus_info), |
820 | fmt: "PCMCIA 0x%lx" , dev->base_addr); |
821 | } |
822 | |
823 | static const struct ethtool_ops netdev_ethtool_ops = { |
824 | .get_drvinfo = netdev_get_drvinfo, |
825 | }; |
826 | |
827 | /* ---------------------------------------------------------------------------- |
828 | mace_start_xmit |
829 | This routine begins the packet transmit function. When completed, |
830 | it will generate a transmit interrupt. |
831 | |
832 | According to /usr/src/linux/net/inet/dev.c, if _start_xmit |
833 | returns 0, the "packet is now solely the responsibility of the |
834 | driver." If _start_xmit returns non-zero, the "transmission |
835 | failed, put skb back into a list." |
836 | ---------------------------------------------------------------------------- */ |
837 | |
838 | static void mace_tx_timeout(struct net_device *dev, unsigned int txqueue) |
839 | { |
840 | mace_private *lp = netdev_priv(dev); |
841 | struct pcmcia_device *link = lp->p_dev; |
842 | |
843 | netdev_notice(dev, format: "transmit timed out -- " ); |
844 | #if RESET_ON_TIMEOUT |
845 | pr_cont("resetting card\n" ); |
846 | pcmcia_reset_card(skt: link->socket); |
847 | #else /* #if RESET_ON_TIMEOUT */ |
848 | pr_cont("NOT resetting card\n" ); |
849 | #endif /* #if RESET_ON_TIMEOUT */ |
850 | netif_trans_update(dev); /* prevent tx timeout */ |
851 | netif_wake_queue(dev); |
852 | } |
853 | |
854 | static netdev_tx_t mace_start_xmit(struct sk_buff *skb, |
855 | struct net_device *dev) |
856 | { |
857 | mace_private *lp = netdev_priv(dev); |
858 | unsigned int ioaddr = dev->base_addr; |
859 | |
860 | netif_stop_queue(dev); |
861 | |
862 | pr_debug("%s: mace_start_xmit(length = %ld) called.\n" , |
863 | dev->name, (long)skb->len); |
864 | |
865 | #if (!TX_INTERRUPTABLE) |
866 | /* Disable MACE TX interrupts. */ |
867 | outb(MACE_IMR_DEFAULT | MACE_IR_XMTINT, |
868 | ioaddr + AM2150_MACE_BASE + MACE_IMR); |
869 | lp->tx_irq_disabled=1; |
870 | #endif /* #if (!TX_INTERRUPTABLE) */ |
871 | |
872 | { |
873 | /* This block must not be interrupted by another transmit request! |
874 | mace_tx_timeout will take care of timer-based retransmissions from |
875 | the upper layers. The interrupt handler is guaranteed never to |
876 | service a transmit interrupt while we are in here. |
877 | */ |
878 | |
879 | dev->stats.tx_bytes += skb->len; |
880 | lp->tx_free_frames--; |
881 | |
882 | /* WARNING: Write the _exact_ number of bytes written in the header! */ |
883 | /* Put out the word header [must be an outw()] . . . */ |
884 | outw(value: skb->len, port: ioaddr + AM2150_XMT); |
885 | /* . . . and the packet [may be any combination of outw() and outb()] */ |
886 | outsw(port: ioaddr + AM2150_XMT, addr: skb->data, count: skb->len >> 1); |
887 | if (skb->len & 1) { |
888 | /* Odd byte transfer */ |
889 | outb(value: skb->data[skb->len-1], port: ioaddr + AM2150_XMT); |
890 | } |
891 | |
892 | #if MULTI_TX |
893 | if (lp->tx_free_frames > 0) |
894 | netif_start_queue(dev); |
895 | #endif /* #if MULTI_TX */ |
896 | } |
897 | |
898 | #if (!TX_INTERRUPTABLE) |
899 | /* Re-enable MACE TX interrupts. */ |
900 | lp->tx_irq_disabled=0; |
901 | outb(MACE_IMR_DEFAULT, ioaddr + AM2150_MACE_BASE + MACE_IMR); |
902 | #endif /* #if (!TX_INTERRUPTABLE) */ |
903 | |
904 | dev_kfree_skb(skb); |
905 | |
906 | return NETDEV_TX_OK; |
907 | } /* mace_start_xmit */ |
908 | |
909 | /* ---------------------------------------------------------------------------- |
910 | mace_interrupt |
911 | The interrupt handler. |
912 | ---------------------------------------------------------------------------- */ |
913 | static irqreturn_t mace_interrupt(int irq, void *dev_id) |
914 | { |
915 | struct net_device *dev = (struct net_device *) dev_id; |
916 | mace_private *lp = netdev_priv(dev); |
917 | unsigned int ioaddr; |
918 | int status; |
919 | int IntrCnt = MACE_MAX_IR_ITERATIONS; |
920 | |
921 | if (!dev) { |
922 | pr_debug("mace_interrupt(): irq 0x%X for unknown device.\n" , |
923 | irq); |
924 | return IRQ_NONE; |
925 | } |
926 | |
927 | ioaddr = dev->base_addr; |
928 | |
929 | if (lp->tx_irq_disabled) { |
930 | const char *msg; |
931 | if (lp->tx_irq_disabled) |
932 | msg = "Interrupt with tx_irq_disabled" ; |
933 | else |
934 | msg = "Re-entering the interrupt handler" ; |
935 | netdev_notice(dev, format: "%s [isr=%02X, imr=%02X]\n" , |
936 | msg, |
937 | inb(port: ioaddr + AM2150_MACE_BASE + MACE_IR), |
938 | inb(port: ioaddr + AM2150_MACE_BASE + MACE_IMR)); |
939 | /* WARNING: MACE_IR has been read! */ |
940 | return IRQ_NONE; |
941 | } |
942 | |
943 | if (!netif_device_present(dev)) { |
944 | netdev_dbg(dev, "interrupt from dead card\n" ); |
945 | return IRQ_NONE; |
946 | } |
947 | |
948 | do { |
949 | /* WARNING: MACE_IR is a READ/CLEAR port! */ |
950 | status = inb(port: ioaddr + AM2150_MACE_BASE + MACE_IR); |
951 | if (!(status & ~MACE_IMR_DEFAULT) && IntrCnt == MACE_MAX_IR_ITERATIONS) |
952 | return IRQ_NONE; |
953 | |
954 | pr_debug("mace_interrupt: irq 0x%X status 0x%X.\n" , irq, status); |
955 | |
956 | if (status & MACE_IR_RCVINT) { |
957 | mace_rx(dev, MACE_MAX_RX_ITERATIONS); |
958 | } |
959 | |
960 | if (status & MACE_IR_XMTINT) { |
961 | unsigned char fifofc; |
962 | unsigned char xmtrc; |
963 | unsigned char xmtfs; |
964 | |
965 | fifofc = inb(port: ioaddr + AM2150_MACE_BASE + MACE_FIFOFC); |
966 | if ((fifofc & MACE_FIFOFC_XMTFC)==0) { |
967 | dev->stats.tx_errors++; |
968 | outb(value: 0xFF, port: ioaddr + AM2150_XMT_SKIP); |
969 | } |
970 | |
971 | /* Transmit Retry Count (XMTRC, reg 4) */ |
972 | xmtrc = inb(port: ioaddr + AM2150_MACE_BASE + MACE_XMTRC); |
973 | if (xmtrc & MACE_XMTRC_EXDEF) lp->mace_stats.exdef++; |
974 | lp->mace_stats.xmtrc += (xmtrc & MACE_XMTRC_XMTRC); |
975 | |
976 | if ( |
977 | (xmtfs = inb(port: ioaddr + AM2150_MACE_BASE + MACE_XMTFS)) & |
978 | MACE_XMTFS_XMTSV /* Transmit Status Valid */ |
979 | ) { |
980 | lp->mace_stats.xmtsv++; |
981 | |
982 | if (xmtfs & ~MACE_XMTFS_XMTSV) { |
983 | if (xmtfs & MACE_XMTFS_UFLO) { |
984 | /* Underflow. Indicates that the Transmit FIFO emptied before |
985 | the end of frame was reached. */ |
986 | lp->mace_stats.uflo++; |
987 | } |
988 | if (xmtfs & MACE_XMTFS_LCOL) { |
989 | /* Late Collision */ |
990 | lp->mace_stats.lcol++; |
991 | } |
992 | if (xmtfs & MACE_XMTFS_MORE) { |
993 | /* MORE than one retry was needed */ |
994 | lp->mace_stats.more++; |
995 | } |
996 | if (xmtfs & MACE_XMTFS_ONE) { |
997 | /* Exactly ONE retry occurred */ |
998 | lp->mace_stats.one++; |
999 | } |
1000 | if (xmtfs & MACE_XMTFS_DEFER) { |
1001 | /* Transmission was defered */ |
1002 | lp->mace_stats.defer++; |
1003 | } |
1004 | if (xmtfs & MACE_XMTFS_LCAR) { |
1005 | /* Loss of carrier */ |
1006 | lp->mace_stats.lcar++; |
1007 | } |
1008 | if (xmtfs & MACE_XMTFS_RTRY) { |
1009 | /* Retry error: transmit aborted after 16 attempts */ |
1010 | lp->mace_stats.rtry++; |
1011 | } |
1012 | } /* if (xmtfs & ~MACE_XMTFS_XMTSV) */ |
1013 | |
1014 | } /* if (xmtfs & MACE_XMTFS_XMTSV) */ |
1015 | |
1016 | dev->stats.tx_packets++; |
1017 | lp->tx_free_frames++; |
1018 | netif_wake_queue(dev); |
1019 | } /* if (status & MACE_IR_XMTINT) */ |
1020 | |
1021 | if (status & ~MACE_IMR_DEFAULT & ~MACE_IR_RCVINT & ~MACE_IR_XMTINT) { |
1022 | if (status & MACE_IR_JAB) { |
1023 | /* Jabber Error. Excessive transmit duration (20-150ms). */ |
1024 | lp->mace_stats.jab++; |
1025 | } |
1026 | if (status & MACE_IR_BABL) { |
1027 | /* Babble Error. >1518 bytes transmitted. */ |
1028 | lp->mace_stats.babl++; |
1029 | } |
1030 | if (status & MACE_IR_CERR) { |
1031 | /* Collision Error. CERR indicates the absence of the |
1032 | Signal Quality Error Test message after a packet |
1033 | transmission. */ |
1034 | lp->mace_stats.cerr++; |
1035 | } |
1036 | if (status & MACE_IR_RCVCCO) { |
1037 | /* Receive Collision Count Overflow; */ |
1038 | lp->mace_stats.rcvcco++; |
1039 | } |
1040 | if (status & MACE_IR_RNTPCO) { |
1041 | /* Runt Packet Count Overflow */ |
1042 | lp->mace_stats.rntpco++; |
1043 | } |
1044 | if (status & MACE_IR_MPCO) { |
1045 | /* Missed Packet Count Overflow */ |
1046 | lp->mace_stats.mpco++; |
1047 | } |
1048 | } /* if (status & ~MACE_IMR_DEFAULT & ~MACE_IR_RCVINT & ~MACE_IR_XMTINT) */ |
1049 | |
1050 | } while ((status & ~MACE_IMR_DEFAULT) && (--IntrCnt)); |
1051 | |
1052 | return IRQ_HANDLED; |
1053 | } /* mace_interrupt */ |
1054 | |
1055 | /* ---------------------------------------------------------------------------- |
1056 | mace_rx |
1057 | Receives packets. |
1058 | ---------------------------------------------------------------------------- */ |
1059 | static int mace_rx(struct net_device *dev, unsigned char RxCnt) |
1060 | { |
1061 | mace_private *lp = netdev_priv(dev); |
1062 | unsigned int ioaddr = dev->base_addr; |
1063 | unsigned char rx_framecnt; |
1064 | unsigned short rx_status; |
1065 | |
1066 | while ( |
1067 | ((rx_framecnt = inb(port: ioaddr + AM2150_RCV_FRAME_COUNT)) > 0) && |
1068 | (rx_framecnt <= 12) && /* rx_framecnt==0xFF if card is extracted. */ |
1069 | (RxCnt--) |
1070 | ) { |
1071 | rx_status = inw(port: ioaddr + AM2150_RCV); |
1072 | |
1073 | pr_debug("%s: in mace_rx(), framecnt 0x%X, rx_status" |
1074 | " 0x%X.\n" , dev->name, rx_framecnt, rx_status); |
1075 | |
1076 | if (rx_status & MACE_RCVFS_RCVSTS) { /* Error, update stats. */ |
1077 | dev->stats.rx_errors++; |
1078 | if (rx_status & MACE_RCVFS_OFLO) { |
1079 | lp->mace_stats.oflo++; |
1080 | } |
1081 | if (rx_status & MACE_RCVFS_CLSN) { |
1082 | lp->mace_stats.clsn++; |
1083 | } |
1084 | if (rx_status & MACE_RCVFS_FRAM) { |
1085 | lp->mace_stats.fram++; |
1086 | } |
1087 | if (rx_status & MACE_RCVFS_FCS) { |
1088 | lp->mace_stats.fcs++; |
1089 | } |
1090 | } else { |
1091 | short pkt_len = (rx_status & ~MACE_RCVFS_RCVSTS) - 4; |
1092 | /* Auto Strip is off, always subtract 4 */ |
1093 | struct sk_buff *skb; |
1094 | |
1095 | lp->mace_stats.rfs_rntpc += inb(port: ioaddr + AM2150_RCV); |
1096 | /* runt packet count */ |
1097 | lp->mace_stats.rfs_rcvcc += inb(port: ioaddr + AM2150_RCV); |
1098 | /* rcv collision count */ |
1099 | |
1100 | pr_debug(" receiving packet size 0x%X rx_status" |
1101 | " 0x%X.\n" , pkt_len, rx_status); |
1102 | |
1103 | skb = netdev_alloc_skb(dev, length: pkt_len + 2); |
1104 | |
1105 | if (skb) { |
1106 | skb_reserve(skb, len: 2); |
1107 | insw(port: ioaddr + AM2150_RCV, addr: skb_put(skb, len: pkt_len), count: pkt_len>>1); |
1108 | if (pkt_len & 1) |
1109 | *(skb_tail_pointer(skb) - 1) = inb(port: ioaddr + AM2150_RCV); |
1110 | skb->protocol = eth_type_trans(skb, dev); |
1111 | |
1112 | netif_rx(skb); /* Send the packet to the upper (protocol) layers. */ |
1113 | |
1114 | dev->stats.rx_packets++; |
1115 | dev->stats.rx_bytes += pkt_len; |
1116 | outb(value: 0xFF, port: ioaddr + AM2150_RCV_NEXT); /* skip to next frame */ |
1117 | continue; |
1118 | } else { |
1119 | pr_debug("%s: couldn't allocate a sk_buff of size" |
1120 | " %d.\n" , dev->name, pkt_len); |
1121 | dev->stats.rx_dropped++; |
1122 | } |
1123 | } |
1124 | outb(value: 0xFF, port: ioaddr + AM2150_RCV_NEXT); /* skip to next frame */ |
1125 | } /* while */ |
1126 | |
1127 | return 0; |
1128 | } /* mace_rx */ |
1129 | |
1130 | /* ---------------------------------------------------------------------------- |
1131 | pr_linux_stats |
1132 | ---------------------------------------------------------------------------- */ |
1133 | static void pr_linux_stats(struct net_device_stats *pstats) |
1134 | { |
1135 | pr_debug("pr_linux_stats\n" ); |
1136 | pr_debug(" rx_packets=%-7ld tx_packets=%ld\n" , |
1137 | (long)pstats->rx_packets, (long)pstats->tx_packets); |
1138 | pr_debug(" rx_errors=%-7ld tx_errors=%ld\n" , |
1139 | (long)pstats->rx_errors, (long)pstats->tx_errors); |
1140 | pr_debug(" rx_dropped=%-7ld tx_dropped=%ld\n" , |
1141 | (long)pstats->rx_dropped, (long)pstats->tx_dropped); |
1142 | pr_debug(" multicast=%-7ld collisions=%ld\n" , |
1143 | (long)pstats->multicast, (long)pstats->collisions); |
1144 | |
1145 | pr_debug(" rx_length_errors=%-7ld rx_over_errors=%ld\n" , |
1146 | (long)pstats->rx_length_errors, (long)pstats->rx_over_errors); |
1147 | pr_debug(" rx_crc_errors=%-7ld rx_frame_errors=%ld\n" , |
1148 | (long)pstats->rx_crc_errors, (long)pstats->rx_frame_errors); |
1149 | pr_debug(" rx_fifo_errors=%-7ld rx_missed_errors=%ld\n" , |
1150 | (long)pstats->rx_fifo_errors, (long)pstats->rx_missed_errors); |
1151 | |
1152 | pr_debug(" tx_aborted_errors=%-7ld tx_carrier_errors=%ld\n" , |
1153 | (long)pstats->tx_aborted_errors, (long)pstats->tx_carrier_errors); |
1154 | pr_debug(" tx_fifo_errors=%-7ld tx_heartbeat_errors=%ld\n" , |
1155 | (long)pstats->tx_fifo_errors, (long)pstats->tx_heartbeat_errors); |
1156 | pr_debug(" tx_window_errors=%ld\n" , |
1157 | (long)pstats->tx_window_errors); |
1158 | } /* pr_linux_stats */ |
1159 | |
1160 | /* ---------------------------------------------------------------------------- |
1161 | pr_mace_stats |
1162 | ---------------------------------------------------------------------------- */ |
1163 | static void pr_mace_stats(mace_statistics *pstats) |
1164 | { |
1165 | pr_debug("pr_mace_stats\n" ); |
1166 | |
1167 | pr_debug(" xmtsv=%-7d uflo=%d\n" , |
1168 | pstats->xmtsv, pstats->uflo); |
1169 | pr_debug(" lcol=%-7d more=%d\n" , |
1170 | pstats->lcol, pstats->more); |
1171 | pr_debug(" one=%-7d defer=%d\n" , |
1172 | pstats->one, pstats->defer); |
1173 | pr_debug(" lcar=%-7d rtry=%d\n" , |
1174 | pstats->lcar, pstats->rtry); |
1175 | |
1176 | /* MACE_XMTRC */ |
1177 | pr_debug(" exdef=%-7d xmtrc=%d\n" , |
1178 | pstats->exdef, pstats->xmtrc); |
1179 | |
1180 | /* RFS1--Receive Status (RCVSTS) */ |
1181 | pr_debug(" oflo=%-7d clsn=%d\n" , |
1182 | pstats->oflo, pstats->clsn); |
1183 | pr_debug(" fram=%-7d fcs=%d\n" , |
1184 | pstats->fram, pstats->fcs); |
1185 | |
1186 | /* RFS2--Runt Packet Count (RNTPC) */ |
1187 | /* RFS3--Receive Collision Count (RCVCC) */ |
1188 | pr_debug(" rfs_rntpc=%-7d rfs_rcvcc=%d\n" , |
1189 | pstats->rfs_rntpc, pstats->rfs_rcvcc); |
1190 | |
1191 | /* MACE_IR */ |
1192 | pr_debug(" jab=%-7d babl=%d\n" , |
1193 | pstats->jab, pstats->babl); |
1194 | pr_debug(" cerr=%-7d rcvcco=%d\n" , |
1195 | pstats->cerr, pstats->rcvcco); |
1196 | pr_debug(" rntpco=%-7d mpco=%d\n" , |
1197 | pstats->rntpco, pstats->mpco); |
1198 | |
1199 | /* MACE_MPC */ |
1200 | pr_debug(" mpc=%d\n" , pstats->mpc); |
1201 | |
1202 | /* MACE_RNTPC */ |
1203 | pr_debug(" rntpc=%d\n" , pstats->rntpc); |
1204 | |
1205 | /* MACE_RCVCC */ |
1206 | pr_debug(" rcvcc=%d\n" , pstats->rcvcc); |
1207 | |
1208 | } /* pr_mace_stats */ |
1209 | |
1210 | /* ---------------------------------------------------------------------------- |
1211 | update_stats |
1212 | Update statistics. We change to register window 1, so this |
1213 | should be run single-threaded if the device is active. This is |
1214 | expected to be a rare operation, and it's simpler for the rest |
1215 | of the driver to assume that window 0 is always valid rather |
1216 | than use a special window-state variable. |
1217 | |
1218 | oflo & uflo should _never_ occur since it would mean the Xilinx |
1219 | was not able to transfer data between the MACE FIFO and the |
1220 | card's SRAM fast enough. If this happens, something is |
1221 | seriously wrong with the hardware. |
1222 | ---------------------------------------------------------------------------- */ |
1223 | static void update_stats(unsigned int ioaddr, struct net_device *dev) |
1224 | { |
1225 | mace_private *lp = netdev_priv(dev); |
1226 | |
1227 | lp->mace_stats.rcvcc += mace_read(lp, ioaddr, MACE_RCVCC); |
1228 | lp->mace_stats.rntpc += mace_read(lp, ioaddr, MACE_RNTPC); |
1229 | lp->mace_stats.mpc += mace_read(lp, ioaddr, MACE_MPC); |
1230 | /* At this point, mace_stats is fully updated for this call. |
1231 | We may now update the netdev stats. */ |
1232 | |
1233 | /* The MACE has no equivalent for netdev stats field which are commented |
1234 | out. */ |
1235 | |
1236 | /* dev->stats.multicast; */ |
1237 | dev->stats.collisions = |
1238 | lp->mace_stats.rcvcco * 256 + lp->mace_stats.rcvcc; |
1239 | /* Collision: The MACE may retry sending a packet 15 times |
1240 | before giving up. The retry count is in XMTRC. |
1241 | Does each retry constitute a collision? |
1242 | If so, why doesn't the RCVCC record these collisions? */ |
1243 | |
1244 | /* detailed rx_errors: */ |
1245 | dev->stats.rx_length_errors = |
1246 | lp->mace_stats.rntpco * 256 + lp->mace_stats.rntpc; |
1247 | /* dev->stats.rx_over_errors */ |
1248 | dev->stats.rx_crc_errors = lp->mace_stats.fcs; |
1249 | dev->stats.rx_frame_errors = lp->mace_stats.fram; |
1250 | dev->stats.rx_fifo_errors = lp->mace_stats.oflo; |
1251 | dev->stats.rx_missed_errors = |
1252 | lp->mace_stats.mpco * 256 + lp->mace_stats.mpc; |
1253 | |
1254 | /* detailed tx_errors */ |
1255 | dev->stats.tx_aborted_errors = lp->mace_stats.rtry; |
1256 | dev->stats.tx_carrier_errors = lp->mace_stats.lcar; |
1257 | /* LCAR usually results from bad cabling. */ |
1258 | dev->stats.tx_fifo_errors = lp->mace_stats.uflo; |
1259 | dev->stats.tx_heartbeat_errors = lp->mace_stats.cerr; |
1260 | /* dev->stats.tx_window_errors; */ |
1261 | } /* update_stats */ |
1262 | |
1263 | /* ---------------------------------------------------------------------------- |
1264 | mace_get_stats |
1265 | Gathers ethernet statistics from the MACE chip. |
1266 | ---------------------------------------------------------------------------- */ |
1267 | static struct net_device_stats *mace_get_stats(struct net_device *dev) |
1268 | { |
1269 | mace_private *lp = netdev_priv(dev); |
1270 | |
1271 | update_stats(ioaddr: dev->base_addr, dev); |
1272 | |
1273 | pr_debug("%s: updating the statistics.\n" , dev->name); |
1274 | pr_linux_stats(pstats: &dev->stats); |
1275 | pr_mace_stats(pstats: &lp->mace_stats); |
1276 | |
1277 | return &dev->stats; |
1278 | } /* net_device_stats */ |
1279 | |
1280 | /* ---------------------------------------------------------------------------- |
1281 | updateCRC |
1282 | Modified from Am79C90 data sheet. |
1283 | ---------------------------------------------------------------------------- */ |
1284 | |
1285 | #ifdef BROKEN_MULTICAST |
1286 | |
1287 | static void updateCRC(int *CRC, int bit) |
1288 | { |
1289 | static const int poly[]={ |
1290 | 1,1,1,0, 1,1,0,1, |
1291 | 1,0,1,1, 1,0,0,0, |
1292 | 1,0,0,0, 0,0,1,1, |
1293 | 0,0,1,0, 0,0,0,0 |
1294 | }; /* CRC polynomial. poly[n] = coefficient of the x**n term of the |
1295 | CRC generator polynomial. */ |
1296 | |
1297 | int j; |
1298 | |
1299 | /* shift CRC and control bit (CRC[32]) */ |
1300 | for (j = 32; j > 0; j--) |
1301 | CRC[j] = CRC[j-1]; |
1302 | CRC[0] = 0; |
1303 | |
1304 | /* If bit XOR(control bit) = 1, set CRC = CRC XOR polynomial. */ |
1305 | if (bit ^ CRC[32]) |
1306 | for (j = 0; j < 32; j++) |
1307 | CRC[j] ^= poly[j]; |
1308 | } /* updateCRC */ |
1309 | |
1310 | /* ---------------------------------------------------------------------------- |
1311 | BuildLAF |
1312 | Build logical address filter. |
1313 | Modified from Am79C90 data sheet. |
1314 | |
1315 | Input |
1316 | ladrf: logical address filter (contents initialized to 0) |
1317 | adr: ethernet address |
1318 | ---------------------------------------------------------------------------- */ |
1319 | static void BuildLAF(int *ladrf, int *adr) |
1320 | { |
1321 | int CRC[33]={1}; /* CRC register, 1 word/bit + extra control bit */ |
1322 | |
1323 | int i, byte; /* temporary array indices */ |
1324 | int hashcode; /* the output object */ |
1325 | |
1326 | CRC[32]=0; |
1327 | |
1328 | for (byte = 0; byte < 6; byte++) |
1329 | for (i = 0; i < 8; i++) |
1330 | updateCRC(CRC, (adr[byte] >> i) & 1); |
1331 | |
1332 | hashcode = 0; |
1333 | for (i = 0; i < 6; i++) |
1334 | hashcode = (hashcode << 1) + CRC[i]; |
1335 | |
1336 | byte = hashcode >> 3; |
1337 | ladrf[byte] |= (1 << (hashcode & 7)); |
1338 | |
1339 | #ifdef PCMCIA_DEBUG |
1340 | if (0) |
1341 | printk(KERN_DEBUG " adr =%pM\n" , adr); |
1342 | printk(KERN_DEBUG " hashcode = %d(decimal), ladrf[0:63] =" , hashcode); |
1343 | for (i = 0; i < 8; i++) |
1344 | pr_cont(" %02X" , ladrf[i]); |
1345 | pr_cont("\n" ); |
1346 | #endif |
1347 | } /* BuildLAF */ |
1348 | |
1349 | /* ---------------------------------------------------------------------------- |
1350 | restore_multicast_list |
1351 | Restores the multicast filter for MACE chip to the last |
1352 | set_multicast_list() call. |
1353 | |
1354 | Input |
1355 | multicast_num_addrs |
1356 | multicast_ladrf[] |
1357 | ---------------------------------------------------------------------------- */ |
1358 | static void restore_multicast_list(struct net_device *dev) |
1359 | { |
1360 | mace_private *lp = netdev_priv(dev); |
1361 | int num_addrs = lp->multicast_num_addrs; |
1362 | int *ladrf = lp->multicast_ladrf; |
1363 | unsigned int ioaddr = dev->base_addr; |
1364 | int i; |
1365 | |
1366 | pr_debug("%s: restoring Rx mode to %d addresses.\n" , |
1367 | dev->name, num_addrs); |
1368 | |
1369 | if (num_addrs > 0) { |
1370 | |
1371 | pr_debug("Attempt to restore multicast list detected.\n" ); |
1372 | |
1373 | mace_write(lp, ioaddr, MACE_IAC, MACE_IAC_ADDRCHG | MACE_IAC_LOGADDR); |
1374 | /* Poll ADDRCHG bit */ |
1375 | while (mace_read(lp, ioaddr, MACE_IAC) & MACE_IAC_ADDRCHG) |
1376 | ; |
1377 | /* Set LADRF register */ |
1378 | for (i = 0; i < MACE_LADRF_LEN; i++) |
1379 | mace_write(lp, ioaddr, MACE_LADRF, ladrf[i]); |
1380 | |
1381 | mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_RCVFCSE | MACE_UTR_LOOP_EXTERNAL); |
1382 | mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV); |
1383 | |
1384 | } else if (num_addrs < 0) { |
1385 | |
1386 | /* Promiscuous mode: receive all packets */ |
1387 | mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL); |
1388 | mace_write(lp, ioaddr, MACE_MACCC, |
1389 | MACE_MACCC_PROM | MACE_MACCC_ENXMT | MACE_MACCC_ENRCV |
1390 | ); |
1391 | |
1392 | } else { |
1393 | |
1394 | /* Normal mode */ |
1395 | mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL); |
1396 | mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV); |
1397 | |
1398 | } |
1399 | } /* restore_multicast_list */ |
1400 | |
1401 | /* ---------------------------------------------------------------------------- |
1402 | set_multicast_list |
1403 | Set or clear the multicast filter for this adaptor. |
1404 | |
1405 | Input |
1406 | num_addrs == -1 Promiscuous mode, receive all packets |
1407 | num_addrs == 0 Normal mode, clear multicast list |
1408 | num_addrs > 0 Multicast mode, receive normal and MC packets, and do |
1409 | best-effort filtering. |
1410 | Output |
1411 | multicast_num_addrs |
1412 | multicast_ladrf[] |
1413 | ---------------------------------------------------------------------------- */ |
1414 | |
1415 | static void set_multicast_list(struct net_device *dev) |
1416 | { |
1417 | mace_private *lp = netdev_priv(dev); |
1418 | int adr[ETH_ALEN] = {0}; /* Ethernet address */ |
1419 | struct netdev_hw_addr *ha; |
1420 | |
1421 | #ifdef PCMCIA_DEBUG |
1422 | { |
1423 | static int old; |
1424 | if (netdev_mc_count(dev) != old) { |
1425 | old = netdev_mc_count(dev); |
1426 | pr_debug("%s: setting Rx mode to %d addresses.\n" , |
1427 | dev->name, old); |
1428 | } |
1429 | } |
1430 | #endif |
1431 | |
1432 | /* Set multicast_num_addrs. */ |
1433 | lp->multicast_num_addrs = netdev_mc_count(dev); |
1434 | |
1435 | /* Set multicast_ladrf. */ |
1436 | if (num_addrs > 0) { |
1437 | /* Calculate multicast logical address filter */ |
1438 | memset(lp->multicast_ladrf, 0, MACE_LADRF_LEN); |
1439 | netdev_for_each_mc_addr(ha, dev) { |
1440 | memcpy(adr, ha->addr, ETH_ALEN); |
1441 | BuildLAF(lp->multicast_ladrf, adr); |
1442 | } |
1443 | } |
1444 | |
1445 | restore_multicast_list(dev); |
1446 | |
1447 | } /* set_multicast_list */ |
1448 | |
1449 | #endif /* BROKEN_MULTICAST */ |
1450 | |
1451 | static void restore_multicast_list(struct net_device *dev) |
1452 | { |
1453 | unsigned int ioaddr = dev->base_addr; |
1454 | mace_private *lp = netdev_priv(dev); |
1455 | |
1456 | pr_debug("%s: restoring Rx mode to %d addresses.\n" , dev->name, |
1457 | lp->multicast_num_addrs); |
1458 | |
1459 | if (dev->flags & IFF_PROMISC) { |
1460 | /* Promiscuous mode: receive all packets */ |
1461 | mace_write(lp,ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL); |
1462 | mace_write(lp, ioaddr, MACE_MACCC, |
1463 | MACE_MACCC_PROM | MACE_MACCC_ENXMT | MACE_MACCC_ENRCV |
1464 | ); |
1465 | } else { |
1466 | /* Normal mode */ |
1467 | mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL); |
1468 | mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV); |
1469 | } |
1470 | } /* restore_multicast_list */ |
1471 | |
1472 | static void set_multicast_list(struct net_device *dev) |
1473 | { |
1474 | mace_private *lp = netdev_priv(dev); |
1475 | |
1476 | #ifdef PCMCIA_DEBUG |
1477 | { |
1478 | static int old; |
1479 | if (netdev_mc_count(dev) != old) { |
1480 | old = netdev_mc_count(dev); |
1481 | pr_debug("%s: setting Rx mode to %d addresses.\n" , |
1482 | dev->name, old); |
1483 | } |
1484 | } |
1485 | #endif |
1486 | |
1487 | lp->multicast_num_addrs = netdev_mc_count(dev); |
1488 | restore_multicast_list(dev); |
1489 | |
1490 | } /* set_multicast_list */ |
1491 | |
1492 | static const struct pcmcia_device_id nmclan_ids[] = { |
1493 | PCMCIA_DEVICE_PROD_ID12("New Media Corporation" , "Ethernet" , 0x085a850b, 0x00b2e941), |
1494 | PCMCIA_DEVICE_PROD_ID12("Portable Add-ons" , "Ethernet+" , 0xebf1d60, 0xad673aaf), |
1495 | PCMCIA_DEVICE_NULL, |
1496 | }; |
1497 | MODULE_DEVICE_TABLE(pcmcia, nmclan_ids); |
1498 | |
1499 | static struct pcmcia_driver nmclan_cs_driver = { |
1500 | .owner = THIS_MODULE, |
1501 | .name = "nmclan_cs" , |
1502 | .probe = nmclan_probe, |
1503 | .remove = nmclan_detach, |
1504 | .id_table = nmclan_ids, |
1505 | .suspend = nmclan_suspend, |
1506 | .resume = nmclan_resume, |
1507 | }; |
1508 | module_pcmcia_driver(nmclan_cs_driver); |
1509 | |