1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* Atlantic Network Driver |
3 | * |
4 | * Copyright (C) 2014-2019 aQuantia Corporation |
5 | * Copyright (C) 2019-2020 Marvell International Ltd. |
6 | */ |
7 | |
8 | /* File hw_atl_llh.c: Definitions of bitfield and register access functions for |
9 | * Atlantic registers. |
10 | */ |
11 | |
12 | #include "hw_atl_llh.h" |
13 | #include "hw_atl_llh_internal.h" |
14 | #include "../aq_hw_utils.h" |
15 | |
16 | void hw_atl_ts_reset_set(struct aq_hw_s *aq_hw, u32 val) |
17 | { |
18 | aq_hw_write_reg_bit(aq_hw, HW_ATL_TS_RESET_ADR, |
19 | HW_ATL_TS_RESET_MSK, |
20 | HW_ATL_TS_RESET_SHIFT, |
21 | val); |
22 | } |
23 | |
24 | void hw_atl_ts_power_down_set(struct aq_hw_s *aq_hw, u32 val) |
25 | { |
26 | aq_hw_write_reg_bit(aq_hw, HW_ATL_TS_POWER_DOWN_ADR, |
27 | HW_ATL_TS_POWER_DOWN_MSK, |
28 | HW_ATL_TS_POWER_DOWN_SHIFT, |
29 | val); |
30 | } |
31 | |
32 | u32 hw_atl_ts_power_down_get(struct aq_hw_s *aq_hw) |
33 | { |
34 | return aq_hw_read_reg_bit(aq_hw, HW_ATL_TS_POWER_DOWN_ADR, |
35 | HW_ATL_TS_POWER_DOWN_MSK, |
36 | HW_ATL_TS_POWER_DOWN_SHIFT); |
37 | } |
38 | |
39 | u32 hw_atl_ts_ready_get(struct aq_hw_s *aq_hw) |
40 | { |
41 | return aq_hw_read_reg_bit(aq_hw, HW_ATL_TS_READY_ADR, |
42 | HW_ATL_TS_READY_MSK, |
43 | HW_ATL_TS_READY_SHIFT); |
44 | } |
45 | |
46 | u32 hw_atl_ts_ready_latch_high_get(struct aq_hw_s *aq_hw) |
47 | { |
48 | return aq_hw_read_reg_bit(aq_hw, HW_ATL_TS_READY_LATCH_HIGH_ADR, |
49 | HW_ATL_TS_READY_LATCH_HIGH_MSK, |
50 | HW_ATL_TS_READY_LATCH_HIGH_SHIFT); |
51 | } |
52 | |
53 | u32 hw_atl_ts_data_get(struct aq_hw_s *aq_hw) |
54 | { |
55 | return aq_hw_read_reg_bit(aq_hw, HW_ATL_TS_DATA_OUT_ADR, |
56 | HW_ATL_TS_DATA_OUT_MSK, |
57 | HW_ATL_TS_DATA_OUT_SHIFT); |
58 | } |
59 | |
60 | /* global */ |
61 | void hw_atl_reg_glb_cpu_sem_set(struct aq_hw_s *aq_hw, u32 glb_cpu_sem, |
62 | u32 semaphore) |
63 | { |
64 | aq_hw_write_reg(hw: aq_hw, HW_ATL_GLB_CPU_SEM_ADR(semaphore), value: glb_cpu_sem); |
65 | } |
66 | |
67 | u32 hw_atl_reg_glb_cpu_sem_get(struct aq_hw_s *aq_hw, u32 semaphore) |
68 | { |
69 | return aq_hw_read_reg(hw: aq_hw, HW_ATL_GLB_CPU_SEM_ADR(semaphore)); |
70 | } |
71 | |
72 | void hw_atl_glb_glb_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 glb_reg_res_dis) |
73 | { |
74 | aq_hw_write_reg_bit(aq_hw, HW_ATL_GLB_REG_RES_DIS_ADR, |
75 | HW_ATL_GLB_REG_RES_DIS_MSK, |
76 | HW_ATL_GLB_REG_RES_DIS_SHIFT, |
77 | val: glb_reg_res_dis); |
78 | } |
79 | |
80 | void hw_atl_glb_soft_res_set(struct aq_hw_s *aq_hw, u32 soft_res) |
81 | { |
82 | aq_hw_write_reg_bit(aq_hw, HW_ATL_GLB_SOFT_RES_ADR, |
83 | HW_ATL_GLB_SOFT_RES_MSK, |
84 | HW_ATL_GLB_SOFT_RES_SHIFT, val: soft_res); |
85 | } |
86 | |
87 | u32 hw_atl_glb_soft_res_get(struct aq_hw_s *aq_hw) |
88 | { |
89 | return aq_hw_read_reg_bit(aq_hw, HW_ATL_GLB_SOFT_RES_ADR, |
90 | HW_ATL_GLB_SOFT_RES_MSK, |
91 | HW_ATL_GLB_SOFT_RES_SHIFT); |
92 | } |
93 | |
94 | u32 hw_atl_reg_glb_mif_id_get(struct aq_hw_s *aq_hw) |
95 | { |
96 | return aq_hw_read_reg(hw: aq_hw, HW_ATL_GLB_MIF_ID_ADR); |
97 | } |
98 | |
99 | /* stats */ |
100 | u32 hw_atl_rpb_rx_dma_drop_pkt_cnt_get(struct aq_hw_s *aq_hw) |
101 | { |
102 | return aq_hw_read_reg(hw: aq_hw, HW_ATL_RPB_RX_DMA_DROP_PKT_CNT_ADR); |
103 | } |
104 | |
105 | u64 hw_atl_stats_rx_dma_good_octet_counter_get(struct aq_hw_s *aq_hw) |
106 | { |
107 | return aq_hw_read_reg64(hw: aq_hw, HW_ATL_STATS_RX_DMA_GOOD_OCTET_COUNTERLSW); |
108 | } |
109 | |
110 | u64 hw_atl_stats_rx_dma_good_pkt_counter_get(struct aq_hw_s *aq_hw) |
111 | { |
112 | return aq_hw_read_reg64(hw: aq_hw, HW_ATL_STATS_RX_DMA_GOOD_PKT_COUNTERLSW); |
113 | } |
114 | |
115 | u64 hw_atl_stats_tx_dma_good_octet_counter_get(struct aq_hw_s *aq_hw) |
116 | { |
117 | return aq_hw_read_reg64(hw: aq_hw, HW_ATL_STATS_TX_DMA_GOOD_OCTET_COUNTERLSW); |
118 | } |
119 | |
120 | u64 hw_atl_stats_tx_dma_good_pkt_counter_get(struct aq_hw_s *aq_hw) |
121 | { |
122 | return aq_hw_read_reg64(hw: aq_hw, HW_ATL_STATS_TX_DMA_GOOD_PKT_COUNTERLSW); |
123 | } |
124 | |
125 | /* interrupt */ |
126 | void hw_atl_itr_irq_auto_masklsw_set(struct aq_hw_s *aq_hw, |
127 | u32 irq_auto_masklsw) |
128 | { |
129 | aq_hw_write_reg(hw: aq_hw, HW_ATL_ITR_IAMRLSW_ADR, value: irq_auto_masklsw); |
130 | } |
131 | |
132 | void hw_atl_itr_irq_map_en_rx_set(struct aq_hw_s *aq_hw, u32 irq_map_en_rx, |
133 | u32 rx) |
134 | { |
135 | /* register address for bitfield imr_rx{r}_en */ |
136 | static u32 itr_imr_rxren_adr[32] = { |
137 | 0x00002100U, 0x00002100U, 0x00002104U, 0x00002104U, |
138 | 0x00002108U, 0x00002108U, 0x0000210CU, 0x0000210CU, |
139 | 0x00002110U, 0x00002110U, 0x00002114U, 0x00002114U, |
140 | 0x00002118U, 0x00002118U, 0x0000211CU, 0x0000211CU, |
141 | 0x00002120U, 0x00002120U, 0x00002124U, 0x00002124U, |
142 | 0x00002128U, 0x00002128U, 0x0000212CU, 0x0000212CU, |
143 | 0x00002130U, 0x00002130U, 0x00002134U, 0x00002134U, |
144 | 0x00002138U, 0x00002138U, 0x0000213CU, 0x0000213CU |
145 | }; |
146 | |
147 | /* bitmask for bitfield imr_rx{r}_en */ |
148 | static u32 itr_imr_rxren_msk[32] = { |
149 | 0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U, |
150 | 0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U, |
151 | 0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U, |
152 | 0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U, |
153 | 0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U, |
154 | 0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U, |
155 | 0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U, |
156 | 0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U |
157 | }; |
158 | |
159 | /* lower bit position of bitfield imr_rx{r}_en */ |
160 | static u32 itr_imr_rxren_shift[32] = { |
161 | 15U, 7U, 15U, 7U, 15U, 7U, 15U, 7U, |
162 | 15U, 7U, 15U, 7U, 15U, 7U, 15U, 7U, |
163 | 15U, 7U, 15U, 7U, 15U, 7U, 15U, 7U, |
164 | 15U, 7U, 15U, 7U, 15U, 7U, 15U, 7U |
165 | }; |
166 | |
167 | aq_hw_write_reg_bit(aq_hw, addr: itr_imr_rxren_adr[rx], |
168 | msk: itr_imr_rxren_msk[rx], |
169 | shift: itr_imr_rxren_shift[rx], |
170 | val: irq_map_en_rx); |
171 | } |
172 | |
173 | void hw_atl_itr_irq_map_en_tx_set(struct aq_hw_s *aq_hw, u32 irq_map_en_tx, |
174 | u32 tx) |
175 | { |
176 | /* register address for bitfield imr_tx{t}_en */ |
177 | static u32 itr_imr_txten_adr[32] = { |
178 | 0x00002100U, 0x00002100U, 0x00002104U, 0x00002104U, |
179 | 0x00002108U, 0x00002108U, 0x0000210CU, 0x0000210CU, |
180 | 0x00002110U, 0x00002110U, 0x00002114U, 0x00002114U, |
181 | 0x00002118U, 0x00002118U, 0x0000211CU, 0x0000211CU, |
182 | 0x00002120U, 0x00002120U, 0x00002124U, 0x00002124U, |
183 | 0x00002128U, 0x00002128U, 0x0000212CU, 0x0000212CU, |
184 | 0x00002130U, 0x00002130U, 0x00002134U, 0x00002134U, |
185 | 0x00002138U, 0x00002138U, 0x0000213CU, 0x0000213CU |
186 | }; |
187 | |
188 | /* bitmask for bitfield imr_tx{t}_en */ |
189 | static u32 itr_imr_txten_msk[32] = { |
190 | 0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U, |
191 | 0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U, |
192 | 0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U, |
193 | 0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U, |
194 | 0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U, |
195 | 0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U, |
196 | 0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U, |
197 | 0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U |
198 | }; |
199 | |
200 | /* lower bit position of bitfield imr_tx{t}_en */ |
201 | static u32 itr_imr_txten_shift[32] = { |
202 | 31U, 23U, 31U, 23U, 31U, 23U, 31U, 23U, |
203 | 31U, 23U, 31U, 23U, 31U, 23U, 31U, 23U, |
204 | 31U, 23U, 31U, 23U, 31U, 23U, 31U, 23U, |
205 | 31U, 23U, 31U, 23U, 31U, 23U, 31U, 23U |
206 | }; |
207 | |
208 | aq_hw_write_reg_bit(aq_hw, addr: itr_imr_txten_adr[tx], |
209 | msk: itr_imr_txten_msk[tx], |
210 | shift: itr_imr_txten_shift[tx], |
211 | val: irq_map_en_tx); |
212 | } |
213 | |
214 | void hw_atl_itr_irq_map_rx_set(struct aq_hw_s *aq_hw, u32 irq_map_rx, u32 rx) |
215 | { |
216 | /* register address for bitfield imr_rx{r}[4:0] */ |
217 | static u32 itr_imr_rxr_adr[32] = { |
218 | 0x00002100U, 0x00002100U, 0x00002104U, 0x00002104U, |
219 | 0x00002108U, 0x00002108U, 0x0000210CU, 0x0000210CU, |
220 | 0x00002110U, 0x00002110U, 0x00002114U, 0x00002114U, |
221 | 0x00002118U, 0x00002118U, 0x0000211CU, 0x0000211CU, |
222 | 0x00002120U, 0x00002120U, 0x00002124U, 0x00002124U, |
223 | 0x00002128U, 0x00002128U, 0x0000212CU, 0x0000212CU, |
224 | 0x00002130U, 0x00002130U, 0x00002134U, 0x00002134U, |
225 | 0x00002138U, 0x00002138U, 0x0000213CU, 0x0000213CU |
226 | }; |
227 | |
228 | /* bitmask for bitfield imr_rx{r}[4:0] */ |
229 | static u32 itr_imr_rxr_msk[32] = { |
230 | 0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU, |
231 | 0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU, |
232 | 0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU, |
233 | 0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU, |
234 | 0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU, |
235 | 0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU, |
236 | 0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU, |
237 | 0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU |
238 | }; |
239 | |
240 | /* lower bit position of bitfield imr_rx{r}[4:0] */ |
241 | static u32 itr_imr_rxr_shift[32] = { |
242 | 8U, 0U, 8U, 0U, 8U, 0U, 8U, 0U, |
243 | 8U, 0U, 8U, 0U, 8U, 0U, 8U, 0U, |
244 | 8U, 0U, 8U, 0U, 8U, 0U, 8U, 0U, |
245 | 8U, 0U, 8U, 0U, 8U, 0U, 8U, 0U |
246 | }; |
247 | |
248 | aq_hw_write_reg_bit(aq_hw, addr: itr_imr_rxr_adr[rx], |
249 | msk: itr_imr_rxr_msk[rx], |
250 | shift: itr_imr_rxr_shift[rx], |
251 | val: irq_map_rx); |
252 | } |
253 | |
254 | void hw_atl_itr_irq_map_tx_set(struct aq_hw_s *aq_hw, u32 irq_map_tx, u32 tx) |
255 | { |
256 | /* register address for bitfield imr_tx{t}[4:0] */ |
257 | static u32 itr_imr_txt_adr[32] = { |
258 | 0x00002100U, 0x00002100U, 0x00002104U, 0x00002104U, |
259 | 0x00002108U, 0x00002108U, 0x0000210CU, 0x0000210CU, |
260 | 0x00002110U, 0x00002110U, 0x00002114U, 0x00002114U, |
261 | 0x00002118U, 0x00002118U, 0x0000211CU, 0x0000211CU, |
262 | 0x00002120U, 0x00002120U, 0x00002124U, 0x00002124U, |
263 | 0x00002128U, 0x00002128U, 0x0000212CU, 0x0000212CU, |
264 | 0x00002130U, 0x00002130U, 0x00002134U, 0x00002134U, |
265 | 0x00002138U, 0x00002138U, 0x0000213CU, 0x0000213CU |
266 | }; |
267 | |
268 | /* bitmask for bitfield imr_tx{t}[4:0] */ |
269 | static u32 itr_imr_txt_msk[32] = { |
270 | 0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U, |
271 | 0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U, |
272 | 0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U, |
273 | 0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U, |
274 | 0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U, |
275 | 0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U, |
276 | 0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U, |
277 | 0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U |
278 | }; |
279 | |
280 | /* lower bit position of bitfield imr_tx{t}[4:0] */ |
281 | static u32 itr_imr_txt_shift[32] = { |
282 | 24U, 16U, 24U, 16U, 24U, 16U, 24U, 16U, |
283 | 24U, 16U, 24U, 16U, 24U, 16U, 24U, 16U, |
284 | 24U, 16U, 24U, 16U, 24U, 16U, 24U, 16U, |
285 | 24U, 16U, 24U, 16U, 24U, 16U, 24U, 16U |
286 | }; |
287 | |
288 | aq_hw_write_reg_bit(aq_hw, addr: itr_imr_txt_adr[tx], |
289 | msk: itr_imr_txt_msk[tx], |
290 | shift: itr_imr_txt_shift[tx], |
291 | val: irq_map_tx); |
292 | } |
293 | |
294 | void hw_atl_itr_irq_msk_clearlsw_set(struct aq_hw_s *aq_hw, |
295 | u32 irq_msk_clearlsw) |
296 | { |
297 | aq_hw_write_reg(hw: aq_hw, HW_ATL_ITR_IMCRLSW_ADR, value: irq_msk_clearlsw); |
298 | } |
299 | |
300 | void hw_atl_itr_irq_msk_setlsw_set(struct aq_hw_s *aq_hw, u32 irq_msk_setlsw) |
301 | { |
302 | aq_hw_write_reg(hw: aq_hw, HW_ATL_ITR_IMSRLSW_ADR, value: irq_msk_setlsw); |
303 | } |
304 | |
305 | void hw_atl_itr_irq_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 irq_reg_res_dis) |
306 | { |
307 | aq_hw_write_reg_bit(aq_hw, HW_ATL_ITR_REG_RES_DSBL_ADR, |
308 | HW_ATL_ITR_REG_RES_DSBL_MSK, |
309 | HW_ATL_ITR_REG_RES_DSBL_SHIFT, val: irq_reg_res_dis); |
310 | } |
311 | |
312 | void hw_atl_itr_irq_status_clearlsw_set(struct aq_hw_s *aq_hw, |
313 | u32 irq_status_clearlsw) |
314 | { |
315 | aq_hw_write_reg(hw: aq_hw, HW_ATL_ITR_ISCRLSW_ADR, value: irq_status_clearlsw); |
316 | } |
317 | |
318 | u32 hw_atl_itr_irq_statuslsw_get(struct aq_hw_s *aq_hw) |
319 | { |
320 | return aq_hw_read_reg(hw: aq_hw, HW_ATL_ITR_ISRLSW_ADR); |
321 | } |
322 | |
323 | u32 hw_atl_itr_res_irq_get(struct aq_hw_s *aq_hw) |
324 | { |
325 | return aq_hw_read_reg_bit(aq_hw, HW_ATL_ITR_RES_ADR, HW_ATL_ITR_RES_MSK, |
326 | HW_ATL_ITR_RES_SHIFT); |
327 | } |
328 | |
329 | void hw_atl_itr_res_irq_set(struct aq_hw_s *aq_hw, u32 res_irq) |
330 | { |
331 | aq_hw_write_reg_bit(aq_hw, HW_ATL_ITR_RES_ADR, HW_ATL_ITR_RES_MSK, |
332 | HW_ATL_ITR_RES_SHIFT, val: res_irq); |
333 | } |
334 | |
335 | /* set RSC interrupt */ |
336 | void hw_atl_itr_rsc_en_set(struct aq_hw_s *aq_hw, u32 enable) |
337 | { |
338 | aq_hw_write_reg(hw: aq_hw, HW_ATL_ITR_RSC_EN_ADR, value: enable); |
339 | } |
340 | |
341 | /* set RSC delay */ |
342 | void hw_atl_itr_rsc_delay_set(struct aq_hw_s *aq_hw, u32 delay) |
343 | { |
344 | aq_hw_write_reg_bit(aq_hw, HW_ATL_ITR_RSC_DELAY_ADR, |
345 | HW_ATL_ITR_RSC_DELAY_MSK, |
346 | HW_ATL_ITR_RSC_DELAY_SHIFT, |
347 | val: delay); |
348 | } |
349 | |
350 | /* rdm */ |
351 | void hw_atl_rdm_cpu_id_set(struct aq_hw_s *aq_hw, u32 cpuid, u32 dca) |
352 | { |
353 | aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCADCPUID_ADR(dca), |
354 | HW_ATL_RDM_DCADCPUID_MSK, |
355 | HW_ATL_RDM_DCADCPUID_SHIFT, val: cpuid); |
356 | } |
357 | |
358 | void hw_atl_rdm_rx_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_dca_en) |
359 | { |
360 | aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCA_EN_ADR, HW_ATL_RDM_DCA_EN_MSK, |
361 | HW_ATL_RDM_DCA_EN_SHIFT, val: rx_dca_en); |
362 | } |
363 | |
364 | void hw_atl_rdm_rx_dca_mode_set(struct aq_hw_s *aq_hw, u32 rx_dca_mode) |
365 | { |
366 | aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCA_MODE_ADR, |
367 | HW_ATL_RDM_DCA_MODE_MSK, |
368 | HW_ATL_RDM_DCA_MODE_SHIFT, val: rx_dca_mode); |
369 | } |
370 | |
371 | void hw_atl_rdm_rx_desc_data_buff_size_set(struct aq_hw_s *aq_hw, |
372 | u32 rx_desc_data_buff_size, |
373 | u32 descriptor) |
374 | { |
375 | aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDDATA_SIZE_ADR(descriptor), |
376 | HW_ATL_RDM_DESCDDATA_SIZE_MSK, |
377 | HW_ATL_RDM_DESCDDATA_SIZE_SHIFT, |
378 | val: rx_desc_data_buff_size); |
379 | } |
380 | |
381 | void hw_atl_rdm_rx_desc_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_desc_dca_en, |
382 | u32 dca) |
383 | { |
384 | aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCADDESC_EN_ADR(dca), |
385 | HW_ATL_RDM_DCADDESC_EN_MSK, |
386 | HW_ATL_RDM_DCADDESC_EN_SHIFT, |
387 | val: rx_desc_dca_en); |
388 | } |
389 | |
390 | void hw_atl_rdm_rx_desc_en_set(struct aq_hw_s *aq_hw, u32 rx_desc_en, |
391 | u32 descriptor) |
392 | { |
393 | aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDEN_ADR(descriptor), |
394 | HW_ATL_RDM_DESCDEN_MSK, |
395 | HW_ATL_RDM_DESCDEN_SHIFT, |
396 | val: rx_desc_en); |
397 | } |
398 | |
399 | void hw_atl_rdm_rx_desc_head_buff_size_set(struct aq_hw_s *aq_hw, |
400 | u32 rx_desc_head_buff_size, |
401 | u32 descriptor) |
402 | { |
403 | aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDHDR_SIZE_ADR(descriptor), |
404 | HW_ATL_RDM_DESCDHDR_SIZE_MSK, |
405 | HW_ATL_RDM_DESCDHDR_SIZE_SHIFT, |
406 | val: rx_desc_head_buff_size); |
407 | } |
408 | |
409 | void hw_atl_rdm_rx_desc_head_splitting_set(struct aq_hw_s *aq_hw, |
410 | u32 rx_desc_head_splitting, |
411 | u32 descriptor) |
412 | { |
413 | aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDHDR_SPLIT_ADR(descriptor), |
414 | HW_ATL_RDM_DESCDHDR_SPLIT_MSK, |
415 | HW_ATL_RDM_DESCDHDR_SPLIT_SHIFT, |
416 | val: rx_desc_head_splitting); |
417 | } |
418 | |
419 | u32 hw_atl_rdm_rx_desc_head_ptr_get(struct aq_hw_s *aq_hw, u32 descriptor) |
420 | { |
421 | return aq_hw_read_reg_bit(aq_hw, HW_ATL_RDM_DESCDHD_ADR(descriptor), |
422 | HW_ATL_RDM_DESCDHD_MSK, |
423 | HW_ATL_RDM_DESCDHD_SHIFT); |
424 | } |
425 | |
426 | void hw_atl_rdm_rx_desc_len_set(struct aq_hw_s *aq_hw, u32 rx_desc_len, |
427 | u32 descriptor) |
428 | { |
429 | aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDLEN_ADR(descriptor), |
430 | HW_ATL_RDM_DESCDLEN_MSK, HW_ATL_RDM_DESCDLEN_SHIFT, |
431 | val: rx_desc_len); |
432 | } |
433 | |
434 | void hw_atl_rdm_rx_desc_res_set(struct aq_hw_s *aq_hw, u32 rx_desc_res, |
435 | u32 descriptor) |
436 | { |
437 | aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDRESET_ADR(descriptor), |
438 | HW_ATL_RDM_DESCDRESET_MSK, |
439 | HW_ATL_RDM_DESCDRESET_SHIFT, |
440 | val: rx_desc_res); |
441 | } |
442 | |
443 | void hw_atl_rdm_rx_desc_wr_wb_irq_en_set(struct aq_hw_s *aq_hw, |
444 | u32 rx_desc_wr_wb_irq_en) |
445 | { |
446 | aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_INT_DESC_WRB_EN_ADR, |
447 | HW_ATL_RDM_INT_DESC_WRB_EN_MSK, |
448 | HW_ATL_RDM_INT_DESC_WRB_EN_SHIFT, |
449 | val: rx_desc_wr_wb_irq_en); |
450 | } |
451 | |
452 | void hw_atl_rdm_rx_head_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_head_dca_en, |
453 | u32 dca) |
454 | { |
455 | aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCADHDR_EN_ADR(dca), |
456 | HW_ATL_RDM_DCADHDR_EN_MSK, |
457 | HW_ATL_RDM_DCADHDR_EN_SHIFT, |
458 | val: rx_head_dca_en); |
459 | } |
460 | |
461 | void hw_atl_rdm_rx_pld_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_pld_dca_en, |
462 | u32 dca) |
463 | { |
464 | aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCADPAY_EN_ADR(dca), |
465 | HW_ATL_RDM_DCADPAY_EN_MSK, |
466 | HW_ATL_RDM_DCADPAY_EN_SHIFT, |
467 | val: rx_pld_dca_en); |
468 | } |
469 | |
470 | void hw_atl_rdm_rdm_intr_moder_en_set(struct aq_hw_s *aq_hw, |
471 | u32 rdm_intr_moder_en) |
472 | { |
473 | aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_INT_RIM_EN_ADR, |
474 | HW_ATL_RDM_INT_RIM_EN_MSK, |
475 | HW_ATL_RDM_INT_RIM_EN_SHIFT, |
476 | val: rdm_intr_moder_en); |
477 | } |
478 | |
479 | /* reg */ |
480 | void hw_atl_reg_gen_irq_map_set(struct aq_hw_s *aq_hw, u32 gen_intr_map, |
481 | u32 regidx) |
482 | { |
483 | aq_hw_write_reg(hw: aq_hw, HW_ATL_GEN_INTR_MAP_ADR(regidx), value: gen_intr_map); |
484 | } |
485 | |
486 | u32 hw_atl_reg_gen_irq_status_get(struct aq_hw_s *aq_hw) |
487 | { |
488 | return aq_hw_read_reg(hw: aq_hw, HW_ATL_GEN_INTR_STAT_ADR); |
489 | } |
490 | |
491 | void hw_atl_reg_irq_glb_ctl_set(struct aq_hw_s *aq_hw, u32 intr_glb_ctl) |
492 | { |
493 | aq_hw_write_reg(hw: aq_hw, HW_ATL_INTR_GLB_CTL_ADR, value: intr_glb_ctl); |
494 | } |
495 | |
496 | void hw_atl_reg_irq_thr_set(struct aq_hw_s *aq_hw, u32 intr_thr, u32 throttle) |
497 | { |
498 | aq_hw_write_reg(hw: aq_hw, HW_ATL_INTR_THR_ADR(throttle), value: intr_thr); |
499 | } |
500 | |
501 | void hw_atl_reg_rx_dma_desc_base_addresslswset(struct aq_hw_s *aq_hw, |
502 | u32 rx_dma_desc_base_addrlsw, |
503 | u32 descriptor) |
504 | { |
505 | aq_hw_write_reg(hw: aq_hw, HW_ATL_RX_DMA_DESC_BASE_ADDRLSW_ADR(descriptor), |
506 | value: rx_dma_desc_base_addrlsw); |
507 | } |
508 | |
509 | void hw_atl_reg_rx_dma_desc_base_addressmswset(struct aq_hw_s *aq_hw, |
510 | u32 rx_dma_desc_base_addrmsw, |
511 | u32 descriptor) |
512 | { |
513 | aq_hw_write_reg(hw: aq_hw, HW_ATL_RX_DMA_DESC_BASE_ADDRMSW_ADR(descriptor), |
514 | value: rx_dma_desc_base_addrmsw); |
515 | } |
516 | |
517 | u32 hw_atl_reg_rx_dma_desc_status_get(struct aq_hw_s *aq_hw, u32 descriptor) |
518 | { |
519 | return aq_hw_read_reg(hw: aq_hw, HW_ATL_RX_DMA_DESC_STAT_ADR(descriptor)); |
520 | } |
521 | |
522 | void hw_atl_reg_rx_dma_desc_tail_ptr_set(struct aq_hw_s *aq_hw, |
523 | u32 rx_dma_desc_tail_ptr, |
524 | u32 descriptor) |
525 | { |
526 | aq_hw_write_reg(hw: aq_hw, HW_ATL_RX_DMA_DESC_TAIL_PTR_ADR(descriptor), |
527 | value: rx_dma_desc_tail_ptr); |
528 | } |
529 | |
530 | void hw_atl_reg_rx_flr_mcst_flr_msk_set(struct aq_hw_s *aq_hw, |
531 | u32 rx_flr_mcst_flr_msk) |
532 | { |
533 | aq_hw_write_reg(hw: aq_hw, HW_ATL_RX_FLR_MCST_FLR_MSK_ADR, |
534 | value: rx_flr_mcst_flr_msk); |
535 | } |
536 | |
537 | void hw_atl_reg_rx_flr_mcst_flr_set(struct aq_hw_s *aq_hw, u32 rx_flr_mcst_flr, |
538 | u32 filter) |
539 | { |
540 | aq_hw_write_reg(hw: aq_hw, HW_ATL_RX_FLR_MCST_FLR_ADR(filter), |
541 | value: rx_flr_mcst_flr); |
542 | } |
543 | |
544 | void (struct aq_hw_s *aq_hw, |
545 | u32 ) |
546 | { |
547 | aq_hw_write_reg(hw: aq_hw, HW_ATL_RX_FLR_RSS_CONTROL1_ADR, |
548 | value: rx_flr_rss_control1); |
549 | } |
550 | |
551 | void hw_atl_reg_rx_flr_control2_set(struct aq_hw_s *aq_hw, |
552 | u32 rx_filter_control2) |
553 | { |
554 | aq_hw_write_reg(hw: aq_hw, HW_ATL_RX_FLR_CONTROL2_ADR, value: rx_filter_control2); |
555 | } |
556 | |
557 | void hw_atl_reg_rx_intr_moder_ctrl_set(struct aq_hw_s *aq_hw, |
558 | u32 rx_intr_moderation_ctl, |
559 | u32 queue) |
560 | { |
561 | aq_hw_write_reg(hw: aq_hw, HW_ATL_RX_INTR_MODERATION_CTL_ADR(queue), |
562 | value: rx_intr_moderation_ctl); |
563 | } |
564 | |
565 | void hw_atl_reg_tx_dma_debug_ctl_set(struct aq_hw_s *aq_hw, |
566 | u32 tx_dma_debug_ctl) |
567 | { |
568 | aq_hw_write_reg(hw: aq_hw, HW_ATL_TX_DMA_DEBUG_CTL_ADR, value: tx_dma_debug_ctl); |
569 | } |
570 | |
571 | void hw_atl_reg_tx_dma_desc_base_addresslswset(struct aq_hw_s *aq_hw, |
572 | u32 tx_dma_desc_base_addrlsw, |
573 | u32 descriptor) |
574 | { |
575 | aq_hw_write_reg(hw: aq_hw, HW_ATL_TX_DMA_DESC_BASE_ADDRLSW_ADR(descriptor), |
576 | value: tx_dma_desc_base_addrlsw); |
577 | } |
578 | |
579 | void hw_atl_reg_tx_dma_desc_base_addressmswset(struct aq_hw_s *aq_hw, |
580 | u32 tx_dma_desc_base_addrmsw, |
581 | u32 descriptor) |
582 | { |
583 | aq_hw_write_reg(hw: aq_hw, HW_ATL_TX_DMA_DESC_BASE_ADDRMSW_ADR(descriptor), |
584 | value: tx_dma_desc_base_addrmsw); |
585 | } |
586 | |
587 | void hw_atl_reg_tx_dma_desc_tail_ptr_set(struct aq_hw_s *aq_hw, |
588 | u32 tx_dma_desc_tail_ptr, |
589 | u32 descriptor) |
590 | { |
591 | aq_hw_write_reg(hw: aq_hw, HW_ATL_TX_DMA_DESC_TAIL_PTR_ADR(descriptor), |
592 | value: tx_dma_desc_tail_ptr); |
593 | } |
594 | |
595 | void hw_atl_reg_tx_intr_moder_ctrl_set(struct aq_hw_s *aq_hw, |
596 | u32 tx_intr_moderation_ctl, |
597 | u32 queue) |
598 | { |
599 | aq_hw_write_reg(hw: aq_hw, HW_ATL_TX_INTR_MODERATION_CTL_ADR(queue), |
600 | value: tx_intr_moderation_ctl); |
601 | } |
602 | |
603 | /* RPB: rx packet buffer */ |
604 | void hw_atl_rpb_dma_sys_lbk_set(struct aq_hw_s *aq_hw, u32 dma_sys_lbk) |
605 | { |
606 | aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_DMA_SYS_LBK_ADR, |
607 | HW_ATL_RPB_DMA_SYS_LBK_MSK, |
608 | HW_ATL_RPB_DMA_SYS_LBK_SHIFT, val: dma_sys_lbk); |
609 | } |
610 | |
611 | void hw_atl_rpb_dma_net_lbk_set(struct aq_hw_s *aq_hw, u32 dma_net_lbk) |
612 | { |
613 | aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_DMA_NET_LBK_ADR, |
614 | HW_ATL_RPB_DMA_NET_LBK_MSK, |
615 | HW_ATL_RPB_DMA_NET_LBK_SHIFT, val: dma_net_lbk); |
616 | } |
617 | |
618 | void hw_atl_rpb_rpf_rx_traf_class_mode_set(struct aq_hw_s *aq_hw, |
619 | u32 rx_traf_class_mode) |
620 | { |
621 | aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RPF_RX_TC_MODE_ADR, |
622 | HW_ATL_RPB_RPF_RX_TC_MODE_MSK, |
623 | HW_ATL_RPB_RPF_RX_TC_MODE_SHIFT, |
624 | val: rx_traf_class_mode); |
625 | } |
626 | |
627 | u32 hw_atl_rpb_rpf_rx_traf_class_mode_get(struct aq_hw_s *aq_hw) |
628 | { |
629 | return aq_hw_read_reg_bit(aq_hw, HW_ATL_RPB_RPF_RX_TC_MODE_ADR, |
630 | HW_ATL_RPB_RPF_RX_TC_MODE_MSK, |
631 | HW_ATL_RPB_RPF_RX_TC_MODE_SHIFT); |
632 | } |
633 | |
634 | void hw_atl_rpb_rx_buff_en_set(struct aq_hw_s *aq_hw, u32 rx_buff_en) |
635 | { |
636 | aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RX_BUF_EN_ADR, |
637 | HW_ATL_RPB_RX_BUF_EN_MSK, |
638 | HW_ATL_RPB_RX_BUF_EN_SHIFT, val: rx_buff_en); |
639 | } |
640 | |
641 | void hw_atl_rpb_rx_buff_hi_threshold_per_tc_set(struct aq_hw_s *aq_hw, |
642 | u32 rx_buff_hi_threshold_per_tc, |
643 | u32 buffer) |
644 | { |
645 | aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RXBHI_THRESH_ADR(buffer), |
646 | HW_ATL_RPB_RXBHI_THRESH_MSK, |
647 | HW_ATL_RPB_RXBHI_THRESH_SHIFT, |
648 | val: rx_buff_hi_threshold_per_tc); |
649 | } |
650 | |
651 | void hw_atl_rpb_rx_buff_lo_threshold_per_tc_set(struct aq_hw_s *aq_hw, |
652 | u32 rx_buff_lo_threshold_per_tc, |
653 | u32 buffer) |
654 | { |
655 | aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RXBLO_THRESH_ADR(buffer), |
656 | HW_ATL_RPB_RXBLO_THRESH_MSK, |
657 | HW_ATL_RPB_RXBLO_THRESH_SHIFT, |
658 | val: rx_buff_lo_threshold_per_tc); |
659 | } |
660 | |
661 | void hw_atl_rpb_rx_flow_ctl_mode_set(struct aq_hw_s *aq_hw, u32 rx_flow_ctl_mode) |
662 | { |
663 | aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RX_FC_MODE_ADR, |
664 | HW_ATL_RPB_RX_FC_MODE_MSK, |
665 | HW_ATL_RPB_RX_FC_MODE_SHIFT, val: rx_flow_ctl_mode); |
666 | } |
667 | |
668 | void hw_atl_rdm_rx_dma_desc_cache_init_tgl(struct aq_hw_s *aq_hw) |
669 | { |
670 | u32 val; |
671 | |
672 | val = aq_hw_read_reg_bit(aq_hw, HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_ADR, |
673 | HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_MSK, |
674 | HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_SHIFT); |
675 | |
676 | aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_ADR, |
677 | HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_MSK, |
678 | HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_SHIFT, |
679 | val: val ^ 1); |
680 | } |
681 | |
682 | u32 hw_atl_rdm_rx_dma_desc_cache_init_done_get(struct aq_hw_s *aq_hw) |
683 | { |
684 | return aq_hw_read_reg_bit(aq_hw, RDM_RX_DMA_DESC_CACHE_INIT_DONE_ADR, |
685 | RDM_RX_DMA_DESC_CACHE_INIT_DONE_MSK, |
686 | RDM_RX_DMA_DESC_CACHE_INIT_DONE_SHIFT); |
687 | } |
688 | |
689 | void hw_atl_rpb_rx_pkt_buff_size_per_tc_set(struct aq_hw_s *aq_hw, |
690 | u32 rx_pkt_buff_size_per_tc, u32 buffer) |
691 | { |
692 | aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RXBBUF_SIZE_ADR(buffer), |
693 | HW_ATL_RPB_RXBBUF_SIZE_MSK, |
694 | HW_ATL_RPB_RXBBUF_SIZE_SHIFT, |
695 | val: rx_pkt_buff_size_per_tc); |
696 | } |
697 | |
698 | void hw_atl_rpb_rx_xoff_en_per_tc_set(struct aq_hw_s *aq_hw, |
699 | u32 rx_xoff_en_per_tc, u32 buffer) |
700 | { |
701 | aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RXBXOFF_EN_ADR(buffer), |
702 | HW_ATL_RPB_RXBXOFF_EN_MSK, |
703 | HW_ATL_RPB_RXBXOFF_EN_SHIFT, |
704 | val: rx_xoff_en_per_tc); |
705 | } |
706 | |
707 | /* rpf */ |
708 | |
709 | void hw_atl_rpfl2broadcast_count_threshold_set(struct aq_hw_s *aq_hw, |
710 | u32 l2broadcast_count_threshold) |
711 | { |
712 | aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2BC_THRESH_ADR, |
713 | HW_ATL_RPFL2BC_THRESH_MSK, |
714 | HW_ATL_RPFL2BC_THRESH_SHIFT, |
715 | val: l2broadcast_count_threshold); |
716 | } |
717 | |
718 | void hw_atl_rpfl2broadcast_en_set(struct aq_hw_s *aq_hw, u32 l2broadcast_en) |
719 | { |
720 | aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2BC_EN_ADR, HW_ATL_RPFL2BC_EN_MSK, |
721 | HW_ATL_RPFL2BC_EN_SHIFT, val: l2broadcast_en); |
722 | } |
723 | |
724 | void hw_atl_rpfl2broadcast_flr_act_set(struct aq_hw_s *aq_hw, |
725 | u32 l2broadcast_flr_act) |
726 | { |
727 | aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2BC_ACT_ADR, |
728 | HW_ATL_RPFL2BC_ACT_MSK, |
729 | HW_ATL_RPFL2BC_ACT_SHIFT, val: l2broadcast_flr_act); |
730 | } |
731 | |
732 | void hw_atl_rpfl2multicast_flr_en_set(struct aq_hw_s *aq_hw, |
733 | u32 l2multicast_flr_en, |
734 | u32 filter) |
735 | { |
736 | aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2MC_ENF_ADR(filter), |
737 | HW_ATL_RPFL2MC_ENF_MSK, |
738 | HW_ATL_RPFL2MC_ENF_SHIFT, val: l2multicast_flr_en); |
739 | } |
740 | |
741 | u32 hw_atl_rpfl2promiscuous_mode_en_get(struct aq_hw_s *aq_hw) |
742 | { |
743 | return aq_hw_read_reg_bit(aq_hw, HW_ATL_RPFL2PROMIS_MODE_ADR, |
744 | HW_ATL_RPFL2PROMIS_MODE_MSK, |
745 | HW_ATL_RPFL2PROMIS_MODE_SHIFT); |
746 | } |
747 | |
748 | void hw_atl_rpfl2promiscuous_mode_en_set(struct aq_hw_s *aq_hw, |
749 | u32 l2promiscuous_mode_en) |
750 | { |
751 | aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2PROMIS_MODE_ADR, |
752 | HW_ATL_RPFL2PROMIS_MODE_MSK, |
753 | HW_ATL_RPFL2PROMIS_MODE_SHIFT, |
754 | val: l2promiscuous_mode_en); |
755 | } |
756 | |
757 | void hw_atl_rpfl2unicast_flr_act_set(struct aq_hw_s *aq_hw, |
758 | u32 l2unicast_flr_act, |
759 | u32 filter) |
760 | { |
761 | aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2UC_ACTF_ADR(filter), |
762 | HW_ATL_RPFL2UC_ACTF_MSK, HW_ATL_RPFL2UC_ACTF_SHIFT, |
763 | val: l2unicast_flr_act); |
764 | } |
765 | |
766 | void hw_atl_rpfl2_uc_flr_en_set(struct aq_hw_s *aq_hw, u32 l2unicast_flr_en, |
767 | u32 filter) |
768 | { |
769 | aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2UC_ENF_ADR(filter), |
770 | HW_ATL_RPFL2UC_ENF_MSK, |
771 | HW_ATL_RPFL2UC_ENF_SHIFT, val: l2unicast_flr_en); |
772 | } |
773 | |
774 | void hw_atl_rpfl2unicast_dest_addresslsw_set(struct aq_hw_s *aq_hw, |
775 | u32 l2unicast_dest_addresslsw, |
776 | u32 filter) |
777 | { |
778 | aq_hw_write_reg(hw: aq_hw, HW_ATL_RPFL2UC_DAFLSW_ADR(filter), |
779 | value: l2unicast_dest_addresslsw); |
780 | } |
781 | |
782 | void hw_atl_rpfl2unicast_dest_addressmsw_set(struct aq_hw_s *aq_hw, |
783 | u32 l2unicast_dest_addressmsw, |
784 | u32 filter) |
785 | { |
786 | aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2UC_DAFMSW_ADR(filter), |
787 | HW_ATL_RPFL2UC_DAFMSW_MSK, |
788 | HW_ATL_RPFL2UC_DAFMSW_SHIFT, |
789 | val: l2unicast_dest_addressmsw); |
790 | } |
791 | |
792 | void hw_atl_rpfl2_accept_all_mc_packets_set(struct aq_hw_s *aq_hw, |
793 | u32 l2_accept_all_mc_packets) |
794 | { |
795 | aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2MC_ACCEPT_ALL_ADR, |
796 | HW_ATL_RPFL2MC_ACCEPT_ALL_MSK, |
797 | HW_ATL_RPFL2MC_ACCEPT_ALL_SHIFT, |
798 | val: l2_accept_all_mc_packets); |
799 | } |
800 | |
801 | void hw_atl_rpf_rpb_user_priority_tc_map_set(struct aq_hw_s *aq_hw, |
802 | u32 user_priority, u32 tc) |
803 | { |
804 | /* register address for bitfield rx_tc_up{t}[2:0] */ |
805 | static u32 rpf_rpb_rx_tc_upt_adr[8] = { |
806 | 0x000054c4U, 0x000054C4U, 0x000054C4U, 0x000054C4U, |
807 | 0x000054c4U, 0x000054C4U, 0x000054C4U, 0x000054C4U |
808 | }; |
809 | |
810 | /* bitmask for bitfield rx_tc_up{t}[2:0] */ |
811 | static u32 rpf_rpb_rx_tc_upt_msk[8] = { |
812 | 0x00000007U, 0x00000070U, 0x00000700U, 0x00007000U, |
813 | 0x00070000U, 0x00700000U, 0x07000000U, 0x70000000U |
814 | }; |
815 | |
816 | /* lower bit position of bitfield rx_tc_up{t}[2:0] */ |
817 | static u32 rpf_rpb_rx_tc_upt_shft[8] = { |
818 | 0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U |
819 | }; |
820 | |
821 | aq_hw_write_reg_bit(aq_hw, addr: rpf_rpb_rx_tc_upt_adr[user_priority], |
822 | msk: rpf_rpb_rx_tc_upt_msk[user_priority], |
823 | shift: rpf_rpb_rx_tc_upt_shft[user_priority], val: tc); |
824 | } |
825 | |
826 | void (struct aq_hw_s *aq_hw, u32 ) |
827 | { |
828 | aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_RSS_KEY_ADDR_ADR, |
829 | HW_ATL_RPF_RSS_KEY_ADDR_MSK, |
830 | HW_ATL_RPF_RSS_KEY_ADDR_SHIFT, |
831 | val: rss_key_addr); |
832 | } |
833 | |
834 | void (struct aq_hw_s *aq_hw, u32 ) |
835 | { |
836 | aq_hw_write_reg(hw: aq_hw, HW_ATL_RPF_RSS_KEY_WR_DATA_ADR, |
837 | value: rss_key_wr_data); |
838 | } |
839 | |
840 | u32 (struct aq_hw_s *aq_hw) |
841 | { |
842 | return aq_hw_read_reg_bit(aq_hw, HW_ATL_RPF_RSS_KEY_WR_ENI_ADR, |
843 | HW_ATL_RPF_RSS_KEY_WR_ENI_MSK, |
844 | HW_ATL_RPF_RSS_KEY_WR_ENI_SHIFT); |
845 | } |
846 | |
847 | void (struct aq_hw_s *aq_hw, u32 ) |
848 | { |
849 | aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_RSS_KEY_WR_ENI_ADR, |
850 | HW_ATL_RPF_RSS_KEY_WR_ENI_MSK, |
851 | HW_ATL_RPF_RSS_KEY_WR_ENI_SHIFT, |
852 | val: rss_key_wr_en); |
853 | } |
854 | |
855 | void (struct aq_hw_s *aq_hw, |
856 | u32 ) |
857 | { |
858 | aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_RSS_REDIR_ADDR_ADR, |
859 | HW_ATL_RPF_RSS_REDIR_ADDR_MSK, |
860 | HW_ATL_RPF_RSS_REDIR_ADDR_SHIFT, |
861 | val: rss_redir_tbl_addr); |
862 | } |
863 | |
864 | void (struct aq_hw_s *aq_hw, |
865 | u32 ) |
866 | { |
867 | aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_RSS_REDIR_WR_DATA_ADR, |
868 | HW_ATL_RPF_RSS_REDIR_WR_DATA_MSK, |
869 | HW_ATL_RPF_RSS_REDIR_WR_DATA_SHIFT, |
870 | val: rss_redir_tbl_wr_data); |
871 | } |
872 | |
873 | u32 (struct aq_hw_s *aq_hw) |
874 | { |
875 | return aq_hw_read_reg_bit(aq_hw, HW_ATL_RPF_RSS_REDIR_WR_ENI_ADR, |
876 | HW_ATL_RPF_RSS_REDIR_WR_ENI_MSK, |
877 | HW_ATL_RPF_RSS_REDIR_WR_ENI_SHIFT); |
878 | } |
879 | |
880 | void (struct aq_hw_s *aq_hw, u32 ) |
881 | { |
882 | aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_RSS_REDIR_WR_ENI_ADR, |
883 | HW_ATL_RPF_RSS_REDIR_WR_ENI_MSK, |
884 | HW_ATL_RPF_RSS_REDIR_WR_ENI_SHIFT, val: rss_redir_wr_en); |
885 | } |
886 | |
887 | void hw_atl_rpf_tpo_to_rpf_sys_lbk_set(struct aq_hw_s *aq_hw, |
888 | u32 tpo_to_rpf_sys_lbk) |
889 | { |
890 | aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_TPO_RPF_SYS_LBK_ADR, |
891 | HW_ATL_RPF_TPO_RPF_SYS_LBK_MSK, |
892 | HW_ATL_RPF_TPO_RPF_SYS_LBK_SHIFT, |
893 | val: tpo_to_rpf_sys_lbk); |
894 | } |
895 | |
896 | void hw_atl_rpf_vlan_inner_etht_set(struct aq_hw_s *aq_hw, u32 vlan_inner_etht) |
897 | { |
898 | aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_INNER_TPID_ADR, |
899 | HW_ATL_RPF_VL_INNER_TPID_MSK, |
900 | HW_ATL_RPF_VL_INNER_TPID_SHIFT, |
901 | val: vlan_inner_etht); |
902 | } |
903 | |
904 | void hw_atl_rpf_vlan_outer_etht_set(struct aq_hw_s *aq_hw, u32 vlan_outer_etht) |
905 | { |
906 | aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_OUTER_TPID_ADR, |
907 | HW_ATL_RPF_VL_OUTER_TPID_MSK, |
908 | HW_ATL_RPF_VL_OUTER_TPID_SHIFT, |
909 | val: vlan_outer_etht); |
910 | } |
911 | |
912 | void hw_atl_rpf_vlan_prom_mode_en_set(struct aq_hw_s *aq_hw, |
913 | u32 vlan_prom_mode_en) |
914 | { |
915 | aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_PROMIS_MODE_ADR, |
916 | HW_ATL_RPF_VL_PROMIS_MODE_MSK, |
917 | HW_ATL_RPF_VL_PROMIS_MODE_SHIFT, |
918 | val: vlan_prom_mode_en); |
919 | } |
920 | |
921 | u32 hw_atl_rpf_vlan_prom_mode_en_get(struct aq_hw_s *aq_hw) |
922 | { |
923 | return aq_hw_read_reg_bit(aq_hw, HW_ATL_RPF_VL_PROMIS_MODE_ADR, |
924 | HW_ATL_RPF_VL_PROMIS_MODE_MSK, |
925 | HW_ATL_RPF_VL_PROMIS_MODE_SHIFT); |
926 | } |
927 | |
928 | void hw_atl_rpf_vlan_accept_untagged_packets_set(struct aq_hw_s *aq_hw, |
929 | u32 vlan_acc_untagged_packets) |
930 | { |
931 | aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_ADR, |
932 | HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_MSK, |
933 | HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_SHIFT, |
934 | val: vlan_acc_untagged_packets); |
935 | } |
936 | |
937 | void hw_atl_rpf_vlan_untagged_act_set(struct aq_hw_s *aq_hw, |
938 | u32 vlan_untagged_act) |
939 | { |
940 | aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_UNTAGGED_ACT_ADR, |
941 | HW_ATL_RPF_VL_UNTAGGED_ACT_MSK, |
942 | HW_ATL_RPF_VL_UNTAGGED_ACT_SHIFT, |
943 | val: vlan_untagged_act); |
944 | } |
945 | |
946 | void hw_atl_rpf_vlan_flr_en_set(struct aq_hw_s *aq_hw, u32 vlan_flr_en, |
947 | u32 filter) |
948 | { |
949 | aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_EN_F_ADR(filter), |
950 | HW_ATL_RPF_VL_EN_F_MSK, |
951 | HW_ATL_RPF_VL_EN_F_SHIFT, |
952 | val: vlan_flr_en); |
953 | } |
954 | |
955 | void hw_atl_rpf_vlan_flr_act_set(struct aq_hw_s *aq_hw, u32 vlan_flr_act, |
956 | u32 filter) |
957 | { |
958 | aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_ACT_F_ADR(filter), |
959 | HW_ATL_RPF_VL_ACT_F_MSK, |
960 | HW_ATL_RPF_VL_ACT_F_SHIFT, |
961 | val: vlan_flr_act); |
962 | } |
963 | |
964 | void hw_atl_rpf_vlan_id_flr_set(struct aq_hw_s *aq_hw, u32 vlan_id_flr, |
965 | u32 filter) |
966 | { |
967 | aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_ID_F_ADR(filter), |
968 | HW_ATL_RPF_VL_ID_F_MSK, |
969 | HW_ATL_RPF_VL_ID_F_SHIFT, |
970 | val: vlan_id_flr); |
971 | } |
972 | |
973 | void hw_atl_rpf_vlan_rxq_en_flr_set(struct aq_hw_s *aq_hw, u32 vlan_rxq_en, |
974 | u32 filter) |
975 | { |
976 | aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_RXQ_EN_F_ADR(filter), |
977 | HW_ATL_RPF_VL_RXQ_EN_F_MSK, |
978 | HW_ATL_RPF_VL_RXQ_EN_F_SHIFT, |
979 | val: vlan_rxq_en); |
980 | } |
981 | |
982 | void hw_atl_rpf_vlan_rxq_flr_set(struct aq_hw_s *aq_hw, u32 vlan_rxq, |
983 | u32 filter) |
984 | { |
985 | aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_RXQ_F_ADR(filter), |
986 | HW_ATL_RPF_VL_RXQ_F_MSK, |
987 | HW_ATL_RPF_VL_RXQ_F_SHIFT, |
988 | val: vlan_rxq); |
989 | }; |
990 | |
991 | void hw_atl_rpf_etht_flr_en_set(struct aq_hw_s *aq_hw, u32 etht_flr_en, |
992 | u32 filter) |
993 | { |
994 | aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_ENF_ADR(filter), |
995 | HW_ATL_RPF_ET_ENF_MSK, |
996 | HW_ATL_RPF_ET_ENF_SHIFT, val: etht_flr_en); |
997 | } |
998 | |
999 | void hw_atl_rpf_etht_user_priority_en_set(struct aq_hw_s *aq_hw, |
1000 | u32 etht_user_priority_en, u32 filter) |
1001 | { |
1002 | aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_UPFEN_ADR(filter), |
1003 | HW_ATL_RPF_ET_UPFEN_MSK, HW_ATL_RPF_ET_UPFEN_SHIFT, |
1004 | val: etht_user_priority_en); |
1005 | } |
1006 | |
1007 | void hw_atl_rpf_etht_rx_queue_en_set(struct aq_hw_s *aq_hw, |
1008 | u32 etht_rx_queue_en, |
1009 | u32 filter) |
1010 | { |
1011 | aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_RXQFEN_ADR(filter), |
1012 | HW_ATL_RPF_ET_RXQFEN_MSK, |
1013 | HW_ATL_RPF_ET_RXQFEN_SHIFT, |
1014 | val: etht_rx_queue_en); |
1015 | } |
1016 | |
1017 | void hw_atl_rpf_etht_user_priority_set(struct aq_hw_s *aq_hw, |
1018 | u32 etht_user_priority, |
1019 | u32 filter) |
1020 | { |
1021 | aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_UPF_ADR(filter), |
1022 | HW_ATL_RPF_ET_UPF_MSK, |
1023 | HW_ATL_RPF_ET_UPF_SHIFT, val: etht_user_priority); |
1024 | } |
1025 | |
1026 | void hw_atl_rpf_etht_rx_queue_set(struct aq_hw_s *aq_hw, u32 etht_rx_queue, |
1027 | u32 filter) |
1028 | { |
1029 | aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_RXQF_ADR(filter), |
1030 | HW_ATL_RPF_ET_RXQF_MSK, |
1031 | HW_ATL_RPF_ET_RXQF_SHIFT, val: etht_rx_queue); |
1032 | } |
1033 | |
1034 | void hw_atl_rpf_etht_mgt_queue_set(struct aq_hw_s *aq_hw, u32 etht_mgt_queue, |
1035 | u32 filter) |
1036 | { |
1037 | aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_MNG_RXQF_ADR(filter), |
1038 | HW_ATL_RPF_ET_MNG_RXQF_MSK, |
1039 | HW_ATL_RPF_ET_MNG_RXQF_SHIFT, |
1040 | val: etht_mgt_queue); |
1041 | } |
1042 | |
1043 | void hw_atl_rpf_etht_flr_act_set(struct aq_hw_s *aq_hw, u32 etht_flr_act, |
1044 | u32 filter) |
1045 | { |
1046 | aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_ACTF_ADR(filter), |
1047 | HW_ATL_RPF_ET_ACTF_MSK, |
1048 | HW_ATL_RPF_ET_ACTF_SHIFT, val: etht_flr_act); |
1049 | } |
1050 | |
1051 | void hw_atl_rpf_etht_flr_set(struct aq_hw_s *aq_hw, u32 etht_flr, u32 filter) |
1052 | { |
1053 | aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_VALF_ADR(filter), |
1054 | HW_ATL_RPF_ET_VALF_MSK, |
1055 | HW_ATL_RPF_ET_VALF_SHIFT, val: etht_flr); |
1056 | } |
1057 | |
1058 | void hw_atl_rpf_l4_spd_set(struct aq_hw_s *aq_hw, u32 val, u32 filter) |
1059 | { |
1060 | aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_L4_SPD_ADR(filter), |
1061 | HW_ATL_RPF_L4_SPD_MSK, |
1062 | HW_ATL_RPF_L4_SPD_SHIFT, val); |
1063 | } |
1064 | |
1065 | void hw_atl_rpf_l4_dpd_set(struct aq_hw_s *aq_hw, u32 val, u32 filter) |
1066 | { |
1067 | aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_L4_DPD_ADR(filter), |
1068 | HW_ATL_RPF_L4_DPD_MSK, |
1069 | HW_ATL_RPF_L4_DPD_SHIFT, val); |
1070 | } |
1071 | |
1072 | /* RPO: rx packet offload */ |
1073 | void (struct aq_hw_s *aq_hw, |
1074 | u32 ) |
1075 | { |
1076 | aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_IPV4CHK_EN_ADR, |
1077 | HW_ATL_RPO_IPV4CHK_EN_MSK, |
1078 | HW_ATL_RPO_IPV4CHK_EN_SHIFT, |
1079 | val: ipv4header_crc_offload_en); |
1080 | } |
1081 | |
1082 | void hw_atl_rpo_rx_desc_vlan_stripping_set(struct aq_hw_s *aq_hw, |
1083 | u32 rx_desc_vlan_stripping, |
1084 | u32 descriptor) |
1085 | { |
1086 | aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_DESCDVL_STRIP_ADR(descriptor), |
1087 | HW_ATL_RPO_DESCDVL_STRIP_MSK, |
1088 | HW_ATL_RPO_DESCDVL_STRIP_SHIFT, |
1089 | val: rx_desc_vlan_stripping); |
1090 | } |
1091 | |
1092 | void hw_atl_rpo_outer_vlan_tag_mode_set(void *context, |
1093 | u32 outervlantagmode) |
1094 | { |
1095 | aq_hw_write_reg_bit(aq_hw: context, HW_ATL_RPO_OUTER_VL_INS_MODE_ADR, |
1096 | HW_ATL_RPO_OUTER_VL_INS_MODE_MSK, |
1097 | HW_ATL_RPO_OUTER_VL_INS_MODE_SHIFT, |
1098 | val: outervlantagmode); |
1099 | } |
1100 | |
1101 | u32 hw_atl_rpo_outer_vlan_tag_mode_get(void *context) |
1102 | { |
1103 | return aq_hw_read_reg_bit(aq_hw: context, HW_ATL_RPO_OUTER_VL_INS_MODE_ADR, |
1104 | HW_ATL_RPO_OUTER_VL_INS_MODE_MSK, |
1105 | HW_ATL_RPO_OUTER_VL_INS_MODE_SHIFT); |
1106 | } |
1107 | |
1108 | void hw_atl_rpo_tcp_udp_crc_offload_en_set(struct aq_hw_s *aq_hw, |
1109 | u32 tcp_udp_crc_offload_en) |
1110 | { |
1111 | aq_hw_write_reg_bit(aq_hw, HW_ATL_RPOL4CHK_EN_ADR, |
1112 | HW_ATL_RPOL4CHK_EN_MSK, |
1113 | HW_ATL_RPOL4CHK_EN_SHIFT, val: tcp_udp_crc_offload_en); |
1114 | } |
1115 | |
1116 | void hw_atl_rpo_lro_en_set(struct aq_hw_s *aq_hw, u32 lro_en) |
1117 | { |
1118 | aq_hw_write_reg(hw: aq_hw, HW_ATL_RPO_LRO_EN_ADR, value: lro_en); |
1119 | } |
1120 | |
1121 | void hw_atl_rpo_lro_patch_optimization_en_set(struct aq_hw_s *aq_hw, |
1122 | u32 lro_patch_optimization_en) |
1123 | { |
1124 | aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_PTOPT_EN_ADR, |
1125 | HW_ATL_RPO_LRO_PTOPT_EN_MSK, |
1126 | HW_ATL_RPO_LRO_PTOPT_EN_SHIFT, |
1127 | val: lro_patch_optimization_en); |
1128 | } |
1129 | |
1130 | void hw_atl_rpo_lro_qsessions_lim_set(struct aq_hw_s *aq_hw, |
1131 | u32 lro_qsessions_lim) |
1132 | { |
1133 | aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_QSES_LMT_ADR, |
1134 | HW_ATL_RPO_LRO_QSES_LMT_MSK, |
1135 | HW_ATL_RPO_LRO_QSES_LMT_SHIFT, |
1136 | val: lro_qsessions_lim); |
1137 | } |
1138 | |
1139 | void hw_atl_rpo_lro_total_desc_lim_set(struct aq_hw_s *aq_hw, |
1140 | u32 lro_total_desc_lim) |
1141 | { |
1142 | aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_TOT_DSC_LMT_ADR, |
1143 | HW_ATL_RPO_LRO_TOT_DSC_LMT_MSK, |
1144 | HW_ATL_RPO_LRO_TOT_DSC_LMT_SHIFT, |
1145 | val: lro_total_desc_lim); |
1146 | } |
1147 | |
1148 | void hw_atl_rpo_lro_min_pay_of_first_pkt_set(struct aq_hw_s *aq_hw, |
1149 | u32 lro_min_pld_of_first_pkt) |
1150 | { |
1151 | aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_PKT_MIN_ADR, |
1152 | HW_ATL_RPO_LRO_PKT_MIN_MSK, |
1153 | HW_ATL_RPO_LRO_PKT_MIN_SHIFT, |
1154 | val: lro_min_pld_of_first_pkt); |
1155 | } |
1156 | |
1157 | void hw_atl_rpo_lro_pkt_lim_set(struct aq_hw_s *aq_hw, u32 lro_pkt_lim) |
1158 | { |
1159 | aq_hw_write_reg(hw: aq_hw, HW_ATL_RPO_LRO_RSC_MAX_ADR, value: lro_pkt_lim); |
1160 | } |
1161 | |
1162 | void hw_atl_rpo_lro_max_num_of_descriptors_set(struct aq_hw_s *aq_hw, |
1163 | u32 lro_max_number_of_descriptors, |
1164 | u32 lro) |
1165 | { |
1166 | /* Register address for bitfield lro{L}_des_max[1:0] */ |
1167 | static u32 rpo_lro_ldes_max_adr[32] = { |
1168 | 0x000055A0U, 0x000055A0U, 0x000055A0U, 0x000055A0U, |
1169 | 0x000055A0U, 0x000055A0U, 0x000055A0U, 0x000055A0U, |
1170 | 0x000055A4U, 0x000055A4U, 0x000055A4U, 0x000055A4U, |
1171 | 0x000055A4U, 0x000055A4U, 0x000055A4U, 0x000055A4U, |
1172 | 0x000055A8U, 0x000055A8U, 0x000055A8U, 0x000055A8U, |
1173 | 0x000055A8U, 0x000055A8U, 0x000055A8U, 0x000055A8U, |
1174 | 0x000055ACU, 0x000055ACU, 0x000055ACU, 0x000055ACU, |
1175 | 0x000055ACU, 0x000055ACU, 0x000055ACU, 0x000055ACU |
1176 | }; |
1177 | |
1178 | /* Bitmask for bitfield lro{L}_des_max[1:0] */ |
1179 | static u32 rpo_lro_ldes_max_msk[32] = { |
1180 | 0x00000003U, 0x00000030U, 0x00000300U, 0x00003000U, |
1181 | 0x00030000U, 0x00300000U, 0x03000000U, 0x30000000U, |
1182 | 0x00000003U, 0x00000030U, 0x00000300U, 0x00003000U, |
1183 | 0x00030000U, 0x00300000U, 0x03000000U, 0x30000000U, |
1184 | 0x00000003U, 0x00000030U, 0x00000300U, 0x00003000U, |
1185 | 0x00030000U, 0x00300000U, 0x03000000U, 0x30000000U, |
1186 | 0x00000003U, 0x00000030U, 0x00000300U, 0x00003000U, |
1187 | 0x00030000U, 0x00300000U, 0x03000000U, 0x30000000U |
1188 | }; |
1189 | |
1190 | /* Lower bit position of bitfield lro{L}_des_max[1:0] */ |
1191 | static u32 rpo_lro_ldes_max_shift[32] = { |
1192 | 0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U, |
1193 | 0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U, |
1194 | 0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U, |
1195 | 0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U |
1196 | }; |
1197 | |
1198 | aq_hw_write_reg_bit(aq_hw, addr: rpo_lro_ldes_max_adr[lro], |
1199 | msk: rpo_lro_ldes_max_msk[lro], |
1200 | shift: rpo_lro_ldes_max_shift[lro], |
1201 | val: lro_max_number_of_descriptors); |
1202 | } |
1203 | |
1204 | void hw_atl_rpo_lro_time_base_divider_set(struct aq_hw_s *aq_hw, |
1205 | u32 lro_time_base_divider) |
1206 | { |
1207 | aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_TB_DIV_ADR, |
1208 | HW_ATL_RPO_LRO_TB_DIV_MSK, |
1209 | HW_ATL_RPO_LRO_TB_DIV_SHIFT, |
1210 | val: lro_time_base_divider); |
1211 | } |
1212 | |
1213 | void hw_atl_rpo_lro_inactive_interval_set(struct aq_hw_s *aq_hw, |
1214 | u32 lro_inactive_interval) |
1215 | { |
1216 | aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_INA_IVAL_ADR, |
1217 | HW_ATL_RPO_LRO_INA_IVAL_MSK, |
1218 | HW_ATL_RPO_LRO_INA_IVAL_SHIFT, |
1219 | val: lro_inactive_interval); |
1220 | } |
1221 | |
1222 | void hw_atl_rpo_lro_max_coalescing_interval_set(struct aq_hw_s *aq_hw, |
1223 | u32 lro_max_coal_interval) |
1224 | { |
1225 | aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_MAX_IVAL_ADR, |
1226 | HW_ATL_RPO_LRO_MAX_IVAL_MSK, |
1227 | HW_ATL_RPO_LRO_MAX_IVAL_SHIFT, |
1228 | val: lro_max_coal_interval); |
1229 | } |
1230 | |
1231 | /* rx */ |
1232 | void hw_atl_rx_rx_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 rx_reg_res_dis) |
1233 | { |
1234 | aq_hw_write_reg_bit(aq_hw, HW_ATL_RX_REG_RES_DSBL_ADR, |
1235 | HW_ATL_RX_REG_RES_DSBL_MSK, |
1236 | HW_ATL_RX_REG_RES_DSBL_SHIFT, |
1237 | val: rx_reg_res_dis); |
1238 | } |
1239 | |
1240 | /* tdm */ |
1241 | void hw_atl_tdm_cpu_id_set(struct aq_hw_s *aq_hw, u32 cpuid, u32 dca) |
1242 | { |
1243 | aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DCADCPUID_ADR(dca), |
1244 | HW_ATL_TDM_DCADCPUID_MSK, |
1245 | HW_ATL_TDM_DCADCPUID_SHIFT, val: cpuid); |
1246 | } |
1247 | |
1248 | void hw_atl_tdm_large_send_offload_en_set(struct aq_hw_s *aq_hw, |
1249 | u32 large_send_offload_en) |
1250 | { |
1251 | aq_hw_write_reg(hw: aq_hw, HW_ATL_TDM_LSO_EN_ADR, value: large_send_offload_en); |
1252 | } |
1253 | |
1254 | void hw_atl_tdm_tx_dca_en_set(struct aq_hw_s *aq_hw, u32 tx_dca_en) |
1255 | { |
1256 | aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DCA_EN_ADR, HW_ATL_TDM_DCA_EN_MSK, |
1257 | HW_ATL_TDM_DCA_EN_SHIFT, val: tx_dca_en); |
1258 | } |
1259 | |
1260 | void hw_atl_tdm_tx_dca_mode_set(struct aq_hw_s *aq_hw, u32 tx_dca_mode) |
1261 | { |
1262 | aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DCA_MODE_ADR, |
1263 | HW_ATL_TDM_DCA_MODE_MSK, |
1264 | HW_ATL_TDM_DCA_MODE_SHIFT, val: tx_dca_mode); |
1265 | } |
1266 | |
1267 | void hw_atl_tdm_tx_desc_dca_en_set(struct aq_hw_s *aq_hw, u32 tx_desc_dca_en, |
1268 | u32 dca) |
1269 | { |
1270 | aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DCADDESC_EN_ADR(dca), |
1271 | HW_ATL_TDM_DCADDESC_EN_MSK, |
1272 | HW_ATL_TDM_DCADDESC_EN_SHIFT, |
1273 | val: tx_desc_dca_en); |
1274 | } |
1275 | |
1276 | void hw_atl_tdm_tx_desc_en_set(struct aq_hw_s *aq_hw, u32 tx_desc_en, |
1277 | u32 descriptor) |
1278 | { |
1279 | aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DESCDEN_ADR(descriptor), |
1280 | HW_ATL_TDM_DESCDEN_MSK, |
1281 | HW_ATL_TDM_DESCDEN_SHIFT, |
1282 | val: tx_desc_en); |
1283 | } |
1284 | |
1285 | u32 hw_atl_tdm_tx_desc_head_ptr_get(struct aq_hw_s *aq_hw, u32 descriptor) |
1286 | { |
1287 | return aq_hw_read_reg_bit(aq_hw, HW_ATL_TDM_DESCDHD_ADR(descriptor), |
1288 | HW_ATL_TDM_DESCDHD_MSK, |
1289 | HW_ATL_TDM_DESCDHD_SHIFT); |
1290 | } |
1291 | |
1292 | void hw_atl_tdm_tx_desc_len_set(struct aq_hw_s *aq_hw, u32 tx_desc_len, |
1293 | u32 descriptor) |
1294 | { |
1295 | aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DESCDLEN_ADR(descriptor), |
1296 | HW_ATL_TDM_DESCDLEN_MSK, |
1297 | HW_ATL_TDM_DESCDLEN_SHIFT, |
1298 | val: tx_desc_len); |
1299 | } |
1300 | |
1301 | void hw_atl_tdm_tx_desc_wr_wb_irq_en_set(struct aq_hw_s *aq_hw, |
1302 | u32 tx_desc_wr_wb_irq_en) |
1303 | { |
1304 | aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_INT_DESC_WRB_EN_ADR, |
1305 | HW_ATL_TDM_INT_DESC_WRB_EN_MSK, |
1306 | HW_ATL_TDM_INT_DESC_WRB_EN_SHIFT, |
1307 | val: tx_desc_wr_wb_irq_en); |
1308 | } |
1309 | |
1310 | void hw_atl_tdm_tx_desc_wr_wb_threshold_set(struct aq_hw_s *aq_hw, |
1311 | u32 tx_desc_wr_wb_threshold, |
1312 | u32 descriptor) |
1313 | { |
1314 | aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DESCDWRB_THRESH_ADR(descriptor), |
1315 | HW_ATL_TDM_DESCDWRB_THRESH_MSK, |
1316 | HW_ATL_TDM_DESCDWRB_THRESH_SHIFT, |
1317 | val: tx_desc_wr_wb_threshold); |
1318 | } |
1319 | |
1320 | void hw_atl_tdm_tdm_intr_moder_en_set(struct aq_hw_s *aq_hw, |
1321 | u32 tdm_irq_moderation_en) |
1322 | { |
1323 | aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_INT_MOD_EN_ADR, |
1324 | HW_ATL_TDM_INT_MOD_EN_MSK, |
1325 | HW_ATL_TDM_INT_MOD_EN_SHIFT, |
1326 | val: tdm_irq_moderation_en); |
1327 | } |
1328 | |
1329 | /* thm */ |
1330 | void hw_atl_thm_lso_tcp_flag_of_first_pkt_set(struct aq_hw_s *aq_hw, |
1331 | u32 lso_tcp_flag_of_first_pkt) |
1332 | { |
1333 | aq_hw_write_reg_bit(aq_hw, HW_ATL_THM_LSO_TCP_FLAG_FIRST_ADR, |
1334 | HW_ATL_THM_LSO_TCP_FLAG_FIRST_MSK, |
1335 | HW_ATL_THM_LSO_TCP_FLAG_FIRST_SHIFT, |
1336 | val: lso_tcp_flag_of_first_pkt); |
1337 | } |
1338 | |
1339 | void hw_atl_thm_lso_tcp_flag_of_last_pkt_set(struct aq_hw_s *aq_hw, |
1340 | u32 lso_tcp_flag_of_last_pkt) |
1341 | { |
1342 | aq_hw_write_reg_bit(aq_hw, HW_ATL_THM_LSO_TCP_FLAG_LAST_ADR, |
1343 | HW_ATL_THM_LSO_TCP_FLAG_LAST_MSK, |
1344 | HW_ATL_THM_LSO_TCP_FLAG_LAST_SHIFT, |
1345 | val: lso_tcp_flag_of_last_pkt); |
1346 | } |
1347 | |
1348 | void hw_atl_thm_lso_tcp_flag_of_middle_pkt_set(struct aq_hw_s *aq_hw, |
1349 | u32 lso_tcp_flag_of_middle_pkt) |
1350 | { |
1351 | aq_hw_write_reg_bit(aq_hw, HW_ATL_THM_LSO_TCP_FLAG_MID_ADR, |
1352 | HW_ATL_THM_LSO_TCP_FLAG_MID_MSK, |
1353 | HW_ATL_THM_LSO_TCP_FLAG_MID_SHIFT, |
1354 | val: lso_tcp_flag_of_middle_pkt); |
1355 | } |
1356 | |
1357 | /* TPB: tx packet buffer */ |
1358 | void hw_atl_tpb_tx_buff_en_set(struct aq_hw_s *aq_hw, u32 tx_buff_en) |
1359 | { |
1360 | aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TX_BUF_EN_ADR, |
1361 | HW_ATL_TPB_TX_BUF_EN_MSK, |
1362 | HW_ATL_TPB_TX_BUF_EN_SHIFT, val: tx_buff_en); |
1363 | } |
1364 | |
1365 | u32 hw_atl_tpb_tps_tx_tc_mode_get(struct aq_hw_s *aq_hw) |
1366 | { |
1367 | return aq_hw_read_reg_bit(aq_hw, HW_ATL_TPB_TX_TC_MODE_ADDR, |
1368 | HW_ATL_TPB_TX_TC_MODE_MSK, |
1369 | HW_ATL_TPB_TX_TC_MODE_SHIFT); |
1370 | } |
1371 | |
1372 | void hw_atl_tpb_tps_tx_tc_mode_set(struct aq_hw_s *aq_hw, |
1373 | u32 tx_traf_class_mode) |
1374 | { |
1375 | aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TX_TC_MODE_ADDR, |
1376 | HW_ATL_TPB_TX_TC_MODE_MSK, |
1377 | HW_ATL_TPB_TX_TC_MODE_SHIFT, |
1378 | val: tx_traf_class_mode); |
1379 | } |
1380 | |
1381 | void hw_atl_tpb_tx_buff_hi_threshold_per_tc_set(struct aq_hw_s *aq_hw, |
1382 | u32 tx_buff_hi_threshold_per_tc, |
1383 | u32 buffer) |
1384 | { |
1385 | aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TXBHI_THRESH_ADR(buffer), |
1386 | HW_ATL_TPB_TXBHI_THRESH_MSK, |
1387 | HW_ATL_TPB_TXBHI_THRESH_SHIFT, |
1388 | val: tx_buff_hi_threshold_per_tc); |
1389 | } |
1390 | |
1391 | void hw_atl_tpb_tx_buff_lo_threshold_per_tc_set(struct aq_hw_s *aq_hw, |
1392 | u32 tx_buff_lo_threshold_per_tc, |
1393 | u32 buffer) |
1394 | { |
1395 | aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TXBLO_THRESH_ADR(buffer), |
1396 | HW_ATL_TPB_TXBLO_THRESH_MSK, |
1397 | HW_ATL_TPB_TXBLO_THRESH_SHIFT, |
1398 | val: tx_buff_lo_threshold_per_tc); |
1399 | } |
1400 | |
1401 | void hw_atl_tpb_tx_dma_sys_lbk_en_set(struct aq_hw_s *aq_hw, u32 tx_dma_sys_lbk_en) |
1402 | { |
1403 | aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_DMA_SYS_LBK_ADR, |
1404 | HW_ATL_TPB_DMA_SYS_LBK_MSK, |
1405 | HW_ATL_TPB_DMA_SYS_LBK_SHIFT, |
1406 | val: tx_dma_sys_lbk_en); |
1407 | } |
1408 | |
1409 | void hw_atl_tpb_tx_dma_net_lbk_en_set(struct aq_hw_s *aq_hw, |
1410 | u32 tx_dma_net_lbk_en) |
1411 | { |
1412 | aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_DMA_NET_LBK_ADR, |
1413 | HW_ATL_TPB_DMA_NET_LBK_MSK, |
1414 | HW_ATL_TPB_DMA_NET_LBK_SHIFT, |
1415 | val: tx_dma_net_lbk_en); |
1416 | } |
1417 | |
1418 | void hw_atl_tpb_tx_tx_clk_gate_en_set(struct aq_hw_s *aq_hw, |
1419 | u32 tx_clk_gate_en) |
1420 | { |
1421 | aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TX_CLK_GATE_EN_ADR, |
1422 | HW_ATL_TPB_TX_CLK_GATE_EN_MSK, |
1423 | HW_ATL_TPB_TX_CLK_GATE_EN_SHIFT, |
1424 | val: tx_clk_gate_en); |
1425 | } |
1426 | |
1427 | void hw_atl_tpb_tx_pkt_buff_size_per_tc_set(struct aq_hw_s *aq_hw, |
1428 | |
1429 | u32 tx_pkt_buff_size_per_tc, u32 buffer) |
1430 | { |
1431 | aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TXBBUF_SIZE_ADR(buffer), |
1432 | HW_ATL_TPB_TXBBUF_SIZE_MSK, |
1433 | HW_ATL_TPB_TXBBUF_SIZE_SHIFT, |
1434 | val: tx_pkt_buff_size_per_tc); |
1435 | } |
1436 | |
1437 | void hw_atl_tpb_tx_path_scp_ins_en_set(struct aq_hw_s *aq_hw, u32 tx_path_scp_ins_en) |
1438 | { |
1439 | aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TX_SCP_INS_EN_ADR, |
1440 | HW_ATL_TPB_TX_SCP_INS_EN_MSK, |
1441 | HW_ATL_TPB_TX_SCP_INS_EN_SHIFT, |
1442 | val: tx_path_scp_ins_en); |
1443 | } |
1444 | |
1445 | /* TPO: tx packet offload */ |
1446 | void (struct aq_hw_s *aq_hw, |
1447 | u32 ) |
1448 | { |
1449 | aq_hw_write_reg_bit(aq_hw, HW_ATL_TPO_IPV4CHK_EN_ADR, |
1450 | HW_ATL_TPO_IPV4CHK_EN_MSK, |
1451 | HW_ATL_TPO_IPV4CHK_EN_SHIFT, |
1452 | val: ipv4header_crc_offload_en); |
1453 | } |
1454 | |
1455 | void hw_atl_tpo_tcp_udp_crc_offload_en_set(struct aq_hw_s *aq_hw, |
1456 | u32 tcp_udp_crc_offload_en) |
1457 | { |
1458 | aq_hw_write_reg_bit(aq_hw, HW_ATL_TPOL4CHK_EN_ADR, |
1459 | HW_ATL_TPOL4CHK_EN_MSK, |
1460 | HW_ATL_TPOL4CHK_EN_SHIFT, |
1461 | val: tcp_udp_crc_offload_en); |
1462 | } |
1463 | |
1464 | void hw_atl_tpo_tx_pkt_sys_lbk_en_set(struct aq_hw_s *aq_hw, |
1465 | u32 tx_pkt_sys_lbk_en) |
1466 | { |
1467 | aq_hw_write_reg_bit(aq_hw, HW_ATL_TPO_PKT_SYS_LBK_ADR, |
1468 | HW_ATL_TPO_PKT_SYS_LBK_MSK, |
1469 | HW_ATL_TPO_PKT_SYS_LBK_SHIFT, |
1470 | val: tx_pkt_sys_lbk_en); |
1471 | } |
1472 | |
1473 | /* TPS: tx packet scheduler */ |
1474 | void hw_atl_tps_tx_pkt_shed_data_arb_mode_set(struct aq_hw_s *aq_hw, |
1475 | u32 tx_pkt_shed_data_arb_mode) |
1476 | { |
1477 | aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DATA_TC_ARB_MODE_ADR, |
1478 | HW_ATL_TPS_DATA_TC_ARB_MODE_MSK, |
1479 | HW_ATL_TPS_DATA_TC_ARB_MODE_SHIFT, |
1480 | val: tx_pkt_shed_data_arb_mode); |
1481 | } |
1482 | |
1483 | void hw_atl_tps_tx_pkt_shed_desc_rate_curr_time_res_set(struct aq_hw_s *aq_hw, |
1484 | u32 curr_time_res) |
1485 | { |
1486 | aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_RATE_TA_RST_ADR, |
1487 | HW_ATL_TPS_DESC_RATE_TA_RST_MSK, |
1488 | HW_ATL_TPS_DESC_RATE_TA_RST_SHIFT, |
1489 | val: curr_time_res); |
1490 | } |
1491 | |
1492 | void hw_atl_tps_tx_pkt_shed_desc_rate_lim_set(struct aq_hw_s *aq_hw, |
1493 | u32 tx_pkt_shed_desc_rate_lim) |
1494 | { |
1495 | aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_RATE_LIM_ADR, |
1496 | HW_ATL_TPS_DESC_RATE_LIM_MSK, |
1497 | HW_ATL_TPS_DESC_RATE_LIM_SHIFT, |
1498 | val: tx_pkt_shed_desc_rate_lim); |
1499 | } |
1500 | |
1501 | void hw_atl_tps_tx_pkt_shed_desc_tc_arb_mode_set(struct aq_hw_s *aq_hw, |
1502 | u32 arb_mode) |
1503 | { |
1504 | aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_TC_ARB_MODE_ADR, |
1505 | HW_ATL_TPS_DESC_TC_ARB_MODE_MSK, |
1506 | HW_ATL_TPS_DESC_TC_ARB_MODE_SHIFT, |
1507 | val: arb_mode); |
1508 | } |
1509 | |
1510 | void hw_atl_tps_tx_pkt_shed_desc_tc_max_credit_set(struct aq_hw_s *aq_hw, |
1511 | const u32 tc, |
1512 | const u32 max_credit) |
1513 | { |
1514 | aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_TCTCREDIT_MAX_ADR(tc), |
1515 | HW_ATL_TPS_DESC_TCTCREDIT_MAX_MSK, |
1516 | HW_ATL_TPS_DESC_TCTCREDIT_MAX_SHIFT, |
1517 | val: max_credit); |
1518 | } |
1519 | |
1520 | void hw_atl_tps_tx_pkt_shed_desc_tc_weight_set(struct aq_hw_s *aq_hw, |
1521 | const u32 tc, |
1522 | const u32 weight) |
1523 | { |
1524 | aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_TCTWEIGHT_ADR(tc), |
1525 | HW_ATL_TPS_DESC_TCTWEIGHT_MSK, |
1526 | HW_ATL_TPS_DESC_TCTWEIGHT_SHIFT, |
1527 | val: weight); |
1528 | } |
1529 | |
1530 | void hw_atl_tps_tx_pkt_shed_desc_vm_arb_mode_set(struct aq_hw_s *aq_hw, |
1531 | u32 arb_mode) |
1532 | { |
1533 | aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_VM_ARB_MODE_ADR, |
1534 | HW_ATL_TPS_DESC_VM_ARB_MODE_MSK, |
1535 | HW_ATL_TPS_DESC_VM_ARB_MODE_SHIFT, |
1536 | val: arb_mode); |
1537 | } |
1538 | |
1539 | void hw_atl_tps_tx_pkt_shed_tc_data_max_credit_set(struct aq_hw_s *aq_hw, |
1540 | const u32 tc, |
1541 | const u32 max_credit) |
1542 | { |
1543 | aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DATA_TCTCREDIT_MAX_ADR(tc), |
1544 | HW_ATL_TPS_DATA_TCTCREDIT_MAX_MSK, |
1545 | HW_ATL_TPS_DATA_TCTCREDIT_MAX_SHIFT, |
1546 | val: max_credit); |
1547 | } |
1548 | |
1549 | void hw_atl_tps_tx_pkt_shed_tc_data_weight_set(struct aq_hw_s *aq_hw, |
1550 | const u32 tc, |
1551 | const u32 weight) |
1552 | { |
1553 | aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DATA_TCTWEIGHT_ADR(tc), |
1554 | HW_ATL_TPS_DATA_TCTWEIGHT_MSK, |
1555 | HW_ATL_TPS_DATA_TCTWEIGHT_SHIFT, |
1556 | val: weight); |
1557 | } |
1558 | |
1559 | void hw_atl_tps_tx_desc_rate_mode_set(struct aq_hw_s *aq_hw, |
1560 | const u32 rate_mode) |
1561 | { |
1562 | aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_TX_DESC_RATE_MODE_ADR, |
1563 | HW_ATL_TPS_TX_DESC_RATE_MODE_MSK, |
1564 | HW_ATL_TPS_TX_DESC_RATE_MODE_SHIFT, |
1565 | val: rate_mode); |
1566 | } |
1567 | |
1568 | void hw_atl_tps_tx_desc_rate_en_set(struct aq_hw_s *aq_hw, const u32 desc, |
1569 | const u32 enable) |
1570 | { |
1571 | aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_RATE_EN_ADR(desc), |
1572 | HW_ATL_TPS_DESC_RATE_EN_MSK, |
1573 | HW_ATL_TPS_DESC_RATE_EN_SHIFT, |
1574 | val: enable); |
1575 | } |
1576 | |
1577 | void hw_atl_tps_tx_desc_rate_x_set(struct aq_hw_s *aq_hw, const u32 desc, |
1578 | const u32 rate_int) |
1579 | { |
1580 | aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_RATE_X_ADR(desc), |
1581 | HW_ATL_TPS_DESC_RATE_X_MSK, |
1582 | HW_ATL_TPS_DESC_RATE_X_SHIFT, |
1583 | val: rate_int); |
1584 | } |
1585 | |
1586 | void hw_atl_tps_tx_desc_rate_y_set(struct aq_hw_s *aq_hw, const u32 desc, |
1587 | const u32 rate_frac) |
1588 | { |
1589 | aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_RATE_Y_ADR(desc), |
1590 | HW_ATL_TPS_DESC_RATE_Y_MSK, |
1591 | HW_ATL_TPS_DESC_RATE_Y_SHIFT, |
1592 | val: rate_frac); |
1593 | } |
1594 | |
1595 | /* tx */ |
1596 | void hw_atl_tx_tx_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 tx_reg_res_dis) |
1597 | { |
1598 | aq_hw_write_reg_bit(aq_hw, HW_ATL_TX_REG_RES_DSBL_ADR, |
1599 | HW_ATL_TX_REG_RES_DSBL_MSK, |
1600 | HW_ATL_TX_REG_RES_DSBL_SHIFT, val: tx_reg_res_dis); |
1601 | } |
1602 | |
1603 | /* msm */ |
1604 | u32 hw_atl_msm_reg_access_status_get(struct aq_hw_s *aq_hw) |
1605 | { |
1606 | return aq_hw_read_reg_bit(aq_hw, HW_ATL_MSM_REG_ACCESS_BUSY_ADR, |
1607 | HW_ATL_MSM_REG_ACCESS_BUSY_MSK, |
1608 | HW_ATL_MSM_REG_ACCESS_BUSY_SHIFT); |
1609 | } |
1610 | |
1611 | void hw_atl_msm_reg_addr_for_indirect_addr_set(struct aq_hw_s *aq_hw, |
1612 | u32 reg_addr_for_indirect_addr) |
1613 | { |
1614 | aq_hw_write_reg_bit(aq_hw, HW_ATL_MSM_REG_ADDR_ADR, |
1615 | HW_ATL_MSM_REG_ADDR_MSK, |
1616 | HW_ATL_MSM_REG_ADDR_SHIFT, |
1617 | val: reg_addr_for_indirect_addr); |
1618 | } |
1619 | |
1620 | void hw_atl_msm_reg_rd_strobe_set(struct aq_hw_s *aq_hw, u32 reg_rd_strobe) |
1621 | { |
1622 | aq_hw_write_reg_bit(aq_hw, HW_ATL_MSM_REG_RD_STROBE_ADR, |
1623 | HW_ATL_MSM_REG_RD_STROBE_MSK, |
1624 | HW_ATL_MSM_REG_RD_STROBE_SHIFT, |
1625 | val: reg_rd_strobe); |
1626 | } |
1627 | |
1628 | u32 hw_atl_msm_reg_rd_data_get(struct aq_hw_s *aq_hw) |
1629 | { |
1630 | return aq_hw_read_reg(hw: aq_hw, HW_ATL_MSM_REG_RD_DATA_ADR); |
1631 | } |
1632 | |
1633 | void hw_atl_msm_reg_wr_data_set(struct aq_hw_s *aq_hw, u32 reg_wr_data) |
1634 | { |
1635 | aq_hw_write_reg(hw: aq_hw, HW_ATL_MSM_REG_WR_DATA_ADR, value: reg_wr_data); |
1636 | } |
1637 | |
1638 | void hw_atl_msm_reg_wr_strobe_set(struct aq_hw_s *aq_hw, u32 reg_wr_strobe) |
1639 | { |
1640 | aq_hw_write_reg_bit(aq_hw, HW_ATL_MSM_REG_WR_STROBE_ADR, |
1641 | HW_ATL_MSM_REG_WR_STROBE_MSK, |
1642 | HW_ATL_MSM_REG_WR_STROBE_SHIFT, |
1643 | val: reg_wr_strobe); |
1644 | } |
1645 | |
1646 | /* pci */ |
1647 | void hw_atl_pci_pci_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 pci_reg_res_dis) |
1648 | { |
1649 | aq_hw_write_reg_bit(aq_hw, HW_ATL_PCI_REG_RES_DSBL_ADR, |
1650 | HW_ATL_PCI_REG_RES_DSBL_MSK, |
1651 | HW_ATL_PCI_REG_RES_DSBL_SHIFT, |
1652 | val: pci_reg_res_dis); |
1653 | } |
1654 | |
1655 | void hw_atl_reg_glb_cpu_scratch_scp_set(struct aq_hw_s *aq_hw, |
1656 | u32 glb_cpu_scratch_scp, |
1657 | u32 scratch_scp) |
1658 | { |
1659 | aq_hw_write_reg(hw: aq_hw, HW_ATL_GLB_CPU_SCRATCH_SCP_ADR(scratch_scp), |
1660 | value: glb_cpu_scratch_scp); |
1661 | } |
1662 | |
1663 | void hw_atl_pcs_ptp_clock_read_enable(struct aq_hw_s *aq_hw, |
1664 | u32 ptp_clock_read_enable) |
1665 | { |
1666 | aq_hw_write_reg_bit(aq_hw, HW_ATL_PCS_PTP_CLOCK_READ_ENABLE_ADR, |
1667 | HW_ATL_PCS_PTP_CLOCK_READ_ENABLE_MSK, |
1668 | HW_ATL_PCS_PTP_CLOCK_READ_ENABLE_SHIFT, |
1669 | val: ptp_clock_read_enable); |
1670 | } |
1671 | |
1672 | u32 hw_atl_pcs_ptp_clock_get(struct aq_hw_s *aq_hw, u32 index) |
1673 | { |
1674 | return aq_hw_read_reg(hw: aq_hw, HW_ATL_PCS_PTP_TS_VAL_ADDR(index)); |
1675 | } |
1676 | |
1677 | void hw_atl_mcp_up_force_intr_set(struct aq_hw_s *aq_hw, u32 up_force_intr) |
1678 | { |
1679 | aq_hw_write_reg_bit(aq_hw, HW_ATL_MCP_UP_FORCE_INTERRUPT_ADR, |
1680 | HW_ATL_MCP_UP_FORCE_INTERRUPT_MSK, |
1681 | HW_ATL_MCP_UP_FORCE_INTERRUPT_SHIFT, |
1682 | val: up_force_intr); |
1683 | } |
1684 | |
1685 | void hw_atl_rpfl3l4_ipv4_dest_addr_clear(struct aq_hw_s *aq_hw, u8 location) |
1686 | { |
1687 | aq_hw_write_reg(hw: aq_hw, HW_ATL_RPF_L3_DSTA_ADR(location), value: 0U); |
1688 | } |
1689 | |
1690 | void hw_atl_rpfl3l4_ipv4_src_addr_clear(struct aq_hw_s *aq_hw, u8 location) |
1691 | { |
1692 | aq_hw_write_reg(hw: aq_hw, HW_ATL_RPF_L3_SRCA_ADR(location), value: 0U); |
1693 | } |
1694 | |
1695 | void hw_atl_rpfl3l4_cmd_clear(struct aq_hw_s *aq_hw, u8 location) |
1696 | { |
1697 | aq_hw_write_reg(hw: aq_hw, HW_ATL_RPF_L3_REG_CTRL_ADR(location), value: 0U); |
1698 | } |
1699 | |
1700 | void hw_atl_rpfl3l4_ipv6_dest_addr_clear(struct aq_hw_s *aq_hw, u8 location) |
1701 | { |
1702 | int i; |
1703 | |
1704 | for (i = 0; i < 4; ++i) |
1705 | aq_hw_write_reg(hw: aq_hw, |
1706 | HW_ATL_RPF_L3_DSTA_ADR(location + i), |
1707 | value: 0U); |
1708 | } |
1709 | |
1710 | void hw_atl_rpfl3l4_ipv6_src_addr_clear(struct aq_hw_s *aq_hw, u8 location) |
1711 | { |
1712 | int i; |
1713 | |
1714 | for (i = 0; i < 4; ++i) |
1715 | aq_hw_write_reg(hw: aq_hw, |
1716 | HW_ATL_RPF_L3_SRCA_ADR(location + i), |
1717 | value: 0U); |
1718 | } |
1719 | |
1720 | void hw_atl_rpfl3l4_ipv4_dest_addr_set(struct aq_hw_s *aq_hw, u8 location, |
1721 | u32 ipv4_dest) |
1722 | { |
1723 | aq_hw_write_reg(hw: aq_hw, HW_ATL_RPF_L3_DSTA_ADR(location), |
1724 | value: ipv4_dest); |
1725 | } |
1726 | |
1727 | void hw_atl_rpfl3l4_ipv4_src_addr_set(struct aq_hw_s *aq_hw, u8 location, |
1728 | u32 ipv4_src) |
1729 | { |
1730 | aq_hw_write_reg(hw: aq_hw, |
1731 | HW_ATL_RPF_L3_SRCA_ADR(location), |
1732 | value: ipv4_src); |
1733 | } |
1734 | |
1735 | void hw_atl_rpfl3l4_cmd_set(struct aq_hw_s *aq_hw, u8 location, u32 cmd) |
1736 | { |
1737 | aq_hw_write_reg(hw: aq_hw, HW_ATL_RPF_L3_REG_CTRL_ADR(location), value: cmd); |
1738 | } |
1739 | |
1740 | void hw_atl_rpfl3l4_ipv6_src_addr_set(struct aq_hw_s *aq_hw, u8 location, |
1741 | u32 *ipv6_src) |
1742 | { |
1743 | int i; |
1744 | |
1745 | for (i = 0; i < 4; ++i) |
1746 | aq_hw_write_reg(hw: aq_hw, |
1747 | HW_ATL_RPF_L3_SRCA_ADR(location + i), |
1748 | value: ipv6_src[3 - i]); |
1749 | } |
1750 | |
1751 | void hw_atl_rpfl3l4_ipv6_dest_addr_set(struct aq_hw_s *aq_hw, u8 location, |
1752 | u32 *ipv6_dest) |
1753 | { |
1754 | int i; |
1755 | |
1756 | for (i = 0; i < 4; ++i) |
1757 | aq_hw_write_reg(hw: aq_hw, |
1758 | HW_ATL_RPF_L3_DSTA_ADR(location + i), |
1759 | value: ipv6_dest[3 - i]); |
1760 | } |
1761 | |
1762 | u32 hw_atl_sem_ram_get(struct aq_hw_s *self) |
1763 | { |
1764 | return hw_atl_reg_glb_cpu_sem_get(aq_hw: self, HW_ATL_FW_SM_RAM); |
1765 | } |
1766 | |
1767 | u32 hw_atl_sem_mdio_get(struct aq_hw_s *self) |
1768 | { |
1769 | return hw_atl_reg_glb_cpu_sem_get(aq_hw: self, HW_ATL_FW_SM_MDIO); |
1770 | } |
1771 | |
1772 | u32 hw_atl_sem_reset1_get(struct aq_hw_s *self) |
1773 | { |
1774 | return hw_atl_reg_glb_cpu_sem_get(aq_hw: self, HW_ATL_FW_SM_RESET1); |
1775 | } |
1776 | |
1777 | u32 hw_atl_sem_reset2_get(struct aq_hw_s *self) |
1778 | { |
1779 | return hw_atl_reg_glb_cpu_sem_get(aq_hw: self, HW_ATL_FW_SM_RESET2); |
1780 | } |
1781 | |
1782 | u32 hw_atl_scrpad_get(struct aq_hw_s *aq_hw, u32 scratch_scp) |
1783 | { |
1784 | return aq_hw_read_reg(hw: aq_hw, |
1785 | HW_ATL_GLB_CPU_SCRATCH_SCP_ADR(scratch_scp)); |
1786 | } |
1787 | |
1788 | u32 hw_atl_scrpad12_get(struct aq_hw_s *self) |
1789 | { |
1790 | return hw_atl_scrpad_get(aq_hw: self, scratch_scp: 0xB); |
1791 | } |
1792 | |
1793 | u32 hw_atl_scrpad25_get(struct aq_hw_s *self) |
1794 | { |
1795 | return hw_atl_scrpad_get(aq_hw: self, scratch_scp: 0x18); |
1796 | } |
1797 | |
1798 | void hw_atl_glb_mdio_iface1_set(struct aq_hw_s *aq_hw, u32 value) |
1799 | { |
1800 | aq_hw_write_reg(hw: aq_hw, HW_ATL_GLB_MDIO_IFACE_N_ADR(1), value); |
1801 | } |
1802 | |
1803 | u32 hw_atl_glb_mdio_iface1_get(struct aq_hw_s *aq_hw) |
1804 | { |
1805 | return aq_hw_read_reg(hw: aq_hw, HW_ATL_GLB_MDIO_IFACE_N_ADR(1)); |
1806 | } |
1807 | |
1808 | void hw_atl_glb_mdio_iface2_set(struct aq_hw_s *aq_hw, u32 value) |
1809 | { |
1810 | aq_hw_write_reg(hw: aq_hw, HW_ATL_GLB_MDIO_IFACE_N_ADR(2), value); |
1811 | } |
1812 | |
1813 | u32 hw_atl_glb_mdio_iface2_get(struct aq_hw_s *aq_hw) |
1814 | { |
1815 | return aq_hw_read_reg(hw: aq_hw, HW_ATL_GLB_MDIO_IFACE_N_ADR(2)); |
1816 | } |
1817 | |
1818 | void hw_atl_glb_mdio_iface3_set(struct aq_hw_s *aq_hw, u32 value) |
1819 | { |
1820 | aq_hw_write_reg(hw: aq_hw, HW_ATL_GLB_MDIO_IFACE_N_ADR(3), value); |
1821 | } |
1822 | |
1823 | u32 hw_atl_glb_mdio_iface3_get(struct aq_hw_s *aq_hw) |
1824 | { |
1825 | return aq_hw_read_reg(hw: aq_hw, HW_ATL_GLB_MDIO_IFACE_N_ADR(3)); |
1826 | } |
1827 | |
1828 | void hw_atl_glb_mdio_iface4_set(struct aq_hw_s *aq_hw, u32 value) |
1829 | { |
1830 | aq_hw_write_reg(hw: aq_hw, HW_ATL_GLB_MDIO_IFACE_N_ADR(4), value); |
1831 | } |
1832 | |
1833 | u32 hw_atl_glb_mdio_iface4_get(struct aq_hw_s *aq_hw) |
1834 | { |
1835 | return aq_hw_read_reg(hw: aq_hw, HW_ATL_GLB_MDIO_IFACE_N_ADR(4)); |
1836 | } |
1837 | |
1838 | void hw_atl_glb_mdio_iface5_set(struct aq_hw_s *aq_hw, u32 value) |
1839 | { |
1840 | aq_hw_write_reg(hw: aq_hw, HW_ATL_GLB_MDIO_IFACE_N_ADR(5), value); |
1841 | } |
1842 | |
1843 | u32 hw_atl_glb_mdio_iface5_get(struct aq_hw_s *aq_hw) |
1844 | { |
1845 | return aq_hw_read_reg(hw: aq_hw, HW_ATL_GLB_MDIO_IFACE_N_ADR(5)); |
1846 | } |
1847 | |
1848 | u32 hw_atl_mdio_busy_get(struct aq_hw_s *aq_hw) |
1849 | { |
1850 | return aq_hw_read_reg_bit(aq_hw, HW_ATL_MDIO_BUSY_ADR, |
1851 | HW_ATL_MDIO_BUSY_MSK, |
1852 | HW_ATL_MDIO_BUSY_SHIFT); |
1853 | } |
1854 | |