1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Copyright(c) 2007 Atheros Corporation. All rights reserved.
4 *
5 * Derived from Intel e1000 driver
6 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
7 */
8
9#ifndef _ATHL1E_HW_H_
10#define _ATHL1E_HW_H_
11
12#include <linux/types.h>
13#include <linux/mii.h>
14
15struct atl1e_adapter;
16struct atl1e_hw;
17
18/* function prototype */
19s32 atl1e_reset_hw(struct atl1e_hw *hw);
20s32 atl1e_read_mac_addr(struct atl1e_hw *hw);
21s32 atl1e_init_hw(struct atl1e_hw *hw);
22s32 atl1e_phy_commit(struct atl1e_hw *hw);
23s32 atl1e_get_speed_and_duplex(struct atl1e_hw *hw, u16 *speed, u16 *duplex);
24u32 atl1e_auto_get_fc(struct atl1e_adapter *adapter, u16 duplex);
25u32 atl1e_hash_mc_addr(struct atl1e_hw *hw, u8 *mc_addr);
26void atl1e_hash_set(struct atl1e_hw *hw, u32 hash_value);
27s32 atl1e_read_phy_reg(struct atl1e_hw *hw, u16 reg_addr, u16 *phy_data);
28s32 atl1e_write_phy_reg(struct atl1e_hw *hw, u32 reg_addr, u16 phy_data);
29s32 atl1e_validate_mdi_setting(struct atl1e_hw *hw);
30void atl1e_hw_set_mac_addr(struct atl1e_hw *hw);
31bool atl1e_read_eeprom(struct atl1e_hw *hw, u32 offset, u32 *p_value);
32bool atl1e_write_eeprom(struct atl1e_hw *hw, u32 offset, u32 value);
33s32 atl1e_phy_enter_power_saving(struct atl1e_hw *hw);
34s32 atl1e_phy_leave_power_saving(struct atl1e_hw *hw);
35s32 atl1e_phy_init(struct atl1e_hw *hw);
36int atl1e_check_eeprom_exist(struct atl1e_hw *hw);
37void atl1e_force_ps(struct atl1e_hw *hw);
38s32 atl1e_restart_autoneg(struct atl1e_hw *hw);
39
40/* register definition */
41#define REG_PM_CTRLSTAT 0x44
42
43#define REG_PCIE_CAP_LIST 0x58
44
45#define REG_DEVICE_CAP 0x5C
46#define DEVICE_CAP_MAX_PAYLOAD_MASK 0x7
47#define DEVICE_CAP_MAX_PAYLOAD_SHIFT 0
48
49#define REG_DEVICE_CTRL 0x60
50#define DEVICE_CTRL_MAX_PAYLOAD_MASK 0x7
51#define DEVICE_CTRL_MAX_PAYLOAD_SHIFT 5
52#define DEVICE_CTRL_MAX_RREQ_SZ_MASK 0x7
53#define DEVICE_CTRL_MAX_RREQ_SZ_SHIFT 12
54
55#define REG_VPD_CAP 0x6C
56#define VPD_CAP_ID_MASK 0xff
57#define VPD_CAP_ID_SHIFT 0
58#define VPD_CAP_NEXT_PTR_MASK 0xFF
59#define VPD_CAP_NEXT_PTR_SHIFT 8
60#define VPD_CAP_VPD_ADDR_MASK 0x7FFF
61#define VPD_CAP_VPD_ADDR_SHIFT 16
62#define VPD_CAP_VPD_FLAG 0x80000000
63
64#define REG_VPD_DATA 0x70
65
66#define REG_SPI_FLASH_CTRL 0x200
67#define SPI_FLASH_CTRL_STS_NON_RDY 0x1
68#define SPI_FLASH_CTRL_STS_WEN 0x2
69#define SPI_FLASH_CTRL_STS_WPEN 0x80
70#define SPI_FLASH_CTRL_DEV_STS_MASK 0xFF
71#define SPI_FLASH_CTRL_DEV_STS_SHIFT 0
72#define SPI_FLASH_CTRL_INS_MASK 0x7
73#define SPI_FLASH_CTRL_INS_SHIFT 8
74#define SPI_FLASH_CTRL_START 0x800
75#define SPI_FLASH_CTRL_EN_VPD 0x2000
76#define SPI_FLASH_CTRL_LDSTART 0x8000
77#define SPI_FLASH_CTRL_CS_HI_MASK 0x3
78#define SPI_FLASH_CTRL_CS_HI_SHIFT 16
79#define SPI_FLASH_CTRL_CS_HOLD_MASK 0x3
80#define SPI_FLASH_CTRL_CS_HOLD_SHIFT 18
81#define SPI_FLASH_CTRL_CLK_LO_MASK 0x3
82#define SPI_FLASH_CTRL_CLK_LO_SHIFT 20
83#define SPI_FLASH_CTRL_CLK_HI_MASK 0x3
84#define SPI_FLASH_CTRL_CLK_HI_SHIFT 22
85#define SPI_FLASH_CTRL_CS_SETUP_MASK 0x3
86#define SPI_FLASH_CTRL_CS_SETUP_SHIFT 24
87#define SPI_FLASH_CTRL_EROM_PGSZ_MASK 0x3
88#define SPI_FLASH_CTRL_EROM_PGSZ_SHIFT 26
89#define SPI_FLASH_CTRL_WAIT_READY 0x10000000
90
91#define REG_SPI_ADDR 0x204
92
93#define REG_SPI_DATA 0x208
94
95#define REG_SPI_FLASH_CONFIG 0x20C
96#define SPI_FLASH_CONFIG_LD_ADDR_MASK 0xFFFFFF
97#define SPI_FLASH_CONFIG_LD_ADDR_SHIFT 0
98#define SPI_FLASH_CONFIG_VPD_ADDR_MASK 0x3
99#define SPI_FLASH_CONFIG_VPD_ADDR_SHIFT 24
100#define SPI_FLASH_CONFIG_LD_EXIST 0x4000000
101
102
103#define REG_SPI_FLASH_OP_PROGRAM 0x210
104#define REG_SPI_FLASH_OP_SC_ERASE 0x211
105#define REG_SPI_FLASH_OP_CHIP_ERASE 0x212
106#define REG_SPI_FLASH_OP_RDID 0x213
107#define REG_SPI_FLASH_OP_WREN 0x214
108#define REG_SPI_FLASH_OP_RDSR 0x215
109#define REG_SPI_FLASH_OP_WRSR 0x216
110#define REG_SPI_FLASH_OP_READ 0x217
111
112#define REG_TWSI_CTRL 0x218
113#define TWSI_CTRL_LD_OFFSET_MASK 0xFF
114#define TWSI_CTRL_LD_OFFSET_SHIFT 0
115#define TWSI_CTRL_LD_SLV_ADDR_MASK 0x7
116#define TWSI_CTRL_LD_SLV_ADDR_SHIFT 8
117#define TWSI_CTRL_SW_LDSTART 0x800
118#define TWSI_CTRL_HW_LDSTART 0x1000
119#define TWSI_CTRL_SMB_SLV_ADDR_MASK 0x7F
120#define TWSI_CTRL_SMB_SLV_ADDR_SHIFT 15
121#define TWSI_CTRL_LD_EXIST 0x400000
122#define TWSI_CTRL_READ_FREQ_SEL_MASK 0x3
123#define TWSI_CTRL_READ_FREQ_SEL_SHIFT 23
124#define TWSI_CTRL_FREQ_SEL_100K 0
125#define TWSI_CTRL_FREQ_SEL_200K 1
126#define TWSI_CTRL_FREQ_SEL_300K 2
127#define TWSI_CTRL_FREQ_SEL_400K 3
128#define TWSI_CTRL_SMB_SLV_ADDR
129#define TWSI_CTRL_WRITE_FREQ_SEL_MASK 0x3
130#define TWSI_CTRL_WRITE_FREQ_SEL_SHIFT 24
131
132
133#define REG_PCIE_DEV_MISC_CTRL 0x21C
134#define PCIE_DEV_MISC_CTRL_EXT_PIPE 0x2
135#define PCIE_DEV_MISC_CTRL_RETRY_BUFDIS 0x1
136#define PCIE_DEV_MISC_CTRL_SPIROM_EXIST 0x4
137#define PCIE_DEV_MISC_CTRL_SERDES_ENDIAN 0x8
138#define PCIE_DEV_MISC_CTRL_SERDES_SEL_DIN 0x10
139
140#define REG_PCIE_PHYMISC 0x1000
141#define PCIE_PHYMISC_FORCE_RCV_DET 0x4
142
143#define REG_LTSSM_TEST_MODE 0x12FC
144#define LTSSM_TEST_MODE_DEF 0xE000
145
146/* Selene Master Control Register */
147#define REG_MASTER_CTRL 0x1400
148#define MASTER_CTRL_SOFT_RST 0x1
149#define MASTER_CTRL_MTIMER_EN 0x2
150#define MASTER_CTRL_ITIMER_EN 0x4
151#define MASTER_CTRL_MANUAL_INT 0x8
152#define MASTER_CTRL_ITIMER2_EN 0x20
153#define MASTER_CTRL_INT_RDCLR 0x40
154#define MASTER_CTRL_LED_MODE 0x200
155#define MASTER_CTRL_REV_NUM_SHIFT 16
156#define MASTER_CTRL_REV_NUM_MASK 0xff
157#define MASTER_CTRL_DEV_ID_SHIFT 24
158#define MASTER_CTRL_DEV_ID_MASK 0xff
159
160/* Timer Initial Value Register */
161#define REG_MANUAL_TIMER_INIT 0x1404
162
163
164/* IRQ ModeratorTimer Initial Value Register */
165#define REG_IRQ_MODU_TIMER_INIT 0x1408 /* w */
166#define REG_IRQ_MODU_TIMER2_INIT 0x140A /* w */
167
168
169#define REG_GPHY_CTRL 0x140C
170#define GPHY_CTRL_EXT_RESET 1
171#define GPHY_CTRL_PIPE_MOD 2
172#define GPHY_CTRL_TEST_MODE_MASK 3
173#define GPHY_CTRL_TEST_MODE_SHIFT 2
174#define GPHY_CTRL_BERT_START 0x10
175#define GPHY_CTRL_GATE_25M_EN 0x20
176#define GPHY_CTRL_LPW_EXIT 0x40
177#define GPHY_CTRL_PHY_IDDQ 0x80
178#define GPHY_CTRL_PHY_IDDQ_DIS 0x100
179#define GPHY_CTRL_PCLK_SEL_DIS 0x200
180#define GPHY_CTRL_HIB_EN 0x400
181#define GPHY_CTRL_HIB_PULSE 0x800
182#define GPHY_CTRL_SEL_ANA_RST 0x1000
183#define GPHY_CTRL_PHY_PLL_ON 0x2000
184#define GPHY_CTRL_PWDOWN_HW 0x4000
185#define GPHY_CTRL_DEFAULT (\
186 GPHY_CTRL_PHY_PLL_ON |\
187 GPHY_CTRL_SEL_ANA_RST |\
188 GPHY_CTRL_HIB_PULSE |\
189 GPHY_CTRL_HIB_EN)
190
191#define GPHY_CTRL_PW_WOL_DIS (\
192 GPHY_CTRL_PHY_PLL_ON |\
193 GPHY_CTRL_SEL_ANA_RST |\
194 GPHY_CTRL_HIB_PULSE |\
195 GPHY_CTRL_HIB_EN |\
196 GPHY_CTRL_PWDOWN_HW |\
197 GPHY_CTRL_PCLK_SEL_DIS |\
198 GPHY_CTRL_PHY_IDDQ)
199
200/* IRQ Anti-Lost Timer Initial Value Register */
201#define REG_CMBDISDMA_TIMER 0x140E
202
203
204/* Block IDLE Status Register */
205#define REG_IDLE_STATUS 0x1410
206#define IDLE_STATUS_RXMAC 1 /* 1: RXMAC state machine is in non-IDLE state. 0: RXMAC is idling */
207#define IDLE_STATUS_TXMAC 2 /* 1: TXMAC state machine is in non-IDLE state. 0: TXMAC is idling */
208#define IDLE_STATUS_RXQ 4 /* 1: RXQ state machine is in non-IDLE state. 0: RXQ is idling */
209#define IDLE_STATUS_TXQ 8 /* 1: TXQ state machine is in non-IDLE state. 0: TXQ is idling */
210#define IDLE_STATUS_DMAR 0x10 /* 1: DMAR state machine is in non-IDLE state. 0: DMAR is idling */
211#define IDLE_STATUS_DMAW 0x20 /* 1: DMAW state machine is in non-IDLE state. 0: DMAW is idling */
212#define IDLE_STATUS_SMB 0x40 /* 1: SMB state machine is in non-IDLE state. 0: SMB is idling */
213#define IDLE_STATUS_CMB 0x80 /* 1: CMB state machine is in non-IDLE state. 0: CMB is idling */
214
215/* MDIO Control Register */
216#define REG_MDIO_CTRL 0x1414
217#define MDIO_DATA_MASK 0xffff /* On MDIO write, the 16-bit control data to write to PHY MII management register */
218#define MDIO_DATA_SHIFT 0 /* On MDIO read, the 16-bit status data that was read from the PHY MII management register*/
219#define MDIO_REG_ADDR_MASK 0x1f /* MDIO register address */
220#define MDIO_REG_ADDR_SHIFT 16
221#define MDIO_RW 0x200000 /* 1: read, 0: write */
222#define MDIO_SUP_PREAMBLE 0x400000 /* Suppress preamble */
223#define MDIO_START 0x800000 /* Write 1 to initiate the MDIO master. And this bit is self cleared after one cycle*/
224#define MDIO_CLK_SEL_SHIFT 24
225#define MDIO_CLK_25_4 0
226#define MDIO_CLK_25_6 2
227#define MDIO_CLK_25_8 3
228#define MDIO_CLK_25_10 4
229#define MDIO_CLK_25_14 5
230#define MDIO_CLK_25_20 6
231#define MDIO_CLK_25_28 7
232#define MDIO_BUSY 0x8000000
233#define MDIO_AP_EN 0x10000000
234#define MDIO_WAIT_TIMES 10
235
236/* MII PHY Status Register */
237#define REG_PHY_STATUS 0x1418
238#define PHY_STATUS_100M 0x20000
239#define PHY_STATUS_EMI_CA 0x40000
240
241/* BIST Control and Status Register0 (for the Packet Memory) */
242#define REG_BIST0_CTRL 0x141c
243#define BIST0_NOW 0x1 /* 1: To trigger BIST0 logic. This bit stays high during the */
244/* BIST process and reset to zero when BIST is done */
245#define BIST0_SRAM_FAIL 0x2 /* 1: The SRAM failure is un-repairable because it has address */
246/* decoder failure or more than 1 cell stuck-to-x failure */
247#define BIST0_FUSE_FLAG 0x4 /* 1: Indicating one cell has been fixed */
248
249/* BIST Control and Status Register1(for the retry buffer of PCI Express) */
250#define REG_BIST1_CTRL 0x1420
251#define BIST1_NOW 0x1 /* 1: To trigger BIST0 logic. This bit stays high during the */
252/* BIST process and reset to zero when BIST is done */
253#define BIST1_SRAM_FAIL 0x2 /* 1: The SRAM failure is un-repairable because it has address */
254/* decoder failure or more than 1 cell stuck-to-x failure.*/
255#define BIST1_FUSE_FLAG 0x4
256
257/* SerDes Lock Detect Control and Status Register */
258#define REG_SERDES_LOCK 0x1424
259#define SERDES_LOCK_DETECT 1 /* 1: SerDes lock detected . This signal comes from Analog SerDes */
260#define SERDES_LOCK_DETECT_EN 2 /* 1: Enable SerDes Lock detect function */
261
262/* MAC Control Register */
263#define REG_MAC_CTRL 0x1480
264#define MAC_CTRL_TX_EN 1 /* 1: Transmit Enable */
265#define MAC_CTRL_RX_EN 2 /* 1: Receive Enable */
266#define MAC_CTRL_TX_FLOW 4 /* 1: Transmit Flow Control Enable */
267#define MAC_CTRL_RX_FLOW 8 /* 1: Receive Flow Control Enable */
268#define MAC_CTRL_LOOPBACK 0x10 /* 1: Loop back at G/MII Interface */
269#define MAC_CTRL_DUPLX 0x20 /* 1: Full-duplex mode 0: Half-duplex mode */
270#define MAC_CTRL_ADD_CRC 0x40 /* 1: Instruct MAC to attach CRC on all egress Ethernet frames */
271#define MAC_CTRL_PAD 0x80 /* 1: Instruct MAC to pad short frames to 60-bytes, and then attach CRC. This bit has higher priority over CRC_EN */
272#define MAC_CTRL_LENCHK 0x100 /* 1: Instruct MAC to check if length field matches the real packet length */
273#define MAC_CTRL_HUGE_EN 0x200 /* 1: receive Jumbo frame enable */
274#define MAC_CTRL_PRMLEN_SHIFT 10 /* Preamble length */
275#define MAC_CTRL_PRMLEN_MASK 0xf
276#define MAC_CTRL_RMV_VLAN 0x4000 /* 1: to remove VLAN Tag automatically from all receive packets */
277#define MAC_CTRL_PROMIS_EN 0x8000 /* 1: Promiscuous Mode Enable */
278#define MAC_CTRL_TX_PAUSE 0x10000 /* 1: transmit test pause */
279#define MAC_CTRL_SCNT 0x20000 /* 1: shortcut slot time counter */
280#define MAC_CTRL_SRST_TX 0x40000 /* 1: synchronized reset Transmit MAC module */
281#define MAC_CTRL_TX_SIMURST 0x80000 /* 1: transmit simulation reset */
282#define MAC_CTRL_SPEED_SHIFT 20 /* 10: gigabit 01:10M/100M */
283#define MAC_CTRL_SPEED_MASK 0x300000
284#define MAC_CTRL_SPEED_1000 2
285#define MAC_CTRL_SPEED_10_100 1
286#define MAC_CTRL_DBG_TX_BKPRESURE 0x400000 /* 1: transmit maximum backoff (half-duplex test bit) */
287#define MAC_CTRL_TX_HUGE 0x800000 /* 1: transmit huge enable */
288#define MAC_CTRL_RX_CHKSUM_EN 0x1000000 /* 1: RX checksum enable */
289#define MAC_CTRL_MC_ALL_EN 0x2000000 /* 1: upload all multicast frame without error to system */
290#define MAC_CTRL_BC_EN 0x4000000 /* 1: upload all broadcast frame without error to system */
291#define MAC_CTRL_DBG 0x8000000 /* 1: upload all received frame to system (Debug Mode) */
292
293/* MAC IPG/IFG Control Register */
294#define REG_MAC_IPG_IFG 0x1484
295#define MAC_IPG_IFG_IPGT_SHIFT 0 /* Desired back to back inter-packet gap. The default is 96-bit time */
296#define MAC_IPG_IFG_IPGT_MASK 0x7f
297#define MAC_IPG_IFG_MIFG_SHIFT 8 /* Minimum number of IFG to enforce in between RX frames */
298#define MAC_IPG_IFG_MIFG_MASK 0xff /* Frame gap below such IFP is dropped */
299#define MAC_IPG_IFG_IPGR1_SHIFT 16 /* 64bit Carrier-Sense window */
300#define MAC_IPG_IFG_IPGR1_MASK 0x7f
301#define MAC_IPG_IFG_IPGR2_SHIFT 24 /* 96-bit IPG window */
302#define MAC_IPG_IFG_IPGR2_MASK 0x7f
303
304/* MAC STATION ADDRESS */
305#define REG_MAC_STA_ADDR 0x1488
306
307/* Hash table for multicast address */
308#define REG_RX_HASH_TABLE 0x1490
309
310
311/* MAC Half-Duplex Control Register */
312#define REG_MAC_HALF_DUPLX_CTRL 0x1498
313#define MAC_HALF_DUPLX_CTRL_LCOL_SHIFT 0 /* Collision Window */
314#define MAC_HALF_DUPLX_CTRL_LCOL_MASK 0x3ff
315#define MAC_HALF_DUPLX_CTRL_RETRY_SHIFT 12 /* Retransmission maximum, afterwards the packet will be discarded */
316#define MAC_HALF_DUPLX_CTRL_RETRY_MASK 0xf
317#define MAC_HALF_DUPLX_CTRL_EXC_DEF_EN 0x10000 /* 1: Allow the transmission of a packet which has been excessively deferred */
318#define MAC_HALF_DUPLX_CTRL_NO_BACK_C 0x20000 /* 1: No back-off on collision, immediately start the retransmission */
319#define MAC_HALF_DUPLX_CTRL_NO_BACK_P 0x40000 /* 1: No back-off on backpressure, immediately start the transmission after back pressure */
320#define MAC_HALF_DUPLX_CTRL_ABEBE 0x80000 /* 1: Alternative Binary Exponential Back-off Enabled */
321#define MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT 20 /* Maximum binary exponential number */
322#define MAC_HALF_DUPLX_CTRL_ABEBT_MASK 0xf
323#define MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT 24 /* IPG to start JAM for collision based flow control in half-duplex */
324#define MAC_HALF_DUPLX_CTRL_JAMIPG_MASK 0xf /* mode. In unit of 8-bit time */
325
326/* Maximum Frame Length Control Register */
327#define REG_MTU 0x149c
328
329/* Wake-On-Lan control register */
330#define REG_WOL_CTRL 0x14a0
331#define WOL_PATTERN_EN 0x00000001
332#define WOL_PATTERN_PME_EN 0x00000002
333#define WOL_MAGIC_EN 0x00000004
334#define WOL_MAGIC_PME_EN 0x00000008
335#define WOL_LINK_CHG_EN 0x00000010
336#define WOL_LINK_CHG_PME_EN 0x00000020
337#define WOL_PATTERN_ST 0x00000100
338#define WOL_MAGIC_ST 0x00000200
339#define WOL_LINKCHG_ST 0x00000400
340#define WOL_CLK_SWITCH_EN 0x00008000
341#define WOL_PT0_EN 0x00010000
342#define WOL_PT1_EN 0x00020000
343#define WOL_PT2_EN 0x00040000
344#define WOL_PT3_EN 0x00080000
345#define WOL_PT4_EN 0x00100000
346#define WOL_PT5_EN 0x00200000
347#define WOL_PT6_EN 0x00400000
348/* WOL Length ( 2 DWORD ) */
349#define REG_WOL_PATTERN_LEN 0x14a4
350#define WOL_PT_LEN_MASK 0x7f
351#define WOL_PT0_LEN_SHIFT 0
352#define WOL_PT1_LEN_SHIFT 8
353#define WOL_PT2_LEN_SHIFT 16
354#define WOL_PT3_LEN_SHIFT 24
355#define WOL_PT4_LEN_SHIFT 0
356#define WOL_PT5_LEN_SHIFT 8
357#define WOL_PT6_LEN_SHIFT 16
358
359/* Internal SRAM Partition Register */
360#define REG_SRAM_TRD_ADDR 0x1518
361#define REG_SRAM_TRD_LEN 0x151C
362#define REG_SRAM_RXF_ADDR 0x1520
363#define REG_SRAM_RXF_LEN 0x1524
364#define REG_SRAM_TXF_ADDR 0x1528
365#define REG_SRAM_TXF_LEN 0x152C
366#define REG_SRAM_TCPH_ADDR 0x1530
367#define REG_SRAM_PKTH_ADDR 0x1532
368
369/* Load Ptr Register */
370#define REG_LOAD_PTR 0x1534 /* Software sets this bit after the initialization of the head and tail */
371
372/*
373 * addresses of all descriptors, as well as the following descriptor
374 * control register, which triggers each function block to load the head
375 * pointer to prepare for the operation. This bit is then self-cleared
376 * after one cycle.
377 */
378
379/* Descriptor Control register */
380#define REG_RXF3_BASE_ADDR_HI 0x153C
381#define REG_DESC_BASE_ADDR_HI 0x1540
382#define REG_RXF0_BASE_ADDR_HI 0x1540 /* share with DESC BASE ADDR HI */
383#define REG_HOST_RXF0_PAGE0_LO 0x1544
384#define REG_HOST_RXF0_PAGE1_LO 0x1548
385#define REG_TPD_BASE_ADDR_LO 0x154C
386#define REG_RXF1_BASE_ADDR_HI 0x1550
387#define REG_RXF2_BASE_ADDR_HI 0x1554
388#define REG_HOST_RXFPAGE_SIZE 0x1558
389#define REG_TPD_RING_SIZE 0x155C
390/* RSS about */
391#define REG_RSS_KEY0 0x14B0
392#define REG_RSS_KEY1 0x14B4
393#define REG_RSS_KEY2 0x14B8
394#define REG_RSS_KEY3 0x14BC
395#define REG_RSS_KEY4 0x14C0
396#define REG_RSS_KEY5 0x14C4
397#define REG_RSS_KEY6 0x14C8
398#define REG_RSS_KEY7 0x14CC
399#define REG_RSS_KEY8 0x14D0
400#define REG_RSS_KEY9 0x14D4
401#define REG_IDT_TABLE4 0x14E0
402#define REG_IDT_TABLE5 0x14E4
403#define REG_IDT_TABLE6 0x14E8
404#define REG_IDT_TABLE7 0x14EC
405#define REG_IDT_TABLE0 0x1560
406#define REG_IDT_TABLE1 0x1564
407#define REG_IDT_TABLE2 0x1568
408#define REG_IDT_TABLE3 0x156C
409#define REG_IDT_TABLE REG_IDT_TABLE0
410#define REG_RSS_HASH_VALUE 0x1570
411#define REG_RSS_HASH_FLAG 0x1574
412#define REG_BASE_CPU_NUMBER 0x157C
413
414
415/* TXQ Control Register */
416#define REG_TXQ_CTRL 0x1580
417#define TXQ_CTRL_NUM_TPD_BURST_MASK 0xF
418#define TXQ_CTRL_NUM_TPD_BURST_SHIFT 0
419#define TXQ_CTRL_EN 0x20 /* 1: Enable TXQ */
420#define TXQ_CTRL_ENH_MODE 0x40 /* Performance enhancement mode, in which up to two back-to-back DMA read commands might be dispatched. */
421#define TXQ_CTRL_TXF_BURST_NUM_SHIFT 16 /* Number of data byte to read in a cache-aligned burst. Each SRAM entry is 8-byte in length. */
422#define TXQ_CTRL_TXF_BURST_NUM_MASK 0xffff
423
424/* Jumbo packet Threshold for task offload */
425#define REG_TX_EARLY_TH 0x1584 /* Jumbo frame threshold in QWORD unit. Packet greater than */
426/* JUMBO_TASK_OFFLOAD_THRESHOLD will not be task offloaded. */
427#define TX_TX_EARLY_TH_MASK 0x7ff
428#define TX_TX_EARLY_TH_SHIFT 0
429
430
431/* RXQ Control Register */
432#define REG_RXQ_CTRL 0x15A0
433#define RXQ_CTRL_PBA_ALIGN_32 0 /* rx-packet alignment */
434#define RXQ_CTRL_PBA_ALIGN_64 1
435#define RXQ_CTRL_PBA_ALIGN_128 2
436#define RXQ_CTRL_PBA_ALIGN_256 3
437#define RXQ_CTRL_Q1_EN 0x10
438#define RXQ_CTRL_Q2_EN 0x20
439#define RXQ_CTRL_Q3_EN 0x40
440#define RXQ_CTRL_IPV6_XSUM_VERIFY_EN 0x80
441#define RXQ_CTRL_HASH_TLEN_SHIFT 8
442#define RXQ_CTRL_HASH_TLEN_MASK 0xFF
443#define RXQ_CTRL_HASH_TYPE_IPV4 0x10000
444#define RXQ_CTRL_HASH_TYPE_IPV4_TCP 0x20000
445#define RXQ_CTRL_HASH_TYPE_IPV6 0x40000
446#define RXQ_CTRL_HASH_TYPE_IPV6_TCP 0x80000
447#define RXQ_CTRL_RSS_MODE_DISABLE 0
448#define RXQ_CTRL_RSS_MODE_SQSINT 0x4000000
449#define RXQ_CTRL_RSS_MODE_MQUESINT 0x8000000
450#define RXQ_CTRL_RSS_MODE_MQUEMINT 0xC000000
451#define RXQ_CTRL_NIP_QUEUE_SEL_TBL 0x10000000
452#define RXQ_CTRL_HASH_ENABLE 0x20000000
453#define RXQ_CTRL_CUT_THRU_EN 0x40000000
454#define RXQ_CTRL_EN 0x80000000
455
456/* Rx jumbo packet threshold and rrd retirement timer */
457#define REG_RXQ_JMBOSZ_RRDTIM 0x15A4
458/*
459 * Jumbo packet threshold for non-VLAN packet, in QWORD (64-bit) unit.
460 * When the packet length greater than or equal to this value, RXQ
461 * shall start cut-through forwarding of the received packet.
462 */
463#define RXQ_JMBOSZ_TH_MASK 0x7ff
464#define RXQ_JMBOSZ_TH_SHIFT 0 /* RRD retirement timer. Decrement by 1 after every 512ns passes*/
465#define RXQ_JMBO_LKAH_MASK 0xf
466#define RXQ_JMBO_LKAH_SHIFT 11
467
468/* RXF flow control register */
469#define REG_RXQ_RXF_PAUSE_THRESH 0x15A8
470#define RXQ_RXF_PAUSE_TH_HI_SHIFT 0
471#define RXQ_RXF_PAUSE_TH_HI_MASK 0xfff
472#define RXQ_RXF_PAUSE_TH_LO_SHIFT 16
473#define RXQ_RXF_PAUSE_TH_LO_MASK 0xfff
474
475
476/* DMA Engine Control Register */
477#define REG_DMA_CTRL 0x15C0
478#define DMA_CTRL_DMAR_IN_ORDER 0x1
479#define DMA_CTRL_DMAR_ENH_ORDER 0x2
480#define DMA_CTRL_DMAR_OUT_ORDER 0x4
481#define DMA_CTRL_RCB_VALUE 0x8
482#define DMA_CTRL_DMAR_BURST_LEN_SHIFT 4
483#define DMA_CTRL_DMAR_BURST_LEN_MASK 7
484#define DMA_CTRL_DMAW_BURST_LEN_SHIFT 7
485#define DMA_CTRL_DMAW_BURST_LEN_MASK 7
486#define DMA_CTRL_DMAR_REQ_PRI 0x400
487#define DMA_CTRL_DMAR_DLY_CNT_MASK 0x1F
488#define DMA_CTRL_DMAR_DLY_CNT_SHIFT 11
489#define DMA_CTRL_DMAW_DLY_CNT_MASK 0xF
490#define DMA_CTRL_DMAW_DLY_CNT_SHIFT 16
491#define DMA_CTRL_TXCMB_EN 0x100000
492#define DMA_CTRL_RXCMB_EN 0x200000
493
494
495/* CMB/SMB Control Register */
496#define REG_SMB_STAT_TIMER 0x15C4
497#define REG_TRIG_RRD_THRESH 0x15CA
498#define REG_TRIG_TPD_THRESH 0x15C8
499#define REG_TRIG_TXTIMER 0x15CC
500#define REG_TRIG_RXTIMER 0x15CE
501
502/* HOST RXF Page 1,2,3 address */
503#define REG_HOST_RXF1_PAGE0_LO 0x15D0
504#define REG_HOST_RXF1_PAGE1_LO 0x15D4
505#define REG_HOST_RXF2_PAGE0_LO 0x15D8
506#define REG_HOST_RXF2_PAGE1_LO 0x15DC
507#define REG_HOST_RXF3_PAGE0_LO 0x15E0
508#define REG_HOST_RXF3_PAGE1_LO 0x15E4
509
510/* Mail box */
511#define REG_MB_RXF1_RADDR 0x15B4
512#define REG_MB_RXF2_RADDR 0x15B8
513#define REG_MB_RXF3_RADDR 0x15BC
514#define REG_MB_TPD_PROD_IDX 0x15F0
515
516/* RXF-Page 0-3 PageNo & Valid bit */
517#define REG_HOST_RXF0_PAGE0_VLD 0x15F4
518#define HOST_RXF_VALID 1
519#define HOST_RXF_PAGENO_SHIFT 1
520#define HOST_RXF_PAGENO_MASK 0x7F
521#define REG_HOST_RXF0_PAGE1_VLD 0x15F5
522#define REG_HOST_RXF1_PAGE0_VLD 0x15F6
523#define REG_HOST_RXF1_PAGE1_VLD 0x15F7
524#define REG_HOST_RXF2_PAGE0_VLD 0x15F8
525#define REG_HOST_RXF2_PAGE1_VLD 0x15F9
526#define REG_HOST_RXF3_PAGE0_VLD 0x15FA
527#define REG_HOST_RXF3_PAGE1_VLD 0x15FB
528
529/* Interrupt Status Register */
530#define REG_ISR 0x1600
531#define ISR_SMB 1
532#define ISR_TIMER 2 /* Interrupt when Timer is counted down to zero */
533/*
534 * Software manual interrupt, for debug. Set when SW_MAN_INT_EN is set
535 * in Table 51 Selene Master Control Register (Offset 0x1400).
536 */
537#define ISR_MANUAL 4
538#define ISR_HW_RXF_OV 8 /* RXF overflow interrupt */
539#define ISR_HOST_RXF0_OV 0x10
540#define ISR_HOST_RXF1_OV 0x20
541#define ISR_HOST_RXF2_OV 0x40
542#define ISR_HOST_RXF3_OV 0x80
543#define ISR_TXF_UN 0x100
544#define ISR_RX0_PAGE_FULL 0x200
545#define ISR_DMAR_TO_RST 0x400
546#define ISR_DMAW_TO_RST 0x800
547#define ISR_GPHY 0x1000
548#define ISR_TX_CREDIT 0x2000
549#define ISR_GPHY_LPW 0x4000 /* GPHY low power state interrupt */
550#define ISR_RX_PKT 0x10000 /* One packet received, triggered by RFD */
551#define ISR_TX_PKT 0x20000 /* One packet transmitted, triggered by TPD */
552#define ISR_TX_DMA 0x40000
553#define ISR_RX_PKT_1 0x80000
554#define ISR_RX_PKT_2 0x100000
555#define ISR_RX_PKT_3 0x200000
556#define ISR_MAC_RX 0x400000
557#define ISR_MAC_TX 0x800000
558#define ISR_UR_DETECTED 0x1000000
559#define ISR_FERR_DETECTED 0x2000000
560#define ISR_NFERR_DETECTED 0x4000000
561#define ISR_CERR_DETECTED 0x8000000
562#define ISR_PHY_LINKDOWN 0x10000000
563#define ISR_DIS_INT 0x80000000
564
565
566/* Interrupt Mask Register */
567#define REG_IMR 0x1604
568
569
570#define IMR_NORMAL_MASK (\
571 ISR_SMB |\
572 ISR_TXF_UN |\
573 ISR_HW_RXF_OV |\
574 ISR_HOST_RXF0_OV|\
575 ISR_MANUAL |\
576 ISR_GPHY |\
577 ISR_GPHY_LPW |\
578 ISR_DMAR_TO_RST |\
579 ISR_DMAW_TO_RST |\
580 ISR_PHY_LINKDOWN|\
581 ISR_RX_PKT |\
582 ISR_TX_PKT)
583
584#define ISR_TX_EVENT (ISR_TXF_UN | ISR_TX_PKT)
585#define ISR_RX_EVENT (ISR_HOST_RXF0_OV | ISR_HW_RXF_OV | ISR_RX_PKT)
586
587#define REG_MAC_RX_STATUS_BIN 0x1700
588#define REG_MAC_RX_STATUS_END 0x175c
589#define REG_MAC_TX_STATUS_BIN 0x1760
590#define REG_MAC_TX_STATUS_END 0x17c0
591
592/* Hardware Offset Register */
593#define REG_HOST_RXF0_PAGEOFF 0x1800
594#define REG_TPD_CONS_IDX 0x1804
595#define REG_HOST_RXF1_PAGEOFF 0x1808
596#define REG_HOST_RXF2_PAGEOFF 0x180C
597#define REG_HOST_RXF3_PAGEOFF 0x1810
598
599/* RXF-Page 0-3 Offset DMA Address */
600#define REG_HOST_RXF0_MB0_LO 0x1820
601#define REG_HOST_RXF0_MB1_LO 0x1824
602#define REG_HOST_RXF1_MB0_LO 0x1828
603#define REG_HOST_RXF1_MB1_LO 0x182C
604#define REG_HOST_RXF2_MB0_LO 0x1830
605#define REG_HOST_RXF2_MB1_LO 0x1834
606#define REG_HOST_RXF3_MB0_LO 0x1838
607#define REG_HOST_RXF3_MB1_LO 0x183C
608
609/* Tpd CMB DMA Address */
610#define REG_HOST_TX_CMB_LO 0x1840
611#define REG_HOST_SMB_ADDR_LO 0x1844
612
613/* DEBUG ADDR */
614#define REG_DEBUG_DATA0 0x1900
615#define REG_DEBUG_DATA1 0x1904
616
617/***************************** MII definition ***************************************/
618/* PHY Common Register */
619#define MII_AT001_PSCR 0x10
620#define MII_AT001_PSSR 0x11
621#define MII_INT_CTRL 0x12
622#define MII_INT_STATUS 0x13
623#define MII_SMARTSPEED 0x14
624#define MII_LBRERROR 0x18
625#define MII_RESV2 0x1a
626
627#define MII_DBG_ADDR 0x1D
628#define MII_DBG_DATA 0x1E
629
630/* Autoneg Advertisement Register */
631#define MII_AR_DEFAULT_CAP_MASK 0
632
633/* 1000BASE-T Control Register */
634#define MII_AT001_CR_1000T_SPEED_MASK \
635 (ADVERTISE_1000FULL | ADVERTISE_1000HALF)
636#define MII_AT001_CR_1000T_DEFAULT_CAP_MASK MII_AT001_CR_1000T_SPEED_MASK
637
638/* AT001 PHY Specific Control Register */
639#define MII_AT001_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */
640#define MII_AT001_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
641#define MII_AT001_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */
642#define MII_AT001_PSCR_MAC_POWERDOWN 0x0008
643#define MII_AT001_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low,
644 * 0=CLK125 toggling
645 */
646#define MII_AT001_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */
647/* Manual MDI configuration */
648#define MII_AT001_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */
649#define MII_AT001_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover,
650 * 100BASE-TX/10BASE-T:
651 * MDI Mode
652 */
653#define MII_AT001_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled
654 * all speeds.
655 */
656#define MII_AT001_PSCR_10BT_EXT_DIST_ENABLE 0x0080
657/* 1=Enable Extended 10BASE-T distance
658 * (Lower 10BASE-T RX Threshold)
659 * 0=Normal 10BASE-T RX Threshold */
660#define MII_AT001_PSCR_MII_5BIT_ENABLE 0x0100
661/* 1=5-Bit interface in 100BASE-TX
662 * 0=MII interface in 100BASE-TX */
663#define MII_AT001_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */
664#define MII_AT001_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */
665#define MII_AT001_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */
666#define MII_AT001_PSCR_POLARITY_REVERSAL_SHIFT 1
667#define MII_AT001_PSCR_AUTO_X_MODE_SHIFT 5
668#define MII_AT001_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7
669/* AT001 PHY Specific Status Register */
670#define MII_AT001_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
671#define MII_AT001_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */
672#define MII_AT001_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
673#define MII_AT001_PSSR_10MBS 0x0000 /* 00=10Mbs */
674#define MII_AT001_PSSR_100MBS 0x4000 /* 01=100Mbs */
675#define MII_AT001_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
676
677#endif /*_ATHL1E_HW_H_*/
678

source code of linux/drivers/net/ethernet/atheros/atl1e/atl1e_hw.h