| 1 | /********************************************************************** |
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| 2 | * Author: Cavium, Inc. |
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| 3 | * |
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| 4 | * Contact: support@cavium.com |
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| 5 | * Please include "LiquidIO" in the subject. |
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| 6 | * |
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| 7 | * Copyright (c) 2003-2016 Cavium, Inc. |
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| 8 | * |
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| 9 | * This file is free software; you can redistribute it and/or modify |
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| 10 | * it under the terms of the GNU General Public License, Version 2, as |
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| 11 | * published by the Free Software Foundation. |
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| 12 | * |
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| 13 | * This file is distributed in the hope that it will be useful, but |
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| 14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty |
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| 15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or |
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| 16 | * NONINFRINGEMENT. See the GNU General Public License for more details. |
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| 17 | ***********************************************************************/ |
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| 18 | /*! \file cn23xx_vf_regs.h |
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| 19 | * \brief Host Driver: Register Address and Register Mask values for |
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| 20 | * Octeon CN23XX vf functions. |
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| 21 | */ |
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| 22 | |
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| 23 | #ifndef __CN23XX_VF_REGS_H__ |
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| 24 | #define __CN23XX_VF_REGS_H__ |
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| 25 | |
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| 26 | #define CN23XX_CONFIG_XPANSION_BAR 0x38 |
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| 27 | |
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| 28 | #define CN23XX_CONFIG_PCIE_CAP 0x70 |
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| 29 | #define CN23XX_CONFIG_PCIE_DEVCAP 0x74 |
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| 30 | #define CN23XX_CONFIG_PCIE_DEVCTL 0x78 |
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| 31 | #define CN23XX_CONFIG_PCIE_LINKCAP 0x7C |
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| 32 | #define CN23XX_CONFIG_PCIE_LINKCTL 0x80 |
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| 33 | #define CN23XX_CONFIG_PCIE_SLOTCAP 0x84 |
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| 34 | #define CN23XX_CONFIG_PCIE_SLOTCTL 0x88 |
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| 35 | |
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| 36 | #define CN23XX_CONFIG_PCIE_FLTMSK 0x720 |
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| 37 | |
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| 38 | /* The input jabber is used to determine the TSO max size. |
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| 39 | * Due to H/W limitation, this needs to be reduced to 60000 |
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| 40 | * in order to use H/W TSO and avoid the WQE malformation |
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| 41 | * PKO_BUG_24989_WQE_LEN |
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| 42 | */ |
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| 43 | #define CN23XX_DEFAULT_INPUT_JABBER 0xEA60 /*60000*/ |
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| 44 | |
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| 45 | /* ############## BAR0 Registers ################ */ |
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| 46 | |
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| 47 | /* Each Input Queue register is at a 16-byte Offset in BAR0 */ |
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| 48 | #define CN23XX_VF_IQ_OFFSET 0x20000 |
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| 49 | |
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| 50 | /*###################### REQUEST QUEUE #########################*/ |
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| 51 | |
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| 52 | /* 64 registers for Input Queue Instr Count - SLI_PKT_IN_DONE0_CNTS */ |
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| 53 | #define CN23XX_VF_SLI_IQ_INSTR_COUNT_START64 0x10040 |
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| 54 | |
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| 55 | /* 64 registers for Input Queues Start Addr - SLI_PKT0_INSTR_BADDR */ |
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| 56 | #define CN23XX_VF_SLI_IQ_BASE_ADDR_START64 0x10010 |
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| 57 | |
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| 58 | /* 64 registers for Input Doorbell - SLI_PKT0_INSTR_BAOFF_DBELL */ |
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| 59 | #define CN23XX_VF_SLI_IQ_DOORBELL_START 0x10020 |
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| 60 | |
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| 61 | /* 64 registers for Input Queue size - SLI_PKT0_INSTR_FIFO_RSIZE */ |
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| 62 | #define CN23XX_VF_SLI_IQ_SIZE_START 0x10030 |
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| 63 | |
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| 64 | /* 64 registers (64-bit) - ES, RO, NS, Arbitration for Input Queue Data & |
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| 65 | * gather list fetches. SLI_PKT(0..63)_INPUT_CONTROL. |
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| 66 | */ |
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| 67 | #define CN23XX_VF_SLI_IQ_PKT_CONTROL_START64 0x10000 |
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| 68 | |
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| 69 | /*------- Request Queue Macros ---------*/ |
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| 70 | #define CN23XX_VF_SLI_IQ_PKT_CONTROL64(iq) \ |
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| 71 | (CN23XX_VF_SLI_IQ_PKT_CONTROL_START64 + ((iq) * CN23XX_VF_IQ_OFFSET)) |
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| 72 | |
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| 73 | #define CN23XX_VF_SLI_IQ_BASE_ADDR64(iq) \ |
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| 74 | (CN23XX_VF_SLI_IQ_BASE_ADDR_START64 + ((iq) * CN23XX_VF_IQ_OFFSET)) |
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| 75 | |
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| 76 | #define CN23XX_VF_SLI_IQ_SIZE(iq) \ |
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| 77 | (CN23XX_VF_SLI_IQ_SIZE_START + ((iq) * CN23XX_VF_IQ_OFFSET)) |
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| 78 | |
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| 79 | #define CN23XX_VF_SLI_IQ_DOORBELL(iq) \ |
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| 80 | (CN23XX_VF_SLI_IQ_DOORBELL_START + ((iq) * CN23XX_VF_IQ_OFFSET)) |
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| 81 | |
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| 82 | #define CN23XX_VF_SLI_IQ_INSTR_COUNT64(iq) \ |
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| 83 | (CN23XX_VF_SLI_IQ_INSTR_COUNT_START64 + ((iq) * CN23XX_VF_IQ_OFFSET)) |
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| 84 | |
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| 85 | /*------------------ Masks ----------------*/ |
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| 86 | #define CN23XX_PKT_INPUT_CTL_VF_NUM BIT_ULL(32) |
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| 87 | #define CN23XX_PKT_INPUT_CTL_MAC_NUM BIT(29) |
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| 88 | /* Number of instructions to be read in one MAC read request. |
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| 89 | * setting to Max value(4) |
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| 90 | */ |
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| 91 | #define CN23XX_PKT_INPUT_CTL_RDSIZE (3 << 25) |
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| 92 | #define CN23XX_PKT_INPUT_CTL_IS_64B BIT(24) |
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| 93 | #define CN23XX_PKT_INPUT_CTL_RST BIT(23) |
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| 94 | #define CN23XX_PKT_INPUT_CTL_QUIET BIT(28) |
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| 95 | #define CN23XX_PKT_INPUT_CTL_RING_ENB BIT(22) |
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| 96 | #define CN23XX_PKT_INPUT_CTL_DATA_NS BIT(8) |
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| 97 | #define CN23XX_PKT_INPUT_CTL_DATA_ES_64B_SWAP BIT(6) |
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| 98 | #define CN23XX_PKT_INPUT_CTL_DATA_RO BIT(5) |
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| 99 | #define CN23XX_PKT_INPUT_CTL_USE_CSR BIT(4) |
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| 100 | #define CN23XX_PKT_INPUT_CTL_GATHER_NS BIT(3) |
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| 101 | #define CN23XX_PKT_INPUT_CTL_GATHER_ES_64B_SWAP (2) |
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| 102 | #define CN23XX_PKT_INPUT_CTL_GATHER_RO (1) |
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| 103 | |
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| 104 | /** Rings per Virtual Function [RO] **/ |
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| 105 | #define CN23XX_PKT_INPUT_CTL_RPVF_MASK (0x3F) |
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| 106 | #define CN23XX_PKT_INPUT_CTL_RPVF_POS (48) |
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| 107 | /* These bits[47:44][RO] give the Physical function number info within the MAC*/ |
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| 108 | #define CN23XX_PKT_INPUT_CTL_PF_NUM_MASK (0x7) |
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| 109 | #define CN23XX_PKT_INPUT_CTL_PF_NUM_POS (45) |
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| 110 | /** These bits[43:32][RO] give the virtual function number info within the PF*/ |
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| 111 | #define CN23XX_PKT_INPUT_CTL_VF_NUM_MASK (0x1FFF) |
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| 112 | #define CN23XX_PKT_INPUT_CTL_VF_NUM_POS (32) |
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| 113 | #define CN23XX_PKT_INPUT_CTL_MAC_NUM_MASK (0x3) |
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| 114 | #define CN23XX_PKT_INPUT_CTL_MAC_NUM_POS (29) |
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| 115 | #define CN23XX_PKT_IN_DONE_WMARK_MASK (0xFFFFULL) |
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| 116 | #define CN23XX_PKT_IN_DONE_WMARK_BIT_POS (32) |
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| 117 | #define CN23XX_PKT_IN_DONE_CNT_MASK (0x00000000FFFFFFFFULL) |
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| 118 | |
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| 119 | #ifdef __LITTLE_ENDIAN_BITFIELD |
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| 120 | #define CN23XX_PKT_INPUT_CTL_MASK \ |
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| 121 | (CN23XX_PKT_INPUT_CTL_RDSIZE \ |
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| 122 | | CN23XX_PKT_INPUT_CTL_DATA_ES_64B_SWAP \ |
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| 123 | | CN23XX_PKT_INPUT_CTL_USE_CSR) |
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| 124 | #else |
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| 125 | #define CN23XX_PKT_INPUT_CTL_MASK \ |
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| 126 | (CN23XX_PKT_INPUT_CTL_RDSIZE \ |
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| 127 | | CN23XX_PKT_INPUT_CTL_DATA_ES_64B_SWAP \ |
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| 128 | | CN23XX_PKT_INPUT_CTL_USE_CSR \ |
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| 129 | | CN23XX_PKT_INPUT_CTL_GATHER_ES_64B_SWAP) |
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| 130 | #endif |
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| 131 | |
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| 132 | /** Masks for SLI_PKT_IN_DONE(0..63)_CNTS Register */ |
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| 133 | #define CN23XX_IN_DONE_CNTS_PI_INT BIT_ULL(62) |
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| 134 | #define CN23XX_IN_DONE_CNTS_CINT_ENB BIT_ULL(48) |
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| 135 | |
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| 136 | /*############################ OUTPUT QUEUE #########################*/ |
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| 137 | |
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| 138 | /* 64 registers for Output queue control - SLI_PKT(0..63)_OUTPUT_CONTROL */ |
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| 139 | #define CN23XX_VF_SLI_OQ_PKT_CONTROL_START 0x10050 |
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| 140 | |
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| 141 | /* 64 registers for Output queue buffer and info size - SLI_PKT0_OUT_SIZE */ |
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| 142 | #define CN23XX_VF_SLI_OQ0_BUFF_INFO_SIZE 0x10060 |
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| 143 | |
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| 144 | /* 64 registers for Output Queue Start Addr - SLI_PKT0_SLIST_BADDR */ |
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| 145 | #define CN23XX_VF_SLI_OQ_BASE_ADDR_START64 0x10070 |
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| 146 | |
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| 147 | /* 64 registers for Output Queue Packet Credits - SLI_PKT0_SLIST_BAOFF_DBELL */ |
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| 148 | #define CN23XX_VF_SLI_OQ_PKT_CREDITS_START 0x10080 |
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| 149 | |
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| 150 | /* 64 registers for Output Queue size - SLI_PKT0_SLIST_FIFO_RSIZE */ |
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| 151 | #define CN23XX_VF_SLI_OQ_SIZE_START 0x10090 |
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| 152 | |
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| 153 | /* 64 registers for Output Queue Packet Count - SLI_PKT0_CNTS */ |
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| 154 | #define CN23XX_VF_SLI_OQ_PKT_SENT_START 0x100B0 |
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| 155 | |
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| 156 | /* 64 registers for Output Queue INT Levels - SLI_PKT0_INT_LEVELS */ |
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| 157 | #define CN23XX_VF_SLI_OQ_PKT_INT_LEVELS_START64 0x100A0 |
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| 158 | |
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| 159 | /* Each Output Queue register is at a 16-byte Offset in BAR0 */ |
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| 160 | #define CN23XX_VF_OQ_OFFSET 0x20000 |
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| 161 | |
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| 162 | /*------- Output Queue Macros ---------*/ |
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| 163 | |
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| 164 | #define CN23XX_VF_SLI_OQ_PKT_CONTROL(oq) \ |
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| 165 | (CN23XX_VF_SLI_OQ_PKT_CONTROL_START + ((oq) * CN23XX_VF_OQ_OFFSET)) |
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| 166 | |
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| 167 | #define CN23XX_VF_SLI_OQ_BASE_ADDR64(oq) \ |
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| 168 | (CN23XX_VF_SLI_OQ_BASE_ADDR_START64 + ((oq) * CN23XX_VF_OQ_OFFSET)) |
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| 169 | |
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| 170 | #define CN23XX_VF_SLI_OQ_SIZE(oq) \ |
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| 171 | (CN23XX_VF_SLI_OQ_SIZE_START + ((oq) * CN23XX_VF_OQ_OFFSET)) |
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| 172 | |
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| 173 | #define CN23XX_VF_SLI_OQ_BUFF_INFO_SIZE(oq) \ |
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| 174 | (CN23XX_VF_SLI_OQ0_BUFF_INFO_SIZE + ((oq) * CN23XX_VF_OQ_OFFSET)) |
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| 175 | |
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| 176 | #define CN23XX_VF_SLI_OQ_PKTS_SENT(oq) \ |
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| 177 | (CN23XX_VF_SLI_OQ_PKT_SENT_START + ((oq) * CN23XX_VF_OQ_OFFSET)) |
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| 178 | |
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| 179 | #define CN23XX_VF_SLI_OQ_PKTS_CREDIT(oq) \ |
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| 180 | (CN23XX_VF_SLI_OQ_PKT_CREDITS_START + ((oq) * CN23XX_VF_OQ_OFFSET)) |
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| 181 | |
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| 182 | #define CN23XX_VF_SLI_OQ_PKT_INT_LEVELS(oq) \ |
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| 183 | (CN23XX_VF_SLI_OQ_PKT_INT_LEVELS_START64 + ((oq) * CN23XX_VF_OQ_OFFSET)) |
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| 184 | |
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| 185 | /* Macro's for accessing CNT and TIME separately from INT_LEVELS */ |
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| 186 | #define CN23XX_VF_SLI_OQ_PKT_INT_LEVELS_CNT(oq) \ |
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| 187 | (CN23XX_VF_SLI_OQ_PKT_INT_LEVELS_START64 + ((oq) * CN23XX_VF_OQ_OFFSET)) |
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| 188 | |
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| 189 | #define CN23XX_VF_SLI_OQ_PKT_INT_LEVELS_TIME(oq) \ |
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| 190 | (CN23XX_VF_SLI_OQ_PKT_INT_LEVELS_START64 + \ |
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| 191 | ((oq) * CN23XX_VF_OQ_OFFSET) + 4) |
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| 192 | |
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| 193 | /*------------------ Masks ----------------*/ |
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| 194 | #define CN23XX_PKT_OUTPUT_CTL_TENB BIT(13) |
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| 195 | #define CN23XX_PKT_OUTPUT_CTL_CENB BIT(12) |
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| 196 | #define CN23XX_PKT_OUTPUT_CTL_IPTR BIT(11) |
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| 197 | #define CN23XX_PKT_OUTPUT_CTL_ES BIT(9) |
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| 198 | #define CN23XX_PKT_OUTPUT_CTL_NSR BIT(8) |
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| 199 | #define CN23XX_PKT_OUTPUT_CTL_ROR BIT(7) |
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| 200 | #define CN23XX_PKT_OUTPUT_CTL_DPTR BIT(6) |
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| 201 | #define CN23XX_PKT_OUTPUT_CTL_BMODE BIT(5) |
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| 202 | #define CN23XX_PKT_OUTPUT_CTL_ES_P BIT(3) |
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| 203 | #define CN23XX_PKT_OUTPUT_CTL_NSR_P BIT(2) |
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| 204 | #define CN23XX_PKT_OUTPUT_CTL_ROR_P BIT(1) |
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| 205 | #define CN23XX_PKT_OUTPUT_CTL_RING_ENB BIT(0) |
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| 206 | |
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| 207 | /*######################### Mailbox Reg Macros ########################*/ |
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| 208 | #define CN23XX_VF_SLI_PKT_MBOX_INT_START 0x10210 |
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| 209 | #define CN23XX_SLI_PKT_PF_VF_MBOX_SIG_START 0x10200 |
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| 210 | |
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| 211 | #define CN23XX_SLI_MBOX_OFFSET 0x20000 |
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| 212 | #define CN23XX_SLI_MBOX_SIG_IDX_OFFSET 0x8 |
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| 213 | |
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| 214 | #define CN23XX_VF_SLI_PKT_MBOX_INT(q) \ |
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| 215 | (CN23XX_VF_SLI_PKT_MBOX_INT_START + ((q) * CN23XX_SLI_MBOX_OFFSET)) |
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| 216 | |
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| 217 | #define CN23XX_SLI_PKT_PF_VF_MBOX_SIG(q, idx) \ |
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| 218 | (CN23XX_SLI_PKT_PF_VF_MBOX_SIG_START + \ |
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| 219 | ((q) * CN23XX_SLI_MBOX_OFFSET + \ |
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| 220 | (idx) * CN23XX_SLI_MBOX_SIG_IDX_OFFSET)) |
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| 221 | |
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| 222 | /*######################## INTERRUPTS #########################*/ |
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| 223 | |
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| 224 | #define CN23XX_VF_SLI_INT_SUM_START 0x100D0 |
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| 225 | |
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| 226 | #define CN23XX_VF_SLI_INT_SUM(q) \ |
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| 227 | (CN23XX_VF_SLI_INT_SUM_START + ((q) * CN23XX_VF_IQ_OFFSET)) |
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| 228 | |
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| 229 | /*------------------ Interrupt Masks ----------------*/ |
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| 230 | |
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| 231 | #define CN23XX_INTR_PO_INT BIT_ULL(63) |
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| 232 | #define CN23XX_INTR_PI_INT BIT_ULL(62) |
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| 233 | #define CN23XX_INTR_MBOX_INT BIT_ULL(61) |
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| 234 | #define CN23XX_INTR_RESEND BIT_ULL(60) |
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| 235 | |
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| 236 | #define CN23XX_INTR_CINT_ENB BIT_ULL(48) |
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| 237 | #define CN23XX_INTR_MBOX_ENB BIT(0) |
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| 238 | |
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| 239 | /*############################ MIO #########################*/ |
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| 240 | #define CN23XX_MIO_PTP_CLOCK_CFG 0x0001070000000f00ULL |
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| 241 | #define CN23XX_MIO_PTP_CLOCK_LO 0x0001070000000f08ULL |
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| 242 | #define CN23XX_MIO_PTP_CLOCK_HI 0x0001070000000f10ULL |
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| 243 | #define CN23XX_MIO_PTP_CLOCK_COMP 0x0001070000000f18ULL |
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| 244 | #define CN23XX_MIO_PTP_TIMESTAMP 0x0001070000000f20ULL |
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| 245 | #define CN23XX_MIO_PTP_EVT_CNT 0x0001070000000f28ULL |
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| 246 | #define CN23XX_MIO_PTP_CKOUT_THRESH_LO 0x0001070000000f30ULL |
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| 247 | #define CN23XX_MIO_PTP_CKOUT_THRESH_HI 0x0001070000000f38ULL |
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| 248 | #define CN23XX_MIO_PTP_CKOUT_HI_INCR 0x0001070000000f40ULL |
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| 249 | #define CN23XX_MIO_PTP_CKOUT_LO_INCR 0x0001070000000f48ULL |
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| 250 | #define CN23XX_MIO_PTP_PPS_THRESH_LO 0x0001070000000f50ULL |
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| 251 | #define CN23XX_MIO_PTP_PPS_THRESH_HI 0x0001070000000f58ULL |
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| 252 | #define CN23XX_MIO_PTP_PPS_HI_INCR 0x0001070000000f60ULL |
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| 253 | #define CN23XX_MIO_PTP_PPS_LO_INCR 0x0001070000000f68ULL |
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| 254 | |
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| 255 | /*############################ RST #########################*/ |
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| 256 | #define CN23XX_RST_BOOT 0x0001180006001600ULL |
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| 257 | |
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| 258 | /*######################## MSIX TABLE #########################*/ |
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| 259 | |
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| 260 | #define CN23XX_MSIX_TABLE_ADDR_START 0x0 |
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| 261 | #define CN23XX_MSIX_TABLE_DATA_START 0x8 |
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| 262 | |
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| 263 | #define CN23XX_MSIX_TABLE_SIZE 0x10 |
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| 264 | #define CN23XX_MSIX_TABLE_ENTRIES 0x41 |
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| 265 | |
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| 266 | #define CN23XX_MSIX_ENTRY_VECTOR_CTL BIT_ULL(32) |
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| 267 | |
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| 268 | #define CN23XX_MSIX_TABLE_ADDR(idx) \ |
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| 269 | (CN23XX_MSIX_TABLE_ADDR_START + ((idx) * CN23XX_MSIX_TABLE_SIZE)) |
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| 270 | |
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| 271 | #define CN23XX_MSIX_TABLE_DATA(idx) \ |
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| 272 | (CN23XX_MSIX_TABLE_DATA_START + ((idx) * CN23XX_MSIX_TABLE_SIZE)) |
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| 273 | |
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| 274 | #endif |
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| 275 | |
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