| 1 | /********************************************************************** |
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| 2 | * Author: Cavium, Inc. |
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| 3 | * |
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| 4 | * Contact: support@cavium.com |
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| 5 | * Please include "LiquidIO" in the subject. |
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| 6 | * |
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| 7 | * Copyright (c) 2003-2016 Cavium, Inc. |
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| 8 | * |
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| 9 | * This file is free software; you can redistribute it and/or modify |
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| 10 | * it under the terms of the GNU General Public License, Version 2, as |
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| 11 | * published by the Free Software Foundation. |
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| 12 | * |
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| 13 | * This file is distributed in the hope that it will be useful, but |
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| 14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty |
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| 15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or |
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| 16 | * NONINFRINGEMENT. See the GNU General Public License for more details. |
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| 17 | ***********************************************************************/ |
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| 18 | /*! \file cn66xx_regs.h |
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| 19 | * \brief Host Driver: Register Address and Register Mask values for |
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| 20 | * Octeon CN66XX devices. |
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| 21 | */ |
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| 22 | |
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| 23 | #ifndef __CN66XX_REGS_H__ |
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| 24 | #define __CN66XX_REGS_H__ |
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| 25 | |
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| 26 | #define CN6XXX_XPANSION_BAR 0x30 |
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| 27 | |
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| 28 | #define CN6XXX_MSI_CAP 0x50 |
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| 29 | #define CN6XXX_MSI_ADDR_LO 0x54 |
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| 30 | #define CN6XXX_MSI_ADDR_HI 0x58 |
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| 31 | #define CN6XXX_MSI_DATA 0x5C |
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| 32 | |
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| 33 | #define CN6XXX_PCIE_CAP 0x70 |
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| 34 | #define CN6XXX_PCIE_DEVCAP 0x74 |
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| 35 | #define CN6XXX_PCIE_DEVCTL 0x78 |
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| 36 | #define CN6XXX_PCIE_LINKCAP 0x7C |
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| 37 | #define CN6XXX_PCIE_LINKCTL 0x80 |
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| 38 | #define CN6XXX_PCIE_SLOTCAP 0x84 |
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| 39 | #define CN6XXX_PCIE_SLOTCTL 0x88 |
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| 40 | |
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| 41 | #define CN6XXX_PCIE_ENH_CAP 0x100 |
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| 42 | #define CN6XXX_PCIE_UNCORR_ERR_STATUS 0x104 |
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| 43 | #define CN6XXX_PCIE_UNCORR_ERR_MASK 0x108 |
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| 44 | #define CN6XXX_PCIE_UNCORR_ERR 0x10C |
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| 45 | #define CN6XXX_PCIE_CORR_ERR_STATUS 0x110 |
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| 46 | #define CN6XXX_PCIE_CORR_ERR_MASK 0x114 |
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| 47 | #define CN6XXX_PCIE_ADV_ERR_CAP 0x118 |
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| 48 | |
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| 49 | #define CN6XXX_PCIE_ACK_REPLAY_TIMER 0x700 |
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| 50 | #define CN6XXX_PCIE_OTHER_MSG 0x704 |
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| 51 | #define CN6XXX_PCIE_PORT_FORCE_LINK 0x708 |
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| 52 | #define CN6XXX_PCIE_ACK_FREQ 0x70C |
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| 53 | #define CN6XXX_PCIE_PORT_LINK_CTL 0x710 |
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| 54 | #define CN6XXX_PCIE_LANE_SKEW 0x714 |
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| 55 | #define CN6XXX_PCIE_SYM_NUM 0x718 |
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| 56 | #define CN6XXX_PCIE_FLTMSK 0x720 |
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| 57 | |
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| 58 | /* ############## BAR0 Registers ################ */ |
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| 59 | |
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| 60 | #define CN6XXX_SLI_CTL_PORT0 0x0050 |
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| 61 | #define CN6XXX_SLI_CTL_PORT1 0x0060 |
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| 62 | |
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| 63 | #define CN6XXX_SLI_WINDOW_CTL 0x02E0 |
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| 64 | #define CN6XXX_SLI_DBG_DATA 0x0310 |
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| 65 | #define CN6XXX_SLI_SCRATCH1 0x03C0 |
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| 66 | #define CN6XXX_SLI_SCRATCH2 0x03D0 |
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| 67 | #define CN6XXX_SLI_CTL_STATUS 0x0570 |
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| 68 | |
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| 69 | #define CN6XXX_WIN_WR_ADDR_LO 0x0000 |
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| 70 | #define CN6XXX_WIN_WR_ADDR_HI 0x0004 |
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| 71 | #define CN6XXX_WIN_WR_ADDR64 CN6XXX_WIN_WR_ADDR_LO |
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| 72 | |
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| 73 | #define CN6XXX_WIN_RD_ADDR_LO 0x0010 |
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| 74 | #define CN6XXX_WIN_RD_ADDR_HI 0x0014 |
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| 75 | #define CN6XXX_WIN_RD_ADDR64 CN6XXX_WIN_RD_ADDR_LO |
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| 76 | |
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| 77 | #define CN6XXX_WIN_WR_DATA_LO 0x0020 |
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| 78 | #define CN6XXX_WIN_WR_DATA_HI 0x0024 |
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| 79 | #define CN6XXX_WIN_WR_DATA64 CN6XXX_WIN_WR_DATA_LO |
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| 80 | |
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| 81 | #define CN6XXX_WIN_RD_DATA_LO 0x0040 |
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| 82 | #define CN6XXX_WIN_RD_DATA_HI 0x0044 |
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| 83 | #define CN6XXX_WIN_RD_DATA64 CN6XXX_WIN_RD_DATA_LO |
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| 84 | |
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| 85 | #define CN6XXX_WIN_WR_MASK_LO 0x0030 |
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| 86 | #define CN6XXX_WIN_WR_MASK_HI 0x0034 |
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| 87 | #define CN6XXX_WIN_WR_MASK_REG CN6XXX_WIN_WR_MASK_LO |
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| 88 | |
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| 89 | /* 1 register (32-bit) to enable Input queues */ |
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| 90 | #define CN6XXX_SLI_PKT_INSTR_ENB 0x1000 |
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| 91 | |
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| 92 | /* 1 register (32-bit) to enable Output queues */ |
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| 93 | #define CN6XXX_SLI_PKT_OUT_ENB 0x1010 |
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| 94 | |
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| 95 | /* 1 register (32-bit) to determine whether Output queues are in reset. */ |
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| 96 | #define CN6XXX_SLI_PORT_IN_RST_OQ 0x11F0 |
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| 97 | |
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| 98 | /* 1 register (32-bit) to determine whether Input queues are in reset. */ |
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| 99 | #define CN6XXX_SLI_PORT_IN_RST_IQ 0x11F4 |
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| 100 | |
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| 101 | /*###################### REQUEST QUEUE #########################*/ |
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| 102 | |
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| 103 | /* 1 register (32-bit) - instr. size of each input queue. */ |
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| 104 | #define CN6XXX_SLI_PKT_INSTR_SIZE 0x1020 |
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| 105 | |
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| 106 | /* 32 registers for Input Queue Instr Count - SLI_PKT_IN_DONE0_CNTS */ |
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| 107 | #define CN6XXX_SLI_IQ_INSTR_COUNT_START 0x2000 |
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| 108 | |
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| 109 | /* 32 registers for Input Queue Start Addr - SLI_PKT0_INSTR_BADDR */ |
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| 110 | #define CN6XXX_SLI_IQ_BASE_ADDR_START64 0x2800 |
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| 111 | |
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| 112 | /* 32 registers for Input Doorbell - SLI_PKT0_INSTR_BAOFF_DBELL */ |
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| 113 | #define CN6XXX_SLI_IQ_DOORBELL_START 0x2C00 |
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| 114 | |
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| 115 | /* 32 registers for Input Queue size - SLI_PKT0_INSTR_FIFO_RSIZE */ |
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| 116 | #define CN6XXX_SLI_IQ_SIZE_START 0x3000 |
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| 117 | |
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| 118 | /* 32 registers for Instruction Header Options - SLI_PKT0_INSTR_HEADER */ |
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| 119 | #define CN6XXX_SLI_IQ_PKT_INSTR_HDR_START64 0x3400 |
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| 120 | |
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| 121 | /* 1 register (64-bit) - Back Pressure for each input queue - SLI_PKT0_IN_BP */ |
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| 122 | #define CN66XX_SLI_INPUT_BP_START64 0x3800 |
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| 123 | |
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| 124 | /* Each Input Queue register is at a 16-byte Offset in BAR0 */ |
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| 125 | #define CN6XXX_IQ_OFFSET 0x10 |
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| 126 | |
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| 127 | /* 1 register (32-bit) - ES, RO, NS, Arbitration for Input Queue Data & |
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| 128 | * gather list fetches. SLI_PKT_INPUT_CONTROL. |
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| 129 | */ |
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| 130 | #define CN6XXX_SLI_PKT_INPUT_CONTROL 0x1170 |
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| 131 | |
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| 132 | /* 1 register (64-bit) - Number of instructions to read at one time |
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| 133 | * - 2 bits for each input ring. SLI_PKT_INSTR_RD_SIZE. |
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| 134 | */ |
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| 135 | #define CN6XXX_SLI_PKT_INSTR_RD_SIZE 0x11A0 |
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| 136 | |
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| 137 | /* 1 register (64-bit) - Assign Input ring to MAC port |
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| 138 | * - 2 bits for each input ring. SLI_PKT_IN_PCIE_PORT. |
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| 139 | */ |
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| 140 | #define CN6XXX_SLI_IN_PCIE_PORT 0x11B0 |
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| 141 | |
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| 142 | /*------- Request Queue Macros ---------*/ |
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| 143 | #define CN6XXX_SLI_IQ_BASE_ADDR64(iq) \ |
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| 144 | (CN6XXX_SLI_IQ_BASE_ADDR_START64 + ((iq) * CN6XXX_IQ_OFFSET)) |
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| 145 | |
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| 146 | #define CN6XXX_SLI_IQ_SIZE(iq) \ |
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| 147 | (CN6XXX_SLI_IQ_SIZE_START + ((iq) * CN6XXX_IQ_OFFSET)) |
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| 148 | |
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| 149 | #define CN6XXX_SLI_IQ_PKT_INSTR_HDR64(iq) \ |
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| 150 | (CN6XXX_SLI_IQ_PKT_INSTR_HDR_START64 + ((iq) * CN6XXX_IQ_OFFSET)) |
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| 151 | |
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| 152 | #define CN6XXX_SLI_IQ_DOORBELL(iq) \ |
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| 153 | (CN6XXX_SLI_IQ_DOORBELL_START + ((iq) * CN6XXX_IQ_OFFSET)) |
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| 154 | |
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| 155 | #define CN6XXX_SLI_IQ_INSTR_COUNT(iq) \ |
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| 156 | (CN6XXX_SLI_IQ_INSTR_COUNT_START + ((iq) * CN6XXX_IQ_OFFSET)) |
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| 157 | |
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| 158 | #define CN66XX_SLI_IQ_BP64(iq) \ |
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| 159 | (CN66XX_SLI_INPUT_BP_START64 + ((iq) * CN6XXX_IQ_OFFSET)) |
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| 160 | |
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| 161 | /*------------------ Masks ----------------*/ |
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| 162 | #define CN6XXX_INPUT_CTL_ROUND_ROBIN_ARB BIT(22) |
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| 163 | #define CN6XXX_INPUT_CTL_DATA_NS BIT(8) |
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| 164 | #define CN6XXX_INPUT_CTL_DATA_ES_64B_SWAP BIT(6) |
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| 165 | #define CN6XXX_INPUT_CTL_DATA_RO BIT(5) |
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| 166 | #define CN6XXX_INPUT_CTL_USE_CSR BIT(4) |
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| 167 | #define CN6XXX_INPUT_CTL_GATHER_NS BIT(3) |
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| 168 | #define CN6XXX_INPUT_CTL_GATHER_ES_64B_SWAP BIT(2) |
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| 169 | #define CN6XXX_INPUT_CTL_GATHER_RO BIT(1) |
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| 170 | |
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| 171 | #ifdef __BIG_ENDIAN_BITFIELD |
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| 172 | #define CN6XXX_INPUT_CTL_MASK \ |
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| 173 | (CN6XXX_INPUT_CTL_DATA_ES_64B_SWAP \ |
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| 174 | | CN6XXX_INPUT_CTL_USE_CSR \ |
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| 175 | | CN6XXX_INPUT_CTL_GATHER_ES_64B_SWAP) |
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| 176 | #else |
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| 177 | #define CN6XXX_INPUT_CTL_MASK \ |
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| 178 | (CN6XXX_INPUT_CTL_DATA_ES_64B_SWAP \ |
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| 179 | | CN6XXX_INPUT_CTL_USE_CSR) |
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| 180 | #endif |
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| 181 | |
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| 182 | /*############################ OUTPUT QUEUE #########################*/ |
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| 183 | |
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| 184 | /* 32 registers for Output queue buffer and info size - SLI_PKT0_OUT_SIZE */ |
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| 185 | #define CN6XXX_SLI_OQ0_BUFF_INFO_SIZE 0x0C00 |
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| 186 | |
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| 187 | /* 32 registers for Output Queue Start Addr - SLI_PKT0_SLIST_BADDR */ |
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| 188 | #define CN6XXX_SLI_OQ_BASE_ADDR_START64 0x1400 |
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| 189 | |
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| 190 | /* 32 registers for Output Queue Packet Credits - SLI_PKT0_SLIST_BAOFF_DBELL */ |
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| 191 | #define CN6XXX_SLI_OQ_PKT_CREDITS_START 0x1800 |
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| 192 | |
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| 193 | /* 32 registers for Output Queue size - SLI_PKT0_SLIST_FIFO_RSIZE */ |
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| 194 | #define CN6XXX_SLI_OQ_SIZE_START 0x1C00 |
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| 195 | |
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| 196 | /* 32 registers for Output Queue Packet Count - SLI_PKT0_CNTS */ |
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| 197 | #define CN6XXX_SLI_OQ_PKT_SENT_START 0x2400 |
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| 198 | |
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| 199 | /* Each Output Queue register is at a 16-byte Offset in BAR0 */ |
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| 200 | #define CN6XXX_OQ_OFFSET 0x10 |
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| 201 | |
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| 202 | /* 1 register (32-bit) - 1 bit for each output queue |
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| 203 | * - Relaxed Ordering setting for reading Output Queues descriptors |
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| 204 | * - SLI_PKT_SLIST_ROR |
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| 205 | */ |
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| 206 | #define CN6XXX_SLI_PKT_SLIST_ROR 0x1030 |
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| 207 | |
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| 208 | /* 1 register (32-bit) - 1 bit for each output queue |
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| 209 | * - No Snoop mode for reading Output Queues descriptors |
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| 210 | * - SLI_PKT_SLIST_NS |
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| 211 | */ |
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| 212 | #define CN6XXX_SLI_PKT_SLIST_NS 0x1040 |
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| 213 | |
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| 214 | /* 1 register (64-bit) - 2 bits for each output queue |
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| 215 | * - Endian-Swap mode for reading Output Queue descriptors |
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| 216 | * - SLI_PKT_SLIST_ES |
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| 217 | */ |
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| 218 | #define CN6XXX_SLI_PKT_SLIST_ES64 0x1050 |
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| 219 | |
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| 220 | /* 1 register (32-bit) - 1 bit for each output queue |
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| 221 | * - InfoPtr mode for Output Queues. |
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| 222 | * - SLI_PKT_IPTR |
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| 223 | */ |
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| 224 | #define CN6XXX_SLI_PKT_IPTR 0x1070 |
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| 225 | |
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| 226 | /* 1 register (32-bit) - 1 bit for each output queue |
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| 227 | * - DPTR format selector for Output queues. |
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| 228 | * - SLI_PKT_DPADDR |
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| 229 | */ |
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| 230 | #define CN6XXX_SLI_PKT_DPADDR 0x1080 |
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| 231 | |
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| 232 | /* 1 register (32-bit) - 1 bit for each output queue |
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| 233 | * - Relaxed Ordering setting for reading Output Queues data |
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| 234 | * - SLI_PKT_DATA_OUT_ROR |
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| 235 | */ |
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| 236 | #define CN6XXX_SLI_PKT_DATA_OUT_ROR 0x1090 |
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| 237 | |
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| 238 | /* 1 register (32-bit) - 1 bit for each output queue |
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| 239 | * - No Snoop mode for reading Output Queues data |
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| 240 | * - SLI_PKT_DATA_OUT_NS |
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| 241 | */ |
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| 242 | #define CN6XXX_SLI_PKT_DATA_OUT_NS 0x10A0 |
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| 243 | |
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| 244 | /* 1 register (64-bit) - 2 bits for each output queue |
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| 245 | * - Endian-Swap mode for reading Output Queue data |
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| 246 | * - SLI_PKT_DATA_OUT_ES |
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| 247 | */ |
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| 248 | #define CN6XXX_SLI_PKT_DATA_OUT_ES64 0x10B0 |
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| 249 | |
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| 250 | /* 1 register (32-bit) - 1 bit for each output queue |
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| 251 | * - Controls whether SLI_PKTn_CNTS is incremented for bytes or for packets. |
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| 252 | * - SLI_PKT_OUT_BMODE |
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| 253 | */ |
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| 254 | #define CN6XXX_SLI_PKT_OUT_BMODE 0x10D0 |
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| 255 | |
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| 256 | /* 1 register (64-bit) - 2 bits for each output queue |
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| 257 | * - Assign PCIE port for Output queues |
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| 258 | * - SLI_PKT_PCIE_PORT. |
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| 259 | */ |
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| 260 | #define CN6XXX_SLI_PKT_PCIE_PORT64 0x10E0 |
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| 261 | |
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| 262 | /* 1 (64-bit) register for Output Queue Packet Count Interrupt Threshold |
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| 263 | * & Time Threshold. The same setting applies to all 32 queues. |
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| 264 | * The register is defined as a 64-bit registers, but we use the |
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| 265 | * 32-bit offsets to define distinct addresses. |
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| 266 | */ |
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| 267 | #define CN6XXX_SLI_OQ_INT_LEVEL_PKTS 0x1120 |
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| 268 | #define CN6XXX_SLI_OQ_INT_LEVEL_TIME 0x1124 |
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| 269 | |
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| 270 | /* 1 (64-bit register) for Output Queue backpressure across all rings. */ |
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| 271 | #define CN6XXX_SLI_OQ_WMARK 0x1180 |
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| 272 | |
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| 273 | /* 1 register to control output queue global backpressure & ring enable. */ |
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| 274 | #define CN6XXX_SLI_PKT_CTL 0x1220 |
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| 275 | |
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| 276 | /*------- Output Queue Macros ---------*/ |
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| 277 | #define CN6XXX_SLI_OQ_BASE_ADDR64(oq) \ |
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| 278 | (CN6XXX_SLI_OQ_BASE_ADDR_START64 + ((oq) * CN6XXX_OQ_OFFSET)) |
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| 279 | |
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| 280 | #define CN6XXX_SLI_OQ_SIZE(oq) \ |
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| 281 | (CN6XXX_SLI_OQ_SIZE_START + ((oq) * CN6XXX_OQ_OFFSET)) |
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| 282 | |
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| 283 | #define CN6XXX_SLI_OQ_BUFF_INFO_SIZE(oq) \ |
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| 284 | (CN6XXX_SLI_OQ0_BUFF_INFO_SIZE + ((oq) * CN6XXX_OQ_OFFSET)) |
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| 285 | |
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| 286 | #define CN6XXX_SLI_OQ_PKTS_SENT(oq) \ |
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| 287 | (CN6XXX_SLI_OQ_PKT_SENT_START + ((oq) * CN6XXX_OQ_OFFSET)) |
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| 288 | |
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| 289 | #define CN6XXX_SLI_OQ_PKTS_CREDIT(oq) \ |
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| 290 | (CN6XXX_SLI_OQ_PKT_CREDITS_START + ((oq) * CN6XXX_OQ_OFFSET)) |
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| 291 | |
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| 292 | /*######################### DMA Counters #########################*/ |
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| 293 | |
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| 294 | /* 2 registers (64-bit) - DMA Count - 1 for each DMA counter 0/1. */ |
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| 295 | #define CN6XXX_DMA_CNT_START 0x0400 |
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| 296 | |
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| 297 | /* 2 registers (64-bit) - DMA Timer 0/1, contains DMA timer values |
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| 298 | * SLI_DMA_0_TIM |
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| 299 | */ |
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| 300 | #define CN6XXX_DMA_TIM_START 0x0420 |
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| 301 | |
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| 302 | /* 2 registers (64-bit) - DMA count & Time Interrupt threshold - |
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| 303 | * SLI_DMA_0_INT_LEVEL |
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| 304 | */ |
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| 305 | #define CN6XXX_DMA_INT_LEVEL_START 0x03E0 |
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| 306 | |
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| 307 | /* Each DMA register is at a 16-byte Offset in BAR0 */ |
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| 308 | #define CN6XXX_DMA_OFFSET 0x10 |
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| 309 | |
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| 310 | /*---------- DMA Counter Macros ---------*/ |
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| 311 | #define CN6XXX_DMA_CNT(dq) \ |
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| 312 | (CN6XXX_DMA_CNT_START + ((dq) * CN6XXX_DMA_OFFSET)) |
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| 313 | |
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| 314 | #define CN6XXX_DMA_INT_LEVEL(dq) \ |
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| 315 | (CN6XXX_DMA_INT_LEVEL_START + ((dq) * CN6XXX_DMA_OFFSET)) |
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| 316 | |
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| 317 | #define CN6XXX_DMA_PKT_INT_LEVEL(dq) \ |
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| 318 | (CN6XXX_DMA_INT_LEVEL_START + ((dq) * CN6XXX_DMA_OFFSET)) |
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| 319 | |
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| 320 | #define CN6XXX_DMA_TIME_INT_LEVEL(dq) \ |
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| 321 | (CN6XXX_DMA_INT_LEVEL_START + 4 + ((dq) * CN6XXX_DMA_OFFSET)) |
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| 322 | |
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| 323 | #define CN6XXX_DMA_TIM(dq) \ |
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| 324 | (CN6XXX_DMA_TIM_START + ((dq) * CN6XXX_DMA_OFFSET)) |
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| 325 | |
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| 326 | /*######################## INTERRUPTS #########################*/ |
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| 327 | |
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| 328 | /* 1 register (64-bit) for Interrupt Summary */ |
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| 329 | #define CN6XXX_SLI_INT_SUM64 0x0330 |
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| 330 | |
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| 331 | /* 1 register (64-bit) for Interrupt Enable */ |
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| 332 | #define CN6XXX_SLI_INT_ENB64_PORT0 0x0340 |
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| 333 | #define CN6XXX_SLI_INT_ENB64_PORT1 0x0350 |
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| 334 | |
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| 335 | /* 1 register (32-bit) to enable Output Queue Packet/Byte Count Interrupt */ |
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| 336 | #define CN6XXX_SLI_PKT_CNT_INT_ENB 0x1150 |
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| 337 | |
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| 338 | /* 1 register (32-bit) to enable Output Queue Packet Timer Interrupt */ |
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| 339 | #define CN6XXX_SLI_PKT_TIME_INT_ENB 0x1160 |
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| 340 | |
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| 341 | /* 1 register (32-bit) to indicate which Output Queue reached pkt threshold */ |
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| 342 | #define CN6XXX_SLI_PKT_CNT_INT 0x1130 |
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| 343 | |
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| 344 | /* 1 register (32-bit) to indicate which Output Queue reached time threshold */ |
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| 345 | #define CN6XXX_SLI_PKT_TIME_INT 0x1140 |
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| 346 | |
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| 347 | /*------------------ Interrupt Masks ----------------*/ |
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| 348 | |
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| 349 | #define CN6XXX_INTR_RML_TIMEOUT_ERR BIT(1) |
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| 350 | #define CN6XXX_INTR_BAR0_RW_TIMEOUT_ERR BIT(2) |
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| 351 | #define CN6XXX_INTR_IO2BIG_ERR BIT(3) |
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| 352 | #define CN6XXX_INTR_PKT_COUNT BIT(4) |
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| 353 | #define CN6XXX_INTR_PKT_TIME BIT(5) |
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| 354 | #define CN6XXX_INTR_M0UPB0_ERR BIT(8) |
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| 355 | #define CN6XXX_INTR_M0UPWI_ERR BIT(9) |
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| 356 | #define CN6XXX_INTR_M0UNB0_ERR BIT(10) |
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| 357 | #define CN6XXX_INTR_M0UNWI_ERR BIT(11) |
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| 358 | #define CN6XXX_INTR_M1UPB0_ERR BIT(12) |
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| 359 | #define CN6XXX_INTR_M1UPWI_ERR BIT(13) |
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| 360 | #define CN6XXX_INTR_M1UNB0_ERR BIT(14) |
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| 361 | #define CN6XXX_INTR_M1UNWI_ERR BIT(15) |
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| 362 | #define CN6XXX_INTR_MIO_INT0 BIT(16) |
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| 363 | #define CN6XXX_INTR_MIO_INT1 BIT(17) |
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| 364 | #define CN6XXX_INTR_MAC_INT0 BIT(18) |
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| 365 | #define CN6XXX_INTR_MAC_INT1 BIT(19) |
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| 366 | |
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| 367 | #define CN6XXX_INTR_DMA0_FORCE BIT_ULL(32) |
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| 368 | #define CN6XXX_INTR_DMA1_FORCE BIT_ULL(33) |
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| 369 | #define CN6XXX_INTR_DMA0_COUNT BIT_ULL(34) |
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| 370 | #define CN6XXX_INTR_DMA1_COUNT BIT_ULL(35) |
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| 371 | #define CN6XXX_INTR_DMA0_TIME BIT_ULL(36) |
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| 372 | #define CN6XXX_INTR_DMA1_TIME BIT_ULL(37) |
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| 373 | #define CN6XXX_INTR_INSTR_DB_OF_ERR BIT_ULL(48) |
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| 374 | #define CN6XXX_INTR_SLIST_DB_OF_ERR BIT_ULL(49) |
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| 375 | #define CN6XXX_INTR_POUT_ERR BIT_ULL(50) |
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| 376 | #define CN6XXX_INTR_PIN_BP_ERR BIT_ULL(51) |
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| 377 | #define CN6XXX_INTR_PGL_ERR BIT_ULL(52) |
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| 378 | #define CN6XXX_INTR_PDI_ERR BIT_ULL(53) |
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| 379 | #define CN6XXX_INTR_POP_ERR BIT_ULL(54) |
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| 380 | #define CN6XXX_INTR_PINS_ERR BIT_ULL(55) |
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| 381 | #define CN6XXX_INTR_SPRT0_ERR BIT_ULL(56) |
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| 382 | #define CN6XXX_INTR_SPRT1_ERR BIT_ULL(57) |
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| 383 | #define CN6XXX_INTR_ILL_PAD_ERR BIT_ULL(60) |
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| 384 | |
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| 385 | #define CN6XXX_INTR_DMA0_DATA (CN6XXX_INTR_DMA0_TIME) |
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| 386 | |
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| 387 | #define CN6XXX_INTR_DMA1_DATA (CN6XXX_INTR_DMA1_TIME) |
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| 388 | |
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| 389 | #define CN6XXX_INTR_DMA_DATA \ |
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| 390 | (CN6XXX_INTR_DMA0_DATA | CN6XXX_INTR_DMA1_DATA) |
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| 391 | |
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| 392 | #define CN6XXX_INTR_PKT_DATA (CN6XXX_INTR_PKT_TIME | \ |
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| 393 | CN6XXX_INTR_PKT_COUNT) |
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| 394 | |
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| 395 | /* Sum of interrupts for all PCI-Express Data Interrupts */ |
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| 396 | #define CN6XXX_INTR_PCIE_DATA \ |
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| 397 | (CN6XXX_INTR_DMA_DATA | CN6XXX_INTR_PKT_DATA) |
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| 398 | |
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| 399 | #define CN6XXX_INTR_MIO \ |
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| 400 | (CN6XXX_INTR_MIO_INT0 | CN6XXX_INTR_MIO_INT1) |
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| 401 | |
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| 402 | #define CN6XXX_INTR_MAC \ |
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| 403 | (CN6XXX_INTR_MAC_INT0 | CN6XXX_INTR_MAC_INT1) |
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| 404 | |
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| 405 | /* Sum of interrupts for error events */ |
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| 406 | #define CN6XXX_INTR_ERR \ |
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| 407 | (CN6XXX_INTR_BAR0_RW_TIMEOUT_ERR \ |
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| 408 | | CN6XXX_INTR_IO2BIG_ERR \ |
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| 409 | | CN6XXX_INTR_M0UPB0_ERR \ |
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| 410 | | CN6XXX_INTR_M0UPWI_ERR \ |
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| 411 | | CN6XXX_INTR_M0UNB0_ERR \ |
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| 412 | | CN6XXX_INTR_M0UNWI_ERR \ |
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| 413 | | CN6XXX_INTR_M1UPB0_ERR \ |
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| 414 | | CN6XXX_INTR_M1UPWI_ERR \ |
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| 415 | | CN6XXX_INTR_M1UNB0_ERR \ |
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| 416 | | CN6XXX_INTR_M1UNWI_ERR \ |
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| 417 | | CN6XXX_INTR_INSTR_DB_OF_ERR \ |
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| 418 | | CN6XXX_INTR_SLIST_DB_OF_ERR \ |
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| 419 | | CN6XXX_INTR_POUT_ERR \ |
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| 420 | | CN6XXX_INTR_PIN_BP_ERR \ |
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| 421 | | CN6XXX_INTR_PGL_ERR \ |
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| 422 | | CN6XXX_INTR_PDI_ERR \ |
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| 423 | | CN6XXX_INTR_POP_ERR \ |
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| 424 | | CN6XXX_INTR_PINS_ERR \ |
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| 425 | | CN6XXX_INTR_SPRT0_ERR \ |
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| 426 | | CN6XXX_INTR_SPRT1_ERR \ |
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| 427 | | CN6XXX_INTR_ILL_PAD_ERR) |
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| 428 | |
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| 429 | /* Programmed Mask for Interrupt Sum */ |
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| 430 | #define CN6XXX_INTR_MASK \ |
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| 431 | (CN6XXX_INTR_PCIE_DATA \ |
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| 432 | | CN6XXX_INTR_DMA0_FORCE \ |
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| 433 | | CN6XXX_INTR_DMA1_FORCE \ |
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| 434 | | CN6XXX_INTR_MIO \ |
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| 435 | | CN6XXX_INTR_MAC \ |
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| 436 | | CN6XXX_INTR_ERR) |
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| 437 | |
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| 438 | #define CN6XXX_SLI_S2M_PORT0_CTL 0x3D80 |
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| 439 | #define CN6XXX_SLI_S2M_PORT1_CTL 0x3D90 |
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| 440 | #define CN6XXX_SLI_S2M_PORTX_CTL(port) \ |
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| 441 | (CN6XXX_SLI_S2M_PORT0_CTL + ((port) * 0x10)) |
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| 442 | |
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| 443 | #define CN6XXX_SLI_INT_ENB64(port) \ |
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| 444 | (CN6XXX_SLI_INT_ENB64_PORT0 + ((port) * 0x10)) |
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| 445 | |
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| 446 | #define CN6XXX_SLI_MAC_NUMBER 0x3E00 |
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| 447 | |
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| 448 | /* CN6XXX BAR1 Index registers. */ |
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| 449 | #define CN6XXX_PEM_BAR1_INDEX000 0x00011800C00000A8ULL |
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| 450 | #define CN6XXX_PEM_OFFSET 0x0000000001000000ULL |
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| 451 | |
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| 452 | #define CN6XXX_BAR1_INDEX_START CN6XXX_PEM_BAR1_INDEX000 |
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| 453 | #define CN6XXX_PCI_BAR1_OFFSET 0x8 |
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| 454 | |
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| 455 | #define CN6XXX_BAR1_REG(idx, port) \ |
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| 456 | (CN6XXX_BAR1_INDEX_START + ((port) * CN6XXX_PEM_OFFSET) + \ |
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| 457 | (CN6XXX_PCI_BAR1_OFFSET * (idx))) |
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| 458 | |
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| 459 | /*############################ DPI #########################*/ |
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| 460 | |
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| 461 | #define CN6XXX_DPI_CTL 0x0001df0000000040ULL |
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| 462 | |
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| 463 | #define CN6XXX_DPI_DMA_CONTROL 0x0001df0000000048ULL |
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| 464 | |
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| 465 | #define CN6XXX_DPI_REQ_GBL_ENB 0x0001df0000000050ULL |
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| 466 | |
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| 467 | #define CN6XXX_DPI_REQ_ERR_RSP 0x0001df0000000058ULL |
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| 468 | |
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| 469 | #define CN6XXX_DPI_REQ_ERR_RST 0x0001df0000000060ULL |
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| 470 | |
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| 471 | #define CN6XXX_DPI_DMA_ENG0_ENB 0x0001df0000000080ULL |
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| 472 | |
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| 473 | #define CN6XXX_DPI_DMA_ENG_ENB(q_no) \ |
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| 474 | (CN6XXX_DPI_DMA_ENG0_ENB + ((q_no) * 8)) |
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| 475 | |
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| 476 | #define CN6XXX_DPI_DMA_ENG0_BUF 0x0001df0000000880ULL |
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| 477 | |
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| 478 | #define CN6XXX_DPI_DMA_ENG_BUF(q_no) \ |
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| 479 | (CN6XXX_DPI_DMA_ENG0_BUF + ((q_no) * 8)) |
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| 480 | |
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| 481 | #define CN6XXX_DPI_SLI_PRT0_CFG 0x0001df0000000900ULL |
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| 482 | #define CN6XXX_DPI_SLI_PRT1_CFG 0x0001df0000000908ULL |
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| 483 | #define CN6XXX_DPI_SLI_PRTX_CFG(port) \ |
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| 484 | (CN6XXX_DPI_SLI_PRT0_CFG + ((port) * 0x10)) |
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| 485 | |
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| 486 | #define CN6XXX_DPI_DMA_COMMIT_MODE BIT_ULL(58) |
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| 487 | #define CN6XXX_DPI_DMA_PKT_HP BIT_ULL(57) |
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| 488 | #define CN6XXX_DPI_DMA_PKT_EN BIT_ULL(56) |
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| 489 | #define CN6XXX_DPI_DMA_O_ES BIT_ULL(15) |
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| 490 | #define CN6XXX_DPI_DMA_O_MODE BIT_ULL(14) |
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| 491 | |
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| 492 | #define CN6XXX_DPI_DMA_CTL_MASK \ |
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| 493 | (CN6XXX_DPI_DMA_COMMIT_MODE | \ |
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| 494 | CN6XXX_DPI_DMA_PKT_HP | \ |
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| 495 | CN6XXX_DPI_DMA_PKT_EN | \ |
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| 496 | CN6XXX_DPI_DMA_O_ES | \ |
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| 497 | CN6XXX_DPI_DMA_O_MODE) |
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| 498 | |
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| 499 | /*############################ CIU #########################*/ |
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| 500 | |
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| 501 | #define CN6XXX_CIU_SOFT_BIST 0x0001070000000738ULL |
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| 502 | #define CN6XXX_CIU_SOFT_RST 0x0001070000000740ULL |
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| 503 | |
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| 504 | /*############################ MIO #########################*/ |
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| 505 | #define CN6XXX_MIO_PTP_CLOCK_CFG 0x0001070000000f00ULL |
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| 506 | #define CN6XXX_MIO_PTP_CLOCK_LO 0x0001070000000f08ULL |
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| 507 | #define CN6XXX_MIO_PTP_CLOCK_HI 0x0001070000000f10ULL |
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| 508 | #define CN6XXX_MIO_PTP_CLOCK_COMP 0x0001070000000f18ULL |
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| 509 | #define CN6XXX_MIO_PTP_TIMESTAMP 0x0001070000000f20ULL |
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| 510 | #define CN6XXX_MIO_PTP_EVT_CNT 0x0001070000000f28ULL |
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| 511 | #define CN6XXX_MIO_PTP_CKOUT_THRESH_LO 0x0001070000000f30ULL |
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| 512 | #define CN6XXX_MIO_PTP_CKOUT_THRESH_HI 0x0001070000000f38ULL |
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| 513 | #define CN6XXX_MIO_PTP_CKOUT_HI_INCR 0x0001070000000f40ULL |
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| 514 | #define CN6XXX_MIO_PTP_CKOUT_LO_INCR 0x0001070000000f48ULL |
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| 515 | #define CN6XXX_MIO_PTP_PPS_THRESH_LO 0x0001070000000f50ULL |
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| 516 | #define CN6XXX_MIO_PTP_PPS_THRESH_HI 0x0001070000000f58ULL |
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| 517 | #define CN6XXX_MIO_PTP_PPS_HI_INCR 0x0001070000000f60ULL |
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| 518 | #define CN6XXX_MIO_PTP_PPS_LO_INCR 0x0001070000000f68ULL |
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| 519 | |
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| 520 | #define CN6XXX_MIO_QLM4_CFG 0x00011800000015B0ULL |
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| 521 | #define CN6XXX_MIO_RST_BOOT 0x0001180000001600ULL |
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| 522 | |
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| 523 | #define CN6XXX_MIO_QLM_CFG_MASK 0x7 |
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| 524 | |
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| 525 | /*############################ LMC #########################*/ |
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| 526 | |
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| 527 | #define CN6XXX_LMC0_RESET_CTL 0x0001180088000180ULL |
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| 528 | #define CN6XXX_LMC0_RESET_CTL_DDR3RST_MASK 0x0000000000000001ULL |
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| 529 | |
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| 530 | #endif |
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| 531 | |
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