| 1 | /********************************************************************** |
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| 2 | * Author: Cavium, Inc. |
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| 3 | * |
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| 4 | * Contact: support@cavium.com |
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| 5 | * Please include "LiquidIO" in the subject. |
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| 6 | * |
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| 7 | * Copyright (c) 2003-2016 Cavium, Inc. |
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| 8 | * |
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| 9 | * This file is free software; you can redistribute it and/or modify |
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| 10 | * it under the terms of the GNU General Public License, Version 2, as |
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| 11 | * published by the Free Software Foundation. |
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| 12 | * |
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| 13 | * This file is distributed in the hope that it will be useful, but |
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| 14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty |
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| 15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or |
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| 16 | * NONINFRINGEMENT. See the GNU General Public License for more |
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| 17 | * details. |
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| 18 | **********************************************************************/ |
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| 19 | |
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| 20 | /*! \file octeon_mem_ops.h |
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| 21 | * \brief Host Driver: Routines used to read/write Octeon memory. |
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| 22 | */ |
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| 23 | |
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| 24 | #ifndef __OCTEON_MEM_OPS_H__ |
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| 25 | #define __OCTEON_MEM_OPS_H__ |
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| 26 | |
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| 27 | /** Read a 64-bit value from a BAR1 mapped core memory address. |
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| 28 | * @param oct - pointer to the octeon device. |
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| 29 | * @param core_addr - the address to read from. |
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| 30 | * |
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| 31 | * The range_idx gives the BAR1 index register for the range of address |
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| 32 | * in which core_addr is mapped. |
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| 33 | * |
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| 34 | * @return 64-bit value read from Core memory |
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| 35 | */ |
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| 36 | u64 octeon_read_device_mem64(struct octeon_device *oct, u64 core_addr); |
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| 37 | |
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| 38 | /** Read a 32-bit value from a BAR1 mapped core memory address. |
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| 39 | * @param oct - pointer to the octeon device. |
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| 40 | * @param core_addr - the address to read from. |
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| 41 | * |
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| 42 | * @return 32-bit value read from Core memory |
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| 43 | */ |
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| 44 | u32 octeon_read_device_mem32(struct octeon_device *oct, u64 core_addr); |
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| 45 | |
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| 46 | /** Write a 32-bit value to a BAR1 mapped core memory address. |
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| 47 | * @param oct - pointer to the octeon device. |
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| 48 | * @param core_addr - the address to write to. |
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| 49 | * @param val - 32-bit value to write. |
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| 50 | */ |
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| 51 | void |
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| 52 | octeon_write_device_mem32(struct octeon_device *oct, |
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| 53 | u64 core_addr, |
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| 54 | u32 val); |
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| 55 | |
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| 56 | /** Read multiple bytes from Octeon memory. |
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| 57 | */ |
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| 58 | void |
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| 59 | octeon_pci_read_core_mem(struct octeon_device *oct, |
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| 60 | u64 coreaddr, |
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| 61 | u8 *buf, |
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| 62 | u32 len); |
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| 63 | |
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| 64 | /** Write multiple bytes into Octeon memory. |
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| 65 | */ |
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| 66 | void |
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| 67 | octeon_pci_write_core_mem(struct octeon_device *oct, |
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| 68 | u64 coreaddr, |
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| 69 | const u8 *buf, |
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| 70 | u32 len); |
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| 71 | |
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| 72 | #endif |
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| 73 | |
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