| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * Copyright (C) 2015 Cavium, Inc. |
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| 4 | */ |
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| 5 | |
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| 6 | #ifndef NIC_REG_H |
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| 7 | #define NIC_REG_H |
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| 8 | |
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| 9 | #define NIC_PF_REG_COUNT 29573 |
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| 10 | #define NIC_VF_REG_COUNT 249 |
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| 11 | |
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| 12 | /* Physical function register offsets */ |
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| 13 | #define NIC_PF_CFG (0x0000) |
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| 14 | #define NIC_PF_STATUS (0x0010) |
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| 15 | #define NIC_PF_INTR_TIMER_CFG (0x0030) |
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| 16 | #define NIC_PF_BIST_STATUS (0x0040) |
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| 17 | #define NIC_PF_SOFT_RESET (0x0050) |
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| 18 | #define NIC_PF_TCP_TIMER (0x0060) |
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| 19 | #define NIC_PF_BP_CFG (0x0080) |
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| 20 | #define NIC_PF_RRM_CFG (0x0088) |
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| 21 | #define NIC_PF_CQM_CFG (0x00A0) |
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| 22 | #define NIC_PF_CNM_CF (0x00A8) |
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| 23 | #define NIC_PF_CNM_STATUS (0x00B0) |
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| 24 | #define NIC_PF_CQ_AVG_CFG (0x00C0) |
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| 25 | #define NIC_PF_RRM_AVG_CFG (0x00C8) |
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| 26 | #define NIC_PF_INTF_0_1_SEND_CFG (0x0200) |
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| 27 | #define NIC_PF_INTF_0_1_BP_CFG (0x0208) |
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| 28 | #define NIC_PF_INTF_0_1_BP_DIS_0_1 (0x0210) |
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| 29 | #define NIC_PF_INTF_0_1_BP_SW_0_1 (0x0220) |
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| 30 | #define NIC_PF_RBDR_BP_STATE_0_3 (0x0240) |
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| 31 | #define NIC_PF_MAILBOX_INT (0x0410) |
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| 32 | #define NIC_PF_MAILBOX_INT_W1S (0x0430) |
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| 33 | #define NIC_PF_MAILBOX_ENA_W1C (0x0450) |
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| 34 | #define NIC_PF_MAILBOX_ENA_W1S (0x0470) |
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| 35 | #define NIC_PF_RX_ETYPE_0_7 (0x0500) |
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| 36 | #define NIC_PF_RX_GENEVE_DEF (0x0580) |
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| 37 | #define UDP_GENEVE_PORT_NUM 0x17C1ULL |
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| 38 | #define NIC_PF_RX_GENEVE_PROT_DEF (0x0588) |
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| 39 | #define IPV6_PROT 0x86DDULL |
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| 40 | #define IPV4_PROT 0x800ULL |
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| 41 | #define ET_PROT 0x6558ULL |
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| 42 | #define NIC_PF_RX_NVGRE_PROT_DEF (0x0598) |
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| 43 | #define NIC_PF_RX_VXLAN_DEF_0_1 (0x05A0) |
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| 44 | #define UDP_VXLAN_PORT_NUM 0x12B5 |
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| 45 | #define NIC_PF_RX_VXLAN_PROT_DEF (0x05B0) |
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| 46 | #define IPV6_PROT_DEF 0x2ULL |
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| 47 | #define IPV4_PROT_DEF 0x1ULL |
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| 48 | #define ET_PROT_DEF 0x3ULL |
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| 49 | #define NIC_PF_RX_CFG (0x05D0) |
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| 50 | #define NIC_PF_PKIND_0_15_CFG (0x0600) |
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| 51 | #define NIC_PF_ECC0_FLIP0 (0x1000) |
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| 52 | #define NIC_PF_ECC1_FLIP0 (0x1008) |
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| 53 | #define NIC_PF_ECC2_FLIP0 (0x1010) |
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| 54 | #define NIC_PF_ECC3_FLIP0 (0x1018) |
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| 55 | #define NIC_PF_ECC0_FLIP1 (0x1080) |
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| 56 | #define NIC_PF_ECC1_FLIP1 (0x1088) |
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| 57 | #define NIC_PF_ECC2_FLIP1 (0x1090) |
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| 58 | #define NIC_PF_ECC3_FLIP1 (0x1098) |
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| 59 | #define NIC_PF_ECC0_CDIS (0x1100) |
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| 60 | #define NIC_PF_ECC1_CDIS (0x1108) |
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| 61 | #define NIC_PF_ECC2_CDIS (0x1110) |
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| 62 | #define NIC_PF_ECC3_CDIS (0x1118) |
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| 63 | #define NIC_PF_BIST0_STATUS (0x1280) |
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| 64 | #define NIC_PF_BIST1_STATUS (0x1288) |
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| 65 | #define NIC_PF_BIST2_STATUS (0x1290) |
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| 66 | #define NIC_PF_BIST3_STATUS (0x1298) |
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| 67 | #define NIC_PF_ECC0_SBE_INT (0x2000) |
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| 68 | #define NIC_PF_ECC0_SBE_INT_W1S (0x2008) |
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| 69 | #define NIC_PF_ECC0_SBE_ENA_W1C (0x2010) |
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| 70 | #define NIC_PF_ECC0_SBE_ENA_W1S (0x2018) |
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| 71 | #define NIC_PF_ECC0_DBE_INT (0x2100) |
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| 72 | #define NIC_PF_ECC0_DBE_INT_W1S (0x2108) |
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| 73 | #define NIC_PF_ECC0_DBE_ENA_W1C (0x2110) |
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| 74 | #define NIC_PF_ECC0_DBE_ENA_W1S (0x2118) |
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| 75 | #define NIC_PF_ECC1_SBE_INT (0x2200) |
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| 76 | #define NIC_PF_ECC1_SBE_INT_W1S (0x2208) |
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| 77 | #define NIC_PF_ECC1_SBE_ENA_W1C (0x2210) |
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| 78 | #define NIC_PF_ECC1_SBE_ENA_W1S (0x2218) |
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| 79 | #define NIC_PF_ECC1_DBE_INT (0x2300) |
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| 80 | #define NIC_PF_ECC1_DBE_INT_W1S (0x2308) |
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| 81 | #define NIC_PF_ECC1_DBE_ENA_W1C (0x2310) |
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| 82 | #define NIC_PF_ECC1_DBE_ENA_W1S (0x2318) |
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| 83 | #define NIC_PF_ECC2_SBE_INT (0x2400) |
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| 84 | #define NIC_PF_ECC2_SBE_INT_W1S (0x2408) |
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| 85 | #define NIC_PF_ECC2_SBE_ENA_W1C (0x2410) |
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| 86 | #define NIC_PF_ECC2_SBE_ENA_W1S (0x2418) |
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| 87 | #define NIC_PF_ECC2_DBE_INT (0x2500) |
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| 88 | #define NIC_PF_ECC2_DBE_INT_W1S (0x2508) |
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| 89 | #define NIC_PF_ECC2_DBE_ENA_W1C (0x2510) |
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| 90 | #define NIC_PF_ECC2_DBE_ENA_W1S (0x2518) |
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| 91 | #define NIC_PF_ECC3_SBE_INT (0x2600) |
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| 92 | #define NIC_PF_ECC3_SBE_INT_W1S (0x2608) |
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| 93 | #define NIC_PF_ECC3_SBE_ENA_W1C (0x2610) |
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| 94 | #define NIC_PF_ECC3_SBE_ENA_W1S (0x2618) |
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| 95 | #define NIC_PF_ECC3_DBE_INT (0x2700) |
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| 96 | #define NIC_PF_ECC3_DBE_INT_W1S (0x2708) |
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| 97 | #define NIC_PF_ECC3_DBE_ENA_W1C (0x2710) |
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| 98 | #define NIC_PF_ECC3_DBE_ENA_W1S (0x2718) |
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| 99 | #define NIC_PF_INTFX_SEND_CFG (0x4000) |
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| 100 | #define NIC_PF_MCAM_0_191_ENA (0x100000) |
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| 101 | #define NIC_PF_MCAM_0_191_M_0_5_DATA (0x110000) |
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| 102 | #define NIC_PF_MCAM_CTRL (0x120000) |
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| 103 | #define NIC_PF_CPI_0_2047_CFG (0x200000) |
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| 104 | #define NIC_PF_MPI_0_2047_CFG (0x210000) |
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| 105 | #define (0x220000) |
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| 106 | #define NIC_PF_LMAC_0_7_CFG (0x240000) |
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| 107 | #define NIC_PF_LMAC_0_7_CFG2 (0x240100) |
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| 108 | #define NIC_PF_LMAC_0_7_SW_XOFF (0x242000) |
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| 109 | #define NIC_PF_LMAC_0_7_CREDIT (0x244000) |
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| 110 | #define NIC_PF_CHAN_0_255_TX_CFG (0x400000) |
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| 111 | #define NIC_PF_CHAN_0_255_RX_CFG (0x420000) |
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| 112 | #define NIC_PF_CHAN_0_255_SW_XOFF (0x440000) |
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| 113 | #define NIC_PF_CHAN_0_255_CREDIT (0x460000) |
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| 114 | #define NIC_PF_CHAN_0_255_RX_BP_CFG (0x480000) |
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| 115 | #define NIC_PF_SW_SYNC_RX (0x490000) |
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| 116 | #define NIC_PF_SW_SYNC_RX_DONE (0x490008) |
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| 117 | #define NIC_PF_TL2_0_63_CFG (0x500000) |
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| 118 | #define NIC_PF_TL2_0_63_PRI (0x520000) |
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| 119 | #define NIC_PF_TL2_LMAC (0x540000) |
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| 120 | #define NIC_PF_TL2_0_63_SH_STATUS (0x580000) |
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| 121 | #define NIC_PF_TL3A_0_63_CFG (0x5F0000) |
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| 122 | #define NIC_PF_TL3_0_255_CFG (0x600000) |
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| 123 | #define NIC_PF_TL3_0_255_CHAN (0x620000) |
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| 124 | #define NIC_PF_TL3_0_255_PIR (0x640000) |
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| 125 | #define NIC_PF_TL3_0_255_SW_XOFF (0x660000) |
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| 126 | #define NIC_PF_TL3_0_255_CNM_RATE (0x680000) |
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| 127 | #define NIC_PF_TL3_0_255_SH_STATUS (0x6A0000) |
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| 128 | #define NIC_PF_TL4A_0_255_CFG (0x6F0000) |
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| 129 | #define NIC_PF_TL4_0_1023_CFG (0x800000) |
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| 130 | #define NIC_PF_TL4_0_1023_SW_XOFF (0x820000) |
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| 131 | #define NIC_PF_TL4_0_1023_SH_STATUS (0x840000) |
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| 132 | #define NIC_PF_TL4A_0_1023_CNM_RATE (0x880000) |
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| 133 | #define NIC_PF_TL4A_0_1023_CNM_STATUS (0x8A0000) |
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| 134 | #define NIC_PF_VF_0_127_MAILBOX_0_1 (0x20002030) |
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| 135 | #define NIC_PF_VNIC_0_127_TX_STAT_0_4 (0x20004000) |
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| 136 | #define NIC_PF_VNIC_0_127_RX_STAT_0_13 (0x20004100) |
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| 137 | #define NIC_PF_QSET_0_127_LOCK_0_15 (0x20006000) |
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| 138 | #define NIC_PF_QSET_0_127_CFG (0x20010000) |
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| 139 | #define NIC_PF_QSET_0_127_RQ_0_7_CFG (0x20010400) |
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| 140 | #define NIC_PF_QSET_0_127_RQ_0_7_DROP_CFG (0x20010420) |
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| 141 | #define NIC_PF_QSET_0_127_RQ_0_7_BP_CFG (0x20010500) |
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| 142 | #define NIC_PF_QSET_0_127_RQ_0_7_STAT_0_1 (0x20010600) |
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| 143 | #define NIC_PF_QSET_0_127_SQ_0_7_CFG (0x20010C00) |
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| 144 | #define NIC_PF_QSET_0_127_SQ_0_7_CFG2 (0x20010C08) |
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| 145 | #define NIC_PF_QSET_0_127_SQ_0_7_STAT_0_1 (0x20010D00) |
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| 146 | |
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| 147 | #define NIC_PF_MSIX_VEC_0_18_ADDR (0x000000) |
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| 148 | #define NIC_PF_MSIX_VEC_0_CTL (0x000008) |
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| 149 | #define NIC_PF_MSIX_PBA_0 (0x0F0000) |
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| 150 | |
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| 151 | /* Virtual function register offsets */ |
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| 152 | #define NIC_VNIC_CFG (0x000020) |
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| 153 | #define NIC_VF_PF_MAILBOX_0_1 (0x000130) |
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| 154 | #define NIC_VF_INT (0x000200) |
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| 155 | #define NIC_VF_INT_W1S (0x000220) |
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| 156 | #define NIC_VF_ENA_W1C (0x000240) |
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| 157 | #define NIC_VF_ENA_W1S (0x000260) |
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| 158 | |
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| 159 | #define (0x0020E0) |
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| 160 | #define (0x002200) |
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| 161 | #define NIC_VNIC_TX_STAT_0_4 (0x004000) |
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| 162 | #define NIC_VNIC_RX_STAT_0_13 (0x004100) |
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| 163 | #define NIC_QSET_RQ_GEN_CFG (0x010010) |
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| 164 | |
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| 165 | #define NIC_QSET_CQ_0_7_CFG (0x010400) |
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| 166 | #define NIC_QSET_CQ_0_7_CFG2 (0x010408) |
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| 167 | #define NIC_QSET_CQ_0_7_THRESH (0x010410) |
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| 168 | #define NIC_QSET_CQ_0_7_BASE (0x010420) |
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| 169 | #define NIC_QSET_CQ_0_7_HEAD (0x010428) |
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| 170 | #define NIC_QSET_CQ_0_7_TAIL (0x010430) |
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| 171 | #define NIC_QSET_CQ_0_7_DOOR (0x010438) |
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| 172 | #define NIC_QSET_CQ_0_7_STATUS (0x010440) |
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| 173 | #define NIC_QSET_CQ_0_7_STATUS2 (0x010448) |
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| 174 | #define NIC_QSET_CQ_0_7_DEBUG (0x010450) |
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| 175 | |
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| 176 | #define NIC_QSET_RQ_0_7_CFG (0x010600) |
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| 177 | #define NIC_QSET_RQ_0_7_STAT_0_1 (0x010700) |
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| 178 | |
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| 179 | #define NIC_QSET_SQ_0_7_CFG (0x010800) |
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| 180 | #define NIC_QSET_SQ_0_7_THRESH (0x010810) |
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| 181 | #define NIC_QSET_SQ_0_7_BASE (0x010820) |
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| 182 | #define NIC_QSET_SQ_0_7_HEAD (0x010828) |
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| 183 | #define NIC_QSET_SQ_0_7_TAIL (0x010830) |
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| 184 | #define NIC_QSET_SQ_0_7_DOOR (0x010838) |
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| 185 | #define NIC_QSET_SQ_0_7_STATUS (0x010840) |
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| 186 | #define NIC_QSET_SQ_0_7_DEBUG (0x010848) |
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| 187 | #define NIC_QSET_SQ_0_7_STAT_0_1 (0x010900) |
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| 188 | |
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| 189 | #define NIC_QSET_RBDR_0_1_CFG (0x010C00) |
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| 190 | #define NIC_QSET_RBDR_0_1_THRESH (0x010C10) |
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| 191 | #define NIC_QSET_RBDR_0_1_BASE (0x010C20) |
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| 192 | #define NIC_QSET_RBDR_0_1_HEAD (0x010C28) |
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| 193 | #define NIC_QSET_RBDR_0_1_TAIL (0x010C30) |
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| 194 | #define NIC_QSET_RBDR_0_1_DOOR (0x010C38) |
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| 195 | #define NIC_QSET_RBDR_0_1_STATUS0 (0x010C40) |
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| 196 | #define NIC_QSET_RBDR_0_1_STATUS1 (0x010C48) |
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| 197 | #define NIC_QSET_RBDR_0_1_PREFETCH_STATUS (0x010C50) |
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| 198 | |
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| 199 | #define NIC_VF_MSIX_VECTOR_0_19_ADDR (0x000000) |
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| 200 | #define NIC_VF_MSIX_VECTOR_0_19_CTL (0x000008) |
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| 201 | #define NIC_VF_MSIX_PBA (0x0F0000) |
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| 202 | |
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| 203 | /* Offsets within registers */ |
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| 204 | #define NIC_MSIX_VEC_SHIFT 4 |
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| 205 | #define NIC_Q_NUM_SHIFT 18 |
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| 206 | #define NIC_QS_ID_SHIFT 21 |
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| 207 | #define NIC_VF_NUM_SHIFT 21 |
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| 208 | |
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| 209 | /* Port kind configuration register */ |
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| 210 | struct pkind_cfg { |
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| 211 | #if defined(__BIG_ENDIAN_BITFIELD) |
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| 212 | u64 reserved_42_63:22; |
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| 213 | u64 hdr_sl:5; /* Header skip length */ |
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| 214 | u64 rx_hdr:3; /* TNS Receive header present */ |
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| 215 | u64 lenerr_en:1;/* L2 length error check enable */ |
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| 216 | u64 reserved_32_32:1; |
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| 217 | u64 maxlen:16; /* Max frame size */ |
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| 218 | u64 minlen:16; /* Min frame size */ |
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| 219 | #elif defined(__LITTLE_ENDIAN_BITFIELD) |
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| 220 | u64 minlen:16; |
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| 221 | u64 maxlen:16; |
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| 222 | u64 reserved_32_32:1; |
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| 223 | u64 lenerr_en:1; |
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| 224 | u64 rx_hdr:3; |
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| 225 | u64 hdr_sl:5; |
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| 226 | u64 reserved_42_63:22; |
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| 227 | #endif |
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| 228 | }; |
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| 229 | |
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| 230 | #endif /* NIC_REG_H */ |
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| 231 | |
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