| 1 | /* Copyright, 1988-1992, Russell Nelson, Crynwr Software |
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| 2 | |
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| 3 | This program is free software; you can redistribute it and/or modify |
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| 4 | it under the terms of the GNU General Public License as published by |
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| 5 | the Free Software Foundation, version 1. |
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| 6 | |
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| 7 | This program is distributed in the hope that it will be useful, |
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| 8 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 9 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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| 10 | GNU General Public License for more details. |
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| 11 | |
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| 12 | You should have received a copy of the GNU General Public License |
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| 13 | along with this program; if not, write to the Free Software |
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| 14 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
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| 15 | */ |
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| 16 | |
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| 17 | |
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| 18 | #define PP_ChipID 0x0000 /* offset 0h -> Corp -ID */ |
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| 19 | /* offset 2h -> Model/Product Number */ |
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| 20 | /* offset 3h -> Chip Revision Number */ |
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| 21 | |
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| 22 | #define PP_ISAIOB 0x0020 /* IO base address */ |
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| 23 | #define PP_CS8900_ISAINT 0x0022 /* ISA interrupt select */ |
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| 24 | #define PP_CS8920_ISAINT 0x0370 /* ISA interrupt select */ |
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| 25 | #define PP_CS8900_ISADMA 0x0024 /* ISA Rec DMA channel */ |
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| 26 | #define PP_CS8920_ISADMA 0x0374 /* ISA Rec DMA channel */ |
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| 27 | #define PP_ISASOF 0x0026 /* ISA DMA offset */ |
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| 28 | #define PP_DmaFrameCnt 0x0028 /* ISA DMA Frame count */ |
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| 29 | #define PP_DmaByteCnt 0x002A /* ISA DMA Byte count */ |
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| 30 | #define PP_CS8900_ISAMemB 0x002C /* Memory base */ |
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| 31 | #define PP_CS8920_ISAMemB 0x0348 /* */ |
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| 32 | |
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| 33 | #define PP_ISABootBase 0x0030 /* Boot Prom base */ |
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| 34 | #define PP_ISABootMask 0x0034 /* Boot Prom Mask */ |
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| 35 | |
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| 36 | /* EEPROM data and command registers */ |
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| 37 | #define PP_EECMD 0x0040 /* NVR Interface Command register */ |
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| 38 | #define PP_EEData 0x0042 /* NVR Interface Data Register */ |
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| 39 | #define PP_DebugReg 0x0044 /* Debug Register */ |
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| 40 | |
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| 41 | #define PP_RxCFG 0x0102 /* Rx Bus config */ |
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| 42 | #define PP_RxCTL 0x0104 /* Receive Control Register */ |
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| 43 | #define PP_TxCFG 0x0106 /* Transmit Config Register */ |
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| 44 | #define PP_TxCMD 0x0108 /* Transmit Command Register */ |
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| 45 | #define PP_BufCFG 0x010A /* Bus configuration Register */ |
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| 46 | #define PP_LineCTL 0x0112 /* Line Config Register */ |
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| 47 | #define PP_SelfCTL 0x0114 /* Self Command Register */ |
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| 48 | #define PP_BusCTL 0x0116 /* ISA bus control Register */ |
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| 49 | #define PP_TestCTL 0x0118 /* Test Register */ |
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| 50 | #define PP_AutoNegCTL 0x011C /* Auto Negotiation Ctrl */ |
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| 51 | |
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| 52 | #define PP_ISQ 0x0120 /* Interrupt Status */ |
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| 53 | #define PP_RxEvent 0x0124 /* Rx Event Register */ |
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| 54 | #define PP_TxEvent 0x0128 /* Tx Event Register */ |
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| 55 | #define PP_BufEvent 0x012C /* Bus Event Register */ |
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| 56 | #define PP_RxMiss 0x0130 /* Receive Miss Count */ |
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| 57 | #define PP_TxCol 0x0132 /* Transmit Collision Count */ |
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| 58 | #define PP_LineST 0x0134 /* Line State Register */ |
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| 59 | #define PP_SelfST 0x0136 /* Self State register */ |
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| 60 | #define PP_BusST 0x0138 /* Bus Status */ |
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| 61 | #define PP_TDR 0x013C /* Time Domain Reflectometry */ |
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| 62 | #define PP_AutoNegST 0x013E /* Auto Neg Status */ |
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| 63 | #define PP_TxCommand 0x0144 /* Tx Command */ |
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| 64 | #define PP_TxLength 0x0146 /* Tx Length */ |
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| 65 | #define PP_LAF 0x0150 /* Hash Table */ |
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| 66 | #define PP_IA 0x0158 /* Physical Address Register */ |
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| 67 | |
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| 68 | #define PP_RxStatus 0x0400 /* Receive start of frame */ |
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| 69 | #define PP_RxLength 0x0402 /* Receive Length of frame */ |
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| 70 | #define PP_RxFrame 0x0404 /* Receive frame pointer */ |
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| 71 | #define PP_TxFrame 0x0A00 /* Transmit frame pointer */ |
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| 72 | |
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| 73 | /* Primary I/O Base Address. If no I/O base is supplied by the user, then this */ |
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| 74 | /* can be used as the default I/O base to access the PacketPage Area. */ |
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| 75 | #define DEFAULTIOBASE 0x0300 |
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| 76 | #define FIRST_IO 0x020C /* First I/O port to check */ |
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| 77 | #define LAST_IO 0x037C /* Last I/O port to check (+10h) */ |
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| 78 | #define ADD_MASK 0x3000 /* Mask it use of the ADD_PORT register */ |
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| 79 | #define ADD_SIG 0x3000 /* Expected ID signature */ |
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| 80 | |
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| 81 | /* On Macs, we only need use the ISA I/O stuff until we do MEMORY_ON */ |
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| 82 | #ifdef CONFIG_MAC |
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| 83 | #define LCSLOTBASE 0xfee00000 |
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| 84 | #define MMIOBASE 0x40000 |
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| 85 | #endif |
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| 86 | |
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| 87 | #define CHIP_EISA_ID_SIG 0x630E /* Product ID Code for Crystal Chip (CS8900 spec 4.3) */ |
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| 88 | #define CHIP_EISA_ID_SIG_STR "0x630E" |
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| 89 | |
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| 90 | #ifdef IBMEIPKT |
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| 91 | #define EISA_ID_SIG 0x4D24 /* IBM */ |
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| 92 | #define PART_NO_SIG 0x1010 /* IBM */ |
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| 93 | #define MONGOOSE_BIT 0x0000 /* IBM */ |
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| 94 | #else |
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| 95 | #define EISA_ID_SIG 0x630E /* PnP Vendor ID (same as chip id for Crystal board) */ |
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| 96 | #define PART_NO_SIG 0x4000 /* ID code CS8920 board (PnP Vendor Product code) */ |
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| 97 | #define MONGOOSE_BIT 0x2000 /* PART_NO_SIG + MONGOOSE_BUT => ID of mongoose */ |
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| 98 | #endif |
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| 99 | |
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| 100 | #define PRODUCT_ID_ADD 0x0002 /* Address of product ID */ |
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| 101 | |
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| 102 | /* Mask to find out the types of registers */ |
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| 103 | #define REG_TYPE_MASK 0x001F |
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| 104 | |
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| 105 | /* Eeprom Commands */ |
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| 106 | #define ERSE_WR_ENBL 0x00F0 |
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| 107 | #define ERSE_WR_DISABLE 0x0000 |
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| 108 | |
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| 109 | /* Defines Control/Config register quintuplet numbers */ |
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| 110 | #define RX_BUF_CFG 0x0003 |
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| 111 | #define RX_CONTROL 0x0005 |
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| 112 | #define TX_CFG 0x0007 |
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| 113 | #define TX_COMMAND 0x0009 |
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| 114 | #define BUF_CFG 0x000B |
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| 115 | #define LINE_CONTROL 0x0013 |
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| 116 | #define SELF_CONTROL 0x0015 |
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| 117 | #define BUS_CONTROL 0x0017 |
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| 118 | #define TEST_CONTROL 0x0019 |
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| 119 | |
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| 120 | /* Defines Status/Count registers quintuplet numbers */ |
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| 121 | #define RX_EVENT 0x0004 |
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| 122 | #define TX_EVENT 0x0008 |
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| 123 | #define BUF_EVENT 0x000C |
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| 124 | #define RX_MISS_COUNT 0x0010 |
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| 125 | #define TX_COL_COUNT 0x0012 |
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| 126 | #define LINE_STATUS 0x0014 |
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| 127 | #define SELF_STATUS 0x0016 |
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| 128 | #define BUS_STATUS 0x0018 |
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| 129 | #define TDR 0x001C |
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| 130 | |
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| 131 | /* PP_RxCFG - Receive Configuration and Interrupt Mask bit definition - Read/write */ |
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| 132 | #define SKIP_1 0x0040 |
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| 133 | #define RX_STREAM_ENBL 0x0080 |
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| 134 | #define RX_OK_ENBL 0x0100 |
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| 135 | #define RX_DMA_ONLY 0x0200 |
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| 136 | #define AUTO_RX_DMA 0x0400 |
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| 137 | #define BUFFER_CRC 0x0800 |
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| 138 | #define RX_CRC_ERROR_ENBL 0x1000 |
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| 139 | #define RX_RUNT_ENBL 0x2000 |
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| 140 | #define 0x4000 |
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| 141 | |
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| 142 | /* PP_RxCTL - Receive Control bit definition - Read/write */ |
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| 143 | #define RX_IA_HASH_ACCEPT 0x0040 |
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| 144 | #define RX_PROM_ACCEPT 0x0080 |
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| 145 | #define RX_OK_ACCEPT 0x0100 |
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| 146 | #define RX_MULTCAST_ACCEPT 0x0200 |
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| 147 | #define RX_IA_ACCEPT 0x0400 |
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| 148 | #define RX_BROADCAST_ACCEPT 0x0800 |
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| 149 | #define RX_BAD_CRC_ACCEPT 0x1000 |
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| 150 | #define RX_RUNT_ACCEPT 0x2000 |
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| 151 | #define 0x4000 |
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| 152 | #define RX_ALL_ACCEPT (RX_PROM_ACCEPT|RX_BAD_CRC_ACCEPT|RX_RUNT_ACCEPT|RX_EXTRA_DATA_ACCEPT) |
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| 153 | /* Default receive mode - individually addressed, broadcast, and error free */ |
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| 154 | #define DEF_RX_ACCEPT (RX_IA_ACCEPT | RX_BROADCAST_ACCEPT | RX_OK_ACCEPT) |
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| 155 | |
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| 156 | /* PP_TxCFG - Transmit Configuration Interrupt Mask bit definition - Read/write */ |
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| 157 | #define TX_LOST_CRS_ENBL 0x0040 |
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| 158 | #define TX_SQE_ERROR_ENBL 0x0080 |
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| 159 | #define TX_OK_ENBL 0x0100 |
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| 160 | #define TX_LATE_COL_ENBL 0x0200 |
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| 161 | #define TX_JBR_ENBL 0x0400 |
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| 162 | #define TX_ANY_COL_ENBL 0x0800 |
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| 163 | #define TX_16_COL_ENBL 0x8000 |
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| 164 | |
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| 165 | /* PP_TxCMD - Transmit Command bit definition - Read-only */ |
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| 166 | #define TX_START_4_BYTES 0x0000 |
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| 167 | #define TX_START_64_BYTES 0x0040 |
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| 168 | #define TX_START_128_BYTES 0x0080 |
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| 169 | #define TX_START_ALL_BYTES 0x00C0 |
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| 170 | #define TX_FORCE 0x0100 |
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| 171 | #define TX_ONE_COL 0x0200 |
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| 172 | #define TX_TWO_PART_DEFF_DISABLE 0x0400 |
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| 173 | #define TX_NO_CRC 0x1000 |
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| 174 | #define TX_RUNT 0x2000 |
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| 175 | |
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| 176 | /* PP_BufCFG - Buffer Configuration Interrupt Mask bit definition - Read/write */ |
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| 177 | #define GENERATE_SW_INTERRUPT 0x0040 |
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| 178 | #define RX_DMA_ENBL 0x0080 |
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| 179 | #define READY_FOR_TX_ENBL 0x0100 |
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| 180 | #define TX_UNDERRUN_ENBL 0x0200 |
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| 181 | #define RX_MISS_ENBL 0x0400 |
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| 182 | #define RX_128_BYTE_ENBL 0x0800 |
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| 183 | #define TX_COL_COUNT_OVRFLOW_ENBL 0x1000 |
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| 184 | #define RX_MISS_COUNT_OVRFLOW_ENBL 0x2000 |
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| 185 | #define RX_DEST_MATCH_ENBL 0x8000 |
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| 186 | |
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| 187 | /* PP_LineCTL - Line Control bit definition - Read/write */ |
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| 188 | #define SERIAL_RX_ON 0x0040 |
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| 189 | #define SERIAL_TX_ON 0x0080 |
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| 190 | #define AUI_ONLY 0x0100 |
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| 191 | #define AUTO_AUI_10BASET 0x0200 |
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| 192 | #define MODIFIED_BACKOFF 0x0800 |
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| 193 | #define NO_AUTO_POLARITY 0x1000 |
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| 194 | #define TWO_PART_DEFDIS 0x2000 |
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| 195 | #define LOW_RX_SQUELCH 0x4000 |
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| 196 | |
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| 197 | /* PP_SelfCTL - Software Self Control bit definition - Read/write */ |
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| 198 | #define POWER_ON_RESET 0x0040 |
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| 199 | #define SW_STOP 0x0100 |
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| 200 | #define SLEEP_ON 0x0200 |
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| 201 | #define AUTO_WAKEUP 0x0400 |
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| 202 | #define HCB0_ENBL 0x1000 |
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| 203 | #define HCB1_ENBL 0x2000 |
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| 204 | #define HCB0 0x4000 |
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| 205 | #define HCB1 0x8000 |
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| 206 | |
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| 207 | /* PP_BusCTL - ISA Bus Control bit definition - Read/write */ |
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| 208 | #define RESET_RX_DMA 0x0040 |
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| 209 | #define MEMORY_ON 0x0400 |
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| 210 | #define DMA_BURST_MODE 0x0800 |
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| 211 | #define IO_CHANNEL_READY_ON 0x1000 |
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| 212 | #define RX_DMA_SIZE_64K 0x2000 |
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| 213 | #define ENABLE_IRQ 0x8000 |
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| 214 | |
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| 215 | /* PP_TestCTL - Test Control bit definition - Read/write */ |
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| 216 | #define LINK_OFF 0x0080 |
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| 217 | #define ENDEC_LOOPBACK 0x0200 |
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| 218 | #define AUI_LOOPBACK 0x0400 |
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| 219 | #define BACKOFF_OFF 0x0800 |
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| 220 | #define FDX_8900 0x4000 |
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| 221 | #define FAST_TEST 0x8000 |
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| 222 | |
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| 223 | /* PP_RxEvent - Receive Event Bit definition - Read-only */ |
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| 224 | #define RX_IA_HASHED 0x0040 |
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| 225 | #define RX_DRIBBLE 0x0080 |
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| 226 | #define RX_OK 0x0100 |
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| 227 | #define RX_HASHED 0x0200 |
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| 228 | #define RX_IA 0x0400 |
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| 229 | #define RX_BROADCAST 0x0800 |
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| 230 | #define RX_CRC_ERROR 0x1000 |
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| 231 | #define RX_RUNT 0x2000 |
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| 232 | #define 0x4000 |
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| 233 | |
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| 234 | #define HASH_INDEX_MASK 0x0FC00 |
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| 235 | |
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| 236 | /* PP_TxEvent - Transmit Event Bit definition - Read-only */ |
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| 237 | #define TX_LOST_CRS 0x0040 |
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| 238 | #define TX_SQE_ERROR 0x0080 |
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| 239 | #define TX_OK 0x0100 |
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| 240 | #define TX_LATE_COL 0x0200 |
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| 241 | #define TX_JBR 0x0400 |
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| 242 | #define TX_16_COL 0x8000 |
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| 243 | #define TX_SEND_OK_BITS (TX_OK|TX_LOST_CRS) |
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| 244 | #define TX_COL_COUNT_MASK 0x7800 |
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| 245 | |
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| 246 | /* PP_BufEvent - Buffer Event Bit definition - Read-only */ |
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| 247 | #define SW_INTERRUPT 0x0040 |
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| 248 | #define RX_DMA 0x0080 |
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| 249 | #define READY_FOR_TX 0x0100 |
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| 250 | #define TX_UNDERRUN 0x0200 |
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| 251 | #define RX_MISS 0x0400 |
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| 252 | #define RX_128_BYTE 0x0800 |
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| 253 | #define TX_COL_OVRFLW 0x1000 |
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| 254 | #define RX_MISS_OVRFLW 0x2000 |
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| 255 | #define RX_DEST_MATCH 0x8000 |
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| 256 | |
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| 257 | /* PP_LineST - Ethernet Line Status bit definition - Read-only */ |
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| 258 | #define LINK_OK 0x0080 |
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| 259 | #define AUI_ON 0x0100 |
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| 260 | #define TENBASET_ON 0x0200 |
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| 261 | #define POLARITY_OK 0x1000 |
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| 262 | #define CRS_OK 0x4000 |
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| 263 | |
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| 264 | /* PP_SelfST - Chip Software Status bit definition */ |
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| 265 | #define ACTIVE_33V 0x0040 |
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| 266 | #define INIT_DONE 0x0080 |
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| 267 | #define SI_BUSY 0x0100 |
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| 268 | #define EEPROM_PRESENT 0x0200 |
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| 269 | #define EEPROM_OK 0x0400 |
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| 270 | #define EL_PRESENT 0x0800 |
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| 271 | #define EE_SIZE_64 0x1000 |
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| 272 | |
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| 273 | /* PP_BusST - ISA Bus Status bit definition */ |
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| 274 | #define TX_BID_ERROR 0x0080 |
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| 275 | #define READY_FOR_TX_NOW 0x0100 |
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| 276 | |
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| 277 | /* PP_AutoNegCTL - Auto Negotiation Control bit definition */ |
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| 278 | #define RE_NEG_NOW 0x0040 |
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| 279 | #define ALLOW_FDX 0x0080 |
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| 280 | #define AUTO_NEG_ENABLE 0x0100 |
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| 281 | #define NLP_ENABLE 0x0200 |
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| 282 | #define FORCE_FDX 0x8000 |
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| 283 | #define AUTO_NEG_BITS (FORCE_FDX|NLP_ENABLE|AUTO_NEG_ENABLE) |
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| 284 | #define AUTO_NEG_MASK (FORCE_FDX|NLP_ENABLE|AUTO_NEG_ENABLE|ALLOW_FDX|RE_NEG_NOW) |
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| 285 | |
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| 286 | /* PP_AutoNegST - Auto Negotiation Status bit definition */ |
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| 287 | #define AUTO_NEG_BUSY 0x0080 |
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| 288 | #define FLP_LINK 0x0100 |
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| 289 | #define FLP_LINK_GOOD 0x0800 |
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| 290 | #define LINK_FAULT 0x1000 |
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| 291 | #define HDX_ACTIVE 0x4000 |
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| 292 | #define FDX_ACTIVE 0x8000 |
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| 293 | |
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| 294 | /* The following block defines the ISQ event types */ |
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| 295 | #define ISQ_RECEIVER_EVENT 0x04 |
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| 296 | #define ISQ_TRANSMITTER_EVENT 0x08 |
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| 297 | #define ISQ_BUFFER_EVENT 0x0c |
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| 298 | #define ISQ_RX_MISS_EVENT 0x10 |
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| 299 | #define ISQ_TX_COL_EVENT 0x12 |
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| 300 | |
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| 301 | #define ISQ_EVENT_MASK 0x003F /* ISQ mask to find out type of event */ |
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| 302 | #define ISQ_HIST 16 /* small history buffer */ |
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| 303 | #define AUTOINCREMENT 0x8000 /* Bit mask to set bit-15 for autoincrement */ |
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| 304 | |
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| 305 | #define TXRXBUFSIZE 0x0600 |
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| 306 | #define RXDMABUFSIZE 0x8000 |
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| 307 | #define RXDMASIZE 0x4000 |
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| 308 | #define TXRX_LENGTH_MASK 0x07FF |
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| 309 | |
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| 310 | /* rx options bits */ |
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| 311 | #define RCV_WITH_RXON 1 /* Set SerRx ON */ |
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| 312 | #define RCV_COUNTS 2 /* Use Framecnt1 */ |
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| 313 | #define RCV_PONG 4 /* Pong respondent */ |
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| 314 | #define RCV_DONG 8 /* Dong operation */ |
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| 315 | #define RCV_POLLING 0x10 /* Poll RxEvent */ |
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| 316 | #define RCV_ISQ 0x20 /* Use ISQ, int */ |
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| 317 | #define RCV_AUTO_DMA 0x100 /* Set AutoRxDMAE */ |
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| 318 | #define RCV_DMA 0x200 /* Set RxDMA only */ |
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| 319 | #define RCV_DMA_ALL 0x400 /* Copy all DMA'ed */ |
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| 320 | #define RCV_FIXED_DATA 0x800 /* Every frame same */ |
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| 321 | #define RCV_IO 0x1000 /* Use ISA IO only */ |
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| 322 | #define RCV_MEMORY 0x2000 /* Use ISA Memory */ |
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| 323 | |
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| 324 | #define RAM_SIZE 0x1000 /* The card has 4k bytes or RAM */ |
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| 325 | #define PKT_START PP_TxFrame /* Start of packet RAM */ |
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| 326 | |
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| 327 | #define RX_FRAME_PORT 0x0000 |
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| 328 | #define TX_FRAME_PORT RX_FRAME_PORT |
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| 329 | #define TX_CMD_PORT 0x0004 |
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| 330 | #define TX_NOW 0x0000 /* Tx packet after 5 bytes copied */ |
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| 331 | #define TX_AFTER_381 0x0040 /* Tx packet after 381 bytes copied */ |
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| 332 | #define TX_AFTER_ALL 0x00c0 /* Tx packet after all bytes copied */ |
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| 333 | #define TX_LEN_PORT 0x0006 |
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| 334 | #define ISQ_PORT 0x0008 |
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| 335 | #define ADD_PORT 0x000A |
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| 336 | #define DATA_PORT 0x000C |
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| 337 | |
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| 338 | #define EEPROM_WRITE_EN 0x00F0 |
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| 339 | #define EEPROM_WRITE_DIS 0x0000 |
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| 340 | #define EEPROM_WRITE_CMD 0x0100 |
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| 341 | #define EEPROM_READ_CMD 0x0200 |
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| 342 | |
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| 343 | /* Receive Header */ |
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| 344 | /* Description of header of each packet in receive area of memory */ |
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| 345 | #define RBUF_EVENT_LOW 0 /* Low byte of RxEvent - status of received frame */ |
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| 346 | #define RBUF_EVENT_HIGH 1 /* High byte of RxEvent - status of received frame */ |
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| 347 | #define RBUF_LEN_LOW 2 /* Length of received data - low byte */ |
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| 348 | #define RBUF_LEN_HI 3 /* Length of received data - high byte */ |
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| 349 | #define RBUF_HEAD_LEN 4 /* Length of this header */ |
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| 350 | |
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| 351 | #define CHIP_READ 0x1 /* Used to mark state of the repins code (chip or dma) */ |
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| 352 | #define DMA_READ 0x2 /* Used to mark state of the repins code (chip or dma) */ |
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| 353 | |
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| 354 | /* for bios scan */ |
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| 355 | /* */ |
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| 356 | #ifdef CSDEBUG |
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| 357 | /* use these values for debugging bios scan */ |
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| 358 | #define BIOS_START_SEG 0x00000 |
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| 359 | #define BIOS_OFFSET_INC 0x0010 |
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| 360 | #else |
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| 361 | #define BIOS_START_SEG 0x0c000 |
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| 362 | #define BIOS_OFFSET_INC 0x0200 |
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| 363 | #endif |
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| 364 | |
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| 365 | #define BIOS_LAST_OFFSET 0x0fc00 |
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| 366 | |
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| 367 | /* Byte offsets into the EEPROM configuration buffer */ |
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| 368 | #define ISA_CNF_OFFSET 0x6 |
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| 369 | #define TX_CTL_OFFSET (ISA_CNF_OFFSET + 8) /* 8900 eeprom */ |
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| 370 | #define AUTO_NEG_CNF_OFFSET (ISA_CNF_OFFSET + 8) /* 8920 eeprom */ |
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| 371 | |
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| 372 | /* the assumption here is that the bits in the eeprom are generally */ |
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| 373 | /* in the same position as those in the autonegctl register. */ |
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| 374 | /* Of course the IMM bit is not in that register so it must be */ |
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| 375 | /* masked out */ |
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| 376 | #define EE_FORCE_FDX 0x8000 |
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| 377 | #define EE_NLP_ENABLE 0x0200 |
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| 378 | #define EE_AUTO_NEG_ENABLE 0x0100 |
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| 379 | #define EE_ALLOW_FDX 0x0080 |
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| 380 | #define EE_AUTO_NEG_CNF_MASK (EE_FORCE_FDX|EE_NLP_ENABLE|EE_AUTO_NEG_ENABLE|EE_ALLOW_FDX) |
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| 381 | |
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| 382 | #define IMM_BIT 0x0040 /* ignore missing media */ |
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| 383 | |
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| 384 | #define ADAPTER_CNF_OFFSET (AUTO_NEG_CNF_OFFSET + 2) |
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| 385 | #define A_CNF_10B_T 0x0001 |
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| 386 | #define A_CNF_AUI 0x0002 |
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| 387 | #define A_CNF_10B_2 0x0004 |
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| 388 | #define A_CNF_MEDIA_TYPE 0x0070 |
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| 389 | #define A_CNF_MEDIA_AUTO 0x0070 |
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| 390 | #define A_CNF_MEDIA_10B_T 0x0020 |
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| 391 | #define A_CNF_MEDIA_AUI 0x0040 |
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| 392 | #define A_CNF_MEDIA_10B_2 0x0010 |
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| 393 | #define A_CNF_DC_DC_POLARITY 0x0080 |
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| 394 | #define A_CNF_NO_AUTO_POLARITY 0x2000 |
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| 395 | #define A_CNF_LOW_RX_SQUELCH 0x4000 |
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| 396 | #define A_CNF_EXTND_10B_2 0x8000 |
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| 397 | |
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| 398 | #define PACKET_PAGE_OFFSET 0x8 |
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| 399 | |
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| 400 | /* Bit definitions for the ISA configuration word from the EEPROM */ |
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| 401 | #define INT_NO_MASK 0x000F |
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| 402 | #define DMA_NO_MASK 0x0070 |
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| 403 | #define ISA_DMA_SIZE 0x0200 |
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| 404 | #define ISA_AUTO_RxDMA 0x0400 |
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| 405 | #define ISA_RxDMA 0x0800 |
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| 406 | #define DMA_BURST 0x1000 |
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| 407 | #define STREAM_TRANSFER 0x2000 |
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| 408 | #define ANY_ISA_DMA (ISA_AUTO_RxDMA | ISA_RxDMA) |
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| 409 | |
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| 410 | /* DMA controller registers */ |
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| 411 | #define DMA_BASE 0x00 /* DMA controller base */ |
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| 412 | #define DMA_BASE_2 0x0C0 /* DMA controller base */ |
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| 413 | |
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| 414 | #define DMA_STAT 0x0D0 /* DMA controller status register */ |
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| 415 | #define DMA_MASK 0x0D4 /* DMA controller mask register */ |
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| 416 | #define DMA_MODE 0x0D6 /* DMA controller mode register */ |
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| 417 | #define DMA_RESETFF 0x0D8 /* DMA controller first/last flip flop */ |
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| 418 | |
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| 419 | /* DMA data */ |
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| 420 | #define DMA_DISABLE 0x04 /* Disable channel n */ |
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| 421 | #define DMA_ENABLE 0x00 /* Enable channel n */ |
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| 422 | /* Demand transfers, incr. address, auto init, writes, ch. n */ |
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| 423 | #define DMA_RX_MODE 0x14 |
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| 424 | /* Demand transfers, incr. address, auto init, reads, ch. n */ |
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| 425 | #define DMA_TX_MODE 0x18 |
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| 426 | |
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| 427 | #define DMA_SIZE (16*1024) /* Size of dma buffer - 16k */ |
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| 428 | |
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| 429 | #define CS8900 0x0000 |
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| 430 | #define CS8920 0x4000 |
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| 431 | #define CS8920M 0x6000 |
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| 432 | #define REVISON_BITS 0x1F00 |
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| 433 | #define EEVER_NUMBER 0x12 |
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| 434 | #define CHKSUM_LEN 0x14 |
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| 435 | #define CHKSUM_VAL 0x0000 |
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| 436 | #define START_EEPROM_DATA 0x001c /* Offset into eeprom for start of data */ |
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| 437 | #define IRQ_MAP_EEPROM_DATA 0x0046 /* Offset into eeprom for the IRQ map */ |
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| 438 | #define IRQ_MAP_LEN 0x0004 /* No of bytes to read for the IRQ map */ |
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| 439 | #define PNP_IRQ_FRMT 0x0022 /* PNP small item IRQ format */ |
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| 440 | #define CS8900_IRQ_MAP 0x1c20 /* This IRQ map is fixed */ |
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| 441 | |
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| 442 | #define CS8920_NO_INTS 0x0F /* Max CS8920 interrupt select # */ |
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| 443 | |
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| 444 | #define PNP_ADD_PORT 0x0279 |
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| 445 | #define PNP_WRITE_PORT 0x0A79 |
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| 446 | |
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| 447 | #define GET_PNP_ISA_STRUCT 0x40 |
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| 448 | #define PNP_ISA_STRUCT_LEN 0x06 |
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| 449 | #define PNP_CSN_CNT_OFF 0x01 |
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| 450 | #define PNP_RD_PORT_OFF 0x02 |
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| 451 | #define PNP_FUNCTION_OK 0x00 |
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| 452 | #define PNP_WAKE 0x03 |
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| 453 | #define PNP_RSRC_DATA 0x04 |
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| 454 | #define PNP_RSRC_READY 0x01 |
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| 455 | #define PNP_STATUS 0x05 |
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| 456 | #define PNP_ACTIVATE 0x30 |
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| 457 | #define PNP_CNF_IO_H 0x60 |
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| 458 | #define PNP_CNF_IO_L 0x61 |
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| 459 | #define PNP_CNF_INT 0x70 |
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| 460 | #define PNP_CNF_DMA 0x74 |
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| 461 | #define PNP_CNF_MEM 0x48 |
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| 462 | |
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