1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright 2008-2010 Cisco Systems, Inc. All rights reserved.
4 * Copyright 2007 Nuova Systems, Inc. All rights reserved.
5 */
6
7#ifndef _CQ_DESC_H_
8#define _CQ_DESC_H_
9
10/*
11 * Completion queue descriptor types
12 */
13enum cq_desc_types {
14 CQ_DESC_TYPE_WQ_ENET = 0,
15 CQ_DESC_TYPE_DESC_COPY = 1,
16 CQ_DESC_TYPE_WQ_EXCH = 2,
17 CQ_DESC_TYPE_RQ_ENET = 3,
18 CQ_DESC_TYPE_RQ_FCP = 4,
19};
20
21/* Completion queue descriptor: 16B
22 *
23 * All completion queues have this basic layout. The
24 * type_specfic area is unique for each completion
25 * queue type.
26 */
27struct cq_desc {
28 __le16 completed_index;
29 __le16 q_number;
30 u8 type_specfic[11];
31 u8 type_color;
32};
33
34#define CQ_DESC_TYPE_BITS 4
35#define CQ_DESC_TYPE_MASK ((1 << CQ_DESC_TYPE_BITS) - 1)
36#define CQ_DESC_COLOR_MASK 1
37#define CQ_DESC_COLOR_SHIFT 7
38#define CQ_DESC_Q_NUM_BITS 10
39#define CQ_DESC_Q_NUM_MASK ((1 << CQ_DESC_Q_NUM_BITS) - 1)
40#define CQ_DESC_COMP_NDX_BITS 12
41#define CQ_DESC_COMP_NDX_MASK ((1 << CQ_DESC_COMP_NDX_BITS) - 1)
42
43static inline void cq_desc_dec(const struct cq_desc *desc_arg,
44 u8 *type, u8 *color, u16 *q_number, u16 *completed_index)
45{
46 const struct cq_desc *desc = desc_arg;
47 const u8 type_color = desc->type_color;
48
49 *color = (type_color >> CQ_DESC_COLOR_SHIFT) & CQ_DESC_COLOR_MASK;
50
51 /*
52 * Make sure color bit is read from desc *before* other fields
53 * are read from desc. Hardware guarantees color bit is last
54 * bit (byte) written. Adding the rmb() prevents the compiler
55 * and/or CPU from reordering the reads which would potentially
56 * result in reading stale values.
57 */
58
59 rmb();
60
61 *type = type_color & CQ_DESC_TYPE_MASK;
62 *q_number = le16_to_cpu(desc->q_number) & CQ_DESC_Q_NUM_MASK;
63 *completed_index = le16_to_cpu(desc->completed_index) &
64 CQ_DESC_COMP_NDX_MASK;
65}
66
67#endif /* _CQ_DESC_H_ */
68

source code of linux/drivers/net/ethernet/cisco/enic/cq_desc.h