1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* |
3 | * Copyright (C) 2005 - 2016 Broadcom |
4 | * All rights reserved. |
5 | * |
6 | * Contact Information: |
7 | * linux-drivers@emulex.com |
8 | * |
9 | * Emulex |
10 | * 3333 Susan Street |
11 | * Costa Mesa, CA 92626 |
12 | */ |
13 | |
14 | /* |
15 | * The driver sends configuration and managements command requests to the |
16 | * firmware in the BE. These requests are communicated to the processor |
17 | * using Work Request Blocks (WRBs) submitted to the MCC-WRB ring or via one |
18 | * WRB inside a MAILBOX. |
19 | * The commands are serviced by the ARM processor in the BladeEngine's MPU. |
20 | */ |
21 | |
22 | struct be_sge { |
23 | u32 pa_lo; |
24 | u32 pa_hi; |
25 | u32 len; |
26 | }; |
27 | |
28 | #define MCC_WRB_EMBEDDED_MASK 1 /* bit 0 of dword 0*/ |
29 | #define MCC_WRB_SGE_CNT_SHIFT 3 /* bits 3 - 7 of dword 0 */ |
30 | #define MCC_WRB_SGE_CNT_MASK 0x1F /* bits 3 - 7 of dword 0 */ |
31 | struct be_mcc_wrb { |
32 | u32 embedded; /* dword 0 */ |
33 | u32 payload_length; /* dword 1 */ |
34 | u32 tag0; /* dword 2 */ |
35 | u32 tag1; /* dword 3 */ |
36 | u32 rsvd; /* dword 4 */ |
37 | union { |
38 | u8 embedded_payload[236]; /* used by embedded cmds */ |
39 | struct be_sge sgl[19]; /* used by non-embedded cmds */ |
40 | } payload; |
41 | }; |
42 | |
43 | #define CQE_FLAGS_VALID_MASK BIT(31) |
44 | #define CQE_FLAGS_ASYNC_MASK BIT(30) |
45 | #define CQE_FLAGS_COMPLETED_MASK BIT(28) |
46 | #define CQE_FLAGS_CONSUMED_MASK BIT(27) |
47 | |
48 | /* Completion Status */ |
49 | enum mcc_base_status { |
50 | MCC_STATUS_SUCCESS = 0, |
51 | MCC_STATUS_FAILED = 1, |
52 | MCC_STATUS_ILLEGAL_REQUEST = 2, |
53 | MCC_STATUS_ILLEGAL_FIELD = 3, |
54 | MCC_STATUS_INSUFFICIENT_BUFFER = 4, |
55 | MCC_STATUS_UNAUTHORIZED_REQUEST = 5, |
56 | MCC_STATUS_NOT_SUPPORTED = 66, |
57 | MCC_STATUS_FEATURE_NOT_SUPPORTED = 68, |
58 | MCC_STATUS_INVALID_LENGTH = 116 |
59 | }; |
60 | |
61 | /* Additional status */ |
62 | enum mcc_addl_status { |
63 | MCC_ADDL_STATUS_INSUFFICIENT_RESOURCES = 0x16, |
64 | MCC_ADDL_STATUS_FLASH_IMAGE_CRC_MISMATCH = 0x4d, |
65 | MCC_ADDL_STATUS_TOO_MANY_INTERFACES = 0x4a, |
66 | MCC_ADDL_STATUS_INSUFFICIENT_VLANS = 0xab, |
67 | MCC_ADDL_STATUS_INVALID_SIGNATURE = 0x56, |
68 | MCC_ADDL_STATUS_MISSING_SIGNATURE = 0x57, |
69 | MCC_ADDL_STATUS_INSUFFICIENT_PRIVILEGES = 0x60 |
70 | }; |
71 | |
72 | #define CQE_BASE_STATUS_MASK 0xFFFF |
73 | #define CQE_BASE_STATUS_SHIFT 0 /* bits 0 - 15 */ |
74 | #define CQE_ADDL_STATUS_MASK 0xFF |
75 | #define CQE_ADDL_STATUS_SHIFT 16 /* bits 16 - 31 */ |
76 | |
77 | #define base_status(status) \ |
78 | ((enum mcc_base_status) \ |
79 | (status > 0 ? (status & CQE_BASE_STATUS_MASK) : 0)) |
80 | #define addl_status(status) \ |
81 | ((enum mcc_addl_status) \ |
82 | (status > 0 ? (status >> CQE_ADDL_STATUS_SHIFT) & \ |
83 | CQE_ADDL_STATUS_MASK : 0)) |
84 | |
85 | struct be_mcc_compl { |
86 | u32 status; /* dword 0 */ |
87 | u32 tag0; /* dword 1 */ |
88 | u32 tag1; /* dword 2 */ |
89 | u32 flags; /* dword 3 */ |
90 | }; |
91 | |
92 | /* When the async bit of mcc_compl flags is set, flags |
93 | * is interpreted as follows: |
94 | */ |
95 | #define ASYNC_EVENT_CODE_SHIFT 8 /* bits 8 - 15 */ |
96 | #define ASYNC_EVENT_CODE_MASK 0xFF |
97 | #define ASYNC_EVENT_TYPE_SHIFT 16 |
98 | #define ASYNC_EVENT_TYPE_MASK 0xFF |
99 | #define ASYNC_EVENT_CODE_LINK_STATE 0x1 |
100 | #define ASYNC_EVENT_CODE_GRP_5 0x5 |
101 | #define ASYNC_EVENT_QOS_SPEED 0x1 |
102 | #define ASYNC_EVENT_COS_PRIORITY 0x2 |
103 | #define ASYNC_EVENT_PVID_STATE 0x3 |
104 | #define ASYNC_EVENT_CODE_QNQ 0x6 |
105 | #define ASYNC_DEBUG_EVENT_TYPE_QNQ 1 |
106 | #define ASYNC_EVENT_CODE_SLIPORT 0x11 |
107 | #define ASYNC_EVENT_PORT_MISCONFIG 0x9 |
108 | #define ASYNC_EVENT_FW_CONTROL 0x5 |
109 | |
110 | enum { |
111 | LINK_DOWN = 0x0, |
112 | LINK_UP = 0x1 |
113 | }; |
114 | #define LINK_STATUS_MASK 0x1 |
115 | #define LOGICAL_LINK_STATUS_MASK 0x2 |
116 | |
117 | /* When the event code of compl->flags is link-state, the mcc_compl |
118 | * must be interpreted as follows |
119 | */ |
120 | struct be_async_event_link_state { |
121 | u8 physical_port; |
122 | u8 port_link_status; |
123 | u8 port_duplex; |
124 | u8 port_speed; |
125 | u8 port_fault; |
126 | u8 rsvd0[7]; |
127 | u32 flags; |
128 | } __packed; |
129 | |
130 | /* When the event code of compl->flags is GRP-5 and event_type is QOS_SPEED |
131 | * the mcc_compl must be interpreted as follows |
132 | */ |
133 | struct be_async_event_grp5_qos_link_speed { |
134 | u8 physical_port; |
135 | u8 rsvd[5]; |
136 | u16 qos_link_speed; |
137 | u32 event_tag; |
138 | u32 flags; |
139 | } __packed; |
140 | |
141 | /* When the event code of compl->flags is GRP5 and event type is |
142 | * CoS-Priority, the mcc_compl must be interpreted as follows |
143 | */ |
144 | struct be_async_event_grp5_cos_priority { |
145 | u8 physical_port; |
146 | u8 available_priority_bmap; |
147 | u8 reco_default_priority; |
148 | u8 valid; |
149 | u8 rsvd0; |
150 | u8 event_tag; |
151 | u32 flags; |
152 | } __packed; |
153 | |
154 | /* When the event code of compl->flags is GRP5 and event type is |
155 | * PVID state, the mcc_compl must be interpreted as follows |
156 | */ |
157 | struct be_async_event_grp5_pvid_state { |
158 | u8 enabled; |
159 | u8 rsvd0; |
160 | u16 tag; |
161 | u32 event_tag; |
162 | u32 rsvd1; |
163 | u32 flags; |
164 | } __packed; |
165 | |
166 | /* async event indicating outer VLAN tag in QnQ */ |
167 | struct be_async_event_qnq { |
168 | u8 valid; /* Indicates if outer VLAN is valid */ |
169 | u8 rsvd0; |
170 | u16 vlan_tag; |
171 | u32 event_tag; |
172 | u8 rsvd1[4]; |
173 | u32 flags; |
174 | } __packed; |
175 | |
176 | enum { |
177 | BE_PHY_FUNCTIONAL = 0, |
178 | BE_PHY_NOT_PRESENT = 1, |
179 | BE_PHY_DIFF_MEDIA = 2, |
180 | BE_PHY_INCOMPATIBLE = 3, |
181 | BE_PHY_UNQUALIFIED = 4, |
182 | BE_PHY_UNCERTIFIED = 5 |
183 | }; |
184 | |
185 | #define PHY_STATE_MSG_SEVERITY 0x6 |
186 | #define PHY_STATE_OPER 0x1 |
187 | #define PHY_STATE_INFO_VALID 0x80 |
188 | #define PHY_STATE_OPER_MSG_NONE 0x2 |
189 | #define DEFAULT_MSG_SEVERITY 0x1 |
190 | |
191 | #define be_phy_state_unknown(phy_state) (phy_state > BE_PHY_UNCERTIFIED) |
192 | #define be_phy_unqualified(phy_state) \ |
193 | (phy_state == BE_PHY_UNQUALIFIED || \ |
194 | phy_state == BE_PHY_UNCERTIFIED) |
195 | #define be_phy_misconfigured(phy_state) \ |
196 | (phy_state == BE_PHY_INCOMPATIBLE || \ |
197 | phy_state == BE_PHY_UNQUALIFIED || \ |
198 | phy_state == BE_PHY_UNCERTIFIED) |
199 | |
200 | extern const char * const be_misconfig_evt_port_state[]; |
201 | |
202 | /* async event indicating misconfigured port */ |
203 | struct be_async_event_misconfig_port { |
204 | /* DATA_WORD1: |
205 | * phy state of port 0: bits 7 - 0 |
206 | * phy state of port 1: bits 15 - 8 |
207 | * phy state of port 2: bits 23 - 16 |
208 | * phy state of port 3: bits 31 - 24 |
209 | */ |
210 | u32 event_data_word1; |
211 | /* DATA_WORD2: |
212 | * phy state info of port 0: bits 7 - 0 |
213 | * phy state info of port 1: bits 15 - 8 |
214 | * phy state info of port 2: bits 23 - 16 |
215 | * phy state info of port 3: bits 31 - 24 |
216 | * |
217 | * PHY STATE INFO: |
218 | * Link operability :bit 0 |
219 | * Message severity :bit 2 - 1 |
220 | * Rsvd :bits 6 - 3 |
221 | * phy state info valid :bit 7 |
222 | */ |
223 | u32 event_data_word2; |
224 | u32 rsvd0; |
225 | u32 flags; |
226 | } __packed; |
227 | |
228 | #define BMC_FILT_BROADCAST_ARP BIT(0) |
229 | #define BMC_FILT_BROADCAST_DHCP_CLIENT BIT(1) |
230 | #define BMC_FILT_BROADCAST_DHCP_SERVER BIT(2) |
231 | #define BMC_FILT_BROADCAST_NET_BIOS BIT(3) |
232 | #define BMC_FILT_BROADCAST BIT(7) |
233 | #define BMC_FILT_MULTICAST_IPV6_NEIGH_ADVER BIT(8) |
234 | #define BMC_FILT_MULTICAST_IPV6_RA BIT(9) |
235 | #define BMC_FILT_MULTICAST_IPV6_RAS BIT(10) |
236 | #define BMC_FILT_MULTICAST BIT(15) |
237 | struct be_async_fw_control { |
238 | u32 event_data_word1; |
239 | u32 event_data_word2; |
240 | u32 evt_tag; |
241 | u32 event_data_word4; |
242 | } __packed; |
243 | |
244 | struct be_mcc_mailbox { |
245 | struct be_mcc_wrb wrb; |
246 | struct be_mcc_compl compl; |
247 | }; |
248 | |
249 | #define CMD_SUBSYSTEM_COMMON 0x1 |
250 | #define CMD_SUBSYSTEM_ETH 0x3 |
251 | #define CMD_SUBSYSTEM_LOWLEVEL 0xb |
252 | |
253 | #define OPCODE_COMMON_NTWK_MAC_QUERY 1 |
254 | #define OPCODE_COMMON_NTWK_MAC_SET 2 |
255 | #define OPCODE_COMMON_NTWK_MULTICAST_SET 3 |
256 | #define OPCODE_COMMON_NTWK_VLAN_CONFIG 4 |
257 | #define OPCODE_COMMON_NTWK_LINK_STATUS_QUERY 5 |
258 | #define OPCODE_COMMON_READ_FLASHROM 6 |
259 | #define OPCODE_COMMON_WRITE_FLASHROM 7 |
260 | #define OPCODE_COMMON_CQ_CREATE 12 |
261 | #define OPCODE_COMMON_EQ_CREATE 13 |
262 | #define OPCODE_COMMON_MCC_CREATE 21 |
263 | #define OPCODE_COMMON_SET_QOS 28 |
264 | #define OPCODE_COMMON_MCC_CREATE_EXT 90 |
265 | #define OPCODE_COMMON_SEEPROM_READ 30 |
266 | #define OPCODE_COMMON_GET_CNTL_ATTRIBUTES 32 |
267 | #define OPCODE_COMMON_NTWK_RX_FILTER 34 |
268 | #define OPCODE_COMMON_GET_FW_VERSION 35 |
269 | #define OPCODE_COMMON_SET_FLOW_CONTROL 36 |
270 | #define OPCODE_COMMON_GET_FLOW_CONTROL 37 |
271 | #define OPCODE_COMMON_SET_FRAME_SIZE 39 |
272 | #define OPCODE_COMMON_MODIFY_EQ_DELAY 41 |
273 | #define OPCODE_COMMON_FIRMWARE_CONFIG 42 |
274 | #define OPCODE_COMMON_NTWK_INTERFACE_CREATE 50 |
275 | #define OPCODE_COMMON_NTWK_INTERFACE_DESTROY 51 |
276 | #define OPCODE_COMMON_MCC_DESTROY 53 |
277 | #define OPCODE_COMMON_CQ_DESTROY 54 |
278 | #define OPCODE_COMMON_EQ_DESTROY 55 |
279 | #define OPCODE_COMMON_QUERY_FIRMWARE_CONFIG 58 |
280 | #define OPCODE_COMMON_NTWK_PMAC_ADD 59 |
281 | #define OPCODE_COMMON_NTWK_PMAC_DEL 60 |
282 | #define OPCODE_COMMON_FUNCTION_RESET 61 |
283 | #define OPCODE_COMMON_MANAGE_FAT 68 |
284 | #define OPCODE_COMMON_ENABLE_DISABLE_BEACON 69 |
285 | #define OPCODE_COMMON_GET_BEACON_STATE 70 |
286 | #define OPCODE_COMMON_READ_TRANSRECV_DATA 73 |
287 | #define OPCODE_COMMON_GET_PORT_NAME 77 |
288 | #define OPCODE_COMMON_SET_LOGICAL_LINK_CONFIG 80 |
289 | #define OPCODE_COMMON_SET_INTERRUPT_ENABLE 89 |
290 | #define OPCODE_COMMON_SET_FN_PRIVILEGES 100 |
291 | #define OPCODE_COMMON_GET_PHY_DETAILS 102 |
292 | #define OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP 103 |
293 | #define OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES 121 |
294 | #define OPCODE_COMMON_GET_EXT_FAT_CAPABILITIES 125 |
295 | #define OPCODE_COMMON_SET_EXT_FAT_CAPABILITIES 126 |
296 | #define OPCODE_COMMON_GET_MAC_LIST 147 |
297 | #define OPCODE_COMMON_SET_MAC_LIST 148 |
298 | #define OPCODE_COMMON_GET_HSW_CONFIG 152 |
299 | #define OPCODE_COMMON_GET_FUNC_CONFIG 160 |
300 | #define OPCODE_COMMON_GET_PROFILE_CONFIG 164 |
301 | #define OPCODE_COMMON_SET_PROFILE_CONFIG 165 |
302 | #define OPCODE_COMMON_GET_ACTIVE_PROFILE 167 |
303 | #define OPCODE_COMMON_SET_HSW_CONFIG 153 |
304 | #define OPCODE_COMMON_GET_FN_PRIVILEGES 170 |
305 | #define OPCODE_COMMON_READ_OBJECT 171 |
306 | #define OPCODE_COMMON_WRITE_OBJECT 172 |
307 | #define OPCODE_COMMON_DELETE_OBJECT 174 |
308 | #define OPCODE_COMMON_SET_FEATURES 191 |
309 | #define OPCODE_COMMON_MANAGE_IFACE_FILTERS 193 |
310 | #define OPCODE_COMMON_GET_IFACE_LIST 194 |
311 | #define OPCODE_COMMON_ENABLE_DISABLE_VF 196 |
312 | |
313 | #define 1 |
314 | #define OPCODE_ETH_ACPI_CONFIG 2 |
315 | #define OPCODE_ETH_PROMISCUOUS 3 |
316 | #define OPCODE_ETH_GET_STATISTICS 4 |
317 | #define OPCODE_ETH_TX_CREATE 7 |
318 | #define OPCODE_ETH_RX_CREATE 8 |
319 | #define OPCODE_ETH_TX_DESTROY 9 |
320 | #define OPCODE_ETH_RX_DESTROY 10 |
321 | #define OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG 12 |
322 | #define OPCODE_ETH_GET_PPORT_STATS 18 |
323 | |
324 | #define OPCODE_LOWLEVEL_HOST_DDR_DMA 17 |
325 | #define OPCODE_LOWLEVEL_LOOPBACK_TEST 18 |
326 | #define OPCODE_LOWLEVEL_SET_LOOPBACK_MODE 19 |
327 | |
328 | struct be_cmd_req_hdr { |
329 | u8 opcode; /* dword 0 */ |
330 | u8 subsystem; /* dword 0 */ |
331 | u8 port_number; /* dword 0 */ |
332 | u8 domain; /* dword 0 */ |
333 | u32 timeout; /* dword 1 */ |
334 | u32 request_length; /* dword 2 */ |
335 | u8 version; /* dword 3 */ |
336 | u8 rsvd[3]; /* dword 3 */ |
337 | }; |
338 | |
339 | #define RESP_HDR_INFO_OPCODE_SHIFT 0 /* bits 0 - 7 */ |
340 | #define RESP_HDR_INFO_SUBSYS_SHIFT 8 /* bits 8 - 15 */ |
341 | struct be_cmd_resp_hdr { |
342 | u8 opcode; /* dword 0 */ |
343 | u8 subsystem; /* dword 0 */ |
344 | u8 rsvd[2]; /* dword 0 */ |
345 | u8 base_status; /* dword 1 */ |
346 | u8 addl_status; /* dword 1 */ |
347 | u8 rsvd1[2]; /* dword 1 */ |
348 | u32 response_length; /* dword 2 */ |
349 | u32 actual_resp_len; /* dword 3 */ |
350 | }; |
351 | |
352 | struct phys_addr { |
353 | u32 lo; |
354 | u32 hi; |
355 | }; |
356 | |
357 | /************************** |
358 | * BE Command definitions * |
359 | **************************/ |
360 | |
361 | /* Pseudo amap definition in which each bit of the actual structure is defined |
362 | * as a byte: used to calculate offset/shift/mask of each field */ |
363 | struct amap_eq_context { |
364 | u8 cidx[13]; /* dword 0*/ |
365 | u8 rsvd0[3]; /* dword 0*/ |
366 | u8 epidx[13]; /* dword 0*/ |
367 | u8 valid; /* dword 0*/ |
368 | u8 rsvd1; /* dword 0*/ |
369 | u8 size; /* dword 0*/ |
370 | u8 pidx[13]; /* dword 1*/ |
371 | u8 rsvd2[3]; /* dword 1*/ |
372 | u8 pd[10]; /* dword 1*/ |
373 | u8 count[3]; /* dword 1*/ |
374 | u8 solevent; /* dword 1*/ |
375 | u8 stalled; /* dword 1*/ |
376 | u8 armed; /* dword 1*/ |
377 | u8 rsvd3[4]; /* dword 2*/ |
378 | u8 func[8]; /* dword 2*/ |
379 | u8 rsvd4; /* dword 2*/ |
380 | u8 delaymult[10]; /* dword 2*/ |
381 | u8 rsvd5[2]; /* dword 2*/ |
382 | u8 phase[2]; /* dword 2*/ |
383 | u8 nodelay; /* dword 2*/ |
384 | u8 rsvd6[4]; /* dword 2*/ |
385 | u8 rsvd7[32]; /* dword 3*/ |
386 | } __packed; |
387 | |
388 | struct be_cmd_req_eq_create { |
389 | struct be_cmd_req_hdr hdr; |
390 | u16 num_pages; /* sword */ |
391 | u16 rsvd0; /* sword */ |
392 | u8 context[sizeof(struct amap_eq_context) / 8]; |
393 | struct phys_addr pages[8]; |
394 | } __packed; |
395 | |
396 | struct be_cmd_resp_eq_create { |
397 | struct be_cmd_resp_hdr resp_hdr; |
398 | u16 eq_id; /* sword */ |
399 | u16 msix_idx; /* available only in v2 */ |
400 | } __packed; |
401 | |
402 | /******************** Mac query ***************************/ |
403 | enum { |
404 | MAC_ADDRESS_TYPE_STORAGE = 0x0, |
405 | MAC_ADDRESS_TYPE_NETWORK = 0x1, |
406 | MAC_ADDRESS_TYPE_PD = 0x2, |
407 | MAC_ADDRESS_TYPE_MANAGEMENT = 0x3 |
408 | }; |
409 | |
410 | struct mac_addr { |
411 | u16 size_of_struct; |
412 | u8 addr[ETH_ALEN]; |
413 | } __packed; |
414 | |
415 | struct be_cmd_req_mac_query { |
416 | struct be_cmd_req_hdr hdr; |
417 | u8 type; |
418 | u8 permanent; |
419 | u16 if_id; |
420 | u32 pmac_id; |
421 | } __packed; |
422 | |
423 | struct be_cmd_resp_mac_query { |
424 | struct be_cmd_resp_hdr hdr; |
425 | struct mac_addr mac; |
426 | }; |
427 | |
428 | /******************** PMac Add ***************************/ |
429 | struct be_cmd_req_pmac_add { |
430 | struct be_cmd_req_hdr hdr; |
431 | u32 if_id; |
432 | u8 mac_address[ETH_ALEN]; |
433 | u8 rsvd0[2]; |
434 | } __packed; |
435 | |
436 | struct be_cmd_resp_pmac_add { |
437 | struct be_cmd_resp_hdr hdr; |
438 | u32 pmac_id; |
439 | }; |
440 | |
441 | /******************** PMac Del ***************************/ |
442 | struct be_cmd_req_pmac_del { |
443 | struct be_cmd_req_hdr hdr; |
444 | u32 if_id; |
445 | u32 pmac_id; |
446 | }; |
447 | |
448 | /******************** Create CQ ***************************/ |
449 | /* Pseudo amap definition in which each bit of the actual structure is defined |
450 | * as a byte: used to calculate offset/shift/mask of each field */ |
451 | struct amap_cq_context_be { |
452 | u8 cidx[11]; /* dword 0*/ |
453 | u8 rsvd0; /* dword 0*/ |
454 | u8 coalescwm[2]; /* dword 0*/ |
455 | u8 nodelay; /* dword 0*/ |
456 | u8 epidx[11]; /* dword 0*/ |
457 | u8 rsvd1; /* dword 0*/ |
458 | u8 count[2]; /* dword 0*/ |
459 | u8 valid; /* dword 0*/ |
460 | u8 solevent; /* dword 0*/ |
461 | u8 eventable; /* dword 0*/ |
462 | u8 pidx[11]; /* dword 1*/ |
463 | u8 rsvd2; /* dword 1*/ |
464 | u8 pd[10]; /* dword 1*/ |
465 | u8 eqid[8]; /* dword 1*/ |
466 | u8 stalled; /* dword 1*/ |
467 | u8 armed; /* dword 1*/ |
468 | u8 rsvd3[4]; /* dword 2*/ |
469 | u8 func[8]; /* dword 2*/ |
470 | u8 rsvd4[20]; /* dword 2*/ |
471 | u8 rsvd5[32]; /* dword 3*/ |
472 | } __packed; |
473 | |
474 | struct amap_cq_context_v2 { |
475 | u8 rsvd0[12]; /* dword 0*/ |
476 | u8 coalescwm[2]; /* dword 0*/ |
477 | u8 nodelay; /* dword 0*/ |
478 | u8 rsvd1[12]; /* dword 0*/ |
479 | u8 count[2]; /* dword 0*/ |
480 | u8 valid; /* dword 0*/ |
481 | u8 rsvd2; /* dword 0*/ |
482 | u8 eventable; /* dword 0*/ |
483 | u8 eqid[16]; /* dword 1*/ |
484 | u8 rsvd3[15]; /* dword 1*/ |
485 | u8 armed; /* dword 1*/ |
486 | u8 rsvd4[32]; /* dword 2*/ |
487 | u8 rsvd5[32]; /* dword 3*/ |
488 | } __packed; |
489 | |
490 | struct be_cmd_req_cq_create { |
491 | struct be_cmd_req_hdr hdr; |
492 | u16 num_pages; |
493 | u8 page_size; |
494 | u8 rsvd0; |
495 | u8 context[sizeof(struct amap_cq_context_be) / 8]; |
496 | struct phys_addr pages[8]; |
497 | } __packed; |
498 | |
499 | |
500 | struct be_cmd_resp_cq_create { |
501 | struct be_cmd_resp_hdr hdr; |
502 | u16 cq_id; |
503 | u16 rsvd0; |
504 | } __packed; |
505 | |
506 | struct be_cmd_req_get_fat { |
507 | struct be_cmd_req_hdr hdr; |
508 | u32 fat_operation; |
509 | u32 read_log_offset; |
510 | u32 read_log_length; |
511 | u32 data_buffer_size; |
512 | u32 data_buffer[1]; |
513 | } __packed; |
514 | |
515 | struct be_cmd_resp_get_fat { |
516 | struct be_cmd_resp_hdr hdr; |
517 | u32 log_size; |
518 | u32 read_log_length; |
519 | u32 rsvd[2]; |
520 | u32 data_buffer[1]; |
521 | } __packed; |
522 | |
523 | |
524 | /******************** Create MCCQ ***************************/ |
525 | /* Pseudo amap definition in which each bit of the actual structure is defined |
526 | * as a byte: used to calculate offset/shift/mask of each field */ |
527 | struct amap_mcc_context_be { |
528 | u8 con_index[14]; |
529 | u8 rsvd0[2]; |
530 | u8 ring_size[4]; |
531 | u8 fetch_wrb; |
532 | u8 fetch_r2t; |
533 | u8 cq_id[10]; |
534 | u8 prod_index[14]; |
535 | u8 fid[8]; |
536 | u8 pdid[9]; |
537 | u8 valid; |
538 | u8 rsvd1[32]; |
539 | u8 rsvd2[32]; |
540 | } __packed; |
541 | |
542 | struct amap_mcc_context_v1 { |
543 | u8 async_cq_id[16]; |
544 | u8 ring_size[4]; |
545 | u8 rsvd0[12]; |
546 | u8 rsvd1[31]; |
547 | u8 valid; |
548 | u8 async_cq_valid[1]; |
549 | u8 rsvd2[31]; |
550 | u8 rsvd3[32]; |
551 | } __packed; |
552 | |
553 | struct be_cmd_req_mcc_create { |
554 | struct be_cmd_req_hdr hdr; |
555 | u16 num_pages; |
556 | u16 cq_id; |
557 | u8 context[sizeof(struct amap_mcc_context_be) / 8]; |
558 | struct phys_addr pages[8]; |
559 | } __packed; |
560 | |
561 | struct be_cmd_req_mcc_ext_create { |
562 | struct be_cmd_req_hdr hdr; |
563 | u16 num_pages; |
564 | u16 cq_id; |
565 | u32 async_event_bitmap[1]; |
566 | u8 context[sizeof(struct amap_mcc_context_v1) / 8]; |
567 | struct phys_addr pages[8]; |
568 | } __packed; |
569 | |
570 | struct be_cmd_resp_mcc_create { |
571 | struct be_cmd_resp_hdr hdr; |
572 | u16 id; |
573 | u16 rsvd0; |
574 | } __packed; |
575 | |
576 | /******************** Create TxQ ***************************/ |
577 | #define BE_ETH_TX_RING_TYPE_STANDARD 2 |
578 | #define BE_ULP1_NUM 1 |
579 | |
580 | struct be_cmd_req_eth_tx_create { |
581 | struct be_cmd_req_hdr hdr; |
582 | u8 num_pages; |
583 | u8 ulp_num; |
584 | u16 type; |
585 | u16 if_id; |
586 | u8 queue_size; |
587 | u8 rsvd0; |
588 | u32 rsvd1; |
589 | u16 cq_id; |
590 | u16 rsvd2; |
591 | u32 rsvd3[13]; |
592 | struct phys_addr pages[8]; |
593 | } __packed; |
594 | |
595 | struct be_cmd_resp_eth_tx_create { |
596 | struct be_cmd_resp_hdr hdr; |
597 | u16 cid; |
598 | u16 rid; |
599 | u32 db_offset; |
600 | u32 rsvd0[4]; |
601 | } __packed; |
602 | |
603 | /******************** Create RxQ ***************************/ |
604 | struct be_cmd_req_eth_rx_create { |
605 | struct be_cmd_req_hdr hdr; |
606 | u16 cq_id; |
607 | u8 frag_size; |
608 | u8 num_pages; |
609 | struct phys_addr pages[2]; |
610 | u32 interface_id; |
611 | u16 max_frame_size; |
612 | u16 rsvd0; |
613 | u32 ; |
614 | } __packed; |
615 | |
616 | struct be_cmd_resp_eth_rx_create { |
617 | struct be_cmd_resp_hdr hdr; |
618 | u16 id; |
619 | u8 ; |
620 | u8 rsvd0; |
621 | } __packed; |
622 | |
623 | /******************** Q Destroy ***************************/ |
624 | /* Type of Queue to be destroyed */ |
625 | enum { |
626 | QTYPE_EQ = 1, |
627 | QTYPE_CQ, |
628 | QTYPE_TXQ, |
629 | QTYPE_RXQ, |
630 | QTYPE_MCCQ |
631 | }; |
632 | |
633 | struct be_cmd_req_q_destroy { |
634 | struct be_cmd_req_hdr hdr; |
635 | u16 id; |
636 | u16 bypass_flush; /* valid only for rx q destroy */ |
637 | } __packed; |
638 | |
639 | /************ I/f Create (it's actually I/f Config Create)**********/ |
640 | |
641 | /* Capability flags for the i/f */ |
642 | enum be_if_flags { |
643 | = 0x4, |
644 | BE_IF_FLAGS_PROMISCUOUS = 0x8, |
645 | BE_IF_FLAGS_BROADCAST = 0x10, |
646 | BE_IF_FLAGS_UNTAGGED = 0x20, |
647 | BE_IF_FLAGS_ULP = 0x40, |
648 | BE_IF_FLAGS_VLAN_PROMISCUOUS = 0x80, |
649 | BE_IF_FLAGS_VLAN = 0x100, |
650 | BE_IF_FLAGS_MCAST_PROMISCUOUS = 0x200, |
651 | BE_IF_FLAGS_PASS_L2_ERRORS = 0x400, |
652 | BE_IF_FLAGS_PASS_L3L4_ERRORS = 0x800, |
653 | BE_IF_FLAGS_MULTICAST = 0x1000, |
654 | = 0x1000000 |
655 | }; |
656 | |
657 | #define BE_IF_CAP_FLAGS_WANT (BE_IF_FLAGS_RSS | BE_IF_FLAGS_PROMISCUOUS |\ |
658 | BE_IF_FLAGS_BROADCAST | BE_IF_FLAGS_VLAN_PROMISCUOUS |\ |
659 | BE_IF_FLAGS_VLAN | BE_IF_FLAGS_MCAST_PROMISCUOUS |\ |
660 | BE_IF_FLAGS_PASS_L3L4_ERRORS | BE_IF_FLAGS_MULTICAST |\ |
661 | BE_IF_FLAGS_UNTAGGED | BE_IF_FLAGS_DEFQ_RSS) |
662 | |
663 | #define BE_IF_FLAGS_ALL_PROMISCUOUS (BE_IF_FLAGS_PROMISCUOUS | \ |
664 | BE_IF_FLAGS_VLAN_PROMISCUOUS |\ |
665 | BE_IF_FLAGS_MCAST_PROMISCUOUS) |
666 | |
667 | #define BE_IF_FILT_FLAGS_BASIC (BE_IF_FLAGS_BROADCAST | \ |
668 | BE_IF_FLAGS_PASS_L3L4_ERRORS | \ |
669 | BE_IF_FLAGS_UNTAGGED) |
670 | |
671 | #define BE_IF_ALL_FILT_FLAGS (BE_IF_FILT_FLAGS_BASIC | \ |
672 | BE_IF_FLAGS_MULTICAST | \ |
673 | BE_IF_FLAGS_ALL_PROMISCUOUS) |
674 | |
675 | /* An RX interface is an object with one or more MAC addresses and |
676 | * filtering capabilities. */ |
677 | struct be_cmd_req_if_create { |
678 | struct be_cmd_req_hdr hdr; |
679 | u32 version; /* ignore currently */ |
680 | u32 capability_flags; |
681 | u32 enable_flags; |
682 | u8 mac_addr[ETH_ALEN]; |
683 | u8 rsvd0; |
684 | u8 pmac_invalid; /* if set, don't attach the mac addr to the i/f */ |
685 | u32 vlan_tag; /* not used currently */ |
686 | } __packed; |
687 | |
688 | struct be_cmd_resp_if_create { |
689 | struct be_cmd_resp_hdr hdr; |
690 | u32 interface_id; |
691 | u32 pmac_id; |
692 | }; |
693 | |
694 | /****** I/f Destroy(it's actually I/f Config Destroy )**********/ |
695 | struct be_cmd_req_if_destroy { |
696 | struct be_cmd_req_hdr hdr; |
697 | u32 interface_id; |
698 | }; |
699 | |
700 | /*************** HW Stats Get **********************************/ |
701 | struct be_port_rxf_stats_v0 { |
702 | u32 rx_bytes_lsd; /* dword 0*/ |
703 | u32 rx_bytes_msd; /* dword 1*/ |
704 | u32 rx_total_frames; /* dword 2*/ |
705 | u32 rx_unicast_frames; /* dword 3*/ |
706 | u32 rx_multicast_frames; /* dword 4*/ |
707 | u32 rx_broadcast_frames; /* dword 5*/ |
708 | u32 rx_crc_errors; /* dword 6*/ |
709 | u32 rx_alignment_symbol_errors; /* dword 7*/ |
710 | u32 rx_pause_frames; /* dword 8*/ |
711 | u32 rx_control_frames; /* dword 9*/ |
712 | u32 rx_in_range_errors; /* dword 10*/ |
713 | u32 rx_out_range_errors; /* dword 11*/ |
714 | u32 rx_frame_too_long; /* dword 12*/ |
715 | u32 rx_address_filtered; /* dword 13*/ |
716 | u32 rx_vlan_filtered; /* dword 14*/ |
717 | u32 rx_dropped_too_small; /* dword 15*/ |
718 | u32 rx_dropped_too_short; /* dword 16*/ |
719 | u32 ; /* dword 17*/ |
720 | u32 rx_dropped_tcp_length; /* dword 18*/ |
721 | u32 rx_dropped_runt; /* dword 19*/ |
722 | u32 rx_64_byte_packets; /* dword 20*/ |
723 | u32 rx_65_127_byte_packets; /* dword 21*/ |
724 | u32 rx_128_256_byte_packets; /* dword 22*/ |
725 | u32 rx_256_511_byte_packets; /* dword 23*/ |
726 | u32 rx_512_1023_byte_packets; /* dword 24*/ |
727 | u32 rx_1024_1518_byte_packets; /* dword 25*/ |
728 | u32 rx_1519_2047_byte_packets; /* dword 26*/ |
729 | u32 rx_2048_4095_byte_packets; /* dword 27*/ |
730 | u32 rx_4096_8191_byte_packets; /* dword 28*/ |
731 | u32 rx_8192_9216_byte_packets; /* dword 29*/ |
732 | u32 rx_ip_checksum_errs; /* dword 30*/ |
733 | u32 rx_tcp_checksum_errs; /* dword 31*/ |
734 | u32 rx_udp_checksum_errs; /* dword 32*/ |
735 | u32 ; /* dword 33*/ |
736 | u32 rx_ipv4_packets; /* dword 34*/ |
737 | u32 rx_ipv6_packets; /* dword 35*/ |
738 | u32 rx_ipv4_bytes_lsd; /* dword 36*/ |
739 | u32 rx_ipv4_bytes_msd; /* dword 37*/ |
740 | u32 rx_ipv6_bytes_lsd; /* dword 38*/ |
741 | u32 rx_ipv6_bytes_msd; /* dword 39*/ |
742 | u32 rx_chute1_packets; /* dword 40*/ |
743 | u32 rx_chute2_packets; /* dword 41*/ |
744 | u32 rx_chute3_packets; /* dword 42*/ |
745 | u32 rx_management_packets; /* dword 43*/ |
746 | u32 rx_switched_unicast_packets; /* dword 44*/ |
747 | u32 rx_switched_multicast_packets; /* dword 45*/ |
748 | u32 rx_switched_broadcast_packets; /* dword 46*/ |
749 | u32 tx_bytes_lsd; /* dword 47*/ |
750 | u32 tx_bytes_msd; /* dword 48*/ |
751 | u32 tx_unicastframes; /* dword 49*/ |
752 | u32 tx_multicastframes; /* dword 50*/ |
753 | u32 tx_broadcastframes; /* dword 51*/ |
754 | u32 tx_pauseframes; /* dword 52*/ |
755 | u32 tx_controlframes; /* dword 53*/ |
756 | u32 tx_64_byte_packets; /* dword 54*/ |
757 | u32 tx_65_127_byte_packets; /* dword 55*/ |
758 | u32 tx_128_256_byte_packets; /* dword 56*/ |
759 | u32 tx_256_511_byte_packets; /* dword 57*/ |
760 | u32 tx_512_1023_byte_packets; /* dword 58*/ |
761 | u32 tx_1024_1518_byte_packets; /* dword 59*/ |
762 | u32 tx_1519_2047_byte_packets; /* dword 60*/ |
763 | u32 tx_2048_4095_byte_packets; /* dword 61*/ |
764 | u32 tx_4096_8191_byte_packets; /* dword 62*/ |
765 | u32 tx_8192_9216_byte_packets; /* dword 63*/ |
766 | u32 rx_fifo_overflow; /* dword 64*/ |
767 | u32 rx_input_fifo_overflow; /* dword 65*/ |
768 | }; |
769 | |
770 | struct be_rxf_stats_v0 { |
771 | struct be_port_rxf_stats_v0 port[2]; |
772 | u32 rx_drops_no_pbuf; /* dword 132*/ |
773 | u32 rx_drops_no_txpb; /* dword 133*/ |
774 | u32 rx_drops_no_erx_descr; /* dword 134*/ |
775 | u32 rx_drops_no_tpre_descr; /* dword 135*/ |
776 | u32 management_rx_port_packets; /* dword 136*/ |
777 | u32 management_rx_port_bytes; /* dword 137*/ |
778 | u32 management_rx_port_pause_frames; /* dword 138*/ |
779 | u32 management_rx_port_errors; /* dword 139*/ |
780 | u32 management_tx_port_packets; /* dword 140*/ |
781 | u32 management_tx_port_bytes; /* dword 141*/ |
782 | u32 management_tx_port_pause; /* dword 142*/ |
783 | u32 management_rx_port_rxfifo_overflow; /* dword 143*/ |
784 | u32 rx_drops_too_many_frags; /* dword 144*/ |
785 | u32 rx_drops_invalid_ring; /* dword 145*/ |
786 | u32 forwarded_packets; /* dword 146*/ |
787 | u32 rx_drops_mtu; /* dword 147*/ |
788 | u32 rsvd0[7]; |
789 | u32 port0_jabber_events; |
790 | u32 port1_jabber_events; |
791 | u32 rsvd1[6]; |
792 | }; |
793 | |
794 | struct be_erx_stats_v0 { |
795 | u32 rx_drops_no_fragments[44]; /* dwordS 0 to 43*/ |
796 | u32 rsvd[4]; |
797 | }; |
798 | |
799 | struct be_pmem_stats { |
800 | u32 eth_red_drops; |
801 | u32 rsvd[5]; |
802 | }; |
803 | |
804 | struct be_hw_stats_v0 { |
805 | struct be_rxf_stats_v0 rxf; |
806 | u32 rsvd[48]; |
807 | struct be_erx_stats_v0 erx; |
808 | struct be_pmem_stats pmem; |
809 | }; |
810 | |
811 | struct be_cmd_req_get_stats_v0 { |
812 | struct be_cmd_req_hdr hdr; |
813 | u8 rsvd[sizeof(struct be_hw_stats_v0)]; |
814 | }; |
815 | |
816 | struct be_cmd_resp_get_stats_v0 { |
817 | struct be_cmd_resp_hdr hdr; |
818 | struct be_hw_stats_v0 hw_stats; |
819 | }; |
820 | |
821 | struct lancer_pport_stats { |
822 | u32 tx_packets_lo; |
823 | u32 tx_packets_hi; |
824 | u32 tx_unicast_packets_lo; |
825 | u32 tx_unicast_packets_hi; |
826 | u32 tx_multicast_packets_lo; |
827 | u32 tx_multicast_packets_hi; |
828 | u32 tx_broadcast_packets_lo; |
829 | u32 tx_broadcast_packets_hi; |
830 | u32 tx_bytes_lo; |
831 | u32 tx_bytes_hi; |
832 | u32 tx_unicast_bytes_lo; |
833 | u32 tx_unicast_bytes_hi; |
834 | u32 tx_multicast_bytes_lo; |
835 | u32 tx_multicast_bytes_hi; |
836 | u32 tx_broadcast_bytes_lo; |
837 | u32 tx_broadcast_bytes_hi; |
838 | u32 tx_discards_lo; |
839 | u32 tx_discards_hi; |
840 | u32 tx_errors_lo; |
841 | u32 tx_errors_hi; |
842 | u32 tx_pause_frames_lo; |
843 | u32 tx_pause_frames_hi; |
844 | u32 tx_pause_on_frames_lo; |
845 | u32 tx_pause_on_frames_hi; |
846 | u32 tx_pause_off_frames_lo; |
847 | u32 tx_pause_off_frames_hi; |
848 | u32 tx_internal_mac_errors_lo; |
849 | u32 tx_internal_mac_errors_hi; |
850 | u32 tx_control_frames_lo; |
851 | u32 tx_control_frames_hi; |
852 | u32 tx_packets_64_bytes_lo; |
853 | u32 tx_packets_64_bytes_hi; |
854 | u32 tx_packets_65_to_127_bytes_lo; |
855 | u32 tx_packets_65_to_127_bytes_hi; |
856 | u32 tx_packets_128_to_255_bytes_lo; |
857 | u32 tx_packets_128_to_255_bytes_hi; |
858 | u32 tx_packets_256_to_511_bytes_lo; |
859 | u32 tx_packets_256_to_511_bytes_hi; |
860 | u32 tx_packets_512_to_1023_bytes_lo; |
861 | u32 tx_packets_512_to_1023_bytes_hi; |
862 | u32 tx_packets_1024_to_1518_bytes_lo; |
863 | u32 tx_packets_1024_to_1518_bytes_hi; |
864 | u32 tx_packets_1519_to_2047_bytes_lo; |
865 | u32 tx_packets_1519_to_2047_bytes_hi; |
866 | u32 tx_packets_2048_to_4095_bytes_lo; |
867 | u32 tx_packets_2048_to_4095_bytes_hi; |
868 | u32 tx_packets_4096_to_8191_bytes_lo; |
869 | u32 tx_packets_4096_to_8191_bytes_hi; |
870 | u32 tx_packets_8192_to_9216_bytes_lo; |
871 | u32 tx_packets_8192_to_9216_bytes_hi; |
872 | u32 tx_lso_packets_lo; |
873 | u32 tx_lso_packets_hi; |
874 | u32 rx_packets_lo; |
875 | u32 rx_packets_hi; |
876 | u32 rx_unicast_packets_lo; |
877 | u32 rx_unicast_packets_hi; |
878 | u32 rx_multicast_packets_lo; |
879 | u32 rx_multicast_packets_hi; |
880 | u32 rx_broadcast_packets_lo; |
881 | u32 rx_broadcast_packets_hi; |
882 | u32 rx_bytes_lo; |
883 | u32 rx_bytes_hi; |
884 | u32 rx_unicast_bytes_lo; |
885 | u32 rx_unicast_bytes_hi; |
886 | u32 rx_multicast_bytes_lo; |
887 | u32 rx_multicast_bytes_hi; |
888 | u32 rx_broadcast_bytes_lo; |
889 | u32 rx_broadcast_bytes_hi; |
890 | u32 rx_unknown_protos; |
891 | u32 rsvd_69; /* Word 69 is reserved */ |
892 | u32 rx_discards_lo; |
893 | u32 rx_discards_hi; |
894 | u32 rx_errors_lo; |
895 | u32 rx_errors_hi; |
896 | u32 rx_crc_errors_lo; |
897 | u32 rx_crc_errors_hi; |
898 | u32 rx_alignment_errors_lo; |
899 | u32 rx_alignment_errors_hi; |
900 | u32 rx_symbol_errors_lo; |
901 | u32 rx_symbol_errors_hi; |
902 | u32 rx_pause_frames_lo; |
903 | u32 rx_pause_frames_hi; |
904 | u32 rx_pause_on_frames_lo; |
905 | u32 rx_pause_on_frames_hi; |
906 | u32 rx_pause_off_frames_lo; |
907 | u32 rx_pause_off_frames_hi; |
908 | u32 rx_frames_too_long_lo; |
909 | u32 rx_frames_too_long_hi; |
910 | u32 rx_internal_mac_errors_lo; |
911 | u32 rx_internal_mac_errors_hi; |
912 | u32 rx_undersize_packets; |
913 | u32 rx_oversize_packets; |
914 | u32 rx_fragment_packets; |
915 | u32 rx_jabbers; |
916 | u32 rx_control_frames_lo; |
917 | u32 rx_control_frames_hi; |
918 | u32 rx_control_frames_unknown_opcode_lo; |
919 | u32 rx_control_frames_unknown_opcode_hi; |
920 | u32 rx_in_range_errors; |
921 | u32 rx_out_of_range_errors; |
922 | u32 rx_address_filtered; |
923 | u32 rx_vlan_filtered; |
924 | u32 rx_dropped_too_small; |
925 | u32 rx_dropped_too_short; |
926 | u32 ; |
927 | u32 rx_dropped_invalid_tcp_length; |
928 | u32 rx_dropped_runt; |
929 | u32 rx_ip_checksum_errors; |
930 | u32 rx_tcp_checksum_errors; |
931 | u32 rx_udp_checksum_errors; |
932 | u32 ; |
933 | u32 rsvd_111; |
934 | u32 rx_ipv4_packets_lo; |
935 | u32 rx_ipv4_packets_hi; |
936 | u32 rx_ipv6_packets_lo; |
937 | u32 rx_ipv6_packets_hi; |
938 | u32 rx_ipv4_bytes_lo; |
939 | u32 rx_ipv4_bytes_hi; |
940 | u32 rx_ipv6_bytes_lo; |
941 | u32 rx_ipv6_bytes_hi; |
942 | u32 rx_nic_packets_lo; |
943 | u32 rx_nic_packets_hi; |
944 | u32 rx_tcp_packets_lo; |
945 | u32 rx_tcp_packets_hi; |
946 | u32 rx_iscsi_packets_lo; |
947 | u32 rx_iscsi_packets_hi; |
948 | u32 rx_management_packets_lo; |
949 | u32 rx_management_packets_hi; |
950 | u32 rx_switched_unicast_packets_lo; |
951 | u32 rx_switched_unicast_packets_hi; |
952 | u32 rx_switched_multicast_packets_lo; |
953 | u32 rx_switched_multicast_packets_hi; |
954 | u32 rx_switched_broadcast_packets_lo; |
955 | u32 rx_switched_broadcast_packets_hi; |
956 | u32 num_forwards_lo; |
957 | u32 num_forwards_hi; |
958 | u32 rx_fifo_overflow; |
959 | u32 rx_input_fifo_overflow; |
960 | u32 rx_drops_too_many_frags_lo; |
961 | u32 rx_drops_too_many_frags_hi; |
962 | u32 rx_drops_invalid_queue; |
963 | u32 rsvd_141; |
964 | u32 rx_drops_mtu_lo; |
965 | u32 rx_drops_mtu_hi; |
966 | u32 rx_packets_64_bytes_lo; |
967 | u32 rx_packets_64_bytes_hi; |
968 | u32 rx_packets_65_to_127_bytes_lo; |
969 | u32 rx_packets_65_to_127_bytes_hi; |
970 | u32 rx_packets_128_to_255_bytes_lo; |
971 | u32 rx_packets_128_to_255_bytes_hi; |
972 | u32 rx_packets_256_to_511_bytes_lo; |
973 | u32 rx_packets_256_to_511_bytes_hi; |
974 | u32 rx_packets_512_to_1023_bytes_lo; |
975 | u32 rx_packets_512_to_1023_bytes_hi; |
976 | u32 rx_packets_1024_to_1518_bytes_lo; |
977 | u32 rx_packets_1024_to_1518_bytes_hi; |
978 | u32 rx_packets_1519_to_2047_bytes_lo; |
979 | u32 rx_packets_1519_to_2047_bytes_hi; |
980 | u32 rx_packets_2048_to_4095_bytes_lo; |
981 | u32 rx_packets_2048_to_4095_bytes_hi; |
982 | u32 rx_packets_4096_to_8191_bytes_lo; |
983 | u32 rx_packets_4096_to_8191_bytes_hi; |
984 | u32 rx_packets_8192_to_9216_bytes_lo; |
985 | u32 rx_packets_8192_to_9216_bytes_hi; |
986 | }; |
987 | |
988 | struct pport_stats_params { |
989 | u16 pport_num; |
990 | u8 rsvd; |
991 | u8 reset_stats; |
992 | }; |
993 | |
994 | struct lancer_cmd_req_pport_stats { |
995 | struct be_cmd_req_hdr hdr; |
996 | union { |
997 | struct pport_stats_params params; |
998 | u8 rsvd[sizeof(struct lancer_pport_stats)]; |
999 | } cmd_params; |
1000 | }; |
1001 | |
1002 | struct lancer_cmd_resp_pport_stats { |
1003 | struct be_cmd_resp_hdr hdr; |
1004 | struct lancer_pport_stats pport_stats; |
1005 | }; |
1006 | |
1007 | static inline struct lancer_pport_stats* |
1008 | pport_stats_from_cmd(struct be_adapter *adapter) |
1009 | { |
1010 | struct lancer_cmd_resp_pport_stats *cmd = adapter->stats_cmd.va; |
1011 | return &cmd->pport_stats; |
1012 | } |
1013 | |
1014 | struct be_cmd_req_get_cntl_addnl_attribs { |
1015 | struct be_cmd_req_hdr hdr; |
1016 | u8 rsvd[8]; |
1017 | }; |
1018 | |
1019 | struct be_cmd_resp_get_cntl_addnl_attribs { |
1020 | struct be_cmd_resp_hdr hdr; |
1021 | u16 ipl_file_number; |
1022 | u8 ipl_file_version; |
1023 | u8 rsvd0; |
1024 | u8 on_die_temperature; /* in degrees centigrade*/ |
1025 | u8 rsvd1[3]; |
1026 | }; |
1027 | |
1028 | struct be_cmd_req_vlan_config { |
1029 | struct be_cmd_req_hdr hdr; |
1030 | u8 interface_id; |
1031 | u8 promiscuous; |
1032 | u8 untagged; |
1033 | u8 num_vlan; |
1034 | u16 normal_vlan[64]; |
1035 | } __packed; |
1036 | |
1037 | /******************* RX FILTER ******************************/ |
1038 | #define BE_MAX_MC 64 /* set mcast promisc if > 64 */ |
1039 | struct macaddr { |
1040 | u8 byte[ETH_ALEN]; |
1041 | }; |
1042 | |
1043 | struct be_cmd_req_rx_filter { |
1044 | struct be_cmd_req_hdr hdr; |
1045 | u32 global_flags_mask; |
1046 | u32 global_flags; |
1047 | u32 if_flags_mask; |
1048 | u32 if_flags; |
1049 | u32 if_id; |
1050 | u32 mcast_num; |
1051 | struct macaddr mcast_mac[BE_MAX_MC]; |
1052 | }; |
1053 | |
1054 | /******************** Link Status Query *******************/ |
1055 | struct be_cmd_req_link_status { |
1056 | struct be_cmd_req_hdr hdr; |
1057 | u32 rsvd; |
1058 | }; |
1059 | |
1060 | enum { |
1061 | PHY_LINK_DUPLEX_NONE = 0x0, |
1062 | PHY_LINK_DUPLEX_HALF = 0x1, |
1063 | PHY_LINK_DUPLEX_FULL = 0x2 |
1064 | }; |
1065 | |
1066 | enum { |
1067 | PHY_LINK_SPEED_ZERO = 0x0, /* => No link */ |
1068 | PHY_LINK_SPEED_10MBPS = 0x1, |
1069 | PHY_LINK_SPEED_100MBPS = 0x2, |
1070 | PHY_LINK_SPEED_1GBPS = 0x3, |
1071 | PHY_LINK_SPEED_10GBPS = 0x4, |
1072 | PHY_LINK_SPEED_20GBPS = 0x5, |
1073 | PHY_LINK_SPEED_25GBPS = 0x6, |
1074 | PHY_LINK_SPEED_40GBPS = 0x7 |
1075 | }; |
1076 | |
1077 | struct be_cmd_resp_link_status { |
1078 | struct be_cmd_resp_hdr hdr; |
1079 | u8 physical_port; |
1080 | u8 mac_duplex; |
1081 | u8 mac_speed; |
1082 | u8 mac_fault; |
1083 | u8 mgmt_mac_duplex; |
1084 | u8 mgmt_mac_speed; |
1085 | u16 link_speed; |
1086 | u8 logical_link_status; |
1087 | u8 rsvd1[3]; |
1088 | } __packed; |
1089 | |
1090 | /******************** Port Identification ***************************/ |
1091 | /* Identifies the type of port attached to NIC */ |
1092 | struct be_cmd_req_port_type { |
1093 | struct be_cmd_req_hdr hdr; |
1094 | __le32 page_num; |
1095 | __le32 port; |
1096 | }; |
1097 | |
1098 | enum { |
1099 | TR_PAGE_A0 = 0xa0, |
1100 | TR_PAGE_A2 = 0xa2 |
1101 | }; |
1102 | |
1103 | /* From SFF-8436 QSFP+ spec */ |
1104 | #define QSFP_PLUS_CABLE_TYPE_OFFSET 0x83 |
1105 | #define QSFP_PLUS_CR4_CABLE 0x8 |
1106 | #define QSFP_PLUS_SR4_CABLE 0x4 |
1107 | #define QSFP_PLUS_LR4_CABLE 0x2 |
1108 | |
1109 | /* From SFF-8472 spec */ |
1110 | #define SFP_PLUS_SFF_8472_COMP 0x5E |
1111 | #define SFP_PLUS_CABLE_TYPE_OFFSET 0x8 |
1112 | #define SFP_PLUS_COPPER_CABLE 0x4 |
1113 | #define SFP_VENDOR_NAME_OFFSET 0x14 |
1114 | #define SFP_VENDOR_PN_OFFSET 0x28 |
1115 | |
1116 | #define PAGE_DATA_LEN 256 |
1117 | struct be_cmd_resp_port_type { |
1118 | struct be_cmd_resp_hdr hdr; |
1119 | u32 page_num; |
1120 | u32 port; |
1121 | u8 page_data[PAGE_DATA_LEN]; |
1122 | }; |
1123 | |
1124 | /******************** Get FW Version *******************/ |
1125 | struct be_cmd_req_get_fw_version { |
1126 | struct be_cmd_req_hdr hdr; |
1127 | u8 rsvd0[FW_VER_LEN]; |
1128 | u8 rsvd1[FW_VER_LEN]; |
1129 | } __packed; |
1130 | |
1131 | struct be_cmd_resp_get_fw_version { |
1132 | struct be_cmd_resp_hdr hdr; |
1133 | u8 firmware_version_string[FW_VER_LEN]; |
1134 | u8 fw_on_flash_version_string[FW_VER_LEN]; |
1135 | } __packed; |
1136 | |
1137 | /******************** Set Flow Contrl *******************/ |
1138 | struct be_cmd_req_set_flow_control { |
1139 | struct be_cmd_req_hdr hdr; |
1140 | u16 tx_flow_control; |
1141 | u16 rx_flow_control; |
1142 | } __packed; |
1143 | |
1144 | /******************** Get Flow Contrl *******************/ |
1145 | struct be_cmd_req_get_flow_control { |
1146 | struct be_cmd_req_hdr hdr; |
1147 | u32 rsvd; |
1148 | }; |
1149 | |
1150 | struct be_cmd_resp_get_flow_control { |
1151 | struct be_cmd_resp_hdr hdr; |
1152 | u16 tx_flow_control; |
1153 | u16 rx_flow_control; |
1154 | } __packed; |
1155 | |
1156 | /******************** Modify EQ Delay *******************/ |
1157 | struct be_set_eqd { |
1158 | u32 eq_id; |
1159 | u32 phase; |
1160 | u32 delay_multiplier; |
1161 | }; |
1162 | |
1163 | struct be_cmd_req_modify_eq_delay { |
1164 | struct be_cmd_req_hdr hdr; |
1165 | u32 num_eq; |
1166 | struct be_set_eqd set_eqd[MAX_EVT_QS]; |
1167 | } __packed; |
1168 | |
1169 | /******************** Get FW Config *******************/ |
1170 | /* The HW can come up in either of the following multi-channel modes |
1171 | * based on the skew/IPL. |
1172 | */ |
1173 | #define RDMA_ENABLED 0x4 |
1174 | #define QNQ_MODE 0x400 |
1175 | #define VNIC_MODE 0x20000 |
1176 | #define UMC_ENABLED 0x1000000 |
1177 | struct be_cmd_req_query_fw_cfg { |
1178 | struct be_cmd_req_hdr hdr; |
1179 | u32 rsvd[31]; |
1180 | }; |
1181 | |
1182 | struct be_cmd_resp_query_fw_cfg { |
1183 | struct be_cmd_resp_hdr hdr; |
1184 | u32 be_config_number; |
1185 | u32 asic_revision; |
1186 | u32 phys_port; |
1187 | u32 function_mode; |
1188 | u32 rsvd[26]; |
1189 | u32 function_caps; |
1190 | }; |
1191 | |
1192 | /******************** RSS Config ****************************************/ |
1193 | /* RSS type Input parameters used to compute RX hash |
1194 | * RSS_ENABLE_IPV4 SRC IPv4, DST IPv4 |
1195 | * RSS_ENABLE_TCP_IPV4 SRC IPv4, DST IPv4, TCP SRC PORT, TCP DST PORT |
1196 | * RSS_ENABLE_IPV6 SRC IPv6, DST IPv6 |
1197 | * RSS_ENABLE_TCP_IPV6 SRC IPv6, DST IPv6, TCP SRC PORT, TCP DST PORT |
1198 | * RSS_ENABLE_UDP_IPV4 SRC IPv4, DST IPv4, UDP SRC PORT, UDP DST PORT |
1199 | * RSS_ENABLE_UDP_IPV6 SRC IPv6, DST IPv6, UDP SRC PORT, UDP DST PORT |
1200 | * |
1201 | * When multiple RSS types are enabled, HW picks the best hash policy |
1202 | * based on the type of the received packet. |
1203 | */ |
1204 | #define 0x0 |
1205 | #define 0x1 |
1206 | #define 0x2 |
1207 | #define 0x4 |
1208 | #define 0x8 |
1209 | #define 0x10 |
1210 | #define 0x20 |
1211 | |
1212 | #define (RXH_IP_DST | RXH_IP_SRC) |
1213 | #define (RXH_L4_B_0_1 | RXH_L4_B_2_3) |
1214 | |
1215 | struct { |
1216 | struct be_cmd_req_hdr ; |
1217 | u32 ; |
1218 | u16 ; |
1219 | u16 ; |
1220 | u32 [10]; |
1221 | u8 [128]; |
1222 | u8 ; |
1223 | u8 [3]; |
1224 | }; |
1225 | |
1226 | /******************** Port Beacon ***************************/ |
1227 | |
1228 | #define BEACON_STATE_ENABLED 0x1 |
1229 | #define BEACON_STATE_DISABLED 0x0 |
1230 | |
1231 | struct be_cmd_req_enable_disable_beacon { |
1232 | struct be_cmd_req_hdr hdr; |
1233 | u8 port_num; |
1234 | u8 beacon_state; |
1235 | u8 beacon_duration; |
1236 | u8 status_duration; |
1237 | } __packed; |
1238 | |
1239 | struct be_cmd_req_get_beacon_state { |
1240 | struct be_cmd_req_hdr hdr; |
1241 | u8 port_num; |
1242 | u8 rsvd0; |
1243 | u16 rsvd1; |
1244 | } __packed; |
1245 | |
1246 | struct be_cmd_resp_get_beacon_state { |
1247 | struct be_cmd_resp_hdr resp_hdr; |
1248 | u8 beacon_state; |
1249 | u8 rsvd0[3]; |
1250 | } __packed; |
1251 | |
1252 | /* Flashrom related descriptors */ |
1253 | #define MAX_FLASH_COMP 32 |
1254 | |
1255 | /* Optypes of each component in the UFI */ |
1256 | enum { |
1257 | OPTYPE_ISCSI_ACTIVE = 0, |
1258 | OPTYPE_REDBOOT = 1, |
1259 | OPTYPE_BIOS = 2, |
1260 | OPTYPE_PXE_BIOS = 3, |
1261 | OPTYPE_OFFSET_SPECIFIED = 7, |
1262 | OPTYPE_FCOE_BIOS = 8, |
1263 | OPTYPE_ISCSI_BACKUP = 9, |
1264 | OPTYPE_FCOE_FW_ACTIVE = 10, |
1265 | OPTYPE_FCOE_FW_BACKUP = 11, |
1266 | OPTYPE_NCSI_FW = 13, |
1267 | OPTYPE_REDBOOT_DIR = 18, |
1268 | OPTYPE_REDBOOT_CONFIG = 19, |
1269 | OPTYPE_SH_PHY_FW = 21, |
1270 | OPTYPE_FLASHISM_JUMPVECTOR = 22, |
1271 | OPTYPE_UFI_DIR = 23, |
1272 | OPTYPE_PHY_FW = 99 |
1273 | }; |
1274 | |
1275 | /* Maximum sizes of components in BE2 FW UFI */ |
1276 | enum { |
1277 | BE2_BIOS_COMP_MAX_SIZE = 0x40000, |
1278 | BE2_REDBOOT_COMP_MAX_SIZE = 0x40000, |
1279 | BE2_COMP_MAX_SIZE = 0x140000 |
1280 | }; |
1281 | |
1282 | /* Maximum sizes of components in BE3 FW UFI */ |
1283 | enum { |
1284 | BE3_NCSI_COMP_MAX_SIZE = 0x40000, |
1285 | BE3_PHY_FW_COMP_MAX_SIZE = 0x40000, |
1286 | BE3_BIOS_COMP_MAX_SIZE = 0x80000, |
1287 | BE3_REDBOOT_COMP_MAX_SIZE = 0x100000, |
1288 | BE3_COMP_MAX_SIZE = 0x200000 |
1289 | }; |
1290 | |
1291 | /* Offsets for components in BE2 FW UFI */ |
1292 | enum { |
1293 | BE2_REDBOOT_START = 0x8000, |
1294 | BE2_FCOE_BIOS_START = 0x80000, |
1295 | BE2_ISCSI_PRIMARY_IMAGE_START = 0x100000, |
1296 | BE2_ISCSI_BACKUP_IMAGE_START = 0x240000, |
1297 | BE2_FCOE_PRIMARY_IMAGE_START = 0x380000, |
1298 | BE2_FCOE_BACKUP_IMAGE_START = 0x4c0000, |
1299 | BE2_ISCSI_BIOS_START = 0x700000, |
1300 | BE2_PXE_BIOS_START = 0x780000 |
1301 | }; |
1302 | |
1303 | /* Offsets for components in BE3 FW UFI */ |
1304 | enum { |
1305 | BE3_REDBOOT_START = 0x40000, |
1306 | BE3_PHY_FW_START = 0x140000, |
1307 | BE3_ISCSI_PRIMARY_IMAGE_START = 0x200000, |
1308 | BE3_ISCSI_BACKUP_IMAGE_START = 0x400000, |
1309 | BE3_FCOE_PRIMARY_IMAGE_START = 0x600000, |
1310 | BE3_FCOE_BACKUP_IMAGE_START = 0x800000, |
1311 | BE3_ISCSI_BIOS_START = 0xc00000, |
1312 | BE3_PXE_BIOS_START = 0xc80000, |
1313 | BE3_FCOE_BIOS_START = 0xd00000, |
1314 | BE3_NCSI_START = 0xf40000 |
1315 | }; |
1316 | |
1317 | /* Component entry types */ |
1318 | enum { |
1319 | IMAGE_NCSI = 0x10, |
1320 | IMAGE_OPTION_ROM_PXE = 0x20, |
1321 | IMAGE_OPTION_ROM_FCOE = 0x21, |
1322 | IMAGE_OPTION_ROM_ISCSI = 0x22, |
1323 | IMAGE_FLASHISM_JUMPVECTOR = 0x30, |
1324 | IMAGE_FIRMWARE_ISCSI = 0xa0, |
1325 | IMAGE_FIRMWARE_FCOE = 0xa2, |
1326 | IMAGE_FIRMWARE_BACKUP_ISCSI = 0xb0, |
1327 | IMAGE_FIRMWARE_BACKUP_FCOE = 0xb2, |
1328 | IMAGE_FIRMWARE_PHY = 0xc0, |
1329 | IMAGE_REDBOOT_DIR = 0xd0, |
1330 | IMAGE_REDBOOT_CONFIG = 0xd1, |
1331 | IMAGE_UFI_DIR = 0xd2, |
1332 | IMAGE_BOOT_CODE = 0xe2 |
1333 | }; |
1334 | |
1335 | struct controller_id { |
1336 | u32 vendor; |
1337 | u32 device; |
1338 | u32 subvendor; |
1339 | u32 subdevice; |
1340 | }; |
1341 | |
1342 | struct flash_comp { |
1343 | unsigned long offset; |
1344 | int optype; |
1345 | int size; |
1346 | int img_type; |
1347 | }; |
1348 | |
1349 | struct image_hdr { |
1350 | u32 imageid; |
1351 | u32 imageoffset; |
1352 | u32 imagelength; |
1353 | u32 image_checksum; |
1354 | u8 image_version[32]; |
1355 | }; |
1356 | |
1357 | struct flash_file_hdr_g2 { |
1358 | u8 sign[32]; |
1359 | u32 cksum; |
1360 | u32 antidote; |
1361 | struct controller_id cont_id; |
1362 | u32 file_len; |
1363 | u32 chunk_num; |
1364 | u32 total_chunks; |
1365 | u32 num_imgs; |
1366 | u8 build[24]; |
1367 | }; |
1368 | |
1369 | /* First letter of the build version of the image */ |
1370 | #define BLD_STR_UFI_TYPE_BE2 '2' |
1371 | #define BLD_STR_UFI_TYPE_BE3 '3' |
1372 | #define BLD_STR_UFI_TYPE_SH '4' |
1373 | |
1374 | struct flash_file_hdr_g3 { |
1375 | u8 sign[52]; |
1376 | u8 ufi_version[4]; |
1377 | u32 file_len; |
1378 | u32 cksum; |
1379 | u32 antidote; |
1380 | u32 num_imgs; |
1381 | u8 build[24]; |
1382 | u8 asic_type_rev; |
1383 | u8 rsvd[31]; |
1384 | }; |
1385 | |
1386 | struct flash_section_hdr { |
1387 | u32 format_rev; |
1388 | u32 cksum; |
1389 | u32 antidote; |
1390 | u32 num_images; |
1391 | u8 id_string[128]; |
1392 | u32 rsvd[4]; |
1393 | } __packed; |
1394 | |
1395 | struct flash_section_hdr_g2 { |
1396 | u32 format_rev; |
1397 | u32 cksum; |
1398 | u32 antidote; |
1399 | u32 build_num; |
1400 | u8 id_string[128]; |
1401 | u32 rsvd[8]; |
1402 | } __packed; |
1403 | |
1404 | struct flash_section_entry { |
1405 | u32 type; |
1406 | u32 offset; |
1407 | u32 pad_size; |
1408 | u32 image_size; |
1409 | u32 cksum; |
1410 | u32 entry_point; |
1411 | u16 optype; |
1412 | u16 rsvd0; |
1413 | u32 rsvd1; |
1414 | u8 ver_data[32]; |
1415 | } __packed; |
1416 | |
1417 | struct flash_section_info { |
1418 | u8 cookie[32]; |
1419 | struct flash_section_hdr fsec_hdr; |
1420 | struct flash_section_entry fsec_entry[32]; |
1421 | } __packed; |
1422 | |
1423 | struct flash_section_info_g2 { |
1424 | u8 cookie[32]; |
1425 | struct flash_section_hdr_g2 fsec_hdr; |
1426 | struct flash_section_entry fsec_entry[32]; |
1427 | } __packed; |
1428 | |
1429 | /****************** Firmware Flash ******************/ |
1430 | #define FLASHROM_OPER_FLASH 1 |
1431 | #define FLASHROM_OPER_SAVE 2 |
1432 | #define FLASHROM_OPER_REPORT 4 |
1433 | #define FLASHROM_OPER_PHY_FLASH 9 |
1434 | #define FLASHROM_OPER_PHY_SAVE 10 |
1435 | |
1436 | struct flashrom_params { |
1437 | u32 op_code; |
1438 | u32 op_type; |
1439 | u32 data_buf_size; |
1440 | u32 offset; |
1441 | }; |
1442 | |
1443 | struct be_cmd_write_flashrom { |
1444 | struct be_cmd_req_hdr hdr; |
1445 | struct flashrom_params params; |
1446 | u8 data_buf[32768]; |
1447 | u8 rsvd[4]; |
1448 | } __packed; |
1449 | |
1450 | /* cmd to read flash crc */ |
1451 | struct be_cmd_read_flash_crc { |
1452 | struct be_cmd_req_hdr hdr; |
1453 | struct flashrom_params params; |
1454 | u8 crc[4]; |
1455 | u8 rsvd[4]; |
1456 | } __packed; |
1457 | |
1458 | /**************** Lancer Firmware Flash ************/ |
1459 | #define LANCER_FW_DOWNLOAD_CHUNK (32 * 1024) |
1460 | #define LANCER_FW_DOWNLOAD_LOCATION "/prg" |
1461 | |
1462 | struct amap_lancer_write_obj_context { |
1463 | u8 write_length[24]; |
1464 | u8 reserved1[7]; |
1465 | u8 eof; |
1466 | } __packed; |
1467 | |
1468 | struct lancer_cmd_req_write_object { |
1469 | struct be_cmd_req_hdr hdr; |
1470 | u8 context[sizeof(struct amap_lancer_write_obj_context) / 8]; |
1471 | u32 write_offset; |
1472 | u8 object_name[104]; |
1473 | u32 descriptor_count; |
1474 | u32 buf_len; |
1475 | u32 addr_low; |
1476 | u32 addr_high; |
1477 | }; |
1478 | |
1479 | #define LANCER_NO_RESET_NEEDED 0x00 |
1480 | #define LANCER_FW_RESET_NEEDED 0x02 |
1481 | struct lancer_cmd_resp_write_object { |
1482 | u8 opcode; |
1483 | u8 subsystem; |
1484 | u8 rsvd1[2]; |
1485 | u8 status; |
1486 | u8 additional_status; |
1487 | u8 rsvd2[2]; |
1488 | u32 resp_len; |
1489 | u32 actual_resp_len; |
1490 | u32 actual_write_len; |
1491 | u8 change_status; |
1492 | u8 rsvd3[3]; |
1493 | }; |
1494 | |
1495 | /************************ Lancer Read FW info **************/ |
1496 | #define LANCER_READ_FILE_CHUNK (32*1024) |
1497 | #define LANCER_READ_FILE_EOF_MASK 0x80000000 |
1498 | |
1499 | #define LANCER_FW_DUMP_FILE "/dbg/dump.bin" |
1500 | #define LANCER_VPD_PF_FILE "/vpd/ntr_pf.vpd" |
1501 | #define LANCER_VPD_VF_FILE "/vpd/ntr_vf.vpd" |
1502 | |
1503 | struct lancer_cmd_req_read_object { |
1504 | struct be_cmd_req_hdr hdr; |
1505 | u32 desired_read_len; |
1506 | u32 read_offset; |
1507 | u8 object_name[104]; |
1508 | u32 descriptor_count; |
1509 | u32 buf_len; |
1510 | u32 addr_low; |
1511 | u32 addr_high; |
1512 | }; |
1513 | |
1514 | struct lancer_cmd_resp_read_object { |
1515 | u8 opcode; |
1516 | u8 subsystem; |
1517 | u8 rsvd1[2]; |
1518 | u8 status; |
1519 | u8 additional_status; |
1520 | u8 rsvd2[2]; |
1521 | u32 resp_len; |
1522 | u32 actual_resp_len; |
1523 | u32 actual_read_len; |
1524 | u32 eof; |
1525 | }; |
1526 | |
1527 | struct lancer_cmd_req_delete_object { |
1528 | struct be_cmd_req_hdr hdr; |
1529 | u32 rsvd1; |
1530 | u32 rsvd2; |
1531 | u8 object_name[104]; |
1532 | }; |
1533 | |
1534 | /************************ WOL *******************************/ |
1535 | struct be_cmd_req_acpi_wol_magic_config{ |
1536 | struct be_cmd_req_hdr hdr; |
1537 | u32 rsvd0[145]; |
1538 | u8 magic_mac[6]; |
1539 | u8 rsvd2[2]; |
1540 | } __packed; |
1541 | |
1542 | struct be_cmd_req_acpi_wol_magic_config_v1 { |
1543 | struct be_cmd_req_hdr hdr; |
1544 | u8 rsvd0[2]; |
1545 | u8 query_options; |
1546 | u8 rsvd1[5]; |
1547 | u32 rsvd2[288]; |
1548 | u8 magic_mac[6]; |
1549 | u8 rsvd3[22]; |
1550 | } __packed; |
1551 | |
1552 | struct be_cmd_resp_acpi_wol_magic_config_v1 { |
1553 | struct be_cmd_resp_hdr hdr; |
1554 | u8 rsvd0[2]; |
1555 | u8 wol_settings; |
1556 | u8 rsvd1[5]; |
1557 | u32 rsvd2[288]; |
1558 | u8 magic_mac[6]; |
1559 | u8 rsvd3[22]; |
1560 | } __packed; |
1561 | |
1562 | #define BE_GET_WOL_CAP 2 |
1563 | |
1564 | #define BE_WOL_CAP 0x1 |
1565 | #define BE_PME_D0_CAP 0x8 |
1566 | #define BE_PME_D1_CAP 0x10 |
1567 | #define BE_PME_D2_CAP 0x20 |
1568 | #define BE_PME_D3HOT_CAP 0x40 |
1569 | #define BE_PME_D3COLD_CAP 0x80 |
1570 | |
1571 | /********************** LoopBack test *********************/ |
1572 | #define SET_LB_MODE_TIMEOUT 12000 |
1573 | |
1574 | struct be_cmd_req_loopback_test { |
1575 | struct be_cmd_req_hdr hdr; |
1576 | u32 loopback_type; |
1577 | u32 num_pkts; |
1578 | u64 pattern; |
1579 | u32 src_port; |
1580 | u32 dest_port; |
1581 | u32 pkt_size; |
1582 | }; |
1583 | |
1584 | struct be_cmd_resp_loopback_test { |
1585 | struct be_cmd_resp_hdr resp_hdr; |
1586 | u32 status; |
1587 | u32 num_txfer; |
1588 | u32 num_rx; |
1589 | u32 miscomp_off; |
1590 | u32 ticks_compl; |
1591 | }; |
1592 | |
1593 | struct be_cmd_req_set_lmode { |
1594 | struct be_cmd_req_hdr hdr; |
1595 | u8 src_port; |
1596 | u8 dest_port; |
1597 | u8 loopback_type; |
1598 | u8 loopback_state; |
1599 | }; |
1600 | |
1601 | /********************** DDR DMA test *********************/ |
1602 | struct be_cmd_req_ddrdma_test { |
1603 | struct be_cmd_req_hdr hdr; |
1604 | u64 pattern; |
1605 | u32 byte_count; |
1606 | u32 rsvd0; |
1607 | u8 snd_buff[4096]; |
1608 | u8 rsvd1[4096]; |
1609 | }; |
1610 | |
1611 | struct be_cmd_resp_ddrdma_test { |
1612 | struct be_cmd_resp_hdr hdr; |
1613 | u64 pattern; |
1614 | u32 byte_cnt; |
1615 | u32 snd_err; |
1616 | u8 rsvd0[4096]; |
1617 | u8 rcv_buff[4096]; |
1618 | }; |
1619 | |
1620 | /*********************** SEEPROM Read ***********************/ |
1621 | |
1622 | #define BE_READ_SEEPROM_LEN 1024 |
1623 | struct be_cmd_req_seeprom_read { |
1624 | struct be_cmd_req_hdr hdr; |
1625 | u8 rsvd0[BE_READ_SEEPROM_LEN]; |
1626 | }; |
1627 | |
1628 | struct be_cmd_resp_seeprom_read { |
1629 | struct be_cmd_req_hdr hdr; |
1630 | u8 seeprom_data[BE_READ_SEEPROM_LEN]; |
1631 | }; |
1632 | |
1633 | enum { |
1634 | PHY_TYPE_CX4_10GB = 0, |
1635 | PHY_TYPE_XFP_10GB, |
1636 | PHY_TYPE_SFP_1GB, |
1637 | PHY_TYPE_SFP_PLUS_10GB, |
1638 | PHY_TYPE_KR_10GB, |
1639 | PHY_TYPE_KX4_10GB, |
1640 | PHY_TYPE_BASET_10GB, |
1641 | PHY_TYPE_BASET_1GB, |
1642 | PHY_TYPE_BASEX_1GB, |
1643 | PHY_TYPE_SGMII, |
1644 | PHY_TYPE_QSFP, |
1645 | PHY_TYPE_KR4_40GB, |
1646 | PHY_TYPE_KR2_20GB, |
1647 | PHY_TYPE_TN_8022, |
1648 | PHY_TYPE_DISABLED = 255 |
1649 | }; |
1650 | |
1651 | #define BE_SUPPORTED_SPEED_NONE 0 |
1652 | #define BE_SUPPORTED_SPEED_10MBPS 1 |
1653 | #define BE_SUPPORTED_SPEED_100MBPS 2 |
1654 | #define BE_SUPPORTED_SPEED_1GBPS 4 |
1655 | #define BE_SUPPORTED_SPEED_10GBPS 8 |
1656 | #define BE_SUPPORTED_SPEED_20GBPS 0x10 |
1657 | #define BE_SUPPORTED_SPEED_40GBPS 0x20 |
1658 | |
1659 | #define BE_AN_EN 0x2 |
1660 | #define BE_PAUSE_SYM_EN 0x80 |
1661 | |
1662 | /* MAC speed valid values */ |
1663 | #define SPEED_DEFAULT 0x0 |
1664 | #define SPEED_FORCED_10GB 0x1 |
1665 | #define SPEED_FORCED_1GB 0x2 |
1666 | #define SPEED_AUTONEG_10GB 0x3 |
1667 | #define SPEED_AUTONEG_1GB 0x4 |
1668 | #define SPEED_AUTONEG_100MB 0x5 |
1669 | #define SPEED_AUTONEG_10GB_1GB 0x6 |
1670 | #define SPEED_AUTONEG_10GB_1GB_100MB 0x7 |
1671 | #define SPEED_AUTONEG_1GB_100MB 0x8 |
1672 | #define SPEED_AUTONEG_10MB 0x9 |
1673 | #define SPEED_AUTONEG_1GB_100MB_10MB 0xa |
1674 | #define SPEED_AUTONEG_100MB_10MB 0xb |
1675 | #define SPEED_FORCED_100MB 0xc |
1676 | #define SPEED_FORCED_10MB 0xd |
1677 | |
1678 | struct be_cmd_req_get_phy_info { |
1679 | struct be_cmd_req_hdr hdr; |
1680 | u8 rsvd0[24]; |
1681 | }; |
1682 | |
1683 | struct be_phy_info { |
1684 | u16 phy_type; |
1685 | u16 interface_type; |
1686 | u32 misc_params; |
1687 | u16 ext_phy_details; |
1688 | u16 rsvd; |
1689 | u16 auto_speeds_supported; |
1690 | u16 fixed_speeds_supported; |
1691 | u32 future_use[2]; |
1692 | }; |
1693 | |
1694 | struct be_cmd_resp_get_phy_info { |
1695 | struct be_cmd_req_hdr hdr; |
1696 | struct be_phy_info phy_info; |
1697 | }; |
1698 | |
1699 | /*********************** Set QOS ***********************/ |
1700 | |
1701 | #define BE_QOS_BITS_NIC 1 |
1702 | |
1703 | struct be_cmd_req_set_qos { |
1704 | struct be_cmd_req_hdr hdr; |
1705 | u32 valid_bits; |
1706 | u32 max_bps_nic; |
1707 | u32 rsvd[7]; |
1708 | }; |
1709 | |
1710 | /*********************** Controller Attributes ***********************/ |
1711 | struct mgmt_hba_attribs { |
1712 | u32 rsvd0[24]; |
1713 | u8 controller_model_number[32]; |
1714 | u32 rsvd1[16]; |
1715 | u32 controller_serial_number[8]; |
1716 | u32 rsvd2[55]; |
1717 | u8 rsvd3[3]; |
1718 | u8 phy_port; |
1719 | u32 rsvd4[15]; |
1720 | u8 rsvd5[2]; |
1721 | u8 pci_funcnum; |
1722 | u8 rsvd6; |
1723 | u32 rsvd7[6]; |
1724 | } __packed; |
1725 | |
1726 | struct mgmt_controller_attrib { |
1727 | struct mgmt_hba_attribs hba_attribs; |
1728 | u32 rsvd0[10]; |
1729 | } __packed; |
1730 | |
1731 | struct be_cmd_req_cntl_attribs { |
1732 | struct be_cmd_req_hdr hdr; |
1733 | }; |
1734 | |
1735 | struct be_cmd_resp_cntl_attribs { |
1736 | struct be_cmd_resp_hdr hdr; |
1737 | struct mgmt_controller_attrib attribs; |
1738 | }; |
1739 | |
1740 | /*********************** Set driver function ***********************/ |
1741 | #define CAPABILITY_SW_TIMESTAMPS 2 |
1742 | #define CAPABILITY_BE3_NATIVE_ERX_API 4 |
1743 | |
1744 | struct be_cmd_req_set_func_cap { |
1745 | struct be_cmd_req_hdr hdr; |
1746 | u32 valid_cap_flags; |
1747 | u32 cap_flags; |
1748 | u8 rsvd[212]; |
1749 | }; |
1750 | |
1751 | struct be_cmd_resp_set_func_cap { |
1752 | struct be_cmd_resp_hdr hdr; |
1753 | u32 valid_cap_flags; |
1754 | u32 cap_flags; |
1755 | u8 rsvd[212]; |
1756 | }; |
1757 | |
1758 | /*********************** Function Privileges ***********************/ |
1759 | enum { |
1760 | BE_PRIV_DEFAULT = 0x1, |
1761 | BE_PRIV_LNKQUERY = 0x2, |
1762 | BE_PRIV_LNKSTATS = 0x4, |
1763 | BE_PRIV_LNKMGMT = 0x8, |
1764 | BE_PRIV_LNKDIAG = 0x10, |
1765 | BE_PRIV_UTILQUERY = 0x20, |
1766 | BE_PRIV_FILTMGMT = 0x40, |
1767 | BE_PRIV_IFACEMGMT = 0x80, |
1768 | BE_PRIV_VHADM = 0x100, |
1769 | BE_PRIV_DEVCFG = 0x200, |
1770 | BE_PRIV_DEVSEC = 0x400 |
1771 | }; |
1772 | #define MAX_PRIVILEGES (BE_PRIV_VHADM | BE_PRIV_DEVCFG | \ |
1773 | BE_PRIV_DEVSEC) |
1774 | #define MIN_PRIVILEGES BE_PRIV_DEFAULT |
1775 | |
1776 | struct be_cmd_priv_map { |
1777 | u8 opcode; |
1778 | u8 subsystem; |
1779 | u32 priv_mask; |
1780 | }; |
1781 | |
1782 | struct be_cmd_req_get_fn_privileges { |
1783 | struct be_cmd_req_hdr hdr; |
1784 | u32 rsvd; |
1785 | }; |
1786 | |
1787 | struct be_cmd_resp_get_fn_privileges { |
1788 | struct be_cmd_resp_hdr hdr; |
1789 | u32 privilege_mask; |
1790 | }; |
1791 | |
1792 | struct be_cmd_req_set_fn_privileges { |
1793 | struct be_cmd_req_hdr hdr; |
1794 | u32 privileges; /* Used by BE3, SH-R */ |
1795 | u32 privileges_lancer; /* Used by Lancer */ |
1796 | }; |
1797 | |
1798 | /******************** GET/SET_MACLIST **************************/ |
1799 | #define BE_MAX_MAC 64 |
1800 | struct be_cmd_req_get_mac_list { |
1801 | struct be_cmd_req_hdr hdr; |
1802 | u8 mac_type; |
1803 | u8 perm_override; |
1804 | u16 iface_id; |
1805 | u32 mac_id; |
1806 | u32 rsvd[3]; |
1807 | } __packed; |
1808 | |
1809 | struct get_list_macaddr { |
1810 | u16 mac_addr_size; |
1811 | union { |
1812 | u8 macaddr[6]; |
1813 | struct { |
1814 | u8 rsvd[2]; |
1815 | u32 mac_id; |
1816 | } __packed s_mac_id; |
1817 | } __packed mac_addr_id; |
1818 | } __packed; |
1819 | |
1820 | struct be_cmd_resp_get_mac_list { |
1821 | struct be_cmd_resp_hdr hdr; |
1822 | struct get_list_macaddr fd_macaddr; /* Factory default mac */ |
1823 | struct get_list_macaddr macid_macaddr; /* soft mac */ |
1824 | u8 true_mac_count; |
1825 | u8 pseudo_mac_count; |
1826 | u8 mac_list_size; |
1827 | u8 rsvd; |
1828 | /* perm override mac */ |
1829 | struct get_list_macaddr macaddr_list[BE_MAX_MAC]; |
1830 | } __packed; |
1831 | |
1832 | struct be_cmd_req_set_mac_list { |
1833 | struct be_cmd_req_hdr hdr; |
1834 | u8 mac_count; |
1835 | u8 rsvd1; |
1836 | u16 rsvd2; |
1837 | struct macaddr mac[BE_MAX_MAC]; |
1838 | } __packed; |
1839 | |
1840 | /*********************** HSW Config ***********************/ |
1841 | #define PORT_FWD_TYPE_VEPA 0x3 |
1842 | #define PORT_FWD_TYPE_VEB 0x2 |
1843 | #define PORT_FWD_TYPE_PASSTHRU 0x1 |
1844 | |
1845 | #define ENABLE_MAC_SPOOFCHK 0x2 |
1846 | #define DISABLE_MAC_SPOOFCHK 0x3 |
1847 | |
1848 | struct amap_set_hsw_context { |
1849 | u8 interface_id[16]; |
1850 | u8 rsvd0[8]; |
1851 | u8 mac_spoofchk[2]; |
1852 | u8 rsvd1[4]; |
1853 | u8 pvid_valid; |
1854 | u8 pport; |
1855 | u8 rsvd2[6]; |
1856 | u8 port_fwd_type[3]; |
1857 | u8 rsvd3[5]; |
1858 | u8 vlan_spoofchk[2]; |
1859 | u8 pvid[16]; |
1860 | u8 rsvd4[32]; |
1861 | u8 rsvd5[32]; |
1862 | u8 rsvd6[32]; |
1863 | } __packed; |
1864 | |
1865 | struct be_cmd_req_set_hsw_config { |
1866 | struct be_cmd_req_hdr hdr; |
1867 | u8 context[sizeof(struct amap_set_hsw_context) / 8]; |
1868 | } __packed; |
1869 | |
1870 | struct amap_get_hsw_req_context { |
1871 | u8 interface_id[16]; |
1872 | u8 rsvd0[14]; |
1873 | u8 pvid_valid; |
1874 | u8 pport; |
1875 | } __packed; |
1876 | |
1877 | struct amap_get_hsw_resp_context { |
1878 | u8 rsvd0[6]; |
1879 | u8 port_fwd_type[3]; |
1880 | u8 rsvd1[5]; |
1881 | u8 spoofchk; |
1882 | u8 rsvd2; |
1883 | u8 pvid[16]; |
1884 | u8 rsvd3[32]; |
1885 | u8 rsvd4[32]; |
1886 | u8 rsvd5[32]; |
1887 | } __packed; |
1888 | |
1889 | struct be_cmd_req_get_hsw_config { |
1890 | struct be_cmd_req_hdr hdr; |
1891 | u8 context[sizeof(struct amap_get_hsw_req_context) / 8]; |
1892 | } __packed; |
1893 | |
1894 | struct be_cmd_resp_get_hsw_config { |
1895 | struct be_cmd_resp_hdr hdr; |
1896 | u8 context[sizeof(struct amap_get_hsw_resp_context) / 8]; |
1897 | u32 rsvd; |
1898 | }; |
1899 | |
1900 | /******************* get port names ***************/ |
1901 | struct be_cmd_req_get_port_name { |
1902 | struct be_cmd_req_hdr hdr; |
1903 | u32 rsvd0; |
1904 | }; |
1905 | |
1906 | struct be_cmd_resp_get_port_name { |
1907 | struct be_cmd_req_hdr hdr; |
1908 | u8 port_name[4]; |
1909 | }; |
1910 | |
1911 | /*************** HW Stats Get v1 **********************************/ |
1912 | #define BE_TXP_SW_SZ 48 |
1913 | struct be_port_rxf_stats_v1 { |
1914 | u32 rsvd0[12]; |
1915 | u32 rx_crc_errors; |
1916 | u32 rx_alignment_symbol_errors; |
1917 | u32 rx_pause_frames; |
1918 | u32 rx_priority_pause_frames; |
1919 | u32 rx_control_frames; |
1920 | u32 rx_in_range_errors; |
1921 | u32 rx_out_range_errors; |
1922 | u32 rx_frame_too_long; |
1923 | u32 rx_address_filtered; |
1924 | u32 rx_dropped_too_small; |
1925 | u32 rx_dropped_too_short; |
1926 | u32 ; |
1927 | u32 rx_dropped_tcp_length; |
1928 | u32 rx_dropped_runt; |
1929 | u32 rsvd1[10]; |
1930 | u32 rx_ip_checksum_errs; |
1931 | u32 rx_tcp_checksum_errs; |
1932 | u32 rx_udp_checksum_errs; |
1933 | u32 rsvd2[7]; |
1934 | u32 rx_switched_unicast_packets; |
1935 | u32 rx_switched_multicast_packets; |
1936 | u32 rx_switched_broadcast_packets; |
1937 | u32 rsvd3[3]; |
1938 | u32 tx_pauseframes; |
1939 | u32 tx_priority_pauseframes; |
1940 | u32 tx_controlframes; |
1941 | u32 rsvd4[10]; |
1942 | u32 rxpp_fifo_overflow_drop; |
1943 | u32 rx_input_fifo_overflow_drop; |
1944 | u32 pmem_fifo_overflow_drop; |
1945 | u32 jabber_events; |
1946 | u32 rsvd5[3]; |
1947 | }; |
1948 | |
1949 | |
1950 | struct be_rxf_stats_v1 { |
1951 | struct be_port_rxf_stats_v1 port[4]; |
1952 | u32 rsvd0[2]; |
1953 | u32 rx_drops_no_pbuf; |
1954 | u32 rx_drops_no_txpb; |
1955 | u32 rx_drops_no_erx_descr; |
1956 | u32 rx_drops_no_tpre_descr; |
1957 | u32 rsvd1[6]; |
1958 | u32 rx_drops_too_many_frags; |
1959 | u32 rx_drops_invalid_ring; |
1960 | u32 forwarded_packets; |
1961 | u32 rx_drops_mtu; |
1962 | u32 rsvd2[14]; |
1963 | }; |
1964 | |
1965 | struct be_erx_stats_v1 { |
1966 | u32 rx_drops_no_fragments[68]; /* dwordS 0 to 67*/ |
1967 | u32 rsvd[4]; |
1968 | }; |
1969 | |
1970 | struct be_port_rxf_stats_v2 { |
1971 | u32 rsvd0[10]; |
1972 | u32 roce_bytes_received_lsd; |
1973 | u32 roce_bytes_received_msd; |
1974 | u32 rsvd1[5]; |
1975 | u32 roce_frames_received; |
1976 | u32 rx_crc_errors; |
1977 | u32 rx_alignment_symbol_errors; |
1978 | u32 rx_pause_frames; |
1979 | u32 rx_priority_pause_frames; |
1980 | u32 rx_control_frames; |
1981 | u32 rx_in_range_errors; |
1982 | u32 rx_out_range_errors; |
1983 | u32 rx_frame_too_long; |
1984 | u32 rx_address_filtered; |
1985 | u32 rx_dropped_too_small; |
1986 | u32 rx_dropped_too_short; |
1987 | u32 ; |
1988 | u32 rx_dropped_tcp_length; |
1989 | u32 rx_dropped_runt; |
1990 | u32 rsvd2[10]; |
1991 | u32 rx_ip_checksum_errs; |
1992 | u32 rx_tcp_checksum_errs; |
1993 | u32 rx_udp_checksum_errs; |
1994 | u32 rsvd3[7]; |
1995 | u32 rx_switched_unicast_packets; |
1996 | u32 rx_switched_multicast_packets; |
1997 | u32 rx_switched_broadcast_packets; |
1998 | u32 rsvd4[3]; |
1999 | u32 tx_pauseframes; |
2000 | u32 tx_priority_pauseframes; |
2001 | u32 tx_controlframes; |
2002 | u32 rsvd5[10]; |
2003 | u32 rxpp_fifo_overflow_drop; |
2004 | u32 rx_input_fifo_overflow_drop; |
2005 | u32 pmem_fifo_overflow_drop; |
2006 | u32 jabber_events; |
2007 | u32 rsvd6[3]; |
2008 | u32 rx_drops_payload_size; |
2009 | u32 ; |
2010 | u32 rx_drops_crc; |
2011 | u32 roce_drops_payload_len; |
2012 | u32 roce_drops_crc; |
2013 | u32 rsvd7[19]; |
2014 | }; |
2015 | |
2016 | struct be_rxf_stats_v2 { |
2017 | struct be_port_rxf_stats_v2 port[4]; |
2018 | u32 rsvd0[2]; |
2019 | u32 rx_drops_no_pbuf; |
2020 | u32 rx_drops_no_txpb; |
2021 | u32 rx_drops_no_erx_descr; |
2022 | u32 rx_drops_no_tpre_descr; |
2023 | u32 rsvd1[6]; |
2024 | u32 rx_drops_too_many_frags; |
2025 | u32 rx_drops_invalid_ring; |
2026 | u32 forwarded_packets; |
2027 | u32 rx_drops_mtu; |
2028 | u32 rsvd2[35]; |
2029 | }; |
2030 | |
2031 | struct be_hw_stats_v1 { |
2032 | struct be_rxf_stats_v1 rxf; |
2033 | u32 rsvd0[BE_TXP_SW_SZ]; |
2034 | struct be_erx_stats_v1 erx; |
2035 | struct be_pmem_stats pmem; |
2036 | u32 rsvd1[18]; |
2037 | }; |
2038 | |
2039 | struct be_cmd_req_get_stats_v1 { |
2040 | struct be_cmd_req_hdr hdr; |
2041 | u8 rsvd[sizeof(struct be_hw_stats_v1)]; |
2042 | }; |
2043 | |
2044 | struct be_cmd_resp_get_stats_v1 { |
2045 | struct be_cmd_resp_hdr hdr; |
2046 | struct be_hw_stats_v1 hw_stats; |
2047 | }; |
2048 | |
2049 | struct be_erx_stats_v2 { |
2050 | u32 rx_drops_no_fragments[136]; /* dwordS 0 to 135*/ |
2051 | u32 rsvd[3]; |
2052 | }; |
2053 | |
2054 | struct be_hw_stats_v2 { |
2055 | struct be_rxf_stats_v2 rxf; |
2056 | u32 rsvd0[BE_TXP_SW_SZ]; |
2057 | struct be_erx_stats_v2 erx; |
2058 | struct be_pmem_stats pmem; |
2059 | u32 rsvd1[18]; |
2060 | }; |
2061 | |
2062 | struct be_cmd_req_get_stats_v2 { |
2063 | struct be_cmd_req_hdr hdr; |
2064 | u8 rsvd[sizeof(struct be_hw_stats_v2)]; |
2065 | }; |
2066 | |
2067 | struct be_cmd_resp_get_stats_v2 { |
2068 | struct be_cmd_resp_hdr hdr; |
2069 | struct be_hw_stats_v2 hw_stats; |
2070 | }; |
2071 | |
2072 | /************** get fat capabilites *******************/ |
2073 | #define MAX_MODULES 27 |
2074 | #define MAX_MODES 4 |
2075 | #define MODE_UART 0 |
2076 | #define FW_LOG_LEVEL_DEFAULT 48 |
2077 | #define FW_LOG_LEVEL_FATAL 64 |
2078 | |
2079 | struct ext_fat_mode { |
2080 | u8 mode; |
2081 | u8 rsvd0; |
2082 | u16 port_mask; |
2083 | u32 dbg_lvl; |
2084 | u64 fun_mask; |
2085 | } __packed; |
2086 | |
2087 | struct ext_fat_modules { |
2088 | u8 modules_str[32]; |
2089 | u32 modules_id; |
2090 | u32 num_modes; |
2091 | struct ext_fat_mode trace_lvl[MAX_MODES]; |
2092 | } __packed; |
2093 | |
2094 | struct be_fat_conf_params { |
2095 | u32 max_log_entries; |
2096 | u32 log_entry_size; |
2097 | u8 log_type; |
2098 | u8 max_log_funs; |
2099 | u8 max_log_ports; |
2100 | u8 rsvd0; |
2101 | u32 supp_modes; |
2102 | u32 num_modules; |
2103 | struct ext_fat_modules module[MAX_MODULES]; |
2104 | } __packed; |
2105 | |
2106 | struct be_cmd_req_get_ext_fat_caps { |
2107 | struct be_cmd_req_hdr hdr; |
2108 | u32 parameter_type; |
2109 | }; |
2110 | |
2111 | struct be_cmd_resp_get_ext_fat_caps { |
2112 | struct be_cmd_resp_hdr hdr; |
2113 | struct be_fat_conf_params get_params; |
2114 | }; |
2115 | |
2116 | struct be_cmd_req_set_ext_fat_caps { |
2117 | struct be_cmd_req_hdr hdr; |
2118 | struct be_fat_conf_params set_params; |
2119 | }; |
2120 | |
2121 | #define RESOURCE_DESC_SIZE_V0 72 |
2122 | #define RESOURCE_DESC_SIZE_V1 88 |
2123 | #define PCIE_RESOURCE_DESC_TYPE_V0 0x40 |
2124 | #define NIC_RESOURCE_DESC_TYPE_V0 0x41 |
2125 | #define PCIE_RESOURCE_DESC_TYPE_V1 0x50 |
2126 | #define NIC_RESOURCE_DESC_TYPE_V1 0x51 |
2127 | #define PORT_RESOURCE_DESC_TYPE_V1 0x55 |
2128 | #define MAX_RESOURCE_DESC 264 |
2129 | |
2130 | #define IF_CAPS_FLAGS_VALID_SHIFT 0 /* IF caps valid */ |
2131 | #define VFT_SHIFT 3 /* VF template */ |
2132 | #define IMM_SHIFT 6 /* Immediate */ |
2133 | #define NOSV_SHIFT 7 /* No save */ |
2134 | |
2135 | #define MISSION_NIC 1 |
2136 | #define MISSION_RDMA 8 |
2137 | |
2138 | struct be_res_desc_hdr { |
2139 | u8 desc_type; |
2140 | u8 desc_len; |
2141 | } __packed; |
2142 | |
2143 | struct be_port_res_desc { |
2144 | struct be_res_desc_hdr hdr; |
2145 | u8 rsvd0; |
2146 | u8 flags; |
2147 | u8 link_num; |
2148 | u8 mc_type; |
2149 | u16 rsvd1; |
2150 | |
2151 | #define NV_TYPE_MASK 0x3 /* bits 0-1 */ |
2152 | #define NV_TYPE_DISABLED 1 |
2153 | #define NV_TYPE_VXLAN 3 |
2154 | #define SOCVID_SHIFT 2 /* Strip outer vlan */ |
2155 | #define RCVID_SHIFT 4 /* Report vlan */ |
2156 | #define PF_NUM_IGNORE 255 |
2157 | u8 nv_flags; |
2158 | u8 rsvd2; |
2159 | __le16 nv_port; /* vxlan/gre port */ |
2160 | u32 rsvd3[19]; |
2161 | } __packed; |
2162 | |
2163 | struct be_pcie_res_desc { |
2164 | struct be_res_desc_hdr hdr; |
2165 | u8 rsvd0; |
2166 | u8 flags; |
2167 | u16 rsvd1; |
2168 | u8 pf_num; |
2169 | u8 rsvd2; |
2170 | u32 rsvd3; |
2171 | u8 sriov_state; |
2172 | u8 pf_state; |
2173 | u8 pf_type; |
2174 | u8 rsvd4; |
2175 | u16 num_vfs; |
2176 | u16 rsvd5; |
2177 | u32 rsvd6[17]; |
2178 | } __packed; |
2179 | |
2180 | struct be_nic_res_desc { |
2181 | struct be_res_desc_hdr hdr; |
2182 | u8 rsvd1; |
2183 | |
2184 | #define QUN_SHIFT 4 /* QoS is in absolute units */ |
2185 | u8 flags; |
2186 | u8 vf_num; |
2187 | u8 rsvd2; |
2188 | u8 pf_num; |
2189 | u8 rsvd3; |
2190 | u16 unicast_mac_count; |
2191 | u8 rsvd4[6]; |
2192 | u16 mcc_count; |
2193 | u16 vlan_count; |
2194 | u16 mcast_mac_count; |
2195 | u16 txq_count; |
2196 | u16 rq_count; |
2197 | u16 ; |
2198 | u16 lro_count; |
2199 | u16 cq_count; |
2200 | u16 toe_conn_count; |
2201 | u16 eq_count; |
2202 | u16 vlan_id; |
2203 | u16 iface_count; |
2204 | u32 cap_flags; |
2205 | u8 link_param; |
2206 | u8 rsvd6; |
2207 | u16 channel_id_param; |
2208 | u32 bw_min; |
2209 | u32 bw_max; |
2210 | u8 acpi_params; |
2211 | u8 wol_param; |
2212 | u16 rsvd7; |
2213 | u16 tunnel_iface_count; |
2214 | u16 direct_tenant_iface_count; |
2215 | u32 rsvd8[6]; |
2216 | } __packed; |
2217 | |
2218 | /************ Multi-Channel type ***********/ |
2219 | enum mc_type { |
2220 | MC_NONE = 0x01, |
2221 | UMC = 0x02, |
2222 | FLEX10 = 0x03, |
2223 | vNIC1 = 0x04, |
2224 | nPAR = 0x05, |
2225 | UFP = 0x06, |
2226 | vNIC2 = 0x07 |
2227 | }; |
2228 | |
2229 | /* Is BE in a multi-channel mode */ |
2230 | static inline bool be_is_mc(struct be_adapter *adapter) |
2231 | { |
2232 | return adapter->mc_type > MC_NONE; |
2233 | } |
2234 | |
2235 | struct be_cmd_req_get_func_config { |
2236 | struct be_cmd_req_hdr hdr; |
2237 | }; |
2238 | |
2239 | struct be_cmd_resp_get_func_config { |
2240 | struct be_cmd_resp_hdr hdr; |
2241 | u32 desc_count; |
2242 | u8 func_param[MAX_RESOURCE_DESC * RESOURCE_DESC_SIZE_V1]; |
2243 | }; |
2244 | |
2245 | enum { |
2246 | RESOURCE_LIMITS, |
2247 | RESOURCE_MODIFIABLE |
2248 | }; |
2249 | |
2250 | struct be_cmd_req_get_profile_config { |
2251 | struct be_cmd_req_hdr hdr; |
2252 | u8 rsvd; |
2253 | #define ACTIVE_PROFILE_TYPE 0x2 |
2254 | #define SAVED_PROFILE_TYPE 0x0 |
2255 | #define QUERY_MODIFIABLE_FIELDS_TYPE BIT(3) |
2256 | u8 type; |
2257 | u16 rsvd1; |
2258 | }; |
2259 | |
2260 | struct be_cmd_resp_get_profile_config { |
2261 | struct be_cmd_resp_hdr hdr; |
2262 | __le16 desc_count; |
2263 | u16 rsvd; |
2264 | u8 func_param[MAX_RESOURCE_DESC * RESOURCE_DESC_SIZE_V1]; |
2265 | }; |
2266 | |
2267 | #define FIELD_MODIFIABLE 0xFFFF |
2268 | struct be_cmd_req_set_profile_config { |
2269 | struct be_cmd_req_hdr hdr; |
2270 | u32 rsvd; |
2271 | u32 desc_count; |
2272 | u8 desc[2 * RESOURCE_DESC_SIZE_V1]; |
2273 | } __packed; |
2274 | |
2275 | struct be_cmd_req_get_active_profile { |
2276 | struct be_cmd_req_hdr hdr; |
2277 | u32 rsvd; |
2278 | } __packed; |
2279 | |
2280 | struct be_cmd_resp_get_active_profile { |
2281 | struct be_cmd_resp_hdr hdr; |
2282 | u16 active_profile_id; |
2283 | u16 next_profile_id; |
2284 | } __packed; |
2285 | |
2286 | struct be_cmd_enable_disable_vf { |
2287 | struct be_cmd_req_hdr hdr; |
2288 | u8 enable; |
2289 | u8 rsvd[3]; |
2290 | }; |
2291 | |
2292 | struct be_cmd_req_intr_set { |
2293 | struct be_cmd_req_hdr hdr; |
2294 | u8 intr_enabled; |
2295 | u8 rsvd[3]; |
2296 | }; |
2297 | |
2298 | static inline bool check_privilege(struct be_adapter *adapter, u32 flags) |
2299 | { |
2300 | return flags & adapter->cmd_privileges ? true : false; |
2301 | } |
2302 | |
2303 | /************** Get IFACE LIST *******************/ |
2304 | struct be_if_desc { |
2305 | u32 if_id; |
2306 | u32 cap_flags; |
2307 | u32 en_flags; |
2308 | }; |
2309 | |
2310 | struct be_cmd_req_get_iface_list { |
2311 | struct be_cmd_req_hdr hdr; |
2312 | }; |
2313 | |
2314 | struct be_cmd_resp_get_iface_list { |
2315 | struct be_cmd_req_hdr hdr; |
2316 | u32 if_cnt; |
2317 | struct be_if_desc if_desc; |
2318 | }; |
2319 | |
2320 | /************** Set Features *******************/ |
2321 | #define BE_FEATURE_UE_RECOVERY 0x10 |
2322 | #define BE_UE_RECOVERY_UER_MASK 0x1 |
2323 | |
2324 | struct be_req_ue_recovery { |
2325 | u32 uer; |
2326 | u32 rsvd; |
2327 | }; |
2328 | |
2329 | struct be_cmd_req_set_features { |
2330 | struct be_cmd_req_hdr hdr; |
2331 | u32 features; |
2332 | u32 parameter_len; |
2333 | union { |
2334 | struct be_req_ue_recovery req; |
2335 | u32 rsvd[2]; |
2336 | } parameter; |
2337 | }; |
2338 | |
2339 | struct be_resp_ue_recovery { |
2340 | u32 uer; |
2341 | u16 ue2rp; |
2342 | u16 ue2sr; |
2343 | }; |
2344 | |
2345 | struct be_cmd_resp_set_features { |
2346 | struct be_cmd_resp_hdr hdr; |
2347 | u32 features; |
2348 | u32 parameter_len; |
2349 | union { |
2350 | struct be_resp_ue_recovery resp; |
2351 | u32 rsvd[2]; |
2352 | } parameter; |
2353 | }; |
2354 | |
2355 | /*************** Set logical link ********************/ |
2356 | #define PLINK_ENABLE BIT(0) |
2357 | #define PLINK_TRACK BIT(8) |
2358 | struct be_cmd_req_set_ll_link { |
2359 | struct be_cmd_req_hdr hdr; |
2360 | u32 link_config; /* Bit 0: UP_DOWN, Bit 9: PLINK */ |
2361 | }; |
2362 | |
2363 | /************** Manage IFACE Filters *******************/ |
2364 | #define OP_CONVERT_NORMAL_TO_TUNNEL 0 |
2365 | #define OP_CONVERT_TUNNEL_TO_NORMAL 1 |
2366 | |
2367 | struct be_cmd_req_manage_iface_filters { |
2368 | struct be_cmd_req_hdr hdr; |
2369 | u8 op; |
2370 | u8 rsvd0; |
2371 | u8 flags; |
2372 | u8 rsvd1; |
2373 | u32 tunnel_iface_id; |
2374 | u32 target_iface_id; |
2375 | u8 mac[6]; |
2376 | u16 vlan_tag; |
2377 | u32 tenant_id; |
2378 | u32 filter_id; |
2379 | u32 cap_flags; |
2380 | u32 cap_control_flags; |
2381 | } __packed; |
2382 | |
2383 | u16 be_POST_stage_get(struct be_adapter *adapter); |
2384 | int be_pci_fnum_get(struct be_adapter *adapter); |
2385 | int be_fw_wait_ready(struct be_adapter *adapter); |
2386 | int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr, |
2387 | bool permanent, u32 if_handle, u32 pmac_id); |
2388 | int be_cmd_pmac_add(struct be_adapter *adapter, const u8 *mac_addr, u32 if_id, |
2389 | u32 *pmac_id, u32 domain); |
2390 | int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, int pmac_id, |
2391 | u32 domain); |
2392 | int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags, |
2393 | u32 *if_handle, u32 domain); |
2394 | int be_cmd_if_destroy(struct be_adapter *adapter, int if_handle, u32 domain); |
2395 | int be_cmd_eq_create(struct be_adapter *adapter, struct be_eq_obj *eqo); |
2396 | int be_cmd_cq_create(struct be_adapter *adapter, struct be_queue_info *cq, |
2397 | struct be_queue_info *eq, bool no_delay, |
2398 | int num_cqe_dma_coalesce); |
2399 | int be_cmd_mccq_create(struct be_adapter *adapter, struct be_queue_info *mccq, |
2400 | struct be_queue_info *cq); |
2401 | int be_cmd_txq_create(struct be_adapter *adapter, struct be_tx_obj *txo); |
2402 | int be_cmd_rxq_create(struct be_adapter *adapter, struct be_queue_info *rxq, |
2403 | u16 cq_id, u16 frag_size, u32 if_id, u32 , u8 *); |
2404 | int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q, |
2405 | int type); |
2406 | int be_cmd_rxq_destroy(struct be_adapter *adapter, struct be_queue_info *q); |
2407 | int be_cmd_link_status_query(struct be_adapter *adapter, u16 *link_speed, |
2408 | u8 *link_status, u32 dom); |
2409 | int be_cmd_reset(struct be_adapter *adapter); |
2410 | int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd); |
2411 | int lancer_cmd_get_pport_stats(struct be_adapter *adapter, |
2412 | struct be_dma_mem *nonemb_cmd); |
2413 | int be_cmd_get_fw_ver(struct be_adapter *adapter); |
2414 | int be_cmd_modify_eqd(struct be_adapter *adapter, struct be_set_eqd *, int num); |
2415 | int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array, |
2416 | u32 num, u32 domain); |
2417 | int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 status); |
2418 | int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc); |
2419 | int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc); |
2420 | int be_cmd_query_fw_cfg(struct be_adapter *adapter); |
2421 | int be_cmd_reset_function(struct be_adapter *adapter); |
2422 | int (struct be_adapter *adapter, u8 *, |
2423 | u32 , u16 table_size, const u8 *); |
2424 | int be_process_mcc(struct be_adapter *adapter); |
2425 | int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num, u8 beacon, |
2426 | u8 status, u8 state); |
2427 | int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, |
2428 | u32 *state); |
2429 | int be_cmd_read_port_transceiver_data(struct be_adapter *adapter, |
2430 | u8 page_num, u32 off, u32 len, u8 *data); |
2431 | int be_cmd_query_cable_type(struct be_adapter *adapter); |
2432 | int be_cmd_query_sfp_info(struct be_adapter *adapter); |
2433 | int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd, |
2434 | u32 data_size, u32 data_offset, const char *obj_name, |
2435 | u32 *data_read, u32 *eof, u8 *addn_status); |
2436 | int lancer_fw_download(struct be_adapter *adapter, const struct firmware *fw); |
2437 | int be_fw_download(struct be_adapter *adapter, const struct firmware *fw); |
2438 | int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac, |
2439 | struct be_dma_mem *nonemb_cmd); |
2440 | int be_cmd_fw_init(struct be_adapter *adapter); |
2441 | int be_cmd_fw_clean(struct be_adapter *adapter); |
2442 | void be_async_mcc_enable(struct be_adapter *adapter); |
2443 | void be_async_mcc_disable(struct be_adapter *adapter); |
2444 | int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num, |
2445 | u32 loopback_type, u32 pkt_size, u32 num_pkts, |
2446 | u64 pattern); |
2447 | int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern, u32 byte_cnt, |
2448 | struct be_dma_mem *cmd); |
2449 | int be_cmd_get_seeprom_data(struct be_adapter *adapter, |
2450 | struct be_dma_mem *nonemb_cmd); |
2451 | int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num, |
2452 | u8 loopback_type, u8 enable); |
2453 | int be_cmd_get_phy_info(struct be_adapter *adapter); |
2454 | int be_cmd_config_qos(struct be_adapter *adapter, u32 max_rate, |
2455 | u16 link_speed, u8 domain); |
2456 | void be_detect_error(struct be_adapter *adapter); |
2457 | int be_cmd_get_die_temperature(struct be_adapter *adapter); |
2458 | int be_cmd_get_cntl_attributes(struct be_adapter *adapter); |
2459 | int be_cmd_get_fat_dump_len(struct be_adapter *adapter, u32 *dump_size); |
2460 | int be_cmd_get_fat_dump(struct be_adapter *adapter, u32 buf_len, void *buf); |
2461 | int be_cmd_req_native_mode(struct be_adapter *adapter); |
2462 | int be_cmd_get_fn_privileges(struct be_adapter *adapter, u32 *privilege, |
2463 | u32 domain); |
2464 | int be_cmd_set_fn_privileges(struct be_adapter *adapter, u32 privileges, |
2465 | u32 vf_num); |
2466 | int be_cmd_get_mac_from_list(struct be_adapter *adapter, u8 *mac, |
2467 | bool *pmac_id_active, u32 *pmac_id, |
2468 | u32 if_handle, u8 domain); |
2469 | int be_cmd_get_active_mac(struct be_adapter *adapter, u32 pmac_id, u8 *mac, |
2470 | u32 if_handle, bool active, u32 domain); |
2471 | int be_cmd_get_perm_mac(struct be_adapter *adapter, u8 *mac); |
2472 | int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array, u8 mac_count, |
2473 | u32 domain); |
2474 | int be_cmd_set_mac(struct be_adapter *adapter, u8 *mac, int if_id, u32 dom); |
2475 | int be_cmd_set_hsw_config(struct be_adapter *adapter, u16 pvid, u32 domain, |
2476 | u16 intf_id, u16 hsw_mode, u8 spoofchk); |
2477 | int be_cmd_get_hsw_config(struct be_adapter *adapter, u16 *pvid, u32 domain, |
2478 | u16 intf_id, u8 *mode, bool *spoofchk); |
2479 | int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter); |
2480 | int be_cmd_set_fw_log_level(struct be_adapter *adapter, u32 level); |
2481 | int be_cmd_get_fw_log_level(struct be_adapter *adapter); |
2482 | int be_cmd_get_ext_fat_capabilites(struct be_adapter *adapter, |
2483 | struct be_dma_mem *cmd); |
2484 | int be_cmd_set_ext_fat_capabilites(struct be_adapter *adapter, |
2485 | struct be_dma_mem *cmd, |
2486 | struct be_fat_conf_params *cfgs); |
2487 | int lancer_physdev_ctrl(struct be_adapter *adapter, u32 mask); |
2488 | int lancer_initiate_dump(struct be_adapter *adapter); |
2489 | int lancer_delete_dump(struct be_adapter *adapter); |
2490 | bool dump_present(struct be_adapter *adapter); |
2491 | int lancer_test_and_set_rdy_state(struct be_adapter *adapter); |
2492 | int be_cmd_query_port_name(struct be_adapter *adapter); |
2493 | int be_cmd_get_func_config(struct be_adapter *adapter, |
2494 | struct be_resources *res); |
2495 | int be_cmd_get_profile_config(struct be_adapter *adapter, |
2496 | struct be_resources *res, |
2497 | struct be_port_resources *port_res, |
2498 | u8 profile_type, u8 query, u8 domain); |
2499 | int be_cmd_get_active_profile(struct be_adapter *adapter, u16 *profile); |
2500 | int be_cmd_get_if_id(struct be_adapter *adapter, struct be_vf_cfg *vf_cfg, |
2501 | int vf_num); |
2502 | int be_cmd_enable_vf(struct be_adapter *adapter, u8 domain); |
2503 | int be_cmd_intr_set(struct be_adapter *adapter, bool intr_enable); |
2504 | int be_cmd_set_logical_link_config(struct be_adapter *adapter, |
2505 | int link_state, u8 domain); |
2506 | int be_cmd_set_vxlan_port(struct be_adapter *adapter, __be16 port); |
2507 | int be_cmd_manage_iface(struct be_adapter *adapter, u32 iface, u8 op); |
2508 | int be_cmd_set_sriov_config(struct be_adapter *adapter, |
2509 | struct be_resources res, u16 num_vfs, |
2510 | struct be_resources *vft_res); |
2511 | int be_cmd_set_features(struct be_adapter *adapter); |
2512 | |