1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
2 | /* |
3 | * Copyright (c) 2014-2015 Hisilicon Limited. |
4 | */ |
5 | |
6 | #ifndef _HNS_DSAF_RCB_H |
7 | #define _HNS_DSAF_RCB_H |
8 | |
9 | #include <linux/netdevice.h> |
10 | #include <linux/platform_device.h> |
11 | |
12 | #include "hnae.h" |
13 | #include "hns_dsaf_main.h" |
14 | |
15 | struct rcb_common_cb; |
16 | |
17 | #define HNS_RCB_IRQ_NUM_PER_QUEUE 2 |
18 | #define HNS_RCB_IRQ_IDX_TX 0 |
19 | #define HNS_RCB_IRQ_IDX_RX 1 |
20 | #define HNS_RCB_TX_REG_OFFSET 0x40 |
21 | |
22 | #define HNS_RCB_SERVICE_NW_ENGINE_NUM DSAF_COMM_CHN |
23 | #define HNS_RCB_DEBUG_NW_ENGINE_NUM 1 |
24 | #define HNS_RCB_RING_MAX_BD_PER_PKT 3 |
25 | #define HNS_RCB_RING_MAX_TXBD_PER_PKT 3 |
26 | #define HNS_RCBV2_RING_MAX_TXBD_PER_PKT 8 |
27 | #define HNS_RCB_MAX_PKT_SIZE MAC_MAX_MTU |
28 | |
29 | #define HNS_RCB_RING_MAX_PENDING_BD 1024 |
30 | #define HNS_RCB_RING_MIN_PENDING_BD 16 |
31 | |
32 | #define HNS_RCB_REG_OFFSET 0x10000 |
33 | |
34 | #define HNS_RCB_TX_FRAMES_LOW 1 |
35 | #define HNS_RCB_RX_FRAMES_LOW 1 |
36 | #define HNS_RCB_TX_FRAMES_HIGH 1023 |
37 | #define HNS_RCB_RX_FRAMES_HIGH 1023 |
38 | #define HNS_RCB_TX_USECS_LOW 1 |
39 | #define HNS_RCB_RX_USECS_LOW 1 |
40 | #define HNS_RCB_TX_USECS_HIGH 1023 |
41 | #define HNS_RCB_RX_USECS_HIGH 1023 |
42 | #define HNS_RCB_MAX_COALESCED_FRAMES 1023 |
43 | #define HNS_RCB_MIN_COALESCED_FRAMES 1 |
44 | #define HNS_RCB_DEF_RX_COALESCED_FRAMES 50 |
45 | #define HNS_RCB_DEF_TX_COALESCED_FRAMES 1 |
46 | #define HNS_RCB_CLK_FREQ_MHZ 350 |
47 | #define HNS_RCB_MAX_COALESCED_USECS 0x3ff |
48 | #define HNS_RCB_DEF_COALESCED_USECS 30 |
49 | #define HNS_RCB_DEF_GAP_TIME_USECS 20 |
50 | #define HNS_RCB_TX_PKTLINE_OFFSET 8 |
51 | |
52 | #define HNS_RCB_COMMON_ENDIAN 1 |
53 | |
54 | #define HNS_BD_SIZE_512_TYPE 0 |
55 | #define HNS_BD_SIZE_1024_TYPE 1 |
56 | #define HNS_BD_SIZE_2048_TYPE 2 |
57 | #define HNS_BD_SIZE_4096_TYPE 3 |
58 | |
59 | #define HNS_RCB_COMMON_DUMP_REG_NUM 80 |
60 | #define HNS_RCB_RING_DUMP_REG_NUM 40 |
61 | #define HNS_RING_STATIC_REG_NUM 28 |
62 | |
63 | #define HNS_DUMP_REG_NUM 500 |
64 | #define HNS_STATIC_REG_NUM 12 |
65 | |
66 | #define HNS_TSO_MODE_8BD_32K 1 |
67 | #define HNS_TSO_MDOE_4BD_16K 0 |
68 | |
69 | enum rcb_int_flag { |
70 | RCB_INT_FLAG_TX = 0x1, |
71 | RCB_INT_FLAG_RX = (0x1 << 1), |
72 | RCB_INT_FLAG_MAX = (0x1 << 2), /*must be the last element */ |
73 | }; |
74 | |
75 | struct hns_ring_hw_stats { |
76 | u64 tx_pkts; |
77 | u64 ppe_tx_ok_pkts; |
78 | u64 ppe_tx_drop_pkts; |
79 | u64 rx_pkts; |
80 | u64 ppe_rx_ok_pkts; |
81 | u64 ppe_rx_drop_pkts; |
82 | }; |
83 | |
84 | struct ring_pair_cb { |
85 | struct rcb_common_cb *rcb_common; /* ring belongs to */ |
86 | struct device *dev; /*device for DMA mapping */ |
87 | struct hnae_queue q; |
88 | |
89 | u16 index; /* global index in a rcb common device */ |
90 | u16 buf_size; |
91 | |
92 | int virq[HNS_RCB_IRQ_NUM_PER_QUEUE]; |
93 | |
94 | u8 port_id_in_comm; |
95 | u8 used_by_vf; |
96 | |
97 | struct hns_ring_hw_stats hw_stats; |
98 | }; |
99 | |
100 | struct rcb_common_cb { |
101 | u8 __iomem *io_base; |
102 | phys_addr_t phy_base; |
103 | struct dsaf_device *dsaf_dev; |
104 | u16 max_vfn; |
105 | u16 max_q_per_vf; |
106 | |
107 | u8 comm_index; |
108 | u32 ring_num; |
109 | u32 desc_num; /* desc num per queue*/ |
110 | |
111 | struct ring_pair_cb ring_pair_cb[] __counted_by(ring_num); |
112 | }; |
113 | |
114 | int hns_rcb_buf_size2type(u32 buf_size); |
115 | |
116 | int hns_rcb_common_get_cfg(struct dsaf_device *dsaf_dev, int comm_index); |
117 | void hns_rcb_common_free_cfg(struct dsaf_device *dsaf_dev, u32 comm_index); |
118 | int hns_rcb_common_init_hw(struct rcb_common_cb *rcb_common); |
119 | void hns_rcb_start(struct hnae_queue *q, u32 val); |
120 | int hns_rcb_get_cfg(struct rcb_common_cb *rcb_common); |
121 | void hns_rcb_get_queue_mode(enum dsaf_mode dsaf_mode, |
122 | u16 *max_vfn, u16 *max_q_per_vf); |
123 | |
124 | void hns_rcb_common_init_commit_hw(struct rcb_common_cb *rcb_common); |
125 | |
126 | void hns_rcb_ring_enable_hw(struct hnae_queue *q, u32 val); |
127 | void hns_rcb_int_clr_hw(struct hnae_queue *q, u32 flag); |
128 | void hns_rcb_int_ctrl_hw(struct hnae_queue *q, u32 flag, u32 enable); |
129 | void hns_rcbv2_int_ctrl_hw(struct hnae_queue *q, u32 flag, u32 mask); |
130 | void hns_rcbv2_int_clr_hw(struct hnae_queue *q, u32 flag); |
131 | |
132 | void hns_rcb_init_hw(struct ring_pair_cb *ring); |
133 | void hns_rcb_reset_ring_hw(struct hnae_queue *q); |
134 | void hns_rcb_wait_fbd_clean(struct hnae_queue **qs, int q_num, u32 flag); |
135 | int hns_rcb_wait_tx_ring_clean(struct hnae_queue *qs); |
136 | u32 hns_rcb_get_rx_coalesced_frames( |
137 | struct rcb_common_cb *rcb_common, u32 port_idx); |
138 | u32 hns_rcb_get_tx_coalesced_frames( |
139 | struct rcb_common_cb *rcb_common, u32 port_idx); |
140 | u32 hns_rcb_get_coalesce_usecs( |
141 | struct rcb_common_cb *rcb_common, u32 port_idx); |
142 | int hns_rcb_set_coalesce_usecs( |
143 | struct rcb_common_cb *rcb_common, u32 port_idx, u32 timeout); |
144 | int hns_rcb_set_rx_coalesced_frames( |
145 | struct rcb_common_cb *rcb_common, u32 port_idx, u32 coalesced_frames); |
146 | int hns_rcb_set_tx_coalesced_frames( |
147 | struct rcb_common_cb *rcb_common, u32 port_idx, u32 coalesced_frames); |
148 | void hns_rcb_update_stats(struct hnae_queue *queue); |
149 | |
150 | void hns_rcb_get_stats(struct hnae_queue *queue, u64 *data); |
151 | |
152 | void hns_rcb_get_common_regs(struct rcb_common_cb *rcb_common, void *data); |
153 | |
154 | int hns_rcb_get_ring_sset_count(int stringset); |
155 | int hns_rcb_get_common_regs_count(void); |
156 | int hns_rcb_get_ring_regs_count(void); |
157 | |
158 | void hns_rcb_get_ring_regs(struct hnae_queue *queue, void *data); |
159 | |
160 | void hns_rcb_get_strings(int stringset, u8 *data, int index); |
161 | void hns_rcb_set_rx_ring_bs(struct hnae_queue *q, u32 buf_size); |
162 | void hns_rcb_set_tx_ring_bs(struct hnae_queue *q, u32 buf_size); |
163 | |
164 | #endif /* _HNS_DSAF_RCB_H */ |
165 | |