1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* |
3 | * Huawei HiNIC PCI Express Linux driver |
4 | * Copyright(c) 2017 Huawei Technologies Co., Ltd |
5 | */ |
6 | |
7 | #ifndef HINIC_HW_WQE_H |
8 | #define HINIC_HW_WQE_H |
9 | |
10 | #include "hinic_common.h" |
11 | |
12 | #define HINIC_CMDQ_CTRL_PI_SHIFT 0 |
13 | #define HINIC_CMDQ_CTRL_CMD_SHIFT 16 |
14 | #define HINIC_CMDQ_CTRL_MOD_SHIFT 24 |
15 | #define HINIC_CMDQ_CTRL_ACK_TYPE_SHIFT 29 |
16 | #define HINIC_CMDQ_CTRL_HW_BUSY_BIT_SHIFT 31 |
17 | |
18 | #define HINIC_CMDQ_CTRL_PI_MASK 0xFFFF |
19 | #define HINIC_CMDQ_CTRL_CMD_MASK 0xFF |
20 | #define HINIC_CMDQ_CTRL_MOD_MASK 0x1F |
21 | #define HINIC_CMDQ_CTRL_ACK_TYPE_MASK 0x3 |
22 | #define HINIC_CMDQ_CTRL_HW_BUSY_BIT_MASK 0x1 |
23 | |
24 | #define HINIC_CMDQ_CTRL_SET(val, member) \ |
25 | (((u32)(val) & HINIC_CMDQ_CTRL_##member##_MASK) \ |
26 | << HINIC_CMDQ_CTRL_##member##_SHIFT) |
27 | |
28 | #define HINIC_CMDQ_CTRL_GET(val, member) \ |
29 | (((val) >> HINIC_CMDQ_CTRL_##member##_SHIFT) \ |
30 | & HINIC_CMDQ_CTRL_##member##_MASK) |
31 | |
32 | #define 0 |
33 | #define 15 |
34 | #define 22 |
35 | #define 23 |
36 | #define 27 |
37 | #define 29 |
38 | #define 31 |
39 | |
40 | #define 0xFF |
41 | #define 0x1 |
42 | #define 0x1 |
43 | #define 0x1 |
44 | #define 0x3 |
45 | #define 0x3 |
46 | #define 0x1 |
47 | |
48 | #define (val, member) \ |
49 | (((u32)(val) & HINIC_CMDQ_WQE_HEADER_##member##_MASK) \ |
50 | << HINIC_CMDQ_WQE_HEADER_##member##_SHIFT) |
51 | |
52 | #define (val, member) \ |
53 | (((val) >> HINIC_CMDQ_WQE_HEADER_##member##_SHIFT) \ |
54 | & HINIC_CMDQ_WQE_HEADER_##member##_MASK) |
55 | |
56 | #define HINIC_SQ_CTRL_BUFDESC_SECT_LEN_SHIFT 0 |
57 | #define HINIC_SQ_CTRL_TASKSECT_LEN_SHIFT 16 |
58 | #define HINIC_SQ_CTRL_DATA_FORMAT_SHIFT 22 |
59 | #define HINIC_SQ_CTRL_LEN_SHIFT 29 |
60 | |
61 | #define HINIC_SQ_CTRL_BUFDESC_SECT_LEN_MASK 0xFF |
62 | #define HINIC_SQ_CTRL_TASKSECT_LEN_MASK 0x1F |
63 | #define HINIC_SQ_CTRL_DATA_FORMAT_MASK 0x1 |
64 | #define HINIC_SQ_CTRL_LEN_MASK 0x3 |
65 | |
66 | #define HINIC_SQ_CTRL_QUEUE_INFO_PLDOFF_SHIFT 2 |
67 | #define HINIC_SQ_CTRL_QUEUE_INFO_UFO_SHIFT 10 |
68 | #define HINIC_SQ_CTRL_QUEUE_INFO_TSO_SHIFT 11 |
69 | #define HINIC_SQ_CTRL_QUEUE_INFO_TCPUDP_CS_SHIFT 12 |
70 | #define HINIC_SQ_CTRL_QUEUE_INFO_MSS_SHIFT 13 |
71 | #define HINIC_SQ_CTRL_QUEUE_INFO_SCTP_SHIFT 27 |
72 | #define HINIC_SQ_CTRL_QUEUE_INFO_UC_SHIFT 28 |
73 | #define HINIC_SQ_CTRL_QUEUE_INFO_PRI_SHIFT 29 |
74 | |
75 | #define HINIC_SQ_CTRL_QUEUE_INFO_PLDOFF_MASK 0xFF |
76 | #define HINIC_SQ_CTRL_QUEUE_INFO_UFO_MASK 0x1 |
77 | #define HINIC_SQ_CTRL_QUEUE_INFO_TSO_MASK 0x1 |
78 | #define HINIC_SQ_CTRL_QUEUE_INFO_TCPUDP_CS_MASK 0x1 |
79 | #define HINIC_SQ_CTRL_QUEUE_INFO_MSS_MASK 0x3FFF |
80 | #define HINIC_SQ_CTRL_QUEUE_INFO_SCTP_MASK 0x1 |
81 | #define HINIC_SQ_CTRL_QUEUE_INFO_UC_MASK 0x1 |
82 | #define HINIC_SQ_CTRL_QUEUE_INFO_PRI_MASK 0x7 |
83 | |
84 | #define HINIC_SQ_CTRL_SET(val, member) \ |
85 | (((u32)(val) & HINIC_SQ_CTRL_##member##_MASK) \ |
86 | << HINIC_SQ_CTRL_##member##_SHIFT) |
87 | |
88 | #define HINIC_SQ_CTRL_GET(val, member) \ |
89 | (((val) >> HINIC_SQ_CTRL_##member##_SHIFT) \ |
90 | & HINIC_SQ_CTRL_##member##_MASK) |
91 | |
92 | #define HINIC_SQ_CTRL_CLEAR(val, member) \ |
93 | ((u32)(val) & (~(HINIC_SQ_CTRL_##member##_MASK \ |
94 | << HINIC_SQ_CTRL_##member##_SHIFT))) |
95 | |
96 | #define HINIC_SQ_TASK_INFO0_L2HDR_LEN_SHIFT 0 |
97 | #define HINIC_SQ_TASK_INFO0_L4_OFFLOAD_SHIFT 8 |
98 | #define HINIC_SQ_TASK_INFO0_INNER_L3TYPE_SHIFT 10 |
99 | #define HINIC_SQ_TASK_INFO0_VLAN_OFFLOAD_SHIFT 12 |
100 | #define HINIC_SQ_TASK_INFO0_PARSE_FLAG_SHIFT 13 |
101 | /* 1 bit reserved */ |
102 | #define HINIC_SQ_TASK_INFO0_TSO_FLAG_SHIFT 15 |
103 | #define HINIC_SQ_TASK_INFO0_VLAN_TAG_SHIFT 16 |
104 | |
105 | #define HINIC_SQ_TASK_INFO0_L2HDR_LEN_MASK 0xFF |
106 | #define HINIC_SQ_TASK_INFO0_L4_OFFLOAD_MASK 0x3 |
107 | #define HINIC_SQ_TASK_INFO0_INNER_L3TYPE_MASK 0x3 |
108 | #define HINIC_SQ_TASK_INFO0_VLAN_OFFLOAD_MASK 0x1 |
109 | #define HINIC_SQ_TASK_INFO0_PARSE_FLAG_MASK 0x1 |
110 | /* 1 bit reserved */ |
111 | #define HINIC_SQ_TASK_INFO0_TSO_FLAG_MASK 0x1 |
112 | #define HINIC_SQ_TASK_INFO0_VLAN_TAG_MASK 0xFFFF |
113 | |
114 | #define HINIC_SQ_TASK_INFO0_SET(val, member) \ |
115 | (((u32)(val) & HINIC_SQ_TASK_INFO0_##member##_MASK) << \ |
116 | HINIC_SQ_TASK_INFO0_##member##_SHIFT) |
117 | |
118 | /* 8 bits reserved */ |
119 | #define HINIC_SQ_TASK_INFO1_MEDIA_TYPE_SHIFT 8 |
120 | #define HINIC_SQ_TASK_INFO1_INNER_L4LEN_SHIFT 16 |
121 | #define HINIC_SQ_TASK_INFO1_INNER_L3LEN_SHIFT 24 |
122 | |
123 | /* 8 bits reserved */ |
124 | #define HINIC_SQ_TASK_INFO1_MEDIA_TYPE_MASK 0xFF |
125 | #define HINIC_SQ_TASK_INFO1_INNER_L4LEN_MASK 0xFF |
126 | #define HINIC_SQ_TASK_INFO1_INNER_L3LEN_MASK 0xFF |
127 | |
128 | #define HINIC_SQ_TASK_INFO1_SET(val, member) \ |
129 | (((u32)(val) & HINIC_SQ_TASK_INFO1_##member##_MASK) << \ |
130 | HINIC_SQ_TASK_INFO1_##member##_SHIFT) |
131 | |
132 | #define HINIC_SQ_TASK_INFO2_TUNNEL_L4LEN_SHIFT 0 |
133 | #define HINIC_SQ_TASK_INFO2_OUTER_L3LEN_SHIFT 8 |
134 | #define HINIC_SQ_TASK_INFO2_TUNNEL_L4TYPE_SHIFT 16 |
135 | /* 1 bit reserved */ |
136 | #define HINIC_SQ_TASK_INFO2_OUTER_L3TYPE_SHIFT 24 |
137 | /* 8 bits reserved */ |
138 | |
139 | #define HINIC_SQ_TASK_INFO2_TUNNEL_L4LEN_MASK 0xFF |
140 | #define HINIC_SQ_TASK_INFO2_OUTER_L3LEN_MASK 0xFF |
141 | #define HINIC_SQ_TASK_INFO2_TUNNEL_L4TYPE_MASK 0x7 |
142 | /* 1 bit reserved */ |
143 | #define HINIC_SQ_TASK_INFO2_OUTER_L3TYPE_MASK 0x3 |
144 | /* 8 bits reserved */ |
145 | |
146 | #define HINIC_SQ_TASK_INFO2_SET(val, member) \ |
147 | (((u32)(val) & HINIC_SQ_TASK_INFO2_##member##_MASK) << \ |
148 | HINIC_SQ_TASK_INFO2_##member##_SHIFT) |
149 | |
150 | /* 31 bits reserved */ |
151 | #define HINIC_SQ_TASK_INFO4_L2TYPE_SHIFT 31 |
152 | |
153 | /* 31 bits reserved */ |
154 | #define HINIC_SQ_TASK_INFO4_L2TYPE_MASK 0x1 |
155 | |
156 | #define HINIC_SQ_TASK_INFO4_SET(val, member) \ |
157 | (((u32)(val) & HINIC_SQ_TASK_INFO4_##member##_MASK) << \ |
158 | HINIC_SQ_TASK_INFO4_##member##_SHIFT) |
159 | |
160 | #define HINIC_RQ_CQE_STATUS_RXDONE_SHIFT 31 |
161 | |
162 | #define HINIC_RQ_CQE_STATUS_RXDONE_MASK 0x1 |
163 | |
164 | #define HINIC_RQ_CQE_STATUS_CSUM_ERR_SHIFT 0 |
165 | |
166 | #define HINIC_RQ_CQE_STATUS_CSUM_ERR_MASK 0xFFFFU |
167 | |
168 | #define HINIC_RQ_CQE_STATUS_GET(val, member) \ |
169 | (((val) >> HINIC_RQ_CQE_STATUS_##member##_SHIFT) & \ |
170 | HINIC_RQ_CQE_STATUS_##member##_MASK) |
171 | |
172 | #define HINIC_RQ_CQE_STATUS_CLEAR(val, member) \ |
173 | ((val) & (~(HINIC_RQ_CQE_STATUS_##member##_MASK << \ |
174 | HINIC_RQ_CQE_STATUS_##member##_SHIFT))) |
175 | |
176 | #define HINIC_RQ_CQE_SGE_LEN_SHIFT 16 |
177 | |
178 | #define HINIC_RQ_CQE_SGE_LEN_MASK 0xFFFF |
179 | |
180 | #define HINIC_RQ_CQE_SGE_GET(val, member) \ |
181 | (((val) >> HINIC_RQ_CQE_SGE_##member##_SHIFT) & \ |
182 | HINIC_RQ_CQE_SGE_##member##_MASK) |
183 | |
184 | #define HINIC_RQ_CTRL_BUFDESC_SECT_LEN_SHIFT 0 |
185 | #define HINIC_RQ_CTRL_COMPLETE_FORMAT_SHIFT 15 |
186 | #define HINIC_RQ_CTRL_COMPLETE_LEN_SHIFT 27 |
187 | #define HINIC_RQ_CTRL_LEN_SHIFT 29 |
188 | |
189 | #define HINIC_RQ_CTRL_BUFDESC_SECT_LEN_MASK 0xFF |
190 | #define HINIC_RQ_CTRL_COMPLETE_FORMAT_MASK 0x1 |
191 | #define HINIC_RQ_CTRL_COMPLETE_LEN_MASK 0x3 |
192 | #define HINIC_RQ_CTRL_LEN_MASK 0x3 |
193 | |
194 | #define HINIC_RQ_CTRL_SET(val, member) \ |
195 | (((u32)(val) & HINIC_RQ_CTRL_##member##_MASK) << \ |
196 | HINIC_RQ_CTRL_##member##_SHIFT) |
197 | |
198 | #define HINIC_SQ_WQE_SIZE(nr_sges) \ |
199 | (sizeof(struct hinic_sq_ctrl) + \ |
200 | sizeof(struct hinic_sq_task) + \ |
201 | (nr_sges) * sizeof(struct hinic_sq_bufdesc)) |
202 | |
203 | #define HINIC_SCMD_DATA_LEN 16 |
204 | |
205 | #define HINIC_MAX_SQ_BUFDESCS 17 |
206 | |
207 | #define HINIC_SQ_WQE_MAX_SIZE 320 |
208 | #define HINIC_RQ_WQE_SIZE 32 |
209 | |
210 | #define HINIC_MSS_DEFAULT 0x3E00 |
211 | #define HINIC_MSS_MIN 0x50 |
212 | |
213 | #define RQ_CQE_STATUS_NUM_LRO_SHIFT 16 |
214 | #define RQ_CQE_STATUS_NUM_LRO_MASK 0xFFU |
215 | |
216 | #define RQ_CQE_STATUS_GET(val, member) (((val) >> \ |
217 | RQ_CQE_STATUS_##member##_SHIFT) & \ |
218 | RQ_CQE_STATUS_##member##_MASK) |
219 | |
220 | #define HINIC_GET_RX_NUM_LRO(status) \ |
221 | RQ_CQE_STATUS_GET(status, NUM_LRO) |
222 | |
223 | #define RQ_CQE_OFFOLAD_TYPE_PKT_TYPE_SHIFT 0 |
224 | #define RQ_CQE_OFFOLAD_TYPE_PKT_TYPE_MASK 0xFFFU |
225 | #define RQ_CQE_OFFOLAD_TYPE_VLAN_EN_SHIFT 21 |
226 | #define RQ_CQE_OFFOLAD_TYPE_VLAN_EN_MASK 0x1U |
227 | |
228 | #define RQ_CQE_OFFOLAD_TYPE_GET(val, member) (((val) >> \ |
229 | RQ_CQE_OFFOLAD_TYPE_##member##_SHIFT) & \ |
230 | RQ_CQE_OFFOLAD_TYPE_##member##_MASK) |
231 | |
232 | #define HINIC_GET_RX_PKT_TYPE(offload_type) \ |
233 | RQ_CQE_OFFOLAD_TYPE_GET(offload_type, PKT_TYPE) |
234 | |
235 | #define HINIC_GET_RX_VLAN_OFFLOAD_EN(offload_type) \ |
236 | RQ_CQE_OFFOLAD_TYPE_GET(offload_type, VLAN_EN) |
237 | |
238 | #define RQ_CQE_SGE_VLAN_MASK 0xFFFFU |
239 | #define RQ_CQE_SGE_VLAN_SHIFT 0 |
240 | |
241 | #define RQ_CQE_SGE_GET(val, member) (((val) >> \ |
242 | RQ_CQE_SGE_##member##_SHIFT) & \ |
243 | RQ_CQE_SGE_##member##_MASK) |
244 | |
245 | #define HINIC_GET_RX_VLAN_TAG(vlan_len) \ |
246 | RQ_CQE_SGE_GET(vlan_len, VLAN) |
247 | |
248 | #define 23 |
249 | #define 24 |
250 | #define 25 |
251 | #define 26 |
252 | #define 27 |
253 | #define 28 |
254 | #define 29 |
255 | #define 30 |
256 | #define 31 |
257 | |
258 | #define (val, member) \ |
259 | (((u32)(val) & 0x1) << HINIC_RSS_TYPE_##member##_SHIFT) |
260 | |
261 | #define (val, member) \ |
262 | (((u32)(val) >> HINIC_RSS_TYPE_##member##_SHIFT) & 0x1) |
263 | |
264 | enum hinic_l3_offload_type { |
265 | L3TYPE_UNKNOWN = 0, |
266 | IPV6_PKT = 1, |
267 | IPV4_PKT_NO_CHKSUM_OFFLOAD = 2, |
268 | IPV4_PKT_WITH_CHKSUM_OFFLOAD = 3, |
269 | }; |
270 | |
271 | enum hinic_l4_offload_type { |
272 | OFFLOAD_DISABLE = 0, |
273 | TCP_OFFLOAD_ENABLE = 1, |
274 | SCTP_OFFLOAD_ENABLE = 2, |
275 | UDP_OFFLOAD_ENABLE = 3, |
276 | }; |
277 | |
278 | enum hinic_l4_tunnel_type { |
279 | NOT_TUNNEL, |
280 | TUNNEL_UDP_NO_CSUM, |
281 | TUNNEL_UDP_CSUM, |
282 | }; |
283 | |
284 | enum hinic_outer_l3type { |
285 | HINIC_OUTER_L3TYPE_UNKNOWN = 0, |
286 | HINIC_OUTER_L3TYPE_IPV6 = 1, |
287 | HINIC_OUTER_L3TYPE_IPV4_NO_CHKSUM = 2, |
288 | HINIC_OUTER_L3TYPE_IPV4_CHKSUM = 3, |
289 | }; |
290 | |
291 | enum hinic_l2type { |
292 | HINIC_L2TYPE_ETH = 0, |
293 | }; |
294 | |
295 | struct { |
296 | u32 ; |
297 | u32 ; |
298 | }; |
299 | |
300 | struct hinic_status { |
301 | u32 status_info; |
302 | }; |
303 | |
304 | struct hinic_ctrl { |
305 | u32 ctrl_info; |
306 | }; |
307 | |
308 | struct hinic_sge_resp { |
309 | struct hinic_sge sge; |
310 | u32 rsvd; |
311 | }; |
312 | |
313 | struct hinic_cmdq_completion { |
314 | /* HW Format */ |
315 | union { |
316 | struct hinic_sge_resp sge_resp; |
317 | u64 direct_resp; |
318 | }; |
319 | }; |
320 | |
321 | struct hinic_scmd_bufdesc { |
322 | u32 buf_len; |
323 | u32 rsvd; |
324 | u8 data[HINIC_SCMD_DATA_LEN]; |
325 | }; |
326 | |
327 | struct hinic_lcmd_bufdesc { |
328 | struct hinic_sge sge; |
329 | u32 rsvd1; |
330 | u64 rsvd2; |
331 | u64 rsvd3; |
332 | }; |
333 | |
334 | struct hinic_cmdq_wqe_scmd { |
335 | struct hinic_cmdq_header ; |
336 | u64 rsvd; |
337 | struct hinic_status status; |
338 | struct hinic_ctrl ctrl; |
339 | struct hinic_cmdq_completion completion; |
340 | struct hinic_scmd_bufdesc buf_desc; |
341 | }; |
342 | |
343 | struct hinic_cmdq_wqe_lcmd { |
344 | struct hinic_cmdq_header ; |
345 | struct hinic_status status; |
346 | struct hinic_ctrl ctrl; |
347 | struct hinic_cmdq_completion completion; |
348 | struct hinic_lcmd_bufdesc buf_desc; |
349 | }; |
350 | |
351 | struct hinic_cmdq_direct_wqe { |
352 | struct hinic_cmdq_wqe_scmd wqe_scmd; |
353 | }; |
354 | |
355 | struct hinic_cmdq_wqe { |
356 | /* HW Format */ |
357 | union { |
358 | struct hinic_cmdq_direct_wqe direct_wqe; |
359 | struct hinic_cmdq_wqe_lcmd wqe_lcmd; |
360 | }; |
361 | }; |
362 | |
363 | struct hinic_sq_ctrl { |
364 | u32 ctrl_info; |
365 | u32 queue_info; |
366 | }; |
367 | |
368 | struct hinic_sq_task { |
369 | u32 pkt_info0; |
370 | u32 pkt_info1; |
371 | u32 pkt_info2; |
372 | u32 ufo_v6_identify; |
373 | u32 pkt_info4; |
374 | u32 zero_pad; |
375 | }; |
376 | |
377 | struct hinic_sq_bufdesc { |
378 | struct hinic_sge sge; |
379 | u32 rsvd; |
380 | }; |
381 | |
382 | struct hinic_sq_wqe { |
383 | struct hinic_sq_ctrl ctrl; |
384 | struct hinic_sq_task task; |
385 | struct hinic_sq_bufdesc buf_descs[HINIC_MAX_SQ_BUFDESCS]; |
386 | }; |
387 | |
388 | struct hinic_rq_cqe { |
389 | u32 status; |
390 | u32 len; |
391 | |
392 | u32 offload_type; |
393 | u32 rsvd3; |
394 | u32 rsvd4; |
395 | u32 rsvd5; |
396 | u32 rsvd6; |
397 | u32 rsvd7; |
398 | }; |
399 | |
400 | struct hinic_rq_ctrl { |
401 | u32 ctrl_info; |
402 | }; |
403 | |
404 | struct hinic_rq_cqe_sect { |
405 | struct hinic_sge sge; |
406 | u32 rsvd; |
407 | }; |
408 | |
409 | struct hinic_rq_bufdesc { |
410 | u32 hi_addr; |
411 | u32 lo_addr; |
412 | }; |
413 | |
414 | struct hinic_rq_wqe { |
415 | struct hinic_rq_ctrl ctrl; |
416 | u32 rsvd; |
417 | struct hinic_rq_cqe_sect cqe_sect; |
418 | struct hinic_rq_bufdesc buf_desc; |
419 | }; |
420 | |
421 | struct hinic_hw_wqe { |
422 | /* HW Format */ |
423 | union { |
424 | struct hinic_cmdq_wqe cmdq_wqe; |
425 | struct hinic_sq_wqe sq_wqe; |
426 | struct hinic_rq_wqe rq_wqe; |
427 | }; |
428 | }; |
429 | |
430 | #endif |
431 | |