1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright (c) 2018, Intel Corporation. */
3
4#ifndef _ICE_ADMINQ_CMD_H_
5#define _ICE_ADMINQ_CMD_H_
6
7/* This header file defines the Admin Queue commands, error codes and
8 * descriptor format. It is shared between Firmware and Software.
9 */
10
11#define ICE_MAX_VSI 768
12#define ICE_AQC_TOPO_MAX_LEVEL_NUM 0x9
13#define ICE_AQ_SET_MAC_FRAME_SIZE_MAX 9728
14
15struct ice_aqc_generic {
16 __le32 param0;
17 __le32 param1;
18 __le32 addr_high;
19 __le32 addr_low;
20};
21
22/* Get version (direct 0x0001) */
23struct ice_aqc_get_ver {
24 __le32 rom_ver;
25 __le32 fw_build;
26 u8 fw_branch;
27 u8 fw_major;
28 u8 fw_minor;
29 u8 fw_patch;
30 u8 api_branch;
31 u8 api_major;
32 u8 api_minor;
33 u8 api_patch;
34};
35
36/* Send driver version (indirect 0x0002) */
37struct ice_aqc_driver_ver {
38 u8 major_ver;
39 u8 minor_ver;
40 u8 build_ver;
41 u8 subbuild_ver;
42 u8 reserved[4];
43 __le32 addr_high;
44 __le32 addr_low;
45};
46
47/* Queue Shutdown (direct 0x0003) */
48struct ice_aqc_q_shutdown {
49 u8 driver_unloading;
50#define ICE_AQC_DRIVER_UNLOADING BIT(0)
51 u8 reserved[15];
52};
53
54/* Request resource ownership (direct 0x0008)
55 * Release resource ownership (direct 0x0009)
56 */
57struct ice_aqc_req_res {
58 __le16 res_id;
59#define ICE_AQC_RES_ID_NVM 1
60#define ICE_AQC_RES_ID_SDP 2
61#define ICE_AQC_RES_ID_CHNG_LOCK 3
62#define ICE_AQC_RES_ID_GLBL_LOCK 4
63 __le16 access_type;
64#define ICE_AQC_RES_ACCESS_READ 1
65#define ICE_AQC_RES_ACCESS_WRITE 2
66
67 /* Upon successful completion, FW writes this value and driver is
68 * expected to release resource before timeout. This value is provided
69 * in milliseconds.
70 */
71 __le32 timeout;
72#define ICE_AQ_RES_NVM_READ_DFLT_TIMEOUT_MS 3000
73#define ICE_AQ_RES_NVM_WRITE_DFLT_TIMEOUT_MS 180000
74#define ICE_AQ_RES_CHNG_LOCK_DFLT_TIMEOUT_MS 1000
75#define ICE_AQ_RES_GLBL_LOCK_DFLT_TIMEOUT_MS 3000
76 /* For SDP: pin ID of the SDP */
77 __le32 res_number;
78 /* Status is only used for ICE_AQC_RES_ID_GLBL_LOCK */
79 __le16 status;
80#define ICE_AQ_RES_GLBL_SUCCESS 0
81#define ICE_AQ_RES_GLBL_IN_PROG 1
82#define ICE_AQ_RES_GLBL_DONE 2
83 u8 reserved[2];
84};
85
86/* Get function capabilities (indirect 0x000A)
87 * Get device capabilities (indirect 0x000B)
88 */
89struct ice_aqc_list_caps {
90 u8 cmd_flags;
91 u8 pf_index;
92 u8 reserved[2];
93 __le32 count;
94 __le32 addr_high;
95 __le32 addr_low;
96};
97
98/* Device/Function buffer entry, repeated per reported capability */
99struct ice_aqc_list_caps_elem {
100 __le16 cap;
101#define ICE_AQC_CAPS_VALID_FUNCTIONS 0x0005
102#define ICE_AQC_CAPS_SRIOV 0x0012
103#define ICE_AQC_CAPS_VF 0x0013
104#define ICE_AQC_CAPS_VSI 0x0017
105#define ICE_AQC_CAPS_DCB 0x0018
106#define ICE_AQC_CAPS_RSS 0x0040
107#define ICE_AQC_CAPS_RXQS 0x0041
108#define ICE_AQC_CAPS_TXQS 0x0042
109#define ICE_AQC_CAPS_MSIX 0x0043
110#define ICE_AQC_CAPS_FD 0x0045
111#define ICE_AQC_CAPS_1588 0x0046
112#define ICE_AQC_CAPS_MAX_MTU 0x0047
113#define ICE_AQC_CAPS_NVM_VER 0x0048
114#define ICE_AQC_CAPS_PENDING_NVM_VER 0x0049
115#define ICE_AQC_CAPS_OROM_VER 0x004A
116#define ICE_AQC_CAPS_PENDING_OROM_VER 0x004B
117#define ICE_AQC_CAPS_NET_VER 0x004C
118#define ICE_AQC_CAPS_PENDING_NET_VER 0x004D
119#define ICE_AQC_CAPS_RDMA 0x0051
120#define ICE_AQC_CAPS_SENSOR_READING 0x0067
121#define ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE 0x0076
122#define ICE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT 0x0077
123#define ICE_AQC_CAPS_NVM_MGMT 0x0080
124#define ICE_AQC_CAPS_FW_LAG_SUPPORT 0x0092
125#define ICE_AQC_BIT_ROCEV2_LAG 0x01
126#define ICE_AQC_BIT_SRIOV_LAG 0x02
127
128 u8 major_ver;
129 u8 minor_ver;
130 /* Number of resources described by this capability */
131 __le32 number;
132 /* Only meaningful for some types of resources */
133 __le32 logical_id;
134 /* Only meaningful for some types of resources */
135 __le32 phys_id;
136 __le64 rsvd1;
137 __le64 rsvd2;
138};
139
140/* Manage MAC address, read command - indirect (0x0107)
141 * This struct is also used for the response
142 */
143struct ice_aqc_manage_mac_read {
144 __le16 flags; /* Zeroed by device driver */
145#define ICE_AQC_MAN_MAC_LAN_ADDR_VALID BIT(4)
146#define ICE_AQC_MAN_MAC_SAN_ADDR_VALID BIT(5)
147#define ICE_AQC_MAN_MAC_PORT_ADDR_VALID BIT(6)
148#define ICE_AQC_MAN_MAC_WOL_ADDR_VALID BIT(7)
149#define ICE_AQC_MAN_MAC_READ_S 4
150#define ICE_AQC_MAN_MAC_READ_M (0xF << ICE_AQC_MAN_MAC_READ_S)
151 u8 rsvd[2];
152 u8 num_addr; /* Used in response */
153 u8 rsvd1[3];
154 __le32 addr_high;
155 __le32 addr_low;
156};
157
158/* Response buffer format for manage MAC read command */
159struct ice_aqc_manage_mac_read_resp {
160 u8 lport_num;
161 u8 addr_type;
162#define ICE_AQC_MAN_MAC_ADDR_TYPE_LAN 0
163#define ICE_AQC_MAN_MAC_ADDR_TYPE_WOL 1
164 u8 mac_addr[ETH_ALEN];
165};
166
167/* Manage MAC address, write command - direct (0x0108) */
168struct ice_aqc_manage_mac_write {
169 u8 rsvd;
170 u8 flags;
171#define ICE_AQC_MAN_MAC_WR_MC_MAG_EN BIT(0)
172#define ICE_AQC_MAN_MAC_WR_WOL_LAA_PFR_KEEP BIT(1)
173#define ICE_AQC_MAN_MAC_WR_S 6
174#define ICE_AQC_MAN_MAC_WR_M ICE_M(3, ICE_AQC_MAN_MAC_WR_S)
175#define ICE_AQC_MAN_MAC_UPDATE_LAA 0
176#define ICE_AQC_MAN_MAC_UPDATE_LAA_WOL BIT(ICE_AQC_MAN_MAC_WR_S)
177 /* byte stream in network order */
178 u8 mac_addr[ETH_ALEN];
179 __le32 addr_high;
180 __le32 addr_low;
181};
182
183/* Clear PXE Command and response (direct 0x0110) */
184struct ice_aqc_clear_pxe {
185 u8 rx_cnt;
186#define ICE_AQC_CLEAR_PXE_RX_CNT 0x2
187 u8 reserved[15];
188};
189
190/* Get switch configuration (0x0200) */
191struct ice_aqc_get_sw_cfg {
192 /* Reserved for command and copy of request flags for response */
193 __le16 flags;
194 /* First desc in case of command and next_elem in case of response
195 * In case of response, if it is not zero, means all the configuration
196 * was not returned and new command shall be sent with this value in
197 * the 'first desc' field
198 */
199 __le16 element;
200 /* Reserved for command, only used for response */
201 __le16 num_elems;
202 __le16 rsvd;
203 __le32 addr_high;
204 __le32 addr_low;
205};
206
207/* Each entry in the response buffer is of the following type: */
208struct ice_aqc_get_sw_cfg_resp_elem {
209 /* VSI/Port Number */
210 __le16 vsi_port_num;
211#define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S 0
212#define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_M \
213 (0x3FF << ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S)
214#define ICE_AQC_GET_SW_CONF_RESP_TYPE_S 14
215#define ICE_AQC_GET_SW_CONF_RESP_TYPE_M (0x3 << ICE_AQC_GET_SW_CONF_RESP_TYPE_S)
216#define ICE_AQC_GET_SW_CONF_RESP_PHYS_PORT 0
217#define ICE_AQC_GET_SW_CONF_RESP_VIRT_PORT 1
218#define ICE_AQC_GET_SW_CONF_RESP_VSI 2
219
220 /* SWID VSI/Port belongs to */
221 __le16 swid;
222
223 /* Bit 14..0 : PF/VF number VSI belongs to
224 * Bit 15 : VF indication bit
225 */
226 __le16 pf_vf_num;
227#define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S 0
228#define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_M \
229 (0x7FFF << ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S)
230#define ICE_AQC_GET_SW_CONF_RESP_IS_VF BIT(15)
231};
232
233/* Set Port parameters, (direct, 0x0203) */
234struct ice_aqc_set_port_params {
235 __le16 cmd_flags;
236#define ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA BIT(2)
237 __le16 bad_frame_vsi;
238 __le16 swid;
239#define ICE_AQC_PORT_SWID_VALID BIT(15)
240#define ICE_AQC_PORT_SWID_M 0xFF
241 u8 reserved[10];
242};
243
244/* These resource type defines are used for all switch resource
245 * commands where a resource type is required, such as:
246 * Get Resource Allocation command (indirect 0x0204)
247 * Allocate Resources command (indirect 0x0208)
248 * Free Resources command (indirect 0x0209)
249 * Get Allocated Resource Descriptors Command (indirect 0x020A)
250 * Share Resource command (indirect 0x020B)
251 */
252#define ICE_AQC_RES_TYPE_VSI_LIST_REP 0x03
253#define ICE_AQC_RES_TYPE_VSI_LIST_PRUNE 0x04
254#define ICE_AQC_RES_TYPE_RECIPE 0x05
255#define ICE_AQC_RES_TYPE_SWID 0x07
256#define ICE_AQC_RES_TYPE_FDIR_COUNTER_BLOCK 0x21
257#define ICE_AQC_RES_TYPE_FDIR_GUARANTEED_ENTRIES 0x22
258#define ICE_AQC_RES_TYPE_FDIR_SHARED_ENTRIES 0x23
259#define ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID 0x58
260#define ICE_AQC_RES_TYPE_FD_PROF_BLDR_TCAM 0x59
261#define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID 0x60
262#define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_TCAM 0x61
263
264#define ICE_AQC_RES_TYPE_FLAG_SHARED BIT(7)
265#define ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM BIT(12)
266#define ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX BIT(13)
267
268#define ICE_AQC_RES_TYPE_FLAG_DEDICATED 0x00
269
270#define ICE_AQC_RES_TYPE_S 0
271#define ICE_AQC_RES_TYPE_M (0x07F << ICE_AQC_RES_TYPE_S)
272
273/* Allocate Resources command (indirect 0x0208)
274 * Free Resources command (indirect 0x0209)
275 * Share Resource command (indirect 0x020B)
276 */
277struct ice_aqc_alloc_free_res_cmd {
278 __le16 num_entries; /* Number of Resource entries */
279 u8 reserved[6];
280 __le32 addr_high;
281 __le32 addr_low;
282};
283
284/* Resource descriptor */
285struct ice_aqc_res_elem {
286 union {
287 __le16 sw_resp;
288 __le16 flu_resp;
289 } e;
290};
291
292/* Buffer for Allocate/Free Resources commands */
293struct ice_aqc_alloc_free_res_elem {
294 __le16 res_type; /* Types defined above cmd 0x0204 */
295#define ICE_AQC_RES_TYPE_SHARED_S 7
296#define ICE_AQC_RES_TYPE_SHARED_M (0x1 << ICE_AQC_RES_TYPE_SHARED_S)
297#define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S 8
298#define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_M \
299 (0xF << ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S)
300 __le16 num_elems;
301 struct ice_aqc_res_elem elem[];
302};
303
304/* Request buffer for Set VLAN Mode AQ command (indirect 0x020C) */
305struct ice_aqc_set_vlan_mode {
306 u8 reserved;
307 u8 l2tag_prio_tagging;
308#define ICE_AQ_VLAN_PRIO_TAG_S 0
309#define ICE_AQ_VLAN_PRIO_TAG_M (0x7 << ICE_AQ_VLAN_PRIO_TAG_S)
310#define ICE_AQ_VLAN_PRIO_TAG_NOT_SUPPORTED 0x0
311#define ICE_AQ_VLAN_PRIO_TAG_STAG 0x1
312#define ICE_AQ_VLAN_PRIO_TAG_OUTER_CTAG 0x2
313#define ICE_AQ_VLAN_PRIO_TAG_OUTER_VLAN 0x3
314#define ICE_AQ_VLAN_PRIO_TAG_INNER_CTAG 0x4
315#define ICE_AQ_VLAN_PRIO_TAG_MAX 0x4
316#define ICE_AQ_VLAN_PRIO_TAG_ERROR 0x7
317 u8 l2tag_reserved[64];
318 u8 rdma_packet;
319#define ICE_AQ_VLAN_RDMA_TAG_S 0
320#define ICE_AQ_VLAN_RDMA_TAG_M (0x3F << ICE_AQ_VLAN_RDMA_TAG_S)
321#define ICE_AQ_SVM_VLAN_RDMA_PKT_FLAG_SETTING 0x10
322#define ICE_AQ_DVM_VLAN_RDMA_PKT_FLAG_SETTING 0x1A
323 u8 rdma_reserved[2];
324 u8 mng_vlan_prot_id;
325#define ICE_AQ_VLAN_MNG_PROTOCOL_ID_OUTER 0x10
326#define ICE_AQ_VLAN_MNG_PROTOCOL_ID_INNER 0x11
327 u8 prot_id_reserved[30];
328};
329
330/* Response buffer for Get VLAN Mode AQ command (indirect 0x020D) */
331struct ice_aqc_get_vlan_mode {
332 u8 vlan_mode;
333#define ICE_AQ_VLAN_MODE_DVM_ENA BIT(0)
334 u8 l2tag_prio_tagging;
335 u8 reserved[98];
336};
337
338/* Add VSI (indirect 0x0210)
339 * Update VSI (indirect 0x0211)
340 * Get VSI (indirect 0x0212)
341 * Free VSI (indirect 0x0213)
342 */
343struct ice_aqc_add_get_update_free_vsi {
344 __le16 vsi_num;
345#define ICE_AQ_VSI_NUM_S 0
346#define ICE_AQ_VSI_NUM_M (0x03FF << ICE_AQ_VSI_NUM_S)
347#define ICE_AQ_VSI_IS_VALID BIT(15)
348 __le16 cmd_flags;
349#define ICE_AQ_VSI_KEEP_ALLOC 0x1
350 u8 vf_id;
351 u8 reserved;
352 __le16 vsi_flags;
353#define ICE_AQ_VSI_TYPE_S 0
354#define ICE_AQ_VSI_TYPE_M (0x3 << ICE_AQ_VSI_TYPE_S)
355#define ICE_AQ_VSI_TYPE_VF 0x0
356#define ICE_AQ_VSI_TYPE_VMDQ2 0x1
357#define ICE_AQ_VSI_TYPE_PF 0x2
358#define ICE_AQ_VSI_TYPE_EMP_MNG 0x3
359 __le32 addr_high;
360 __le32 addr_low;
361};
362
363/* Response descriptor for:
364 * Add VSI (indirect 0x0210)
365 * Update VSI (indirect 0x0211)
366 * Free VSI (indirect 0x0213)
367 */
368struct ice_aqc_add_update_free_vsi_resp {
369 __le16 vsi_num;
370 __le16 ext_status;
371 __le16 vsi_used;
372 __le16 vsi_free;
373 __le32 addr_high;
374 __le32 addr_low;
375};
376
377struct ice_aqc_vsi_props {
378 __le16 valid_sections;
379#define ICE_AQ_VSI_PROP_SW_VALID BIT(0)
380#define ICE_AQ_VSI_PROP_SECURITY_VALID BIT(1)
381#define ICE_AQ_VSI_PROP_VLAN_VALID BIT(2)
382#define ICE_AQ_VSI_PROP_OUTER_TAG_VALID BIT(3)
383#define ICE_AQ_VSI_PROP_INGRESS_UP_VALID BIT(4)
384#define ICE_AQ_VSI_PROP_EGRESS_UP_VALID BIT(5)
385#define ICE_AQ_VSI_PROP_RXQ_MAP_VALID BIT(6)
386#define ICE_AQ_VSI_PROP_Q_OPT_VALID BIT(7)
387#define ICE_AQ_VSI_PROP_OUTER_UP_VALID BIT(8)
388#define ICE_AQ_VSI_PROP_FLOW_DIR_VALID BIT(11)
389#define ICE_AQ_VSI_PROP_PASID_VALID BIT(12)
390 /* switch section */
391 u8 sw_id;
392 u8 sw_flags;
393#define ICE_AQ_VSI_SW_FLAG_ALLOW_LB BIT(5)
394#define ICE_AQ_VSI_SW_FLAG_LOCAL_LB BIT(6)
395#define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE BIT(7)
396 u8 sw_flags2;
397#define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S 0
398#define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M (0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S)
399#define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA BIT(0)
400#define ICE_AQ_VSI_SW_FLAG_LAN_ENA BIT(4)
401 u8 veb_stat_id;
402#define ICE_AQ_VSI_SW_VEB_STAT_ID_S 0
403#define ICE_AQ_VSI_SW_VEB_STAT_ID_M (0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S)
404#define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID BIT(5)
405 /* security section */
406 u8 sec_flags;
407#define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD BIT(0)
408#define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF BIT(2)
409#define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S 4
410#define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M (0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S)
411#define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA BIT(0)
412 u8 sec_reserved;
413 /* VLAN section */
414 __le16 port_based_inner_vlan; /* VLANS include priority bits */
415 u8 inner_vlan_reserved[2];
416 u8 inner_vlan_flags;
417#define ICE_AQ_VSI_INNER_VLAN_TX_MODE_S 0
418#define ICE_AQ_VSI_INNER_VLAN_TX_MODE_M (0x3 << ICE_AQ_VSI_INNER_VLAN_TX_MODE_S)
419#define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED 0x1
420#define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTTAGGED 0x2
421#define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL 0x3
422#define ICE_AQ_VSI_INNER_VLAN_INSERT_PVID BIT(2)
423#define ICE_AQ_VSI_INNER_VLAN_EMODE_S 3
424#define ICE_AQ_VSI_INNER_VLAN_EMODE_M (0x3 << ICE_AQ_VSI_INNER_VLAN_EMODE_S)
425#define ICE_AQ_VSI_INNER_VLAN_EMODE_STR_BOTH 0x0U
426#define ICE_AQ_VSI_INNER_VLAN_EMODE_STR_UP 0x1U
427#define ICE_AQ_VSI_INNER_VLAN_EMODE_STR 0x2U
428#define ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING 0x3U
429 u8 inner_vlan_reserved2[3];
430 /* ingress egress up sections */
431 __le32 ingress_table; /* bitmap, 3 bits per up */
432#define ICE_AQ_VSI_UP_TABLE_UP0_S 0
433#define ICE_AQ_VSI_UP_TABLE_UP0_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S)
434#define ICE_AQ_VSI_UP_TABLE_UP1_S 3
435#define ICE_AQ_VSI_UP_TABLE_UP1_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S)
436#define ICE_AQ_VSI_UP_TABLE_UP2_S 6
437#define ICE_AQ_VSI_UP_TABLE_UP2_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S)
438#define ICE_AQ_VSI_UP_TABLE_UP3_S 9
439#define ICE_AQ_VSI_UP_TABLE_UP3_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S)
440#define ICE_AQ_VSI_UP_TABLE_UP4_S 12
441#define ICE_AQ_VSI_UP_TABLE_UP4_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S)
442#define ICE_AQ_VSI_UP_TABLE_UP5_S 15
443#define ICE_AQ_VSI_UP_TABLE_UP5_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S)
444#define ICE_AQ_VSI_UP_TABLE_UP6_S 18
445#define ICE_AQ_VSI_UP_TABLE_UP6_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S)
446#define ICE_AQ_VSI_UP_TABLE_UP7_S 21
447#define ICE_AQ_VSI_UP_TABLE_UP7_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S)
448 __le32 egress_table; /* same defines as for ingress table */
449 /* outer tags section */
450 __le16 port_based_outer_vlan;
451 u8 outer_vlan_flags;
452#define ICE_AQ_VSI_OUTER_VLAN_EMODE_S 0
453#define ICE_AQ_VSI_OUTER_VLAN_EMODE_M (0x3 << ICE_AQ_VSI_OUTER_VLAN_EMODE_S)
454#define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_BOTH 0x0
455#define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_UP 0x1
456#define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW 0x2
457#define ICE_AQ_VSI_OUTER_VLAN_EMODE_NOTHING 0x3
458#define ICE_AQ_VSI_OUTER_TAG_TYPE_S 2
459#define ICE_AQ_VSI_OUTER_TAG_TYPE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S)
460#define ICE_AQ_VSI_OUTER_TAG_NONE 0x0
461#define ICE_AQ_VSI_OUTER_TAG_STAG 0x1
462#define ICE_AQ_VSI_OUTER_TAG_VLAN_8100 0x2
463#define ICE_AQ_VSI_OUTER_TAG_VLAN_9100 0x3
464#define ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_INSERT BIT(4)
465#define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S 5
466#define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_M (0x3 << ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S)
467#define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ACCEPTUNTAGGED 0x1
468#define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ACCEPTTAGGED 0x2
469#define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ALL 0x3
470#define ICE_AQ_VSI_OUTER_VLAN_BLOCK_TX_DESC BIT(7)
471 u8 outer_vlan_reserved;
472 /* queue mapping section */
473 __le16 mapping_flags;
474#define ICE_AQ_VSI_Q_MAP_CONTIG 0x0
475#define ICE_AQ_VSI_Q_MAP_NONCONTIG BIT(0)
476 __le16 q_mapping[16];
477#define ICE_AQ_VSI_Q_S 0
478#define ICE_AQ_VSI_Q_M (0x7FF << ICE_AQ_VSI_Q_S)
479 __le16 tc_mapping[8];
480#define ICE_AQ_VSI_TC_Q_OFFSET_S 0
481#define ICE_AQ_VSI_TC_Q_OFFSET_M (0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S)
482#define ICE_AQ_VSI_TC_Q_NUM_S 11
483#define ICE_AQ_VSI_TC_Q_NUM_M (0xF << ICE_AQ_VSI_TC_Q_NUM_S)
484 /* queueing option section */
485 u8 q_opt_rss;
486#define ICE_AQ_VSI_Q_OPT_RSS_LUT_S 0
487#define ICE_AQ_VSI_Q_OPT_RSS_LUT_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S)
488#define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI 0x0
489#define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF 0x2
490#define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL 0x3
491#define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S 2
492#define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M (0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S)
493#define ICE_AQ_VSI_Q_OPT_RSS_HASH_S 6
494#define ICE_AQ_VSI_Q_OPT_RSS_HASH_M GENMASK(7, 6)
495#define ICE_AQ_VSI_Q_OPT_RSS_HASH_TPLZ 0x0U
496#define ICE_AQ_VSI_Q_OPT_RSS_HASH_SYM_TPLZ 0x1U
497#define ICE_AQ_VSI_Q_OPT_RSS_HASH_XOR 0x2U
498#define ICE_AQ_VSI_Q_OPT_RSS_HASH_JHASH 0x3U
499 u8 q_opt_tc;
500#define ICE_AQ_VSI_Q_OPT_TC_OVR_S 0
501#define ICE_AQ_VSI_Q_OPT_TC_OVR_M (0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S)
502#define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR BIT(7)
503 u8 q_opt_flags;
504#define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN BIT(0)
505 u8 q_opt_reserved[3];
506 /* outer up section */
507 __le32 outer_up_table; /* same structure and defines as ingress tbl */
508 /* section 10 */
509 __le16 sect_10_reserved;
510 /* flow director section */
511 __le16 fd_options;
512#define ICE_AQ_VSI_FD_ENABLE BIT(0)
513#define ICE_AQ_VSI_FD_TX_AUTO_ENABLE BIT(1)
514#define ICE_AQ_VSI_FD_PROG_ENABLE BIT(3)
515 __le16 max_fd_fltr_dedicated;
516 __le16 max_fd_fltr_shared;
517 __le16 fd_def_q;
518#define ICE_AQ_VSI_FD_DEF_Q_S 0
519#define ICE_AQ_VSI_FD_DEF_Q_M (0x7FF << ICE_AQ_VSI_FD_DEF_Q_S)
520#define ICE_AQ_VSI_FD_DEF_GRP_S 12
521#define ICE_AQ_VSI_FD_DEF_GRP_M (0x7 << ICE_AQ_VSI_FD_DEF_GRP_S)
522 __le16 fd_report_opt;
523#define ICE_AQ_VSI_FD_REPORT_Q_S 0
524#define ICE_AQ_VSI_FD_REPORT_Q_M (0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S)
525#define ICE_AQ_VSI_FD_DEF_PRIORITY_S 12
526#define ICE_AQ_VSI_FD_DEF_PRIORITY_M (0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S)
527#define ICE_AQ_VSI_FD_DEF_DROP BIT(15)
528 /* PASID section */
529 __le32 pasid_id;
530#define ICE_AQ_VSI_PASID_ID_S 0
531#define ICE_AQ_VSI_PASID_ID_M (0xFFFFF << ICE_AQ_VSI_PASID_ID_S)
532#define ICE_AQ_VSI_PASID_ID_VALID BIT(31)
533 u8 reserved[24];
534};
535
536#define ICE_MAX_NUM_RECIPES 64
537
538/* Add/Get Recipe (indirect 0x0290/0x0292) */
539struct ice_aqc_add_get_recipe {
540 __le16 num_sub_recipes; /* Input in Add cmd, Output in Get cmd */
541 __le16 return_index; /* Input, used for Get cmd only */
542 u8 reserved[4];
543 __le32 addr_high;
544 __le32 addr_low;
545};
546
547struct ice_aqc_recipe_content {
548 u8 rid;
549#define ICE_AQ_RECIPE_ID_S 0
550#define ICE_AQ_RECIPE_ID_M (0x3F << ICE_AQ_RECIPE_ID_S)
551#define ICE_AQ_RECIPE_ID_IS_ROOT BIT(7)
552#define ICE_AQ_SW_ID_LKUP_IDX 0
553 u8 lkup_indx[5];
554#define ICE_AQ_RECIPE_LKUP_DATA_S 0
555#define ICE_AQ_RECIPE_LKUP_DATA_M (0x3F << ICE_AQ_RECIPE_LKUP_DATA_S)
556#define ICE_AQ_RECIPE_LKUP_IGNORE BIT(7)
557#define ICE_AQ_SW_ID_LKUP_MASK 0x00FF
558 __le16 mask[5];
559 u8 result_indx;
560#define ICE_AQ_RECIPE_RESULT_DATA_S 0
561#define ICE_AQ_RECIPE_RESULT_DATA_M (0x3F << ICE_AQ_RECIPE_RESULT_DATA_S)
562#define ICE_AQ_RECIPE_RESULT_EN BIT(7)
563 u8 rsvd0[3];
564 u8 act_ctrl_join_priority;
565 u8 act_ctrl_fwd_priority;
566#define ICE_AQ_RECIPE_FWD_PRIORITY_S 0
567#define ICE_AQ_RECIPE_FWD_PRIORITY_M (0xF << ICE_AQ_RECIPE_FWD_PRIORITY_S)
568 u8 act_ctrl;
569#define ICE_AQ_RECIPE_ACT_NEED_PASS_L2 BIT(0)
570#define ICE_AQ_RECIPE_ACT_ALLOW_PASS_L2 BIT(1)
571#define ICE_AQ_RECIPE_ACT_INV_ACT BIT(2)
572#define ICE_AQ_RECIPE_ACT_PRUNE_INDX_S 4
573#define ICE_AQ_RECIPE_ACT_PRUNE_INDX_M (0x3 << ICE_AQ_RECIPE_ACT_PRUNE_INDX_S)
574 u8 rsvd1;
575 __le32 dflt_act;
576#define ICE_AQ_RECIPE_DFLT_ACT_S 0
577#define ICE_AQ_RECIPE_DFLT_ACT_M (0x7FFFF << ICE_AQ_RECIPE_DFLT_ACT_S)
578#define ICE_AQ_RECIPE_DFLT_ACT_VALID BIT(31)
579};
580
581struct ice_aqc_recipe_data_elem {
582 u8 recipe_indx;
583 u8 resp_bits;
584#define ICE_AQ_RECIPE_WAS_UPDATED BIT(0)
585 u8 rsvd0[2];
586 u8 recipe_bitmap[8];
587 u8 rsvd1[4];
588 struct ice_aqc_recipe_content content;
589 u8 rsvd2[20];
590};
591
592/* Set/Get Recipes to Profile Association (direct 0x0291/0x0293) */
593struct ice_aqc_recipe_to_profile {
594 __le16 profile_id;
595 u8 rsvd[6];
596 __le64 recipe_assoc;
597};
598static_assert(sizeof(struct ice_aqc_recipe_to_profile) == 16);
599
600/* Add/Update/Remove/Get switch rules (indirect 0x02A0, 0x02A1, 0x02A2, 0x02A3)
601 */
602struct ice_aqc_sw_rules {
603 /* ops: add switch rules, referring the number of rules.
604 * ops: update switch rules, referring the number of filters
605 * ops: remove switch rules, referring the entry index.
606 * ops: get switch rules, referring to the number of filters.
607 */
608 __le16 num_rules_fltr_entry_index;
609 u8 reserved[6];
610 __le32 addr_high;
611 __le32 addr_low;
612};
613
614/* Add switch rule response:
615 * Content of return buffer is same as the input buffer. The status field and
616 * LUT index are updated as part of the response
617 */
618struct ice_aqc_sw_rules_elem_hdr {
619 __le16 type; /* Switch rule type, one of T_... */
620#define ICE_AQC_SW_RULES_T_LKUP_RX 0x0
621#define ICE_AQC_SW_RULES_T_LKUP_TX 0x1
622#define ICE_AQC_SW_RULES_T_LG_ACT 0x2
623#define ICE_AQC_SW_RULES_T_VSI_LIST_SET 0x3
624#define ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR 0x4
625#define ICE_AQC_SW_RULES_T_PRUNE_LIST_SET 0x5
626#define ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR 0x6
627 __le16 status;
628} __packed __aligned(sizeof(__le16));
629
630/* Add/Update/Get/Remove lookup Rx/Tx command/response entry
631 * This structures describes the lookup rules and associated actions. "index"
632 * is returned as part of a response to a successful Add command, and can be
633 * used to identify the rule for Update/Get/Remove commands.
634 */
635struct ice_sw_rule_lkup_rx_tx {
636 struct ice_aqc_sw_rules_elem_hdr hdr;
637
638 __le16 recipe_id;
639#define ICE_SW_RECIPE_LOGICAL_PORT_FWD 10
640 /* Source port for LOOKUP_RX and source VSI in case of LOOKUP_TX */
641 __le16 src;
642 __le32 act;
643
644 /* Bit 0:1 - Action type */
645#define ICE_SINGLE_ACT_TYPE_S 0x00
646#define ICE_SINGLE_ACT_TYPE_M (0x3 << ICE_SINGLE_ACT_TYPE_S)
647
648 /* Bit 2 - Loop back enable
649 * Bit 3 - LAN enable
650 */
651#define ICE_SINGLE_ACT_LB_ENABLE BIT(2)
652#define ICE_SINGLE_ACT_LAN_ENABLE BIT(3)
653
654 /* Action type = 0 - Forward to VSI or VSI list */
655#define ICE_SINGLE_ACT_VSI_FORWARDING 0x0
656
657#define ICE_SINGLE_ACT_VSI_ID_S 4
658#define ICE_SINGLE_ACT_VSI_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_ID_S)
659#define ICE_SINGLE_ACT_VSI_LIST_ID_S 4
660#define ICE_SINGLE_ACT_VSI_LIST_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_LIST_ID_S)
661 /* This bit needs to be set if action is forward to VSI list */
662#define ICE_SINGLE_ACT_VSI_LIST BIT(14)
663#define ICE_SINGLE_ACT_VALID_BIT BIT(17)
664#define ICE_SINGLE_ACT_DROP BIT(18)
665
666 /* Action type = 1 - Forward to Queue of Queue group */
667#define ICE_SINGLE_ACT_TO_Q 0x1
668#define ICE_SINGLE_ACT_Q_INDEX_S 4
669#define ICE_SINGLE_ACT_Q_INDEX_M (0x7FF << ICE_SINGLE_ACT_Q_INDEX_S)
670#define ICE_SINGLE_ACT_Q_REGION_S 15
671#define ICE_SINGLE_ACT_Q_REGION_M (0x7 << ICE_SINGLE_ACT_Q_REGION_S)
672#define ICE_SINGLE_ACT_Q_PRIORITY BIT(18)
673
674 /* Action type = 2 - Prune */
675#define ICE_SINGLE_ACT_PRUNE 0x2
676#define ICE_SINGLE_ACT_EGRESS BIT(15)
677#define ICE_SINGLE_ACT_INGRESS BIT(16)
678#define ICE_SINGLE_ACT_PRUNET BIT(17)
679 /* Bit 18 should be set to 0 for this action */
680
681 /* Action type = 2 - Pointer */
682#define ICE_SINGLE_ACT_PTR 0x2
683#define ICE_SINGLE_ACT_PTR_VAL_S 4
684#define ICE_SINGLE_ACT_PTR_VAL_M (0x1FFF << ICE_SINGLE_ACT_PTR_VAL_S)
685 /* Bit 18 should be set to 1 */
686#define ICE_SINGLE_ACT_PTR_BIT BIT(18)
687
688 /* Action type = 3 - Other actions. Last two bits
689 * are other action identifier
690 */
691#define ICE_SINGLE_ACT_OTHER_ACTS 0x3
692#define ICE_SINGLE_OTHER_ACT_IDENTIFIER_S 17
693#define ICE_SINGLE_OTHER_ACT_IDENTIFIER_M \
694 (0x3 << ICE_SINGLE_OTHER_ACT_IDENTIFIER_S)
695
696 /* Bit 17:18 - Defines other actions */
697 /* Other action = 0 - Mirror VSI */
698#define ICE_SINGLE_OTHER_ACT_MIRROR 0
699#define ICE_SINGLE_ACT_MIRROR_VSI_ID_S 4
700#define ICE_SINGLE_ACT_MIRROR_VSI_ID_M \
701 (0x3FF << ICE_SINGLE_ACT_MIRROR_VSI_ID_S)
702
703 /* Other action = 3 - Set Stat count */
704#define ICE_SINGLE_OTHER_ACT_STAT_COUNT 3
705#define ICE_SINGLE_ACT_STAT_COUNT_INDEX_S 4
706#define ICE_SINGLE_ACT_STAT_COUNT_INDEX_M \
707 (0x7F << ICE_SINGLE_ACT_STAT_COUNT_INDEX_S)
708
709 __le16 index; /* The index of the rule in the lookup table */
710 /* Length and values of the header to be matched per recipe or
711 * lookup-type
712 */
713 __le16 hdr_len;
714 u8 hdr_data[];
715} __packed __aligned(sizeof(__le16));
716
717/* Add/Update/Remove large action command/response entry
718 * "index" is returned as part of a response to a successful Add command, and
719 * can be used to identify the action for Update/Get/Remove commands.
720 */
721struct ice_sw_rule_lg_act {
722 struct ice_aqc_sw_rules_elem_hdr hdr;
723
724 __le16 index; /* Index in large action table */
725 __le16 size;
726 /* Max number of large actions */
727#define ICE_MAX_LG_ACT 4
728 /* Bit 0:1 - Action type */
729#define ICE_LG_ACT_TYPE_S 0
730#define ICE_LG_ACT_TYPE_M (0x7 << ICE_LG_ACT_TYPE_S)
731
732 /* Action type = 0 - Forward to VSI or VSI list */
733#define ICE_LG_ACT_VSI_FORWARDING 0
734#define ICE_LG_ACT_VSI_ID_S 3
735#define ICE_LG_ACT_VSI_ID_M (0x3FF << ICE_LG_ACT_VSI_ID_S)
736#define ICE_LG_ACT_VSI_LIST_ID_S 3
737#define ICE_LG_ACT_VSI_LIST_ID_M (0x3FF << ICE_LG_ACT_VSI_LIST_ID_S)
738 /* This bit needs to be set if action is forward to VSI list */
739#define ICE_LG_ACT_VSI_LIST BIT(13)
740
741#define ICE_LG_ACT_VALID_BIT BIT(16)
742
743 /* Action type = 1 - Forward to Queue of Queue group */
744#define ICE_LG_ACT_TO_Q 0x1
745#define ICE_LG_ACT_Q_INDEX_S 3
746#define ICE_LG_ACT_Q_INDEX_M (0x7FF << ICE_LG_ACT_Q_INDEX_S)
747#define ICE_LG_ACT_Q_REGION_S 14
748#define ICE_LG_ACT_Q_REGION_M (0x7 << ICE_LG_ACT_Q_REGION_S)
749#define ICE_LG_ACT_Q_PRIORITY_SET BIT(17)
750
751 /* Action type = 2 - Prune */
752#define ICE_LG_ACT_PRUNE 0x2
753#define ICE_LG_ACT_EGRESS BIT(14)
754#define ICE_LG_ACT_INGRESS BIT(15)
755#define ICE_LG_ACT_PRUNET BIT(16)
756
757 /* Action type = 3 - Mirror VSI */
758#define ICE_LG_OTHER_ACT_MIRROR 0x3
759#define ICE_LG_ACT_MIRROR_VSI_ID_S 3
760#define ICE_LG_ACT_MIRROR_VSI_ID_M (0x3FF << ICE_LG_ACT_MIRROR_VSI_ID_S)
761
762 /* Action type = 5 - Generic Value */
763#define ICE_LG_ACT_GENERIC 0x5
764#define ICE_LG_ACT_GENERIC_VALUE_S 3
765#define ICE_LG_ACT_GENERIC_VALUE_M (0xFFFF << ICE_LG_ACT_GENERIC_VALUE_S)
766#define ICE_LG_ACT_GENERIC_OFFSET_S 19
767#define ICE_LG_ACT_GENERIC_OFFSET_M (0x7 << ICE_LG_ACT_GENERIC_OFFSET_S)
768#define ICE_LG_ACT_GENERIC_PRIORITY_S 22
769#define ICE_LG_ACT_GENERIC_PRIORITY_M (0x7 << ICE_LG_ACT_GENERIC_PRIORITY_S)
770#define ICE_LG_ACT_GENERIC_OFF_RX_DESC_PROF_IDX 7
771
772 /* Action = 7 - Set Stat count */
773#define ICE_LG_ACT_STAT_COUNT 0x7
774#define ICE_LG_ACT_STAT_COUNT_S 3
775#define ICE_LG_ACT_STAT_COUNT_M (0x7F << ICE_LG_ACT_STAT_COUNT_S)
776 __le32 act[]; /* array of size for actions */
777} __packed __aligned(sizeof(__le16));
778
779/* Add/Update/Remove VSI list command/response entry
780 * "index" is returned as part of a response to a successful Add command, and
781 * can be used to identify the VSI list for Update/Get/Remove commands.
782 */
783struct ice_sw_rule_vsi_list {
784 struct ice_aqc_sw_rules_elem_hdr hdr;
785
786 __le16 index; /* Index of VSI/Prune list */
787 __le16 number_vsi;
788 __le16 vsi[]; /* Array of number_vsi VSI numbers */
789} __packed __aligned(sizeof(__le16));
790
791/* Query PFC Mode (direct 0x0302)
792 * Set PFC Mode (direct 0x0303)
793 */
794struct ice_aqc_set_query_pfc_mode {
795 u8 pfc_mode;
796/* For Query Command response, reserved in all other cases */
797#define ICE_AQC_PFC_VLAN_BASED_PFC 1
798#define ICE_AQC_PFC_DSCP_BASED_PFC 2
799 u8 rsvd[15];
800};
801/* Get Default Topology (indirect 0x0400) */
802struct ice_aqc_get_topo {
803 u8 port_num;
804 u8 num_branches;
805 __le16 reserved1;
806 __le32 reserved2;
807 __le32 addr_high;
808 __le32 addr_low;
809};
810
811/* Update TSE (indirect 0x0403)
812 * Get TSE (indirect 0x0404)
813 * Add TSE (indirect 0x0401)
814 * Delete TSE (indirect 0x040F)
815 * Move TSE (indirect 0x0408)
816 * Suspend Nodes (indirect 0x0409)
817 * Resume Nodes (indirect 0x040A)
818 */
819struct ice_aqc_sched_elem_cmd {
820 __le16 num_elem_req; /* Used by commands */
821 __le16 num_elem_resp; /* Used by responses */
822 __le32 reserved;
823 __le32 addr_high;
824 __le32 addr_low;
825};
826
827struct ice_aqc_txsched_move_grp_info_hdr {
828 __le32 src_parent_teid;
829 __le32 dest_parent_teid;
830 __le16 num_elems;
831 u8 mode;
832#define ICE_AQC_MOVE_ELEM_MODE_SAME_PF 0x0
833#define ICE_AQC_MOVE_ELEM_MODE_GIVE_OWN 0x1
834#define ICE_AQC_MOVE_ELEM_MODE_KEEP_OWN 0x2
835 u8 reserved;
836};
837
838struct ice_aqc_move_elem {
839 struct ice_aqc_txsched_move_grp_info_hdr hdr;
840 __le32 teid[];
841};
842
843struct ice_aqc_elem_info_bw {
844 __le16 bw_profile_idx;
845 __le16 bw_alloc;
846};
847
848struct ice_aqc_txsched_elem {
849 u8 elem_type; /* Special field, reserved for some aq calls */
850#define ICE_AQC_ELEM_TYPE_UNDEFINED 0x0
851#define ICE_AQC_ELEM_TYPE_ROOT_PORT 0x1
852#define ICE_AQC_ELEM_TYPE_TC 0x2
853#define ICE_AQC_ELEM_TYPE_SE_GENERIC 0x3
854#define ICE_AQC_ELEM_TYPE_ENTRY_POINT 0x4
855#define ICE_AQC_ELEM_TYPE_LEAF 0x5
856#define ICE_AQC_ELEM_TYPE_SE_PADDED 0x6
857 u8 valid_sections;
858#define ICE_AQC_ELEM_VALID_GENERIC BIT(0)
859#define ICE_AQC_ELEM_VALID_CIR BIT(1)
860#define ICE_AQC_ELEM_VALID_EIR BIT(2)
861#define ICE_AQC_ELEM_VALID_SHARED BIT(3)
862 u8 generic;
863#define ICE_AQC_ELEM_GENERIC_MODE_M 0x1
864#define ICE_AQC_ELEM_GENERIC_PRIO_S 0x1
865#define ICE_AQC_ELEM_GENERIC_PRIO_M GENMASK(3, 1)
866#define ICE_AQC_ELEM_GENERIC_SP_S 0x4
867#define ICE_AQC_ELEM_GENERIC_SP_M GENMASK(4, 4)
868#define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S 0x5
869#define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_M \
870 (0x3 << ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S)
871 u8 flags; /* Special field, reserved for some aq calls */
872#define ICE_AQC_ELEM_FLAG_SUSPEND_M 0x1
873 struct ice_aqc_elem_info_bw cir_bw;
874 struct ice_aqc_elem_info_bw eir_bw;
875 __le16 srl_id;
876 __le16 reserved2;
877};
878
879struct ice_aqc_txsched_elem_data {
880 __le32 parent_teid;
881 __le32 node_teid;
882 struct ice_aqc_txsched_elem data;
883};
884
885struct ice_aqc_txsched_topo_grp_info_hdr {
886 __le32 parent_teid;
887 __le16 num_elems;
888 __le16 reserved2;
889};
890
891struct ice_aqc_add_elem {
892 struct ice_aqc_txsched_topo_grp_info_hdr hdr;
893 struct ice_aqc_txsched_elem_data generic[];
894};
895
896struct ice_aqc_get_topo_elem {
897 struct ice_aqc_txsched_topo_grp_info_hdr hdr;
898 struct ice_aqc_txsched_elem_data
899 generic[ICE_AQC_TOPO_MAX_LEVEL_NUM];
900};
901
902struct ice_aqc_delete_elem {
903 struct ice_aqc_txsched_topo_grp_info_hdr hdr;
904 __le32 teid[];
905};
906
907/* Query Port ETS (indirect 0x040E)
908 *
909 * This indirect command is used to query port TC node configuration.
910 */
911struct ice_aqc_query_port_ets {
912 __le32 port_teid;
913 __le32 reserved;
914 __le32 addr_high;
915 __le32 addr_low;
916};
917
918struct ice_aqc_port_ets_elem {
919 u8 tc_valid_bits;
920 u8 reserved[3];
921 /* 3 bits for UP per TC 0-7, 4th byte reserved */
922 __le32 up2tc;
923 u8 tc_bw_share[8];
924 __le32 port_eir_prof_id;
925 __le32 port_cir_prof_id;
926 /* 3 bits per Node priority to TC 0-7, 4th byte reserved */
927 __le32 tc_node_prio;
928#define ICE_TC_NODE_PRIO_S 0x4
929 u8 reserved1[4];
930 __le32 tc_node_teid[8]; /* Used for response, reserved in command */
931};
932
933/* Rate limiting profile for
934 * Add RL profile (indirect 0x0410)
935 * Query RL profile (indirect 0x0411)
936 * Remove RL profile (indirect 0x0415)
937 * These indirect commands acts on single or multiple
938 * RL profiles with specified data.
939 */
940struct ice_aqc_rl_profile {
941 __le16 num_profiles;
942 __le16 num_processed; /* Only for response. Reserved in Command. */
943 u8 reserved[4];
944 __le32 addr_high;
945 __le32 addr_low;
946};
947
948struct ice_aqc_rl_profile_elem {
949 u8 level;
950 u8 flags;
951#define ICE_AQC_RL_PROFILE_TYPE_S 0x0
952#define ICE_AQC_RL_PROFILE_TYPE_M (0x3 << ICE_AQC_RL_PROFILE_TYPE_S)
953#define ICE_AQC_RL_PROFILE_TYPE_CIR 0
954#define ICE_AQC_RL_PROFILE_TYPE_EIR 1
955#define ICE_AQC_RL_PROFILE_TYPE_SRL 2
956/* The following flag is used for Query RL Profile Data */
957#define ICE_AQC_RL_PROFILE_INVAL_S 0x7
958#define ICE_AQC_RL_PROFILE_INVAL_M (0x1 << ICE_AQC_RL_PROFILE_INVAL_S)
959
960 __le16 profile_id;
961 __le16 max_burst_size;
962 __le16 rl_multiply;
963 __le16 wake_up_calc;
964 __le16 rl_encode;
965};
966
967/* Query Scheduler Resource Allocation (indirect 0x0412)
968 * This indirect command retrieves the scheduler resources allocated by
969 * EMP Firmware to the given PF.
970 */
971struct ice_aqc_query_txsched_res {
972 u8 reserved[8];
973 __le32 addr_high;
974 __le32 addr_low;
975};
976
977struct ice_aqc_generic_sched_props {
978 __le16 phys_levels;
979 __le16 logical_levels;
980 u8 flattening_bitmap;
981 u8 max_device_cgds;
982 u8 max_pf_cgds;
983 u8 rsvd0;
984 __le16 rdma_qsets;
985 u8 rsvd1[22];
986};
987
988struct ice_aqc_layer_props {
989 u8 logical_layer;
990 u8 chunk_size;
991 __le16 max_device_nodes;
992 __le16 max_pf_nodes;
993 u8 rsvd0[4];
994 __le16 max_sibl_grp_sz;
995 __le16 max_cir_rl_profiles;
996 __le16 max_eir_rl_profiles;
997 __le16 max_srl_profiles;
998 u8 rsvd1[14];
999};
1000
1001struct ice_aqc_query_txsched_res_resp {
1002 struct ice_aqc_generic_sched_props sched_props;
1003 struct ice_aqc_layer_props layer_props[ICE_AQC_TOPO_MAX_LEVEL_NUM];
1004};
1005
1006/* Get PHY capabilities (indirect 0x0600) */
1007struct ice_aqc_get_phy_caps {
1008 u8 lport_num;
1009 u8 reserved;
1010 __le16 param0;
1011 /* 18.0 - Report qualified modules */
1012#define ICE_AQC_GET_PHY_RQM BIT(0)
1013 /* 18.1 - 18.3 : Report mode
1014 * 000b - Report NVM capabilities
1015 * 001b - Report topology capabilities
1016 * 010b - Report SW configured
1017 * 100b - Report default capabilities
1018 */
1019#define ICE_AQC_REPORT_MODE_S 1
1020#define ICE_AQC_REPORT_MODE_M (7 << ICE_AQC_REPORT_MODE_S)
1021#define ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA 0
1022#define ICE_AQC_REPORT_TOPO_CAP_MEDIA BIT(1)
1023#define ICE_AQC_REPORT_ACTIVE_CFG BIT(2)
1024#define ICE_AQC_REPORT_DFLT_CFG BIT(3)
1025 __le32 reserved1;
1026 __le32 addr_high;
1027 __le32 addr_low;
1028};
1029
1030/* This is #define of PHY type (Extended):
1031 * The first set of defines is for phy_type_low.
1032 */
1033#define ICE_PHY_TYPE_LOW_100BASE_TX BIT_ULL(0)
1034#define ICE_PHY_TYPE_LOW_100M_SGMII BIT_ULL(1)
1035#define ICE_PHY_TYPE_LOW_1000BASE_T BIT_ULL(2)
1036#define ICE_PHY_TYPE_LOW_1000BASE_SX BIT_ULL(3)
1037#define ICE_PHY_TYPE_LOW_1000BASE_LX BIT_ULL(4)
1038#define ICE_PHY_TYPE_LOW_1000BASE_KX BIT_ULL(5)
1039#define ICE_PHY_TYPE_LOW_1G_SGMII BIT_ULL(6)
1040#define ICE_PHY_TYPE_LOW_2500BASE_T BIT_ULL(7)
1041#define ICE_PHY_TYPE_LOW_2500BASE_X BIT_ULL(8)
1042#define ICE_PHY_TYPE_LOW_2500BASE_KX BIT_ULL(9)
1043#define ICE_PHY_TYPE_LOW_5GBASE_T BIT_ULL(10)
1044#define ICE_PHY_TYPE_LOW_5GBASE_KR BIT_ULL(11)
1045#define ICE_PHY_TYPE_LOW_10GBASE_T BIT_ULL(12)
1046#define ICE_PHY_TYPE_LOW_10G_SFI_DA BIT_ULL(13)
1047#define ICE_PHY_TYPE_LOW_10GBASE_SR BIT_ULL(14)
1048#define ICE_PHY_TYPE_LOW_10GBASE_LR BIT_ULL(15)
1049#define ICE_PHY_TYPE_LOW_10GBASE_KR_CR1 BIT_ULL(16)
1050#define ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC BIT_ULL(17)
1051#define ICE_PHY_TYPE_LOW_10G_SFI_C2C BIT_ULL(18)
1052#define ICE_PHY_TYPE_LOW_25GBASE_T BIT_ULL(19)
1053#define ICE_PHY_TYPE_LOW_25GBASE_CR BIT_ULL(20)
1054#define ICE_PHY_TYPE_LOW_25GBASE_CR_S BIT_ULL(21)
1055#define ICE_PHY_TYPE_LOW_25GBASE_CR1 BIT_ULL(22)
1056#define ICE_PHY_TYPE_LOW_25GBASE_SR BIT_ULL(23)
1057#define ICE_PHY_TYPE_LOW_25GBASE_LR BIT_ULL(24)
1058#define ICE_PHY_TYPE_LOW_25GBASE_KR BIT_ULL(25)
1059#define ICE_PHY_TYPE_LOW_25GBASE_KR_S BIT_ULL(26)
1060#define ICE_PHY_TYPE_LOW_25GBASE_KR1 BIT_ULL(27)
1061#define ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC BIT_ULL(28)
1062#define ICE_PHY_TYPE_LOW_25G_AUI_C2C BIT_ULL(29)
1063#define ICE_PHY_TYPE_LOW_40GBASE_CR4 BIT_ULL(30)
1064#define ICE_PHY_TYPE_LOW_40GBASE_SR4 BIT_ULL(31)
1065#define ICE_PHY_TYPE_LOW_40GBASE_LR4 BIT_ULL(32)
1066#define ICE_PHY_TYPE_LOW_40GBASE_KR4 BIT_ULL(33)
1067#define ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC BIT_ULL(34)
1068#define ICE_PHY_TYPE_LOW_40G_XLAUI BIT_ULL(35)
1069#define ICE_PHY_TYPE_LOW_50GBASE_CR2 BIT_ULL(36)
1070#define ICE_PHY_TYPE_LOW_50GBASE_SR2 BIT_ULL(37)
1071#define ICE_PHY_TYPE_LOW_50GBASE_LR2 BIT_ULL(38)
1072#define ICE_PHY_TYPE_LOW_50GBASE_KR2 BIT_ULL(39)
1073#define ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC BIT_ULL(40)
1074#define ICE_PHY_TYPE_LOW_50G_LAUI2 BIT_ULL(41)
1075#define ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC BIT_ULL(42)
1076#define ICE_PHY_TYPE_LOW_50G_AUI2 BIT_ULL(43)
1077#define ICE_PHY_TYPE_LOW_50GBASE_CP BIT_ULL(44)
1078#define ICE_PHY_TYPE_LOW_50GBASE_SR BIT_ULL(45)
1079#define ICE_PHY_TYPE_LOW_50GBASE_FR BIT_ULL(46)
1080#define ICE_PHY_TYPE_LOW_50GBASE_LR BIT_ULL(47)
1081#define ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4 BIT_ULL(48)
1082#define ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC BIT_ULL(49)
1083#define ICE_PHY_TYPE_LOW_50G_AUI1 BIT_ULL(50)
1084#define ICE_PHY_TYPE_LOW_100GBASE_CR4 BIT_ULL(51)
1085#define ICE_PHY_TYPE_LOW_100GBASE_SR4 BIT_ULL(52)
1086#define ICE_PHY_TYPE_LOW_100GBASE_LR4 BIT_ULL(53)
1087#define ICE_PHY_TYPE_LOW_100GBASE_KR4 BIT_ULL(54)
1088#define ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC BIT_ULL(55)
1089#define ICE_PHY_TYPE_LOW_100G_CAUI4 BIT_ULL(56)
1090#define ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC BIT_ULL(57)
1091#define ICE_PHY_TYPE_LOW_100G_AUI4 BIT_ULL(58)
1092#define ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4 BIT_ULL(59)
1093#define ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4 BIT_ULL(60)
1094#define ICE_PHY_TYPE_LOW_100GBASE_CP2 BIT_ULL(61)
1095#define ICE_PHY_TYPE_LOW_100GBASE_SR2 BIT_ULL(62)
1096#define ICE_PHY_TYPE_LOW_100GBASE_DR BIT_ULL(63)
1097#define ICE_PHY_TYPE_LOW_MAX_INDEX 63
1098/* The second set of defines is for phy_type_high. */
1099#define ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4 BIT_ULL(0)
1100#define ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC BIT_ULL(1)
1101#define ICE_PHY_TYPE_HIGH_100G_CAUI2 BIT_ULL(2)
1102#define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC BIT_ULL(3)
1103#define ICE_PHY_TYPE_HIGH_100G_AUI2 BIT_ULL(4)
1104#define ICE_PHY_TYPE_HIGH_200G_CR4_PAM4 BIT_ULL(5)
1105#define ICE_PHY_TYPE_HIGH_200G_SR4 BIT_ULL(6)
1106#define ICE_PHY_TYPE_HIGH_200G_FR4 BIT_ULL(7)
1107#define ICE_PHY_TYPE_HIGH_200G_LR4 BIT_ULL(8)
1108#define ICE_PHY_TYPE_HIGH_200G_DR4 BIT_ULL(9)
1109#define ICE_PHY_TYPE_HIGH_200G_KR4_PAM4 BIT_ULL(10)
1110#define ICE_PHY_TYPE_HIGH_200G_AUI4_AOC_ACC BIT_ULL(11)
1111#define ICE_PHY_TYPE_HIGH_200G_AUI4 BIT_ULL(12)
1112#define ICE_PHY_TYPE_HIGH_MAX_INDEX 12
1113
1114struct ice_aqc_get_phy_caps_data {
1115 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
1116 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
1117 u8 caps;
1118#define ICE_AQC_PHY_EN_TX_LINK_PAUSE BIT(0)
1119#define ICE_AQC_PHY_EN_RX_LINK_PAUSE BIT(1)
1120#define ICE_AQC_PHY_LOW_POWER_MODE BIT(2)
1121#define ICE_AQC_PHY_EN_LINK BIT(3)
1122#define ICE_AQC_PHY_AN_MODE BIT(4)
1123#define ICE_AQC_GET_PHY_EN_MOD_QUAL BIT(5)
1124#define ICE_AQC_PHY_EN_AUTO_FEC BIT(7)
1125#define ICE_AQC_PHY_CAPS_MASK ICE_M(0xff, 0)
1126 u8 low_power_ctrl_an;
1127#define ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG BIT(0)
1128#define ICE_AQC_PHY_AN_EN_CLAUSE28 BIT(1)
1129#define ICE_AQC_PHY_AN_EN_CLAUSE73 BIT(2)
1130#define ICE_AQC_PHY_AN_EN_CLAUSE37 BIT(3)
1131 __le16 eee_cap;
1132#define ICE_AQC_PHY_EEE_EN_100BASE_TX BIT(0)
1133#define ICE_AQC_PHY_EEE_EN_1000BASE_T BIT(1)
1134#define ICE_AQC_PHY_EEE_EN_10GBASE_T BIT(2)
1135#define ICE_AQC_PHY_EEE_EN_1000BASE_KX BIT(3)
1136#define ICE_AQC_PHY_EEE_EN_10GBASE_KR BIT(4)
1137#define ICE_AQC_PHY_EEE_EN_25GBASE_KR BIT(5)
1138#define ICE_AQC_PHY_EEE_EN_40GBASE_KR4 BIT(6)
1139 __le16 eeer_value;
1140 u8 phy_id_oui[4]; /* PHY/Module ID connected on the port */
1141 u8 phy_fw_ver[8];
1142 u8 link_fec_options;
1143#define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN BIT(0)
1144#define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ BIT(1)
1145#define ICE_AQC_PHY_FEC_25G_RS_528_REQ BIT(2)
1146#define ICE_AQC_PHY_FEC_25G_KR_REQ BIT(3)
1147#define ICE_AQC_PHY_FEC_25G_RS_544_REQ BIT(4)
1148#define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN BIT(6)
1149#define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN BIT(7)
1150#define ICE_AQC_PHY_FEC_MASK ICE_M(0xdf, 0)
1151 u8 module_compliance_enforcement;
1152#define ICE_AQC_MOD_ENFORCE_STRICT_MODE BIT(0)
1153 u8 extended_compliance_code;
1154#define ICE_MODULE_TYPE_TOTAL_BYTE 3
1155 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];
1156#define ICE_AQC_MOD_TYPE_BYTE0_SFP_PLUS 0xA0
1157#define ICE_AQC_MOD_TYPE_BYTE0_QSFP_PLUS 0x80
1158#define ICE_AQC_MOD_TYPE_IDENT 1
1159#define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE BIT(0)
1160#define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE BIT(1)
1161#define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_SR BIT(4)
1162#define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LR BIT(5)
1163#define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LRM BIT(6)
1164#define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_ER BIT(7)
1165#define ICE_AQC_MOD_TYPE_BYTE2_SFP_PLUS 0xA0
1166#define ICE_AQC_MOD_TYPE_BYTE2_QSFP_PLUS 0x86
1167 u8 qualified_module_count;
1168 u8 rsvd2[7]; /* Bytes 47:41 reserved */
1169#define ICE_AQC_QUAL_MOD_COUNT_MAX 16
1170 struct {
1171 u8 v_oui[3];
1172 u8 rsvd3;
1173 u8 v_part[16];
1174 __le32 v_rev;
1175 __le64 rsvd4;
1176 } qual_modules[ICE_AQC_QUAL_MOD_COUNT_MAX];
1177};
1178
1179/* Set PHY capabilities (direct 0x0601)
1180 * NOTE: This command must be followed by setup link and restart auto-neg
1181 */
1182struct ice_aqc_set_phy_cfg {
1183 u8 lport_num;
1184 u8 reserved[7];
1185 __le32 addr_high;
1186 __le32 addr_low;
1187};
1188
1189/* Set PHY config command data structure */
1190struct ice_aqc_set_phy_cfg_data {
1191 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
1192 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
1193 u8 caps;
1194#define ICE_AQ_PHY_ENA_VALID_MASK ICE_M(0xef, 0)
1195#define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY BIT(0)
1196#define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY BIT(1)
1197#define ICE_AQ_PHY_ENA_LOW_POWER BIT(2)
1198#define ICE_AQ_PHY_ENA_LINK BIT(3)
1199#define ICE_AQ_PHY_ENA_AUTO_LINK_UPDT BIT(5)
1200#define ICE_AQ_PHY_ENA_LESM BIT(6)
1201#define ICE_AQ_PHY_ENA_AUTO_FEC BIT(7)
1202 u8 low_power_ctrl_an;
1203 __le16 eee_cap; /* Value from ice_aqc_get_phy_caps */
1204 __le16 eeer_value;
1205 u8 link_fec_opt; /* Use defines from ice_aqc_get_phy_caps */
1206 u8 module_compliance_enforcement;
1207};
1208
1209/* Set MAC Config command data structure (direct 0x0603) */
1210struct ice_aqc_set_mac_cfg {
1211 __le16 max_frame_size;
1212 u8 params;
1213#define ICE_AQ_SET_MAC_PACE_S 3
1214#define ICE_AQ_SET_MAC_PACE_M (0xF << ICE_AQ_SET_MAC_PACE_S)
1215#define ICE_AQ_SET_MAC_PACE_TYPE_M BIT(7)
1216#define ICE_AQ_SET_MAC_PACE_TYPE_RATE 0
1217#define ICE_AQ_SET_MAC_PACE_TYPE_FIXED ICE_AQ_SET_MAC_PACE_TYPE_M
1218 u8 tx_tmr_priority;
1219 __le16 tx_tmr_value;
1220 __le16 fc_refresh_threshold;
1221 u8 drop_opts;
1222#define ICE_AQ_SET_MAC_AUTO_DROP_MASK BIT(0)
1223#define ICE_AQ_SET_MAC_AUTO_DROP_NONE 0
1224#define ICE_AQ_SET_MAC_AUTO_DROP_BLOCKING_PKTS BIT(0)
1225 u8 reserved[7];
1226};
1227
1228/* Restart AN command data structure (direct 0x0605)
1229 * Also used for response, with only the lport_num field present.
1230 */
1231struct ice_aqc_restart_an {
1232 u8 lport_num;
1233 u8 reserved;
1234 u8 cmd_flags;
1235#define ICE_AQC_RESTART_AN_LINK_RESTART BIT(1)
1236#define ICE_AQC_RESTART_AN_LINK_ENABLE BIT(2)
1237 u8 reserved2[13];
1238};
1239
1240/* Get link status (indirect 0x0607), also used for Link Status Event */
1241struct ice_aqc_get_link_status {
1242 u8 lport_num;
1243 u8 reserved;
1244 __le16 cmd_flags;
1245#define ICE_AQ_LSE_M 0x3
1246#define ICE_AQ_LSE_NOP 0x0
1247#define ICE_AQ_LSE_DIS 0x2
1248#define ICE_AQ_LSE_ENA 0x3
1249 /* only response uses this flag */
1250#define ICE_AQ_LSE_IS_ENABLED 0x1
1251 __le32 reserved2;
1252 __le32 addr_high;
1253 __le32 addr_low;
1254};
1255
1256/* Get link status response data structure, also used for Link Status Event */
1257struct ice_aqc_get_link_status_data {
1258 u8 topo_media_conflict;
1259#define ICE_AQ_LINK_TOPO_CONFLICT BIT(0)
1260#define ICE_AQ_LINK_MEDIA_CONFLICT BIT(1)
1261#define ICE_AQ_LINK_TOPO_CORRUPT BIT(2)
1262#define ICE_AQ_LINK_TOPO_UNREACH_PRT BIT(4)
1263#define ICE_AQ_LINK_TOPO_UNDRUTIL_PRT BIT(5)
1264#define ICE_AQ_LINK_TOPO_UNDRUTIL_MEDIA BIT(6)
1265#define ICE_AQ_LINK_TOPO_UNSUPP_MEDIA BIT(7)
1266 u8 link_cfg_err;
1267#define ICE_AQ_LINK_MODULE_POWER_UNSUPPORTED BIT(5)
1268#define ICE_AQ_LINK_EXTERNAL_PHY_LOAD_FAILURE BIT(6)
1269#define ICE_AQ_LINK_INVAL_MAX_POWER_LIMIT BIT(7)
1270 u8 link_info;
1271#define ICE_AQ_LINK_UP BIT(0) /* Link Status */
1272#define ICE_AQ_LINK_FAULT BIT(1)
1273#define ICE_AQ_LINK_FAULT_TX BIT(2)
1274#define ICE_AQ_LINK_FAULT_RX BIT(3)
1275#define ICE_AQ_LINK_FAULT_REMOTE BIT(4)
1276#define ICE_AQ_LINK_UP_PORT BIT(5) /* External Port Link Status */
1277#define ICE_AQ_MEDIA_AVAILABLE BIT(6)
1278#define ICE_AQ_SIGNAL_DETECT BIT(7)
1279 u8 an_info;
1280#define ICE_AQ_AN_COMPLETED BIT(0)
1281#define ICE_AQ_LP_AN_ABILITY BIT(1)
1282#define ICE_AQ_PD_FAULT BIT(2) /* Parallel Detection Fault */
1283#define ICE_AQ_FEC_EN BIT(3)
1284#define ICE_AQ_PHY_LOW_POWER BIT(4) /* Low Power State */
1285#define ICE_AQ_LINK_PAUSE_TX BIT(5)
1286#define ICE_AQ_LINK_PAUSE_RX BIT(6)
1287#define ICE_AQ_QUALIFIED_MODULE BIT(7)
1288 u8 ext_info;
1289#define ICE_AQ_LINK_PHY_TEMP_ALARM BIT(0)
1290#define ICE_AQ_LINK_EXCESSIVE_ERRORS BIT(1) /* Excessive Link Errors */
1291 /* Port Tx Suspended */
1292#define ICE_AQ_LINK_TX_S 2
1293#define ICE_AQ_LINK_TX_M (0x03 << ICE_AQ_LINK_TX_S)
1294#define ICE_AQ_LINK_TX_ACTIVE 0
1295#define ICE_AQ_LINK_TX_DRAINED 1
1296#define ICE_AQ_LINK_TX_FLUSHED 3
1297 u8 reserved2;
1298 __le16 max_frame_size;
1299 u8 cfg;
1300#define ICE_AQ_LINK_25G_KR_FEC_EN BIT(0)
1301#define ICE_AQ_LINK_25G_RS_528_FEC_EN BIT(1)
1302#define ICE_AQ_LINK_25G_RS_544_FEC_EN BIT(2)
1303#define ICE_AQ_FEC_MASK ICE_M(0x7, 0)
1304 /* Pacing Config */
1305#define ICE_AQ_CFG_PACING_S 3
1306#define ICE_AQ_CFG_PACING_M (0xF << ICE_AQ_CFG_PACING_S)
1307#define ICE_AQ_CFG_PACING_TYPE_M BIT(7)
1308#define ICE_AQ_CFG_PACING_TYPE_AVG 0
1309#define ICE_AQ_CFG_PACING_TYPE_FIXED ICE_AQ_CFG_PACING_TYPE_M
1310 /* External Device Power Ability */
1311 u8 power_desc;
1312#define ICE_AQ_PWR_CLASS_M 0x3F
1313#define ICE_AQ_LINK_PWR_BASET_LOW_HIGH 0
1314#define ICE_AQ_LINK_PWR_BASET_HIGH 1
1315#define ICE_AQ_LINK_PWR_QSFP_CLASS_1 0
1316#define ICE_AQ_LINK_PWR_QSFP_CLASS_2 1
1317#define ICE_AQ_LINK_PWR_QSFP_CLASS_3 2
1318#define ICE_AQ_LINK_PWR_QSFP_CLASS_4 3
1319 __le16 link_speed;
1320#define ICE_AQ_LINK_SPEED_M 0x7FF
1321#define ICE_AQ_LINK_SPEED_10MB BIT(0)
1322#define ICE_AQ_LINK_SPEED_100MB BIT(1)
1323#define ICE_AQ_LINK_SPEED_1000MB BIT(2)
1324#define ICE_AQ_LINK_SPEED_2500MB BIT(3)
1325#define ICE_AQ_LINK_SPEED_5GB BIT(4)
1326#define ICE_AQ_LINK_SPEED_10GB BIT(5)
1327#define ICE_AQ_LINK_SPEED_20GB BIT(6)
1328#define ICE_AQ_LINK_SPEED_25GB BIT(7)
1329#define ICE_AQ_LINK_SPEED_40GB BIT(8)
1330#define ICE_AQ_LINK_SPEED_50GB BIT(9)
1331#define ICE_AQ_LINK_SPEED_100GB BIT(10)
1332#define ICE_AQ_LINK_SPEED_200GB BIT(11)
1333#define ICE_AQ_LINK_SPEED_UNKNOWN BIT(15)
1334 /* Aligns next field to 8-byte boundary */
1335 __le16 reserved3;
1336 u8 ext_fec_status;
1337 /* RS 272 FEC enabled */
1338#define ICE_AQ_LINK_RS_272_FEC_EN BIT(0)
1339 u8 reserved4;
1340 /* Use values from ICE_PHY_TYPE_LOW_* */
1341 __le64 phy_type_low;
1342 /* Use values from ICE_PHY_TYPE_HIGH_* */
1343 __le64 phy_type_high;
1344#define ICE_AQC_LS_DATA_SIZE_V1 \
1345 offsetofend(struct ice_aqc_get_link_status_data, phy_type_high)
1346 /* Get link status v2 link partner data */
1347 __le64 lp_phy_type_low;
1348 __le64 lp_phy_type_high;
1349 u8 lp_fec_adv;
1350#define ICE_AQ_LINK_LP_10G_KR_FEC_CAP BIT(0)
1351#define ICE_AQ_LINK_LP_25G_KR_FEC_CAP BIT(1)
1352#define ICE_AQ_LINK_LP_RS_528_FEC_CAP BIT(2)
1353#define ICE_AQ_LINK_LP_50G_KR_272_FEC_CAP BIT(3)
1354#define ICE_AQ_LINK_LP_100G_KR_272_FEC_CAP BIT(4)
1355#define ICE_AQ_LINK_LP_200G_KR_272_FEC_CAP BIT(5)
1356 u8 lp_fec_req;
1357#define ICE_AQ_LINK_LP_10G_KR_FEC_REQ BIT(0)
1358#define ICE_AQ_LINK_LP_25G_KR_FEC_REQ BIT(1)
1359#define ICE_AQ_LINK_LP_RS_528_FEC_REQ BIT(2)
1360#define ICE_AQ_LINK_LP_KR_272_FEC_REQ BIT(3)
1361 u8 lp_flowcontrol;
1362#define ICE_AQ_LINK_LP_PAUSE_ADV BIT(0)
1363#define ICE_AQ_LINK_LP_ASM_DIR_ADV BIT(1)
1364 u8 reserved5[5];
1365#define ICE_AQC_LS_DATA_SIZE_V2 \
1366 offsetofend(struct ice_aqc_get_link_status_data, reserved5)
1367} __packed;
1368
1369/* Set event mask command (direct 0x0613) */
1370struct ice_aqc_set_event_mask {
1371 u8 lport_num;
1372 u8 reserved[7];
1373 __le16 event_mask;
1374#define ICE_AQ_LINK_EVENT_UPDOWN BIT(1)
1375#define ICE_AQ_LINK_EVENT_MEDIA_NA BIT(2)
1376#define ICE_AQ_LINK_EVENT_LINK_FAULT BIT(3)
1377#define ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM BIT(4)
1378#define ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS BIT(5)
1379#define ICE_AQ_LINK_EVENT_SIGNAL_DETECT BIT(6)
1380#define ICE_AQ_LINK_EVENT_AN_COMPLETED BIT(7)
1381#define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL BIT(8)
1382#define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED BIT(9)
1383#define ICE_AQ_LINK_EVENT_PHY_FW_LOAD_FAIL BIT(12)
1384 u8 reserved1[6];
1385};
1386
1387/* Set MAC Loopback command (direct 0x0620) */
1388struct ice_aqc_set_mac_lb {
1389 u8 lb_mode;
1390#define ICE_AQ_MAC_LB_EN BIT(0)
1391#define ICE_AQ_MAC_LB_OSC_CLK BIT(1)
1392 u8 reserved[15];
1393};
1394
1395/* Set PHY recovered clock output (direct 0x0630) */
1396struct ice_aqc_set_phy_rec_clk_out {
1397 u8 phy_output;
1398 u8 port_num;
1399#define ICE_AQC_SET_PHY_REC_CLK_OUT_CURR_PORT 0xFF
1400 u8 flags;
1401#define ICE_AQC_SET_PHY_REC_CLK_OUT_OUT_EN BIT(0)
1402 u8 rsvd;
1403 __le32 freq;
1404 u8 rsvd2[6];
1405 __le16 node_handle;
1406};
1407
1408/* Get PHY recovered clock output (direct 0x0631) */
1409struct ice_aqc_get_phy_rec_clk_out {
1410 u8 phy_output;
1411 u8 port_num;
1412#define ICE_AQC_GET_PHY_REC_CLK_OUT_CURR_PORT 0xFF
1413 u8 flags;
1414#define ICE_AQC_GET_PHY_REC_CLK_OUT_OUT_EN BIT(0)
1415 u8 rsvd[11];
1416 __le16 node_handle;
1417};
1418
1419/* Get sensor reading (direct 0x0632) */
1420struct ice_aqc_get_sensor_reading {
1421 u8 sensor;
1422 u8 format;
1423 u8 reserved[6];
1424 __le32 addr_high;
1425 __le32 addr_low;
1426};
1427
1428/* Get sensor reading response (direct 0x0632) */
1429struct ice_aqc_get_sensor_reading_resp {
1430 union {
1431 u8 raw[8];
1432 /* Output data for sensor 0x00, format 0x00 */
1433 struct _packed {
1434 s8 temp;
1435 u8 temp_warning_threshold;
1436 u8 temp_critical_threshold;
1437 u8 temp_fatal_threshold;
1438 u8 reserved[4];
1439 } s0f0;
1440 } data;
1441};
1442
1443struct ice_aqc_link_topo_params {
1444 u8 lport_num;
1445 u8 lport_num_valid;
1446#define ICE_AQC_LINK_TOPO_PORT_NUM_VALID BIT(0)
1447 u8 node_type_ctx;
1448#define ICE_AQC_LINK_TOPO_NODE_TYPE_S 0
1449#define ICE_AQC_LINK_TOPO_NODE_TYPE_M (0xF << ICE_AQC_LINK_TOPO_NODE_TYPE_S)
1450#define ICE_AQC_LINK_TOPO_NODE_TYPE_PHY 0
1451#define ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL 1
1452#define ICE_AQC_LINK_TOPO_NODE_TYPE_MUX_CTRL 2
1453#define ICE_AQC_LINK_TOPO_NODE_TYPE_LED_CTRL 3
1454#define ICE_AQC_LINK_TOPO_NODE_TYPE_LED 4
1455#define ICE_AQC_LINK_TOPO_NODE_TYPE_THERMAL 5
1456#define ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE 6
1457#define ICE_AQC_LINK_TOPO_NODE_TYPE_MEZZ 7
1458#define ICE_AQC_LINK_TOPO_NODE_TYPE_ID_EEPROM 8
1459#define ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_CTRL 9
1460#define ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_MUX 10
1461#define ICE_AQC_LINK_TOPO_NODE_TYPE_GPS 11
1462#define ICE_AQC_LINK_TOPO_NODE_CTX_S 4
1463#define ICE_AQC_LINK_TOPO_NODE_CTX_M \
1464 (0xF << ICE_AQC_LINK_TOPO_NODE_CTX_S)
1465#define ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL 0
1466#define ICE_AQC_LINK_TOPO_NODE_CTX_BOARD 1
1467#define ICE_AQC_LINK_TOPO_NODE_CTX_PORT 2
1468#define ICE_AQC_LINK_TOPO_NODE_CTX_NODE 3
1469#define ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED 4
1470#define ICE_AQC_LINK_TOPO_NODE_CTX_OVERRIDE 5
1471 u8 index;
1472};
1473
1474struct ice_aqc_link_topo_addr {
1475 struct ice_aqc_link_topo_params topo_params;
1476 __le16 handle;
1477#define ICE_AQC_LINK_TOPO_HANDLE_S 0
1478#define ICE_AQC_LINK_TOPO_HANDLE_M (0x3FF << ICE_AQC_LINK_TOPO_HANDLE_S)
1479/* Used to decode the handle field */
1480#define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_M BIT(9)
1481#define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_LOM BIT(9)
1482#define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_MEZZ 0
1483#define ICE_AQC_LINK_TOPO_HANDLE_NODE_S 0
1484/* In case of a Mezzanine type */
1485#define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_NODE_M \
1486 (0x3F << ICE_AQC_LINK_TOPO_HANDLE_NODE_S)
1487#define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S 6
1488#define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_M (0x7 << ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S)
1489/* In case of a LOM type */
1490#define ICE_AQC_LINK_TOPO_HANDLE_LOM_NODE_M \
1491 (0x1FF << ICE_AQC_LINK_TOPO_HANDLE_NODE_S)
1492};
1493
1494/* Get Link Topology Handle (direct, 0x06E0) */
1495struct ice_aqc_get_link_topo {
1496 struct ice_aqc_link_topo_addr addr;
1497 u8 node_part_num;
1498#define ICE_AQC_GET_LINK_TOPO_NODE_NR_PCA9575 0x21
1499#define ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032 0x24
1500#define ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384 0x25
1501#define ICE_AQC_GET_LINK_TOPO_NODE_NR_E822_PHY 0x30
1502#define ICE_AQC_GET_LINK_TOPO_NODE_NR_C827 0x31
1503#define ICE_AQC_GET_LINK_TOPO_NODE_NR_GEN_CLK_MUX 0x47
1504#define ICE_AQC_GET_LINK_TOPO_NODE_NR_GEN_GPS 0x48
1505 u8 rsvd[9];
1506};
1507
1508/* Read/Write I2C (direct, 0x06E2/0x06E3) */
1509struct ice_aqc_i2c {
1510 struct ice_aqc_link_topo_addr topo_addr;
1511 __le16 i2c_addr;
1512 u8 i2c_params;
1513#define ICE_AQC_I2C_DATA_SIZE_M GENMASK(3, 0)
1514#define ICE_AQC_I2C_USE_REPEATED_START BIT(7)
1515
1516 u8 rsvd;
1517 __le16 i2c_bus_addr;
1518 u8 i2c_data[4]; /* Used only by write command, reserved in read. */
1519};
1520
1521/* Read I2C Response (direct, 0x06E2) */
1522struct ice_aqc_read_i2c_resp {
1523 u8 i2c_data[16];
1524};
1525
1526/* Set Port Identification LED (direct, 0x06E9) */
1527struct ice_aqc_set_port_id_led {
1528 u8 lport_num;
1529 u8 lport_num_valid;
1530 u8 ident_mode;
1531#define ICE_AQC_PORT_IDENT_LED_BLINK BIT(0)
1532#define ICE_AQC_PORT_IDENT_LED_ORIG 0
1533 u8 rsvd[13];
1534};
1535
1536/* Get Port Options (indirect, 0x06EA) */
1537struct ice_aqc_get_port_options {
1538 u8 lport_num;
1539 u8 lport_num_valid;
1540 u8 port_options_count;
1541#define ICE_AQC_PORT_OPT_COUNT_M GENMASK(3, 0)
1542#define ICE_AQC_PORT_OPT_MAX 16
1543
1544 u8 innermost_phy_index;
1545 u8 port_options;
1546#define ICE_AQC_PORT_OPT_ACTIVE_M GENMASK(3, 0)
1547#define ICE_AQC_PORT_OPT_VALID BIT(7)
1548
1549 u8 pending_port_option_status;
1550#define ICE_AQC_PENDING_PORT_OPT_IDX_M GENMASK(3, 0)
1551#define ICE_AQC_PENDING_PORT_OPT_VALID BIT(7)
1552
1553 u8 rsvd[2];
1554 __le32 addr_high;
1555 __le32 addr_low;
1556};
1557
1558struct ice_aqc_get_port_options_elem {
1559 u8 pmd;
1560#define ICE_AQC_PORT_OPT_PMD_COUNT_M GENMASK(3, 0)
1561
1562 u8 max_lane_speed;
1563#define ICE_AQC_PORT_OPT_MAX_LANE_M GENMASK(3, 0)
1564#define ICE_AQC_PORT_OPT_MAX_LANE_100M 0
1565#define ICE_AQC_PORT_OPT_MAX_LANE_1G 1
1566#define ICE_AQC_PORT_OPT_MAX_LANE_2500M 2
1567#define ICE_AQC_PORT_OPT_MAX_LANE_5G 3
1568#define ICE_AQC_PORT_OPT_MAX_LANE_10G 4
1569#define ICE_AQC_PORT_OPT_MAX_LANE_25G 5
1570#define ICE_AQC_PORT_OPT_MAX_LANE_50G 6
1571#define ICE_AQC_PORT_OPT_MAX_LANE_100G 7
1572
1573 u8 global_scid[2];
1574 u8 phy_scid[2];
1575 u8 pf2port_cid[2];
1576};
1577
1578/* Set Port Option (direct, 0x06EB) */
1579struct ice_aqc_set_port_option {
1580 u8 lport_num;
1581 u8 lport_num_valid;
1582 u8 selected_port_option;
1583 u8 rsvd[13];
1584};
1585
1586/* Set/Get GPIO (direct, 0x06EC/0x06ED) */
1587struct ice_aqc_gpio {
1588 __le16 gpio_ctrl_handle;
1589#define ICE_AQC_GPIO_HANDLE_S 0
1590#define ICE_AQC_GPIO_HANDLE_M (0x3FF << ICE_AQC_GPIO_HANDLE_S)
1591 u8 gpio_num;
1592 u8 gpio_val;
1593 u8 rsvd[12];
1594};
1595
1596/* Read/Write SFF EEPROM command (indirect 0x06EE) */
1597struct ice_aqc_sff_eeprom {
1598 u8 lport_num;
1599 u8 lport_num_valid;
1600#define ICE_AQC_SFF_PORT_NUM_VALID BIT(0)
1601 __le16 i2c_bus_addr;
1602#define ICE_AQC_SFF_I2CBUS_7BIT_M 0x7F
1603#define ICE_AQC_SFF_I2CBUS_10BIT_M 0x3FF
1604#define ICE_AQC_SFF_I2CBUS_TYPE_M BIT(10)
1605#define ICE_AQC_SFF_I2CBUS_TYPE_7BIT 0
1606#define ICE_AQC_SFF_I2CBUS_TYPE_10BIT ICE_AQC_SFF_I2CBUS_TYPE_M
1607#define ICE_AQC_SFF_SET_EEPROM_PAGE_S 11
1608#define ICE_AQC_SFF_SET_EEPROM_PAGE_M (0x3 << ICE_AQC_SFF_SET_EEPROM_PAGE_S)
1609#define ICE_AQC_SFF_NO_PAGE_CHANGE 0
1610#define ICE_AQC_SFF_SET_23_ON_MISMATCH 1
1611#define ICE_AQC_SFF_SET_22_ON_MISMATCH 2
1612#define ICE_AQC_SFF_IS_WRITE BIT(15)
1613 __le16 i2c_mem_addr;
1614 __le16 eeprom_page;
1615#define ICE_AQC_SFF_EEPROM_BANK_S 0
1616#define ICE_AQC_SFF_EEPROM_BANK_M (0xFF << ICE_AQC_SFF_EEPROM_BANK_S)
1617#define ICE_AQC_SFF_EEPROM_PAGE_S 8
1618#define ICE_AQC_SFF_EEPROM_PAGE_M (0xFF << ICE_AQC_SFF_EEPROM_PAGE_S)
1619 __le32 addr_high;
1620 __le32 addr_low;
1621};
1622
1623/* NVM Read command (indirect 0x0701)
1624 * NVM Erase commands (direct 0x0702)
1625 * NVM Update commands (indirect 0x0703)
1626 */
1627struct ice_aqc_nvm {
1628#define ICE_AQC_NVM_MAX_OFFSET 0xFFFFFF
1629 __le16 offset_low;
1630 u8 offset_high;
1631 u8 cmd_flags;
1632#define ICE_AQC_NVM_LAST_CMD BIT(0)
1633#define ICE_AQC_NVM_PCIR_REQ BIT(0) /* Used by NVM Update reply */
1634#define ICE_AQC_NVM_PRESERVATION_S 1
1635#define ICE_AQC_NVM_PRESERVATION_M (3 << ICE_AQC_NVM_PRESERVATION_S)
1636#define ICE_AQC_NVM_NO_PRESERVATION (0 << ICE_AQC_NVM_PRESERVATION_S)
1637#define ICE_AQC_NVM_PRESERVE_ALL BIT(1)
1638#define ICE_AQC_NVM_FACTORY_DEFAULT (2 << ICE_AQC_NVM_PRESERVATION_S)
1639#define ICE_AQC_NVM_PRESERVE_SELECTED (3 << ICE_AQC_NVM_PRESERVATION_S)
1640#define ICE_AQC_NVM_ACTIV_SEL_NVM BIT(3) /* Write Activate/SR Dump only */
1641#define ICE_AQC_NVM_ACTIV_SEL_OROM BIT(4)
1642#define ICE_AQC_NVM_ACTIV_SEL_NETLIST BIT(5)
1643#define ICE_AQC_NVM_SPECIAL_UPDATE BIT(6)
1644#define ICE_AQC_NVM_REVERT_LAST_ACTIV BIT(6) /* Write Activate only */
1645#define ICE_AQC_NVM_ACTIV_SEL_MASK ICE_M(0x7, 3)
1646#define ICE_AQC_NVM_FLASH_ONLY BIT(7)
1647#define ICE_AQC_NVM_RESET_LVL_M ICE_M(0x3, 0) /* Write reply only */
1648#define ICE_AQC_NVM_POR_FLAG 0
1649#define ICE_AQC_NVM_PERST_FLAG 1
1650#define ICE_AQC_NVM_EMPR_FLAG 2
1651#define ICE_AQC_NVM_EMPR_ENA BIT(0) /* Write Activate reply only */
1652 /* For Write Activate, several flags are sent as part of a separate
1653 * flags2 field using a separate byte. For simplicity of the software
1654 * interface, we pass the flags as a 16 bit value so these flags are
1655 * all offset by 8 bits
1656 */
1657#define ICE_AQC_NVM_ACTIV_REQ_EMPR BIT(8) /* NVM Write Activate only */
1658 __le16 module_typeid;
1659 __le16 length;
1660#define ICE_AQC_NVM_ERASE_LEN 0xFFFF
1661 __le32 addr_high;
1662 __le32 addr_low;
1663};
1664
1665#define ICE_AQC_NVM_START_POINT 0
1666
1667/* NVM Checksum Command (direct, 0x0706) */
1668struct ice_aqc_nvm_checksum {
1669 u8 flags;
1670#define ICE_AQC_NVM_CHECKSUM_VERIFY BIT(0)
1671#define ICE_AQC_NVM_CHECKSUM_RECALC BIT(1)
1672 u8 rsvd;
1673 __le16 checksum; /* Used only by response */
1674#define ICE_AQC_NVM_CHECKSUM_CORRECT 0xBABA
1675 u8 rsvd2[12];
1676};
1677
1678/* Used for NVM Set Package Data command - 0x070A */
1679struct ice_aqc_nvm_pkg_data {
1680 u8 reserved[3];
1681 u8 cmd_flags;
1682#define ICE_AQC_NVM_PKG_DELETE BIT(0) /* used for command call */
1683#define ICE_AQC_NVM_PKG_SKIPPED BIT(0) /* used for command response */
1684
1685 u32 reserved1;
1686 __le32 addr_high;
1687 __le32 addr_low;
1688};
1689
1690/* Used for Pass Component Table command - 0x070B */
1691struct ice_aqc_nvm_pass_comp_tbl {
1692 u8 component_response; /* Response only */
1693#define ICE_AQ_NVM_PASS_COMP_CAN_BE_UPDATED 0x0
1694#define ICE_AQ_NVM_PASS_COMP_CAN_MAY_BE_UPDATEABLE 0x1
1695#define ICE_AQ_NVM_PASS_COMP_CAN_NOT_BE_UPDATED 0x2
1696 u8 component_response_code; /* Response only */
1697#define ICE_AQ_NVM_PASS_COMP_CAN_BE_UPDATED_CODE 0x0
1698#define ICE_AQ_NVM_PASS_COMP_STAMP_IDENTICAL_CODE 0x1
1699#define ICE_AQ_NVM_PASS_COMP_STAMP_LOWER 0x2
1700#define ICE_AQ_NVM_PASS_COMP_INVALID_STAMP_CODE 0x3
1701#define ICE_AQ_NVM_PASS_COMP_CONFLICT_CODE 0x4
1702#define ICE_AQ_NVM_PASS_COMP_PRE_REQ_NOT_MET_CODE 0x5
1703#define ICE_AQ_NVM_PASS_COMP_NOT_SUPPORTED_CODE 0x6
1704#define ICE_AQ_NVM_PASS_COMP_CANNOT_DOWNGRADE_CODE 0x7
1705#define ICE_AQ_NVM_PASS_COMP_INCOMPLETE_IMAGE_CODE 0x8
1706#define ICE_AQ_NVM_PASS_COMP_VER_STR_IDENTICAL_CODE 0xA
1707#define ICE_AQ_NVM_PASS_COMP_VER_STR_LOWER_CODE 0xB
1708 u8 reserved;
1709 u8 transfer_flag;
1710#define ICE_AQ_NVM_PASS_COMP_TBL_START 0x1
1711#define ICE_AQ_NVM_PASS_COMP_TBL_MIDDLE 0x2
1712#define ICE_AQ_NVM_PASS_COMP_TBL_END 0x4
1713#define ICE_AQ_NVM_PASS_COMP_TBL_START_AND_END 0x5
1714 __le32 reserved1;
1715 __le32 addr_high;
1716 __le32 addr_low;
1717};
1718
1719struct ice_aqc_nvm_comp_tbl {
1720 __le16 comp_class;
1721#define NVM_COMP_CLASS_ALL_FW 0x000A
1722
1723 __le16 comp_id;
1724#define NVM_COMP_ID_OROM 0x5
1725#define NVM_COMP_ID_NVM 0x6
1726#define NVM_COMP_ID_NETLIST 0x8
1727
1728 u8 comp_class_idx;
1729#define FWU_COMP_CLASS_IDX_NOT_USE 0x0
1730
1731 __le32 comp_cmp_stamp;
1732 u8 cvs_type;
1733#define NVM_CVS_TYPE_ASCII 0x1
1734
1735 u8 cvs_len;
1736 u8 cvs[]; /* Component Version String */
1737} __packed;
1738
1739/* Send to PF command (indirect 0x0801) ID is only used by PF
1740 *
1741 * Send to VF command (indirect 0x0802) ID is only used by PF
1742 *
1743 */
1744struct ice_aqc_pf_vf_msg {
1745 __le32 id;
1746 u32 reserved;
1747 __le32 addr_high;
1748 __le32 addr_low;
1749};
1750
1751/* Get LLDP MIB (indirect 0x0A00)
1752 * Note: This is also used by the LLDP MIB Change Event (0x0A01)
1753 * as the format is the same.
1754 */
1755struct ice_aqc_lldp_get_mib {
1756 u8 type;
1757#define ICE_AQ_LLDP_MIB_TYPE_S 0
1758#define ICE_AQ_LLDP_MIB_TYPE_M (0x3 << ICE_AQ_LLDP_MIB_TYPE_S)
1759#define ICE_AQ_LLDP_MIB_LOCAL 0
1760#define ICE_AQ_LLDP_MIB_REMOTE 1
1761#define ICE_AQ_LLDP_MIB_LOCAL_AND_REMOTE 2
1762#define ICE_AQ_LLDP_BRID_TYPE_S 2
1763#define ICE_AQ_LLDP_BRID_TYPE_M (0x3 << ICE_AQ_LLDP_BRID_TYPE_S)
1764#define ICE_AQ_LLDP_BRID_TYPE_NEAREST_BRID 0
1765#define ICE_AQ_LLDP_BRID_TYPE_NON_TPMR 1
1766/* Tx pause flags in the 0xA01 event use ICE_AQ_LLDP_TX_* */
1767#define ICE_AQ_LLDP_TX_S 0x4
1768#define ICE_AQ_LLDP_TX_M (0x03 << ICE_AQ_LLDP_TX_S)
1769#define ICE_AQ_LLDP_TX_ACTIVE 0
1770#define ICE_AQ_LLDP_TX_SUSPENDED 1
1771#define ICE_AQ_LLDP_TX_FLUSHED 3
1772/* DCBX mode */
1773#define ICE_AQ_LLDP_DCBX_M GENMASK(7, 6)
1774#define ICE_AQ_LLDP_DCBX_NA 0
1775#define ICE_AQ_LLDP_DCBX_CEE 1
1776#define ICE_AQ_LLDP_DCBX_IEEE 2
1777
1778 u8 state;
1779#define ICE_AQ_LLDP_MIB_CHANGE_STATE_M BIT(0)
1780#define ICE_AQ_LLDP_MIB_CHANGE_EXECUTED 0
1781#define ICE_AQ_LLDP_MIB_CHANGE_PENDING 1
1782
1783/* The following bytes are reserved for the Get LLDP MIB command (0x0A00)
1784 * and in the LLDP MIB Change Event (0x0A01). They are valid for the
1785 * Get LLDP MIB (0x0A00) response only.
1786 */
1787 __le16 local_len;
1788 __le16 remote_len;
1789 u8 reserved[2];
1790 __le32 addr_high;
1791 __le32 addr_low;
1792};
1793
1794/* Configure LLDP MIB Change Event (direct 0x0A01) */
1795/* For MIB Change Event use ice_aqc_lldp_get_mib structure above */
1796struct ice_aqc_lldp_set_mib_change {
1797 u8 command;
1798#define ICE_AQ_LLDP_MIB_UPDATE_ENABLE 0x0
1799#define ICE_AQ_LLDP_MIB_UPDATE_DIS 0x1
1800#define ICE_AQ_LLDP_MIB_PENDING_M BIT(1)
1801#define ICE_AQ_LLDP_MIB_PENDING_DISABLE 0
1802#define ICE_AQ_LLDP_MIB_PENDING_ENABLE 1
1803 u8 reserved[15];
1804};
1805
1806/* Stop LLDP (direct 0x0A05) */
1807struct ice_aqc_lldp_stop {
1808 u8 command;
1809#define ICE_AQ_LLDP_AGENT_STATE_MASK BIT(0)
1810#define ICE_AQ_LLDP_AGENT_STOP 0x0
1811#define ICE_AQ_LLDP_AGENT_SHUTDOWN ICE_AQ_LLDP_AGENT_STATE_MASK
1812#define ICE_AQ_LLDP_AGENT_PERSIST_DIS BIT(1)
1813 u8 reserved[15];
1814};
1815
1816/* Start LLDP (direct 0x0A06) */
1817struct ice_aqc_lldp_start {
1818 u8 command;
1819#define ICE_AQ_LLDP_AGENT_START BIT(0)
1820#define ICE_AQ_LLDP_AGENT_PERSIST_ENA BIT(1)
1821 u8 reserved[15];
1822};
1823
1824/* Get CEE DCBX Oper Config (0x0A07)
1825 * The command uses the generic descriptor struct and
1826 * returns the struct below as an indirect response.
1827 */
1828struct ice_aqc_get_cee_dcb_cfg_resp {
1829 u8 oper_num_tc;
1830 u8 oper_prio_tc[4];
1831 u8 oper_tc_bw[8];
1832 u8 oper_pfc_en;
1833 __le16 oper_app_prio;
1834#define ICE_AQC_CEE_APP_FCOE_S 0
1835#define ICE_AQC_CEE_APP_FCOE_M (0x7 << ICE_AQC_CEE_APP_FCOE_S)
1836#define ICE_AQC_CEE_APP_ISCSI_S 3
1837#define ICE_AQC_CEE_APP_ISCSI_M (0x7 << ICE_AQC_CEE_APP_ISCSI_S)
1838#define ICE_AQC_CEE_APP_FIP_S 8
1839#define ICE_AQC_CEE_APP_FIP_M (0x7 << ICE_AQC_CEE_APP_FIP_S)
1840 __le32 tlv_status;
1841#define ICE_AQC_CEE_PG_STATUS_S 0
1842#define ICE_AQC_CEE_PG_STATUS_M (0x7 << ICE_AQC_CEE_PG_STATUS_S)
1843#define ICE_AQC_CEE_PFC_STATUS_S 3
1844#define ICE_AQC_CEE_PFC_STATUS_M (0x7 << ICE_AQC_CEE_PFC_STATUS_S)
1845#define ICE_AQC_CEE_FCOE_STATUS_S 8
1846#define ICE_AQC_CEE_FCOE_STATUS_M (0x7 << ICE_AQC_CEE_FCOE_STATUS_S)
1847#define ICE_AQC_CEE_ISCSI_STATUS_S 11
1848#define ICE_AQC_CEE_ISCSI_STATUS_M (0x7 << ICE_AQC_CEE_ISCSI_STATUS_S)
1849#define ICE_AQC_CEE_FIP_STATUS_S 16
1850#define ICE_AQC_CEE_FIP_STATUS_M (0x7 << ICE_AQC_CEE_FIP_STATUS_S)
1851 u8 reserved[12];
1852};
1853
1854/* Set Local LLDP MIB (indirect 0x0A08)
1855 * Used to replace the local MIB of a given LLDP agent. e.g. DCBX
1856 */
1857struct ice_aqc_lldp_set_local_mib {
1858 u8 type;
1859#define SET_LOCAL_MIB_TYPE_DCBX_M BIT(0)
1860#define SET_LOCAL_MIB_TYPE_LOCAL_MIB 0
1861#define SET_LOCAL_MIB_TYPE_CEE_M BIT(1)
1862#define SET_LOCAL_MIB_TYPE_CEE_WILLING 0
1863#define SET_LOCAL_MIB_TYPE_CEE_NON_WILLING SET_LOCAL_MIB_TYPE_CEE_M
1864 u8 reserved0;
1865 __le16 length;
1866 u8 reserved1[4];
1867 __le32 addr_high;
1868 __le32 addr_low;
1869};
1870
1871/* Stop/Start LLDP Agent (direct 0x0A09)
1872 * Used for stopping/starting specific LLDP agent. e.g. DCBX.
1873 * The same structure is used for the response, with the command field
1874 * being used as the status field.
1875 */
1876struct ice_aqc_lldp_stop_start_specific_agent {
1877 u8 command;
1878#define ICE_AQC_START_STOP_AGENT_M BIT(0)
1879#define ICE_AQC_START_STOP_AGENT_STOP_DCBX 0
1880#define ICE_AQC_START_STOP_AGENT_START_DCBX ICE_AQC_START_STOP_AGENT_M
1881 u8 reserved[15];
1882};
1883
1884/* LLDP Filter Control (direct 0x0A0A) */
1885struct ice_aqc_lldp_filter_ctrl {
1886 u8 cmd_flags;
1887#define ICE_AQC_LLDP_FILTER_ACTION_ADD 0x0
1888#define ICE_AQC_LLDP_FILTER_ACTION_DELETE 0x1
1889 u8 reserved1;
1890 __le16 vsi_num;
1891 u8 reserved2[12];
1892};
1893
1894#define ICE_AQC_RSS_VSI_VALID BIT(15)
1895
1896/* Get/Set RSS key (indirect 0x0B04/0x0B02) */
1897struct ice_aqc_get_set_rss_key {
1898 __le16 vsi_id;
1899 u8 reserved[6];
1900 __le32 addr_high;
1901 __le32 addr_low;
1902};
1903
1904#define ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE 0x28
1905#define ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE 0xC
1906#define ICE_GET_SET_RSS_KEY_EXTEND_KEY_SIZE \
1907 (ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE + \
1908 ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE)
1909
1910struct ice_aqc_get_set_rss_keys {
1911 u8 standard_rss_key[ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE];
1912 u8 extended_hash_key[ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE];
1913};
1914
1915enum ice_lut_type {
1916 ICE_LUT_VSI = 0,
1917 ICE_LUT_PF = 1,
1918 ICE_LUT_GLOBAL = 2,
1919};
1920
1921enum ice_lut_size {
1922 ICE_LUT_VSI_SIZE = 64,
1923 ICE_LUT_GLOBAL_SIZE = 512,
1924 ICE_LUT_PF_SIZE = 2048,
1925};
1926
1927/* enum ice_aqc_lut_flags combines constants used to fill
1928 * &ice_aqc_get_set_rss_lut ::flags, which is an amalgamation of global LUT ID,
1929 * LUT size and LUT type, last of which does not need neither shift nor mask.
1930 */
1931enum ice_aqc_lut_flags {
1932 ICE_AQC_LUT_SIZE_SMALL = 0, /* size = 64 or 128 */
1933 ICE_AQC_LUT_SIZE_512 = BIT(2),
1934 ICE_AQC_LUT_SIZE_2K = BIT(3),
1935
1936 ICE_AQC_LUT_GLOBAL_IDX = GENMASK(7, 4),
1937};
1938
1939/* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */
1940struct ice_aqc_get_set_rss_lut {
1941 __le16 vsi_id;
1942 __le16 flags;
1943 __le32 reserved;
1944 __le32 addr_high;
1945 __le32 addr_low;
1946};
1947
1948/* Sideband Control Interface Commands */
1949/* Neighbor Device Request (indirect 0x0C00); also used for the response. */
1950struct ice_aqc_neigh_dev_req {
1951 __le16 sb_data_len;
1952 u8 reserved[6];
1953 __le32 addr_high;
1954 __le32 addr_low;
1955};
1956
1957/* Add Tx LAN Queues (indirect 0x0C30) */
1958struct ice_aqc_add_txqs {
1959 u8 num_qgrps;
1960 u8 reserved[3];
1961 __le32 reserved1;
1962 __le32 addr_high;
1963 __le32 addr_low;
1964};
1965
1966/* This is the descriptor of each queue entry for the Add Tx LAN Queues
1967 * command (0x0C30). Only used within struct ice_aqc_add_tx_qgrp.
1968 */
1969struct ice_aqc_add_txqs_perq {
1970 __le16 txq_id;
1971 u8 rsvd[2];
1972 __le32 q_teid;
1973 u8 txq_ctx[22];
1974 u8 rsvd2[2];
1975 struct ice_aqc_txsched_elem info;
1976};
1977
1978/* The format of the command buffer for Add Tx LAN Queues (0x0C30)
1979 * is an array of the following structs. Please note that the length of
1980 * each struct ice_aqc_add_tx_qgrp is variable due
1981 * to the variable number of queues in each group!
1982 */
1983struct ice_aqc_add_tx_qgrp {
1984 __le32 parent_teid;
1985 u8 num_txqs;
1986 u8 rsvd[3];
1987 struct ice_aqc_add_txqs_perq txqs[];
1988};
1989
1990/* Disable Tx LAN Queues (indirect 0x0C31) */
1991struct ice_aqc_dis_txqs {
1992 u8 cmd_type;
1993#define ICE_AQC_Q_DIS_CMD_S 0
1994#define ICE_AQC_Q_DIS_CMD_M (0x3 << ICE_AQC_Q_DIS_CMD_S)
1995#define ICE_AQC_Q_DIS_CMD_NO_FUNC_RESET (0 << ICE_AQC_Q_DIS_CMD_S)
1996#define ICE_AQC_Q_DIS_CMD_VM_RESET BIT(ICE_AQC_Q_DIS_CMD_S)
1997#define ICE_AQC_Q_DIS_CMD_VF_RESET (2 << ICE_AQC_Q_DIS_CMD_S)
1998#define ICE_AQC_Q_DIS_CMD_PF_RESET (3 << ICE_AQC_Q_DIS_CMD_S)
1999#define ICE_AQC_Q_DIS_CMD_SUBSEQ_CALL BIT(2)
2000#define ICE_AQC_Q_DIS_CMD_FLUSH_PIPE BIT(3)
2001 u8 num_entries;
2002 __le16 vmvf_and_timeout;
2003#define ICE_AQC_Q_DIS_VMVF_NUM_S 0
2004#define ICE_AQC_Q_DIS_VMVF_NUM_M (0x3FF << ICE_AQC_Q_DIS_VMVF_NUM_S)
2005#define ICE_AQC_Q_DIS_TIMEOUT_S 10
2006#define ICE_AQC_Q_DIS_TIMEOUT_M (0x3F << ICE_AQC_Q_DIS_TIMEOUT_S)
2007 __le32 blocked_cgds;
2008 __le32 addr_high;
2009 __le32 addr_low;
2010};
2011
2012/* The buffer for Disable Tx LAN Queues (indirect 0x0C31)
2013 * contains the following structures, arrayed one after the
2014 * other.
2015 * Note: Since the q_id is 16 bits wide, if the
2016 * number of queues is even, then 2 bytes of alignment MUST be
2017 * added before the start of the next group, to allow correct
2018 * alignment of the parent_teid field.
2019 */
2020struct ice_aqc_dis_txq_item {
2021 __le32 parent_teid;
2022 u8 num_qs;
2023 u8 rsvd;
2024 /* The length of the q_id array varies according to num_qs */
2025#define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S 15
2026#define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_LAN_Q \
2027 (0 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S)
2028#define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET \
2029 (1 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S)
2030 __le16 q_id[];
2031} __packed;
2032
2033/* Move/Reconfigure Tx queue (indirect 0x0C32) */
2034struct ice_aqc_cfg_txqs {
2035 u8 cmd_type;
2036#define ICE_AQC_Q_CFG_MOVE_NODE 0x1
2037#define ICE_AQC_Q_CFG_TC_CHNG 0x2
2038#define ICE_AQC_Q_CFG_MOVE_TC_CHNG 0x3
2039#define ICE_AQC_Q_CFG_SUBSEQ_CALL BIT(2)
2040#define ICE_AQC_Q_CFG_FLUSH BIT(3)
2041 u8 num_qs;
2042 u8 port_num_chng;
2043#define ICE_AQC_Q_CFG_SRC_PRT_M 0x7
2044#define ICE_AQC_Q_CFG_DST_PRT_S 3
2045#define ICE_AQC_Q_CFG_DST_PRT_M (0x7 << ICE_AQC_Q_CFG_DST_PRT_S)
2046 u8 time_out;
2047#define ICE_AQC_Q_CFG_TIMEOUT_S 2
2048#define ICE_AQC_Q_CFG_TIMEOUT_M (0x1F << ICE_AQC_Q_CFG_TIMEOUT_S)
2049 __le32 blocked_cgds;
2050 __le32 addr_high;
2051 __le32 addr_low;
2052};
2053
2054/* Per Q struct for Move/Reconfigure Tx LAN Queues (indirect 0x0C32) */
2055struct ice_aqc_cfg_txq_perq {
2056 __le16 q_handle;
2057 u8 tc;
2058 u8 rsvd;
2059 __le32 q_teid;
2060};
2061
2062/* The buffer for Move/Reconfigure Tx LAN Queues (indirect 0x0C32) */
2063struct ice_aqc_cfg_txqs_buf {
2064 __le32 src_parent_teid;
2065 __le32 dst_parent_teid;
2066 struct ice_aqc_cfg_txq_perq queue_info[];
2067};
2068
2069/* Add Tx RDMA Queue Set (indirect 0x0C33) */
2070struct ice_aqc_add_rdma_qset {
2071 u8 num_qset_grps;
2072 u8 reserved[7];
2073 __le32 addr_high;
2074 __le32 addr_low;
2075};
2076
2077/* This is the descriptor of each Qset entry for the Add Tx RDMA Queue Set
2078 * command (0x0C33). Only used within struct ice_aqc_add_rdma_qset.
2079 */
2080struct ice_aqc_add_tx_rdma_qset_entry {
2081 __le16 tx_qset_id;
2082 u8 rsvd[2];
2083 __le32 qset_teid;
2084 struct ice_aqc_txsched_elem info;
2085};
2086
2087/* The format of the command buffer for Add Tx RDMA Queue Set(0x0C33)
2088 * is an array of the following structs. Please note that the length of
2089 * each struct ice_aqc_add_rdma_qset is variable due to the variable
2090 * number of queues in each group!
2091 */
2092struct ice_aqc_add_rdma_qset_data {
2093 __le32 parent_teid;
2094 __le16 num_qsets;
2095 u8 rsvd[2];
2096 struct ice_aqc_add_tx_rdma_qset_entry rdma_qsets[];
2097};
2098
2099/* Download Package (indirect 0x0C40) */
2100/* Also used for Update Package (indirect 0x0C41 and 0x0C42) */
2101struct ice_aqc_download_pkg {
2102 u8 flags;
2103#define ICE_AQC_DOWNLOAD_PKG_LAST_BUF 0x01
2104 u8 reserved[3];
2105 __le32 reserved1;
2106 __le32 addr_high;
2107 __le32 addr_low;
2108};
2109
2110struct ice_aqc_download_pkg_resp {
2111 __le32 error_offset;
2112 __le32 error_info;
2113 __le32 addr_high;
2114 __le32 addr_low;
2115};
2116
2117/* Get Package Info List (indirect 0x0C43) */
2118struct ice_aqc_get_pkg_info_list {
2119 __le32 reserved1;
2120 __le32 reserved2;
2121 __le32 addr_high;
2122 __le32 addr_low;
2123};
2124
2125/* Version format for packages */
2126struct ice_pkg_ver {
2127 u8 major;
2128 u8 minor;
2129 u8 update;
2130 u8 draft;
2131};
2132
2133#define ICE_PKG_NAME_SIZE 32
2134#define ICE_SEG_ID_SIZE 28
2135#define ICE_SEG_NAME_SIZE 28
2136
2137struct ice_aqc_get_pkg_info {
2138 struct ice_pkg_ver ver;
2139 char name[ICE_SEG_NAME_SIZE];
2140 __le32 track_id;
2141 u8 is_in_nvm;
2142 u8 is_active;
2143 u8 is_active_at_boot;
2144 u8 is_modified;
2145};
2146
2147/* Get Package Info List response buffer format (0x0C43) */
2148struct ice_aqc_get_pkg_info_resp {
2149 __le32 count;
2150 struct ice_aqc_get_pkg_info pkg_info[];
2151};
2152
2153/* Get CGU abilities command response data structure (indirect 0x0C61) */
2154struct ice_aqc_get_cgu_abilities {
2155 u8 num_inputs;
2156 u8 num_outputs;
2157 u8 pps_dpll_idx;
2158 u8 eec_dpll_idx;
2159 __le32 max_in_freq;
2160 __le32 max_in_phase_adj;
2161 __le32 max_out_freq;
2162 __le32 max_out_phase_adj;
2163 u8 cgu_part_num;
2164 u8 rsvd[3];
2165};
2166
2167/* Set CGU input config (direct 0x0C62) */
2168struct ice_aqc_set_cgu_input_config {
2169 u8 input_idx;
2170 u8 flags1;
2171#define ICE_AQC_SET_CGU_IN_CFG_FLG1_UPDATE_FREQ BIT(6)
2172#define ICE_AQC_SET_CGU_IN_CFG_FLG1_UPDATE_DELAY BIT(7)
2173 u8 flags2;
2174#define ICE_AQC_SET_CGU_IN_CFG_FLG2_INPUT_EN BIT(5)
2175#define ICE_AQC_SET_CGU_IN_CFG_FLG2_ESYNC_EN BIT(6)
2176 u8 rsvd;
2177 __le32 freq;
2178 __le32 phase_delay;
2179 u8 rsvd2[2];
2180 __le16 node_handle;
2181};
2182
2183/* Get CGU input config response descriptor structure (direct 0x0C63) */
2184struct ice_aqc_get_cgu_input_config {
2185 u8 input_idx;
2186 u8 status;
2187#define ICE_AQC_GET_CGU_IN_CFG_STATUS_LOS BIT(0)
2188#define ICE_AQC_GET_CGU_IN_CFG_STATUS_SCM_FAIL BIT(1)
2189#define ICE_AQC_GET_CGU_IN_CFG_STATUS_CFM_FAIL BIT(2)
2190#define ICE_AQC_GET_CGU_IN_CFG_STATUS_GST_FAIL BIT(3)
2191#define ICE_AQC_GET_CGU_IN_CFG_STATUS_PFM_FAIL BIT(4)
2192#define ICE_AQC_GET_CGU_IN_CFG_STATUS_ESYNC_FAIL BIT(6)
2193#define ICE_AQC_GET_CGU_IN_CFG_STATUS_ESYNC_CAP BIT(7)
2194 u8 type;
2195#define ICE_AQC_GET_CGU_IN_CFG_TYPE_READ_ONLY BIT(0)
2196#define ICE_AQC_GET_CGU_IN_CFG_TYPE_GPS BIT(4)
2197#define ICE_AQC_GET_CGU_IN_CFG_TYPE_EXTERNAL BIT(5)
2198#define ICE_AQC_GET_CGU_IN_CFG_TYPE_PHY BIT(6)
2199 u8 flags1;
2200#define ICE_AQC_GET_CGU_IN_CFG_FLG1_PHASE_DELAY_SUPP BIT(0)
2201#define ICE_AQC_GET_CGU_IN_CFG_FLG1_1PPS_SUPP BIT(2)
2202#define ICE_AQC_GET_CGU_IN_CFG_FLG1_10MHZ_SUPP BIT(3)
2203#define ICE_AQC_GET_CGU_IN_CFG_FLG1_ANYFREQ BIT(7)
2204 __le32 freq;
2205 __le32 phase_delay;
2206 u8 flags2;
2207#define ICE_AQC_GET_CGU_IN_CFG_FLG2_INPUT_EN BIT(5)
2208#define ICE_AQC_GET_CGU_IN_CFG_FLG2_ESYNC_EN BIT(6)
2209 u8 rsvd[1];
2210 __le16 node_handle;
2211};
2212
2213/* Set CGU output config (direct 0x0C64) */
2214struct ice_aqc_set_cgu_output_config {
2215 u8 output_idx;
2216 u8 flags;
2217#define ICE_AQC_SET_CGU_OUT_CFG_OUT_EN BIT(0)
2218#define ICE_AQC_SET_CGU_OUT_CFG_ESYNC_EN BIT(1)
2219#define ICE_AQC_SET_CGU_OUT_CFG_UPDATE_FREQ BIT(2)
2220#define ICE_AQC_SET_CGU_OUT_CFG_UPDATE_PHASE BIT(3)
2221#define ICE_AQC_SET_CGU_OUT_CFG_UPDATE_SRC_SEL BIT(4)
2222 u8 src_sel;
2223#define ICE_AQC_SET_CGU_OUT_CFG_DPLL_SRC_SEL ICE_M(0x1F, 0)
2224 u8 rsvd;
2225 __le32 freq;
2226 __le32 phase_delay;
2227 u8 rsvd2[2];
2228 __le16 node_handle;
2229};
2230
2231/* Get CGU output config (direct 0x0C65) */
2232struct ice_aqc_get_cgu_output_config {
2233 u8 output_idx;
2234 u8 flags;
2235#define ICE_AQC_GET_CGU_OUT_CFG_OUT_EN BIT(0)
2236#define ICE_AQC_GET_CGU_OUT_CFG_ESYNC_EN BIT(1)
2237#define ICE_AQC_GET_CGU_OUT_CFG_ESYNC_ABILITY BIT(2)
2238 u8 src_sel;
2239#define ICE_AQC_GET_CGU_OUT_CFG_DPLL_SRC_SEL_SHIFT 0
2240#define ICE_AQC_GET_CGU_OUT_CFG_DPLL_SRC_SEL \
2241 ICE_M(0x1F, ICE_AQC_GET_CGU_OUT_CFG_DPLL_SRC_SEL_SHIFT)
2242#define ICE_AQC_GET_CGU_OUT_CFG_DPLL_MODE_SHIFT 5
2243#define ICE_AQC_GET_CGU_OUT_CFG_DPLL_MODE \
2244 ICE_M(0x7, ICE_AQC_GET_CGU_OUT_CFG_DPLL_MODE_SHIFT)
2245 u8 rsvd;
2246 __le32 freq;
2247 __le32 src_freq;
2248 u8 rsvd2[2];
2249 __le16 node_handle;
2250};
2251
2252/* Get CGU DPLL status (direct 0x0C66) */
2253struct ice_aqc_get_cgu_dpll_status {
2254 u8 dpll_num;
2255 u8 ref_state;
2256#define ICE_AQC_GET_CGU_DPLL_STATUS_REF_SW_LOS BIT(0)
2257#define ICE_AQC_GET_CGU_DPLL_STATUS_REF_SW_SCM BIT(1)
2258#define ICE_AQC_GET_CGU_DPLL_STATUS_REF_SW_CFM BIT(2)
2259#define ICE_AQC_GET_CGU_DPLL_STATUS_REF_SW_GST BIT(3)
2260#define ICE_AQC_GET_CGU_DPLL_STATUS_REF_SW_PFM BIT(4)
2261#define ICE_AQC_GET_CGU_DPLL_STATUS_FAST_LOCK_EN BIT(5)
2262#define ICE_AQC_GET_CGU_DPLL_STATUS_REF_SW_ESYNC BIT(6)
2263 u8 dpll_state;
2264#define ICE_AQC_GET_CGU_DPLL_STATUS_STATE_LOCK BIT(0)
2265#define ICE_AQC_GET_CGU_DPLL_STATUS_STATE_HO BIT(1)
2266#define ICE_AQC_GET_CGU_DPLL_STATUS_STATE_HO_READY BIT(2)
2267#define ICE_AQC_GET_CGU_DPLL_STATUS_STATE_FLHIT BIT(5)
2268#define ICE_AQC_GET_CGU_DPLL_STATUS_STATE_PSLHIT BIT(7)
2269 u8 config;
2270#define ICE_AQC_GET_CGU_DPLL_CONFIG_CLK_REF_SEL ICE_M(0x1F, 0)
2271#define ICE_AQC_GET_CGU_DPLL_CONFIG_MODE_SHIFT 5
2272#define ICE_AQC_GET_CGU_DPLL_CONFIG_MODE \
2273 ICE_M(0x7, ICE_AQC_GET_CGU_DPLL_CONFIG_MODE_SHIFT)
2274#define ICE_AQC_GET_CGU_DPLL_CONFIG_MODE_FREERUN 0
2275#define ICE_AQC_GET_CGU_DPLL_CONFIG_MODE_AUTOMATIC \
2276 ICE_M(0x3, ICE_AQC_GET_CGU_DPLL_CONFIG_MODE_SHIFT)
2277 __le32 phase_offset_h;
2278 __le32 phase_offset_l;
2279 u8 eec_mode;
2280#define ICE_AQC_GET_CGU_DPLL_STATUS_EEC_MODE_1 0xA
2281#define ICE_AQC_GET_CGU_DPLL_STATUS_EEC_MODE_2 0xB
2282#define ICE_AQC_GET_CGU_DPLL_STATUS_EEC_MODE_UNKNOWN 0xF
2283 u8 rsvd[1];
2284 __le16 node_handle;
2285};
2286
2287/* Set CGU DPLL config (direct 0x0C67) */
2288struct ice_aqc_set_cgu_dpll_config {
2289 u8 dpll_num;
2290 u8 ref_state;
2291#define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_SW_LOS BIT(0)
2292#define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_SW_SCM BIT(1)
2293#define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_SW_CFM BIT(2)
2294#define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_SW_GST BIT(3)
2295#define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_SW_PFM BIT(4)
2296#define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_FLOCK_EN BIT(5)
2297#define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_SW_ESYNC BIT(6)
2298 u8 rsvd;
2299 u8 config;
2300#define ICE_AQC_SET_CGU_DPLL_CONFIG_CLK_REF_SEL ICE_M(0x1F, 0)
2301#define ICE_AQC_SET_CGU_DPLL_CONFIG_MODE_SHIFT 5
2302#define ICE_AQC_SET_CGU_DPLL_CONFIG_MODE \
2303 ICE_M(0x7, ICE_AQC_SET_CGU_DPLL_CONFIG_MODE_SHIFT)
2304#define ICE_AQC_SET_CGU_DPLL_CONFIG_MODE_FREERUN 0
2305#define ICE_AQC_SET_CGU_DPLL_CONFIG_MODE_AUTOMATIC \
2306 ICE_M(0x3, ICE_AQC_SET_CGU_DPLL_CONFIG_MODE_SHIFT)
2307 u8 rsvd2[8];
2308 u8 eec_mode;
2309 u8 rsvd3[1];
2310 __le16 node_handle;
2311};
2312
2313/* Set CGU reference priority (direct 0x0C68) */
2314struct ice_aqc_set_cgu_ref_prio {
2315 u8 dpll_num;
2316 u8 ref_idx;
2317 u8 ref_priority;
2318 u8 rsvd[11];
2319 __le16 node_handle;
2320};
2321
2322/* Get CGU reference priority (direct 0x0C69) */
2323struct ice_aqc_get_cgu_ref_prio {
2324 u8 dpll_num;
2325 u8 ref_idx;
2326 u8 ref_priority; /* Valid only in response */
2327 u8 rsvd[13];
2328};
2329
2330/* Get CGU info (direct 0x0C6A) */
2331struct ice_aqc_get_cgu_info {
2332 __le32 cgu_id;
2333 __le32 cgu_cfg_ver;
2334 __le32 cgu_fw_ver;
2335 u8 node_part_num;
2336 u8 dev_rev;
2337 __le16 node_handle;
2338};
2339
2340/* Driver Shared Parameters (direct, 0x0C90) */
2341struct ice_aqc_driver_shared_params {
2342 u8 set_or_get_op;
2343#define ICE_AQC_DRIVER_PARAM_OP_MASK BIT(0)
2344#define ICE_AQC_DRIVER_PARAM_SET 0
2345#define ICE_AQC_DRIVER_PARAM_GET 1
2346 u8 param_indx;
2347#define ICE_AQC_DRIVER_PARAM_MAX_IDX 15
2348 u8 rsvd[2];
2349 __le32 param_val;
2350 __le32 addr_high;
2351 __le32 addr_low;
2352};
2353
2354/* Lan Queue Overflow Event (direct, 0x1001) */
2355struct ice_aqc_event_lan_overflow {
2356 __le32 prtdcb_ruptq;
2357 __le32 qtx_ctl;
2358 u8 reserved[8];
2359};
2360
2361enum ice_aqc_fw_logging_mod {
2362 ICE_AQC_FW_LOG_ID_GENERAL = 0,
2363 ICE_AQC_FW_LOG_ID_CTRL,
2364 ICE_AQC_FW_LOG_ID_LINK,
2365 ICE_AQC_FW_LOG_ID_LINK_TOPO,
2366 ICE_AQC_FW_LOG_ID_DNL,
2367 ICE_AQC_FW_LOG_ID_I2C,
2368 ICE_AQC_FW_LOG_ID_SDP,
2369 ICE_AQC_FW_LOG_ID_MDIO,
2370 ICE_AQC_FW_LOG_ID_ADMINQ,
2371 ICE_AQC_FW_LOG_ID_HDMA,
2372 ICE_AQC_FW_LOG_ID_LLDP,
2373 ICE_AQC_FW_LOG_ID_DCBX,
2374 ICE_AQC_FW_LOG_ID_DCB,
2375 ICE_AQC_FW_LOG_ID_XLR,
2376 ICE_AQC_FW_LOG_ID_NVM,
2377 ICE_AQC_FW_LOG_ID_AUTH,
2378 ICE_AQC_FW_LOG_ID_VPD,
2379 ICE_AQC_FW_LOG_ID_IOSF,
2380 ICE_AQC_FW_LOG_ID_PARSER,
2381 ICE_AQC_FW_LOG_ID_SW,
2382 ICE_AQC_FW_LOG_ID_SCHEDULER,
2383 ICE_AQC_FW_LOG_ID_TXQ,
2384 ICE_AQC_FW_LOG_ID_RSVD,
2385 ICE_AQC_FW_LOG_ID_POST,
2386 ICE_AQC_FW_LOG_ID_WATCHDOG,
2387 ICE_AQC_FW_LOG_ID_TASK_DISPATCH,
2388 ICE_AQC_FW_LOG_ID_MNG,
2389 ICE_AQC_FW_LOG_ID_SYNCE,
2390 ICE_AQC_FW_LOG_ID_HEALTH,
2391 ICE_AQC_FW_LOG_ID_TSDRV,
2392 ICE_AQC_FW_LOG_ID_PFREG,
2393 ICE_AQC_FW_LOG_ID_MDLVER,
2394 ICE_AQC_FW_LOG_ID_MAX,
2395};
2396
2397/* Set FW Logging configuration (indirect 0xFF30)
2398 * Register for FW Logging (indirect 0xFF31)
2399 * Query FW Logging (indirect 0xFF32)
2400 * FW Log Event (indirect 0xFF33)
2401 */
2402struct ice_aqc_fw_log {
2403 u8 cmd_flags;
2404#define ICE_AQC_FW_LOG_CONF_UART_EN BIT(0)
2405#define ICE_AQC_FW_LOG_CONF_AQ_EN BIT(1)
2406#define ICE_AQC_FW_LOG_QUERY_REGISTERED BIT(2)
2407#define ICE_AQC_FW_LOG_CONF_SET_VALID BIT(3)
2408#define ICE_AQC_FW_LOG_AQ_REGISTER BIT(0)
2409#define ICE_AQC_FW_LOG_AQ_QUERY BIT(2)
2410
2411 u8 rsp_flag;
2412 __le16 fw_rt_msb;
2413 union {
2414 struct {
2415 __le32 fw_rt_lsb;
2416 } sync;
2417 struct {
2418 __le16 log_resolution;
2419#define ICE_AQC_FW_LOG_MIN_RESOLUTION (1)
2420#define ICE_AQC_FW_LOG_MAX_RESOLUTION (128)
2421
2422 __le16 mdl_cnt;
2423 } cfg;
2424 } ops;
2425 __le32 addr_high;
2426 __le32 addr_low;
2427};
2428
2429/* Response Buffer for:
2430 * Set Firmware Logging Configuration (0xFF30)
2431 * Query FW Logging (0xFF32)
2432 */
2433struct ice_aqc_fw_log_cfg_resp {
2434 __le16 module_identifier;
2435 u8 log_level;
2436 u8 rsvd0;
2437};
2438
2439/**
2440 * struct ice_aq_desc - Admin Queue (AQ) descriptor
2441 * @flags: ICE_AQ_FLAG_* flags
2442 * @opcode: AQ command opcode
2443 * @datalen: length in bytes of indirect/external data buffer
2444 * @retval: return value from firmware
2445 * @cookie_high: opaque data high-half
2446 * @cookie_low: opaque data low-half
2447 * @params: command-specific parameters
2448 *
2449 * Descriptor format for commands the driver posts on the Admin Transmit Queue
2450 * (ATQ). The firmware writes back onto the command descriptor and returns
2451 * the result of the command. Asynchronous events that are not an immediate
2452 * result of the command are written to the Admin Receive Queue (ARQ) using
2453 * the same descriptor format. Descriptors are in little-endian notation with
2454 * 32-bit words.
2455 */
2456struct ice_aq_desc {
2457 __le16 flags;
2458 __le16 opcode;
2459 __le16 datalen;
2460 __le16 retval;
2461 __le32 cookie_high;
2462 __le32 cookie_low;
2463 union {
2464 u8 raw[16];
2465 struct ice_aqc_generic generic;
2466 struct ice_aqc_get_ver get_ver;
2467 struct ice_aqc_driver_ver driver_ver;
2468 struct ice_aqc_q_shutdown q_shutdown;
2469 struct ice_aqc_req_res res_owner;
2470 struct ice_aqc_manage_mac_read mac_read;
2471 struct ice_aqc_manage_mac_write mac_write;
2472 struct ice_aqc_clear_pxe clear_pxe;
2473 struct ice_aqc_list_caps get_cap;
2474 struct ice_aqc_get_phy_caps get_phy;
2475 struct ice_aqc_set_phy_cfg set_phy;
2476 struct ice_aqc_restart_an restart_an;
2477 struct ice_aqc_set_phy_rec_clk_out set_phy_rec_clk_out;
2478 struct ice_aqc_get_phy_rec_clk_out get_phy_rec_clk_out;
2479 struct ice_aqc_get_sensor_reading get_sensor_reading;
2480 struct ice_aqc_get_sensor_reading_resp get_sensor_reading_resp;
2481 struct ice_aqc_gpio read_write_gpio;
2482 struct ice_aqc_sff_eeprom read_write_sff_param;
2483 struct ice_aqc_set_port_id_led set_port_id_led;
2484 struct ice_aqc_get_port_options get_port_options;
2485 struct ice_aqc_set_port_option set_port_option;
2486 struct ice_aqc_get_sw_cfg get_sw_conf;
2487 struct ice_aqc_set_port_params set_port_params;
2488 struct ice_aqc_sw_rules sw_rules;
2489 struct ice_aqc_add_get_recipe add_get_recipe;
2490 struct ice_aqc_recipe_to_profile recipe_to_profile;
2491 struct ice_aqc_get_topo get_topo;
2492 struct ice_aqc_sched_elem_cmd sched_elem_cmd;
2493 struct ice_aqc_query_txsched_res query_sched_res;
2494 struct ice_aqc_query_port_ets port_ets;
2495 struct ice_aqc_rl_profile rl_profile;
2496 struct ice_aqc_nvm nvm;
2497 struct ice_aqc_nvm_checksum nvm_checksum;
2498 struct ice_aqc_nvm_pkg_data pkg_data;
2499 struct ice_aqc_nvm_pass_comp_tbl pass_comp_tbl;
2500 struct ice_aqc_pf_vf_msg virt;
2501 struct ice_aqc_set_query_pfc_mode set_query_pfc_mode;
2502 struct ice_aqc_lldp_get_mib lldp_get_mib;
2503 struct ice_aqc_lldp_set_mib_change lldp_set_event;
2504 struct ice_aqc_lldp_stop lldp_stop;
2505 struct ice_aqc_lldp_start lldp_start;
2506 struct ice_aqc_lldp_set_local_mib lldp_set_mib;
2507 struct ice_aqc_lldp_stop_start_specific_agent lldp_agent_ctrl;
2508 struct ice_aqc_lldp_filter_ctrl lldp_filter_ctrl;
2509 struct ice_aqc_get_set_rss_lut get_set_rss_lut;
2510 struct ice_aqc_get_set_rss_key get_set_rss_key;
2511 struct ice_aqc_neigh_dev_req neigh_dev;
2512 struct ice_aqc_add_txqs add_txqs;
2513 struct ice_aqc_dis_txqs dis_txqs;
2514 struct ice_aqc_cfg_txqs cfg_txqs;
2515 struct ice_aqc_add_rdma_qset add_rdma_qset;
2516 struct ice_aqc_add_get_update_free_vsi vsi_cmd;
2517 struct ice_aqc_add_update_free_vsi_resp add_update_free_vsi_res;
2518 struct ice_aqc_download_pkg download_pkg;
2519 struct ice_aqc_set_cgu_input_config set_cgu_input_config;
2520 struct ice_aqc_get_cgu_input_config get_cgu_input_config;
2521 struct ice_aqc_set_cgu_output_config set_cgu_output_config;
2522 struct ice_aqc_get_cgu_output_config get_cgu_output_config;
2523 struct ice_aqc_get_cgu_dpll_status get_cgu_dpll_status;
2524 struct ice_aqc_set_cgu_dpll_config set_cgu_dpll_config;
2525 struct ice_aqc_set_cgu_ref_prio set_cgu_ref_prio;
2526 struct ice_aqc_get_cgu_ref_prio get_cgu_ref_prio;
2527 struct ice_aqc_get_cgu_info get_cgu_info;
2528 struct ice_aqc_driver_shared_params drv_shared_params;
2529 struct ice_aqc_fw_log fw_log;
2530 struct ice_aqc_set_mac_lb set_mac_lb;
2531 struct ice_aqc_alloc_free_res_cmd sw_res_ctrl;
2532 struct ice_aqc_set_mac_cfg set_mac_cfg;
2533 struct ice_aqc_set_event_mask set_event_mask;
2534 struct ice_aqc_get_link_status get_link_status;
2535 struct ice_aqc_event_lan_overflow lan_overflow;
2536 struct ice_aqc_get_link_topo get_link_topo;
2537 struct ice_aqc_i2c read_write_i2c;
2538 struct ice_aqc_read_i2c_resp read_i2c_resp;
2539 } params;
2540};
2541
2542/* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */
2543#define ICE_AQ_LG_BUF 512
2544
2545#define ICE_AQ_FLAG_ERR_S 2
2546#define ICE_AQ_FLAG_LB_S 9
2547#define ICE_AQ_FLAG_RD_S 10
2548#define ICE_AQ_FLAG_BUF_S 12
2549#define ICE_AQ_FLAG_SI_S 13
2550
2551#define ICE_AQ_FLAG_ERR BIT(ICE_AQ_FLAG_ERR_S) /* 0x4 */
2552#define ICE_AQ_FLAG_LB BIT(ICE_AQ_FLAG_LB_S) /* 0x200 */
2553#define ICE_AQ_FLAG_RD BIT(ICE_AQ_FLAG_RD_S) /* 0x400 */
2554#define ICE_AQ_FLAG_BUF BIT(ICE_AQ_FLAG_BUF_S) /* 0x1000 */
2555#define ICE_AQ_FLAG_SI BIT(ICE_AQ_FLAG_SI_S) /* 0x2000 */
2556
2557/* error codes */
2558enum ice_aq_err {
2559 ICE_AQ_RC_OK = 0, /* Success */
2560 ICE_AQ_RC_EPERM = 1, /* Operation not permitted */
2561 ICE_AQ_RC_ENOENT = 2, /* No such element */
2562 ICE_AQ_RC_ENOMEM = 9, /* Out of memory */
2563 ICE_AQ_RC_EBUSY = 12, /* Device or resource busy */
2564 ICE_AQ_RC_EEXIST = 13, /* Object already exists */
2565 ICE_AQ_RC_EINVAL = 14, /* Invalid argument */
2566 ICE_AQ_RC_ENOSPC = 16, /* No space left or allocation failure */
2567 ICE_AQ_RC_ENOSYS = 17, /* Function not implemented */
2568 ICE_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */
2569 ICE_AQ_RC_ENOSEC = 24, /* Missing security manifest */
2570 ICE_AQ_RC_EBADSIG = 25, /* Bad RSA signature */
2571 ICE_AQ_RC_ESVN = 26, /* SVN number prohibits this package */
2572 ICE_AQ_RC_EBADMAN = 27, /* Manifest hash mismatch */
2573 ICE_AQ_RC_EBADBUF = 28, /* Buffer hash mismatches manifest */
2574};
2575
2576/* Admin Queue command opcodes */
2577enum ice_adminq_opc {
2578 /* AQ commands */
2579 ice_aqc_opc_get_ver = 0x0001,
2580 ice_aqc_opc_driver_ver = 0x0002,
2581 ice_aqc_opc_q_shutdown = 0x0003,
2582
2583 /* resource ownership */
2584 ice_aqc_opc_req_res = 0x0008,
2585 ice_aqc_opc_release_res = 0x0009,
2586
2587 /* device/function capabilities */
2588 ice_aqc_opc_list_func_caps = 0x000A,
2589 ice_aqc_opc_list_dev_caps = 0x000B,
2590
2591 /* manage MAC address */
2592 ice_aqc_opc_manage_mac_read = 0x0107,
2593 ice_aqc_opc_manage_mac_write = 0x0108,
2594
2595 /* PXE */
2596 ice_aqc_opc_clear_pxe_mode = 0x0110,
2597
2598 /* internal switch commands */
2599 ice_aqc_opc_get_sw_cfg = 0x0200,
2600 ice_aqc_opc_set_port_params = 0x0203,
2601
2602 /* Alloc/Free/Get Resources */
2603 ice_aqc_opc_alloc_res = 0x0208,
2604 ice_aqc_opc_free_res = 0x0209,
2605 ice_aqc_opc_share_res = 0x020B,
2606 ice_aqc_opc_set_vlan_mode_parameters = 0x020C,
2607 ice_aqc_opc_get_vlan_mode_parameters = 0x020D,
2608
2609 /* VSI commands */
2610 ice_aqc_opc_add_vsi = 0x0210,
2611 ice_aqc_opc_update_vsi = 0x0211,
2612 ice_aqc_opc_free_vsi = 0x0213,
2613
2614 /* recipe commands */
2615 ice_aqc_opc_add_recipe = 0x0290,
2616 ice_aqc_opc_recipe_to_profile = 0x0291,
2617 ice_aqc_opc_get_recipe = 0x0292,
2618 ice_aqc_opc_get_recipe_to_profile = 0x0293,
2619
2620 /* switch rules population commands */
2621 ice_aqc_opc_add_sw_rules = 0x02A0,
2622 ice_aqc_opc_update_sw_rules = 0x02A1,
2623 ice_aqc_opc_remove_sw_rules = 0x02A2,
2624
2625 ice_aqc_opc_clear_pf_cfg = 0x02A4,
2626
2627 /* DCB commands */
2628 ice_aqc_opc_query_pfc_mode = 0x0302,
2629 ice_aqc_opc_set_pfc_mode = 0x0303,
2630
2631 /* transmit scheduler commands */
2632 ice_aqc_opc_get_dflt_topo = 0x0400,
2633 ice_aqc_opc_add_sched_elems = 0x0401,
2634 ice_aqc_opc_cfg_sched_elems = 0x0403,
2635 ice_aqc_opc_get_sched_elems = 0x0404,
2636 ice_aqc_opc_move_sched_elems = 0x0408,
2637 ice_aqc_opc_suspend_sched_elems = 0x0409,
2638 ice_aqc_opc_resume_sched_elems = 0x040A,
2639 ice_aqc_opc_query_port_ets = 0x040E,
2640 ice_aqc_opc_delete_sched_elems = 0x040F,
2641 ice_aqc_opc_add_rl_profiles = 0x0410,
2642 ice_aqc_opc_query_sched_res = 0x0412,
2643 ice_aqc_opc_remove_rl_profiles = 0x0415,
2644
2645 /* PHY commands */
2646 ice_aqc_opc_get_phy_caps = 0x0600,
2647 ice_aqc_opc_set_phy_cfg = 0x0601,
2648 ice_aqc_opc_set_mac_cfg = 0x0603,
2649 ice_aqc_opc_restart_an = 0x0605,
2650 ice_aqc_opc_get_link_status = 0x0607,
2651 ice_aqc_opc_set_event_mask = 0x0613,
2652 ice_aqc_opc_set_mac_lb = 0x0620,
2653 ice_aqc_opc_set_phy_rec_clk_out = 0x0630,
2654 ice_aqc_opc_get_phy_rec_clk_out = 0x0631,
2655 ice_aqc_opc_get_sensor_reading = 0x0632,
2656 ice_aqc_opc_get_link_topo = 0x06E0,
2657 ice_aqc_opc_read_i2c = 0x06E2,
2658 ice_aqc_opc_write_i2c = 0x06E3,
2659 ice_aqc_opc_set_port_id_led = 0x06E9,
2660 ice_aqc_opc_get_port_options = 0x06EA,
2661 ice_aqc_opc_set_port_option = 0x06EB,
2662 ice_aqc_opc_set_gpio = 0x06EC,
2663 ice_aqc_opc_get_gpio = 0x06ED,
2664 ice_aqc_opc_sff_eeprom = 0x06EE,
2665
2666 /* NVM commands */
2667 ice_aqc_opc_nvm_read = 0x0701,
2668 ice_aqc_opc_nvm_erase = 0x0702,
2669 ice_aqc_opc_nvm_write = 0x0703,
2670 ice_aqc_opc_nvm_checksum = 0x0706,
2671 ice_aqc_opc_nvm_write_activate = 0x0707,
2672 ice_aqc_opc_nvm_update_empr = 0x0709,
2673 ice_aqc_opc_nvm_pkg_data = 0x070A,
2674 ice_aqc_opc_nvm_pass_component_tbl = 0x070B,
2675
2676 /* PF/VF mailbox commands */
2677 ice_mbx_opc_send_msg_to_pf = 0x0801,
2678 ice_mbx_opc_send_msg_to_vf = 0x0802,
2679 /* LLDP commands */
2680 ice_aqc_opc_lldp_get_mib = 0x0A00,
2681 ice_aqc_opc_lldp_set_mib_change = 0x0A01,
2682 ice_aqc_opc_lldp_stop = 0x0A05,
2683 ice_aqc_opc_lldp_start = 0x0A06,
2684 ice_aqc_opc_get_cee_dcb_cfg = 0x0A07,
2685 ice_aqc_opc_lldp_set_local_mib = 0x0A08,
2686 ice_aqc_opc_lldp_stop_start_specific_agent = 0x0A09,
2687 ice_aqc_opc_lldp_filter_ctrl = 0x0A0A,
2688 ice_aqc_opc_lldp_execute_pending_mib = 0x0A0B,
2689
2690 /* RSS commands */
2691 ice_aqc_opc_set_rss_key = 0x0B02,
2692 ice_aqc_opc_set_rss_lut = 0x0B03,
2693 ice_aqc_opc_get_rss_key = 0x0B04,
2694 ice_aqc_opc_get_rss_lut = 0x0B05,
2695
2696 /* Sideband Control Interface commands */
2697 ice_aqc_opc_neighbour_device_request = 0x0C00,
2698
2699 /* Tx queue handling commands/events */
2700 ice_aqc_opc_add_txqs = 0x0C30,
2701 ice_aqc_opc_dis_txqs = 0x0C31,
2702 ice_aqc_opc_cfg_txqs = 0x0C32,
2703 ice_aqc_opc_add_rdma_qset = 0x0C33,
2704
2705 /* package commands */
2706 ice_aqc_opc_download_pkg = 0x0C40,
2707 ice_aqc_opc_upload_section = 0x0C41,
2708 ice_aqc_opc_update_pkg = 0x0C42,
2709 ice_aqc_opc_get_pkg_info_list = 0x0C43,
2710
2711 /* 1588/SyncE commands/events */
2712 ice_aqc_opc_get_cgu_abilities = 0x0C61,
2713 ice_aqc_opc_set_cgu_input_config = 0x0C62,
2714 ice_aqc_opc_get_cgu_input_config = 0x0C63,
2715 ice_aqc_opc_set_cgu_output_config = 0x0C64,
2716 ice_aqc_opc_get_cgu_output_config = 0x0C65,
2717 ice_aqc_opc_get_cgu_dpll_status = 0x0C66,
2718 ice_aqc_opc_set_cgu_dpll_config = 0x0C67,
2719 ice_aqc_opc_set_cgu_ref_prio = 0x0C68,
2720 ice_aqc_opc_get_cgu_ref_prio = 0x0C69,
2721 ice_aqc_opc_get_cgu_info = 0x0C6A,
2722
2723 ice_aqc_opc_driver_shared_params = 0x0C90,
2724
2725 /* Standalone Commands/Events */
2726 ice_aqc_opc_event_lan_overflow = 0x1001,
2727
2728 /* FW Logging Commands */
2729 ice_aqc_opc_fw_logs_config = 0xFF30,
2730 ice_aqc_opc_fw_logs_register = 0xFF31,
2731 ice_aqc_opc_fw_logs_query = 0xFF32,
2732 ice_aqc_opc_fw_logs_event = 0xFF33,
2733};
2734
2735#endif /* _ICE_ADMINQ_CMD_H_ */
2736

source code of linux/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h