1/* SPDX-License-Identifier: GPL-2.0-only */
2/* Copyright (C) 2023 Intel Corporation */
3
4#ifndef _IDPF_LAN_TXRX_H_
5#define _IDPF_LAN_TXRX_H_
6
7enum idpf_rss_hash {
8 IDPF_HASH_INVALID = 0,
9 /* Values 1 - 28 are reserved for future use */
10 IDPF_HASH_NONF_UNICAST_IPV4_UDP = 29,
11 IDPF_HASH_NONF_MULTICAST_IPV4_UDP,
12 IDPF_HASH_NONF_IPV4_UDP,
13 IDPF_HASH_NONF_IPV4_TCP_SYN_NO_ACK,
14 IDPF_HASH_NONF_IPV4_TCP,
15 IDPF_HASH_NONF_IPV4_SCTP,
16 IDPF_HASH_NONF_IPV4_OTHER,
17 IDPF_HASH_FRAG_IPV4,
18 /* Values 37-38 are reserved */
19 IDPF_HASH_NONF_UNICAST_IPV6_UDP = 39,
20 IDPF_HASH_NONF_MULTICAST_IPV6_UDP,
21 IDPF_HASH_NONF_IPV6_UDP,
22 IDPF_HASH_NONF_IPV6_TCP_SYN_NO_ACK,
23 IDPF_HASH_NONF_IPV6_TCP,
24 IDPF_HASH_NONF_IPV6_SCTP,
25 IDPF_HASH_NONF_IPV6_OTHER,
26 IDPF_HASH_FRAG_IPV6,
27 IDPF_HASH_NONF_RSVD47,
28 IDPF_HASH_NONF_FCOE_OX,
29 IDPF_HASH_NONF_FCOE_RX,
30 IDPF_HASH_NONF_FCOE_OTHER,
31 /* Values 51-62 are reserved */
32 IDPF_HASH_L2_PAYLOAD = 63,
33
34 IDPF_HASH_MAX
35};
36
37/* Supported RSS offloads */
38#define IDPF_DEFAULT_RSS_HASH \
39 (BIT_ULL(IDPF_HASH_NONF_IPV4_UDP) | \
40 BIT_ULL(IDPF_HASH_NONF_IPV4_SCTP) | \
41 BIT_ULL(IDPF_HASH_NONF_IPV4_TCP) | \
42 BIT_ULL(IDPF_HASH_NONF_IPV4_OTHER) | \
43 BIT_ULL(IDPF_HASH_FRAG_IPV4) | \
44 BIT_ULL(IDPF_HASH_NONF_IPV6_UDP) | \
45 BIT_ULL(IDPF_HASH_NONF_IPV6_TCP) | \
46 BIT_ULL(IDPF_HASH_NONF_IPV6_SCTP) | \
47 BIT_ULL(IDPF_HASH_NONF_IPV6_OTHER) | \
48 BIT_ULL(IDPF_HASH_FRAG_IPV6) | \
49 BIT_ULL(IDPF_HASH_L2_PAYLOAD))
50
51#define IDPF_DEFAULT_RSS_HASH_EXPANDED (IDPF_DEFAULT_RSS_HASH | \
52 BIT_ULL(IDPF_HASH_NONF_IPV4_TCP_SYN_NO_ACK) | \
53 BIT_ULL(IDPF_HASH_NONF_UNICAST_IPV4_UDP) | \
54 BIT_ULL(IDPF_HASH_NONF_MULTICAST_IPV4_UDP) | \
55 BIT_ULL(IDPF_HASH_NONF_IPV6_TCP_SYN_NO_ACK) | \
56 BIT_ULL(IDPF_HASH_NONF_UNICAST_IPV6_UDP) | \
57 BIT_ULL(IDPF_HASH_NONF_MULTICAST_IPV6_UDP))
58
59/* For idpf_splitq_base_tx_compl_desc */
60#define IDPF_TXD_COMPLQ_GEN_S 15
61#define IDPF_TXD_COMPLQ_GEN_M BIT_ULL(IDPF_TXD_COMPLQ_GEN_S)
62#define IDPF_TXD_COMPLQ_COMPL_TYPE_S 11
63#define IDPF_TXD_COMPLQ_COMPL_TYPE_M GENMASK_ULL(13, 11)
64#define IDPF_TXD_COMPLQ_QID_S 0
65#define IDPF_TXD_COMPLQ_QID_M GENMASK_ULL(9, 0)
66
67/* For base mode TX descriptors */
68
69#define IDPF_TXD_CTX_QW0_TUNN_L4T_CS_S 23
70#define IDPF_TXD_CTX_QW0_TUNN_L4T_CS_M BIT_ULL(IDPF_TXD_CTX_QW0_TUNN_L4T_CS_S)
71#define IDPF_TXD_CTX_QW0_TUNN_DECTTL_S 19
72#define IDPF_TXD_CTX_QW0_TUNN_DECTTL_M \
73 (0xFULL << IDPF_TXD_CTX_QW0_TUNN_DECTTL_S)
74#define IDPF_TXD_CTX_QW0_TUNN_NATLEN_S 12
75#define IDPF_TXD_CTX_QW0_TUNN_NATLEN_M \
76 (0X7FULL << IDPF_TXD_CTX_QW0_TUNN_NATLEN_S)
77#define IDPF_TXD_CTX_QW0_TUNN_EIP_NOINC_S 11
78#define IDPF_TXD_CTX_QW0_TUNN_EIP_NOINC_M \
79 BIT_ULL(IDPF_TXD_CTX_QW0_TUNN_EIP_NOINC_S)
80#define IDPF_TXD_CTX_EIP_NOINC_IPID_CONST \
81 IDPF_TXD_CTX_QW0_TUNN_EIP_NOINC_M
82#define IDPF_TXD_CTX_QW0_TUNN_NATT_S 9
83#define IDPF_TXD_CTX_QW0_TUNN_NATT_M (0x3ULL << IDPF_TXD_CTX_QW0_TUNN_NATT_S)
84#define IDPF_TXD_CTX_UDP_TUNNELING BIT_ULL(IDPF_TXD_CTX_QW0_TUNN_NATT_S)
85#define IDPF_TXD_CTX_GRE_TUNNELING (0x2ULL << IDPF_TXD_CTX_QW0_TUNN_NATT_S)
86#define IDPF_TXD_CTX_QW0_TUNN_EXT_IPLEN_S 2
87#define IDPF_TXD_CTX_QW0_TUNN_EXT_IPLEN_M \
88 (0x3FULL << IDPF_TXD_CTX_QW0_TUNN_EXT_IPLEN_S)
89#define IDPF_TXD_CTX_QW0_TUNN_EXT_IP_S 0
90#define IDPF_TXD_CTX_QW0_TUNN_EXT_IP_M \
91 (0x3ULL << IDPF_TXD_CTX_QW0_TUNN_EXT_IP_S)
92
93#define IDPF_TXD_CTX_QW1_MSS_S 50
94#define IDPF_TXD_CTX_QW1_MSS_M GENMASK_ULL(63, 50)
95#define IDPF_TXD_CTX_QW1_TSO_LEN_S 30
96#define IDPF_TXD_CTX_QW1_TSO_LEN_M GENMASK_ULL(47, 30)
97#define IDPF_TXD_CTX_QW1_CMD_S 4
98#define IDPF_TXD_CTX_QW1_CMD_M GENMASK_ULL(15, 4)
99#define IDPF_TXD_CTX_QW1_DTYPE_S 0
100#define IDPF_TXD_CTX_QW1_DTYPE_M GENMASK_ULL(3, 0)
101#define IDPF_TXD_QW1_L2TAG1_S 48
102#define IDPF_TXD_QW1_L2TAG1_M GENMASK_ULL(63, 48)
103#define IDPF_TXD_QW1_TX_BUF_SZ_S 34
104#define IDPF_TXD_QW1_TX_BUF_SZ_M GENMASK_ULL(47, 34)
105#define IDPF_TXD_QW1_OFFSET_S 16
106#define IDPF_TXD_QW1_OFFSET_M GENMASK_ULL(33, 16)
107#define IDPF_TXD_QW1_CMD_S 4
108#define IDPF_TXD_QW1_CMD_M GENMASK_ULL(15, 4)
109#define IDPF_TXD_QW1_DTYPE_S 0
110#define IDPF_TXD_QW1_DTYPE_M GENMASK_ULL(3, 0)
111
112/* TX Completion Descriptor Completion Types */
113#define IDPF_TXD_COMPLT_ITR_FLUSH 0
114/* Descriptor completion type 1 is reserved */
115#define IDPF_TXD_COMPLT_RS 2
116/* Descriptor completion type 3 is reserved */
117#define IDPF_TXD_COMPLT_RE 4
118#define IDPF_TXD_COMPLT_SW_MARKER 5
119
120enum idpf_tx_desc_dtype_value {
121 IDPF_TX_DESC_DTYPE_DATA = 0,
122 IDPF_TX_DESC_DTYPE_CTX = 1,
123 /* DTYPE 2 is reserved
124 * DTYPE 3 is free for future use
125 * DTYPE 4 is reserved
126 */
127 IDPF_TX_DESC_DTYPE_FLEX_TSO_CTX = 5,
128 /* DTYPE 6 is reserved */
129 IDPF_TX_DESC_DTYPE_FLEX_L2TAG1_L2TAG2 = 7,
130 /* DTYPE 8, 9 are free for future use
131 * DTYPE 10 is reserved
132 * DTYPE 11 is free for future use
133 */
134 IDPF_TX_DESC_DTYPE_FLEX_FLOW_SCHE = 12,
135 /* DTYPE 13, 14 are free for future use */
136
137 /* DESC_DONE - HW has completed write-back of descriptor */
138 IDPF_TX_DESC_DTYPE_DESC_DONE = 15,
139};
140
141enum idpf_tx_ctx_desc_cmd_bits {
142 IDPF_TX_CTX_DESC_TSO = 0x01,
143 IDPF_TX_CTX_DESC_TSYN = 0x02,
144 IDPF_TX_CTX_DESC_IL2TAG2 = 0x04,
145 IDPF_TX_CTX_DESC_RSVD = 0x08,
146 IDPF_TX_CTX_DESC_SWTCH_NOTAG = 0x00,
147 IDPF_TX_CTX_DESC_SWTCH_UPLINK = 0x10,
148 IDPF_TX_CTX_DESC_SWTCH_LOCAL = 0x20,
149 IDPF_TX_CTX_DESC_SWTCH_VSI = 0x30,
150 IDPF_TX_CTX_DESC_FILT_AU_EN = 0x40,
151 IDPF_TX_CTX_DESC_FILT_AU_EVICT = 0x80,
152 IDPF_TX_CTX_DESC_RSVD1 = 0xF00
153};
154
155enum idpf_tx_desc_len_fields {
156 /* Note: These are predefined bit offsets */
157 IDPF_TX_DESC_LEN_MACLEN_S = 0, /* 7 BITS */
158 IDPF_TX_DESC_LEN_IPLEN_S = 7, /* 7 BITS */
159 IDPF_TX_DESC_LEN_L4_LEN_S = 14 /* 4 BITS */
160};
161
162enum idpf_tx_base_desc_cmd_bits {
163 IDPF_TX_DESC_CMD_EOP = BIT(0),
164 IDPF_TX_DESC_CMD_RS = BIT(1),
165 /* only on VFs else RSVD */
166 IDPF_TX_DESC_CMD_ICRC = BIT(2),
167 IDPF_TX_DESC_CMD_IL2TAG1 = BIT(3),
168 IDPF_TX_DESC_CMD_RSVD1 = BIT(4),
169 IDPF_TX_DESC_CMD_IIPT_IPV6 = BIT(5),
170 IDPF_TX_DESC_CMD_IIPT_IPV4 = BIT(6),
171 IDPF_TX_DESC_CMD_IIPT_IPV4_CSUM = GENMASK(6, 5),
172 IDPF_TX_DESC_CMD_RSVD2 = BIT(7),
173 IDPF_TX_DESC_CMD_L4T_EOFT_TCP = BIT(8),
174 IDPF_TX_DESC_CMD_L4T_EOFT_SCTP = BIT(9),
175 IDPF_TX_DESC_CMD_L4T_EOFT_UDP = GENMASK(9, 8),
176 IDPF_TX_DESC_CMD_RSVD3 = BIT(10),
177 IDPF_TX_DESC_CMD_RSVD4 = BIT(11),
178};
179
180/* Transmit descriptors */
181/* splitq tx buf, singleq tx buf and singleq compl desc */
182struct idpf_base_tx_desc {
183 __le64 buf_addr; /* Address of descriptor's data buf */
184 __le64 qw1; /* type_cmd_offset_bsz_l2tag1 */
185}; /* read used with buffer queues */
186
187struct idpf_splitq_tx_compl_desc {
188 /* qid=[10:0] comptype=[13:11] rsvd=[14] gen=[15] */
189 __le16 qid_comptype_gen;
190 union {
191 __le16 q_head; /* Queue head */
192 __le16 compl_tag; /* Completion tag */
193 } q_head_compl_tag;
194 u8 ts[3];
195 u8 rsvd; /* Reserved */
196}; /* writeback used with completion queues */
197
198/* Context descriptors */
199struct idpf_base_tx_ctx_desc {
200 struct {
201 __le32 tunneling_params;
202 __le16 l2tag2;
203 __le16 rsvd1;
204 } qw0;
205 __le64 qw1; /* type_cmd_tlen_mss/rt_hint */
206};
207
208/* Common cmd field defines for all desc except Flex Flow Scheduler (0x0C) */
209enum idpf_tx_flex_desc_cmd_bits {
210 IDPF_TX_FLEX_DESC_CMD_EOP = BIT(0),
211 IDPF_TX_FLEX_DESC_CMD_RS = BIT(1),
212 IDPF_TX_FLEX_DESC_CMD_RE = BIT(2),
213 IDPF_TX_FLEX_DESC_CMD_IL2TAG1 = BIT(3),
214 IDPF_TX_FLEX_DESC_CMD_DUMMY = BIT(4),
215 IDPF_TX_FLEX_DESC_CMD_CS_EN = BIT(5),
216 IDPF_TX_FLEX_DESC_CMD_FILT_AU_EN = BIT(6),
217 IDPF_TX_FLEX_DESC_CMD_FILT_AU_EVICT = BIT(7),
218};
219
220struct idpf_flex_tx_desc {
221 __le64 buf_addr; /* Packet buffer address */
222 struct {
223#define IDPF_FLEX_TXD_QW1_DTYPE_S 0
224#define IDPF_FLEX_TXD_QW1_DTYPE_M GENMASK(4, 0)
225#define IDPF_FLEX_TXD_QW1_CMD_S 5
226#define IDPF_FLEX_TXD_QW1_CMD_M GENMASK(15, 5)
227 __le16 cmd_dtype;
228 /* DTYPE=IDPF_TX_DESC_DTYPE_FLEX_L2TAG1_L2TAG2 (0x07) */
229 struct {
230 __le16 l2tag1;
231 __le16 l2tag2;
232 } l2tags;
233 __le16 buf_size;
234 } qw1;
235};
236
237struct idpf_flex_tx_sched_desc {
238 __le64 buf_addr; /* Packet buffer address */
239
240 /* DTYPE = IDPF_TX_DESC_DTYPE_FLEX_FLOW_SCHE_16B (0x0C) */
241 struct {
242 u8 cmd_dtype;
243#define IDPF_TXD_FLEX_FLOW_DTYPE_M GENMASK(4, 0)
244#define IDPF_TXD_FLEX_FLOW_CMD_EOP BIT(5)
245#define IDPF_TXD_FLEX_FLOW_CMD_CS_EN BIT(6)
246#define IDPF_TXD_FLEX_FLOW_CMD_RE BIT(7)
247
248 /* [23:23] Horizon Overflow bit, [22:0] timestamp */
249 u8 ts[3];
250#define IDPF_TXD_FLOW_SCH_HORIZON_OVERFLOW_M BIT(7)
251
252 __le16 compl_tag;
253 __le16 rxr_bufsize;
254#define IDPF_TXD_FLEX_FLOW_RXR BIT(14)
255#define IDPF_TXD_FLEX_FLOW_BUFSIZE_M GENMASK(13, 0)
256 } qw1;
257};
258
259/* Common cmd fields for all flex context descriptors
260 * Note: these defines already account for the 5 bit dtype in the cmd_dtype
261 * field
262 */
263enum idpf_tx_flex_ctx_desc_cmd_bits {
264 IDPF_TX_FLEX_CTX_DESC_CMD_TSO = BIT(5),
265 IDPF_TX_FLEX_CTX_DESC_CMD_TSYN_EN = BIT(6),
266 IDPF_TX_FLEX_CTX_DESC_CMD_L2TAG2 = BIT(7),
267 IDPF_TX_FLEX_CTX_DESC_CMD_SWTCH_UPLNK = BIT(9),
268 IDPF_TX_FLEX_CTX_DESC_CMD_SWTCH_LOCAL = BIT(10),
269 IDPF_TX_FLEX_CTX_DESC_CMD_SWTCH_TARGETVSI = GENMASK(10, 9),
270};
271
272/* Standard flex descriptor TSO context quad word */
273struct idpf_flex_tx_tso_ctx_qw {
274 __le32 flex_tlen;
275#define IDPF_TXD_FLEX_CTX_TLEN_M GENMASK(17, 0)
276#define IDPF_TXD_FLEX_TSO_CTX_FLEX_S 24
277 __le16 mss_rt;
278#define IDPF_TXD_FLEX_CTX_MSS_RT_M GENMASK(13, 0)
279 u8 hdr_len;
280 u8 flex;
281};
282
283struct idpf_flex_tx_ctx_desc {
284 /* DTYPE = IDPF_TX_DESC_DTYPE_FLEX_TSO_CTX (0x05) */
285 struct {
286 struct idpf_flex_tx_tso_ctx_qw qw0;
287 struct {
288 __le16 cmd_dtype;
289 u8 flex[6];
290 } qw1;
291 } tso;
292};
293#endif /* _IDPF_LAN_TXRX_H_ */
294

source code of linux/drivers/net/ethernet/intel/idpf/idpf_lan_txrx.h