| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* Copyright (C) 2023 Intel Corporation */ |
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| 3 | |
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| 4 | #ifndef _IDPF_LAN_VF_REGS_H_ |
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| 5 | #define _IDPF_LAN_VF_REGS_H_ |
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| 6 | |
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| 7 | /* Reset */ |
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| 8 | #define VFGEN_RSTAT 0x00008800 |
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| 9 | #define VFGEN_RSTAT_VFR_STATE_S 0 |
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| 10 | #define VFGEN_RSTAT_VFR_STATE_M GENMASK(1, 0) |
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| 11 | |
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| 12 | /* Control(VF Mailbox) Queue */ |
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| 13 | #define VF_BASE 0x00006000 |
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| 14 | |
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| 15 | #define VF_ATQBAL (VF_BASE + 0x1C00) |
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| 16 | #define VF_ATQBAH (VF_BASE + 0x1800) |
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| 17 | #define VF_ATQLEN (VF_BASE + 0x0800) |
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| 18 | #define VF_ATQLEN_ATQLEN_S 0 |
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| 19 | #define VF_ATQLEN_ATQLEN_M GENMASK(9, 0) |
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| 20 | #define VF_ATQLEN_ATQVFE_S 28 |
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| 21 | #define VF_ATQLEN_ATQVFE_M BIT(VF_ATQLEN_ATQVFE_S) |
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| 22 | #define VF_ATQLEN_ATQOVFL_S 29 |
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| 23 | #define VF_ATQLEN_ATQOVFL_M BIT(VF_ATQLEN_ATQOVFL_S) |
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| 24 | #define VF_ATQLEN_ATQCRIT_S 30 |
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| 25 | #define VF_ATQLEN_ATQCRIT_M BIT(VF_ATQLEN_ATQCRIT_S) |
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| 26 | #define VF_ATQLEN_ATQENABLE_S 31 |
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| 27 | #define VF_ATQLEN_ATQENABLE_M BIT(VF_ATQLEN_ATQENABLE_S) |
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| 28 | #define VF_ATQH (VF_BASE + 0x0400) |
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| 29 | #define VF_ATQH_ATQH_S 0 |
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| 30 | #define VF_ATQH_ATQH_M GENMASK(9, 0) |
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| 31 | #define VF_ATQT (VF_BASE + 0x2400) |
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| 32 | |
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| 33 | #define VF_ARQBAL (VF_BASE + 0x0C00) |
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| 34 | #define VF_ARQBAH (VF_BASE) |
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| 35 | #define VF_ARQLEN (VF_BASE + 0x2000) |
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| 36 | #define VF_ARQLEN_ARQLEN_S 0 |
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| 37 | #define VF_ARQLEN_ARQLEN_M GENMASK(9, 0) |
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| 38 | #define VF_ARQLEN_ARQVFE_S 28 |
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| 39 | #define VF_ARQLEN_ARQVFE_M BIT(VF_ARQLEN_ARQVFE_S) |
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| 40 | #define VF_ARQLEN_ARQOVFL_S 29 |
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| 41 | #define VF_ARQLEN_ARQOVFL_M BIT(VF_ARQLEN_ARQOVFL_S) |
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| 42 | #define VF_ARQLEN_ARQCRIT_S 30 |
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| 43 | #define VF_ARQLEN_ARQCRIT_M BIT(VF_ARQLEN_ARQCRIT_S) |
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| 44 | #define VF_ARQLEN_ARQENABLE_S 31 |
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| 45 | #define VF_ARQLEN_ARQENABLE_M BIT(VF_ARQLEN_ARQENABLE_S) |
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| 46 | #define VF_ARQH (VF_BASE + 0x1400) |
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| 47 | #define VF_ARQH_ARQH_S 0 |
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| 48 | #define VF_ARQH_ARQH_M GENMASK(12, 0) |
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| 49 | #define VF_ARQT (VF_BASE + 0x1000) |
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| 50 | |
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| 51 | /* Transmit queues */ |
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| 52 | #define VF_QTX_TAIL_BASE 0x00000000 |
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| 53 | #define VF_QTX_TAIL(_QTX) (VF_QTX_TAIL_BASE + (_QTX) * 0x4) |
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| 54 | #define VF_QTX_TAIL_EXT_BASE 0x00040000 |
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| 55 | #define VF_QTX_TAIL_EXT(_QTX) (VF_QTX_TAIL_EXT_BASE + ((_QTX) * 4)) |
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| 56 | |
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| 57 | /* Receive queues */ |
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| 58 | #define VF_QRX_TAIL_BASE 0x00002000 |
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| 59 | #define VF_QRX_TAIL(_QRX) (VF_QRX_TAIL_BASE + ((_QRX) * 4)) |
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| 60 | #define VF_QRX_TAIL_EXT_BASE 0x00050000 |
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| 61 | #define VF_QRX_TAIL_EXT(_QRX) (VF_QRX_TAIL_EXT_BASE + ((_QRX) * 4)) |
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| 62 | #define VF_QRXB_TAIL_BASE 0x00060000 |
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| 63 | #define VF_QRXB_TAIL(_QRX) (VF_QRXB_TAIL_BASE + ((_QRX) * 4)) |
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| 64 | |
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| 65 | /* Interrupts */ |
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| 66 | #define VF_INT_DYN_CTL0 0x00005C00 |
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| 67 | #define VF_INT_DYN_CTL0_INTENA_S 0 |
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| 68 | #define VF_INT_DYN_CTL0_INTENA_M BIT(VF_INT_DYN_CTL0_INTENA_S) |
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| 69 | #define VF_INT_DYN_CTL0_ITR_INDX_S 3 |
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| 70 | #define VF_INT_DYN_CTL0_ITR_INDX_M GENMASK(4, 3) |
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| 71 | #define VF_INT_DYN_CTLN(_INT) (0x00003800 + ((_INT) * 4)) |
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| 72 | #define VF_INT_DYN_CTLN_EXT(_INT) (0x00070000 + ((_INT) * 4)) |
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| 73 | #define VF_INT_DYN_CTLN_INTENA_S 0 |
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| 74 | #define VF_INT_DYN_CTLN_INTENA_M BIT(VF_INT_DYN_CTLN_INTENA_S) |
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| 75 | #define VF_INT_DYN_CTLN_CLEARPBA_S 1 |
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| 76 | #define VF_INT_DYN_CTLN_CLEARPBA_M BIT(VF_INT_DYN_CTLN_CLEARPBA_S) |
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| 77 | #define VF_INT_DYN_CTLN_SWINT_TRIG_S 2 |
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| 78 | #define VF_INT_DYN_CTLN_SWINT_TRIG_M BIT(VF_INT_DYN_CTLN_SWINT_TRIG_S) |
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| 79 | #define VF_INT_DYN_CTLN_ITR_INDX_S 3 |
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| 80 | #define VF_INT_DYN_CTLN_ITR_INDX_M GENMASK(4, 3) |
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| 81 | #define VF_INT_DYN_CTLN_INTERVAL_S 5 |
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| 82 | #define VF_INT_DYN_CTLN_INTERVAL_M BIT(VF_INT_DYN_CTLN_INTERVAL_S) |
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| 83 | #define VF_INT_DYN_CTLN_SW_ITR_INDX_ENA_S 24 |
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| 84 | #define VF_INT_DYN_CTLN_SW_ITR_INDX_ENA_M BIT(VF_INT_DYN_CTLN_SW_ITR_INDX_ENA_S) |
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| 85 | #define VF_INT_DYN_CTLN_SW_ITR_INDX_S 25 |
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| 86 | #define VF_INT_DYN_CTLN_SW_ITR_INDX_M BIT(VF_INT_DYN_CTLN_SW_ITR_INDX_S) |
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| 87 | #define VF_INT_DYN_CTLN_WB_ON_ITR_S 30 |
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| 88 | #define VF_INT_DYN_CTLN_WB_ON_ITR_M BIT(VF_INT_DYN_CTLN_WB_ON_ITR_S) |
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| 89 | #define VF_INT_DYN_CTLN_INTENA_MSK_S 31 |
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| 90 | #define VF_INT_DYN_CTLN_INTENA_MSK_M BIT(VF_INT_DYN_CTLN_INTENA_MSK_S) |
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| 91 | /* _ITR is ITR index, _INT is interrupt index, _itrn_indx_spacing is spacing |
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| 92 | * b/w itrn registers of the same vector |
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| 93 | */ |
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| 94 | #define VF_INT_ITR0(_ITR) (0x00004C00 + ((_ITR) * 4)) |
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| 95 | #define VF_INT_ITRN_ADDR(_ITR, _reg_start, _itrn_indx_spacing) \ |
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| 96 | ((_reg_start) + ((_ITR) * (_itrn_indx_spacing))) |
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| 97 | /* For VF with 16 vector support, itrn_reg_spacing is 0x4, itrn_indx_spacing |
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| 98 | * is 0x40 and base register offset is 0x00002800 |
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| 99 | */ |
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| 100 | #define VF_INT_ITRN(_INT, _ITR) \ |
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| 101 | (0x00002800 + ((_INT) * 4) + ((_ITR) * 0x40)) |
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| 102 | /* For VF with 64 vector support, itrn_reg_spacing is 0x4, itrn_indx_spacing |
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| 103 | * is 0x100 and base register offset is 0x00002C00 |
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| 104 | */ |
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| 105 | #define VF_INT_ITRN_64(_INT, _ITR) \ |
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| 106 | (0x00002C00 + ((_INT) * 4) + ((_ITR) * 0x100)) |
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| 107 | /* For VF with 2k vector support, itrn_reg_spacing is 0x4, itrn_indx_spacing |
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| 108 | * is 0x2000 and base register offset is 0x00072000 |
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| 109 | */ |
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| 110 | #define VF_INT_ITRN_2K(_INT, _ITR) \ |
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| 111 | (0x00072000 + ((_INT) * 4) + ((_ITR) * 0x2000)) |
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| 112 | #define VF_INT_ITRN_MAX_INDEX 2 |
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| 113 | #define VF_INT_ITRN_INTERVAL_S 0 |
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| 114 | #define VF_INT_ITRN_INTERVAL_M GENMASK(11, 0) |
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| 115 | #define VF_INT_PBA_CLEAR 0x00008900 |
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| 116 | |
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| 117 | #define VF_INT_ICR0_ENA1 0x00005000 |
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| 118 | #define VF_INT_ICR0_ENA1_ADMINQ_S 30 |
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| 119 | #define VF_INT_ICR0_ENA1_ADMINQ_M BIT(VF_INT_ICR0_ENA1_ADMINQ_S) |
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| 120 | #define VF_INT_ICR0_ENA1_RSVD_S 31 |
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| 121 | #define VF_INT_ICR01 0x00004800 |
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| 122 | #define VF_QF_HENA(_i) (0x0000C400 + ((_i) * 4)) |
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| 123 | #define VF_QF_HENA_MAX_INDX 1 |
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| 124 | #define VF_QF_HKEY(_i) (0x0000CC00 + ((_i) * 4)) |
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| 125 | #define VF_QF_HKEY_MAX_INDX 12 |
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| 126 | #define VF_QF_HLUT(_i) (0x0000D000 + ((_i) * 4)) |
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| 127 | #define VF_QF_HLUT_MAX_INDX 15 |
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| 128 | #endif |
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| 129 | |
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