1/* SPDX-License-Identifier: GPL-2.0-only */
2/* Copyright (C) 2023 Intel Corporation */
3
4#ifndef _VIRTCHNL2_LAN_DESC_H_
5#define _VIRTCHNL2_LAN_DESC_H_
6
7#include <linux/bits.h>
8
9/* This is an interface definition file where existing enums and their values
10 * must remain unchanged over time, so we specify explicit values for all enums.
11 */
12
13/* Transmit descriptor ID flags
14 */
15enum virtchnl2_tx_desc_ids {
16 VIRTCHNL2_TXDID_DATA = BIT(0),
17 VIRTCHNL2_TXDID_CTX = BIT(1),
18 /* TXDID bit 2 is reserved
19 * TXDID bit 3 is free for future use
20 * TXDID bit 4 is reserved
21 */
22 VIRTCHNL2_TXDID_FLEX_TSO_CTX = BIT(5),
23 /* TXDID bit 6 is reserved */
24 VIRTCHNL2_TXDID_FLEX_L2TAG1_L2TAG2 = BIT(7),
25 /* TXDID bits 8 and 9 are free for future use
26 * TXDID bit 10 is reserved
27 * TXDID bit 11 is free for future use
28 */
29 VIRTCHNL2_TXDID_FLEX_FLOW_SCHED = BIT(12),
30 /* TXDID bits 13 and 14 are free for future use */
31 VIRTCHNL2_TXDID_DESC_DONE = BIT(15),
32};
33
34/* Receive descriptor IDs */
35enum virtchnl2_rx_desc_ids {
36 VIRTCHNL2_RXDID_1_32B_BASE = 1,
37 /* FLEX_SQ_NIC and FLEX_SPLITQ share desc ids because they can be
38 * differentiated based on queue model; e.g. single queue model can
39 * only use FLEX_SQ_NIC and split queue model can only use FLEX_SPLITQ
40 * for DID 2.
41 */
42 VIRTCHNL2_RXDID_2_FLEX_SPLITQ = 2,
43 VIRTCHNL2_RXDID_2_FLEX_SQ_NIC = VIRTCHNL2_RXDID_2_FLEX_SPLITQ,
44 /* 3 through 6 are reserved */
45 VIRTCHNL2_RXDID_7_HW_RSVD = 7,
46 /* 8 through 15 are free */
47};
48
49/* Receive descriptor ID bitmasks */
50#define VIRTCHNL2_RXDID_M(bit) BIT_ULL(VIRTCHNL2_RXDID_##bit)
51
52enum virtchnl2_rx_desc_id_bitmasks {
53 VIRTCHNL2_RXDID_1_32B_BASE_M = VIRTCHNL2_RXDID_M(1_32B_BASE),
54 VIRTCHNL2_RXDID_2_FLEX_SPLITQ_M = VIRTCHNL2_RXDID_M(2_FLEX_SPLITQ),
55 VIRTCHNL2_RXDID_2_FLEX_SQ_NIC_M = VIRTCHNL2_RXDID_M(2_FLEX_SQ_NIC),
56 VIRTCHNL2_RXDID_7_HW_RSVD_M = VIRTCHNL2_RXDID_M(7_HW_RSVD),
57};
58
59/* For splitq virtchnl2_rx_flex_desc_adv_nic_3 desc members */
60#define VIRTCHNL2_RX_FLEX_DESC_ADV_RXDID_M GENMASK(3, 0)
61#define VIRTCHNL2_RX_FLEX_DESC_ADV_UMBCAST_M GENMASK(7, 6)
62#define VIRTCHNL2_RX_FLEX_DESC_ADV_PTYPE_M GENMASK(9, 0)
63#define VIRTCHNL2_RX_FLEX_DESC_ADV_RAW_CSUM_INV_S 12
64#define VIRTCHNL2_RX_FLEX_DESC_ADV_RAW_CSUM_INV_M \
65 BIT_ULL(VIRTCHNL2_RX_FLEX_DESC_ADV_RAW_CSUM_INV_S)
66#define VIRTCHNL2_RX_FLEX_DESC_ADV_FF0_M GENMASK(15, 13)
67#define VIRTCHNL2_RX_FLEX_DESC_ADV_LEN_PBUF_M GENMASK(13, 0)
68#define VIRTCHNL2_RX_FLEX_DESC_ADV_GEN_S 14
69#define VIRTCHNL2_RX_FLEX_DESC_ADV_GEN_M \
70 BIT_ULL(VIRTCHNL2_RX_FLEX_DESC_ADV_GEN_S)
71#define VIRTCHNL2_RX_FLEX_DESC_ADV_BUFQ_ID_S 15
72#define VIRTCHNL2_RX_FLEX_DESC_ADV_BUFQ_ID_M \
73 BIT_ULL(VIRTCHNL2_RX_FLEX_DESC_ADV_BUFQ_ID_S)
74#define VIRTCHNL2_RX_FLEX_DESC_ADV_LEN_HDR_M GENMASK(9, 0)
75#define VIRTCHNL2_RX_FLEX_DESC_ADV_RSC_S 10
76#define VIRTCHNL2_RX_FLEX_DESC_ADV_RSC_M \
77 BIT_ULL(VIRTCHNL2_RX_FLEX_DESC_ADV_RSC_S)
78#define VIRTCHNL2_RX_FLEX_DESC_ADV_SPH_S 11
79#define VIRTCHNL2_RX_FLEX_DESC_ADV_SPH_M \
80 BIT_ULL(VIRTCHNL2_RX_FLEX_DESC_ADV_SPH_S)
81#define VIRTCHNL2_RX_FLEX_DESC_ADV_FF1_S 12
82#define VIRTCHNL2_RX_FLEX_DESC_ADV_FF1_M GENMASK(14, 12)
83#define VIRTCHNL2_RX_FLEX_DESC_ADV_MISS_S 15
84#define VIRTCHNL2_RX_FLEX_DESC_ADV_MISS_M \
85 BIT_ULL(VIRTCHNL2_RX_FLEX_DESC_ADV_MISS_S)
86
87/* Bitmasks for splitq virtchnl2_rx_flex_desc_adv_nic_3 */
88enum virtchl2_rx_flex_desc_adv_status_error_0_qw1_bits {
89 VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS0_DD_M = BIT(0),
90 VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS0_EOF_M = BIT(1),
91 VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS0_HBO_M = BIT(2),
92 VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS0_L3L4P_M = BIT(3),
93 VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS0_XSUM_IPE_M = BIT(4),
94 VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS0_XSUM_L4E_M = BIT(5),
95 VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS0_XSUM_EIPE_M = BIT(6),
96 VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS0_XSUM_EUDPE_M = BIT(7),
97};
98
99/* Bitmasks for splitq virtchnl2_rx_flex_desc_adv_nic_3 */
100enum virtchnl2_rx_flex_desc_adv_status_error_0_qw0_bits {
101 VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS0_LPBK_M = BIT(0),
102 VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS0_IPV6EXADD_M = BIT(1),
103 VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS0_RXE_M = BIT(2),
104 VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS0_CRCP_M = BIT(3),
105 VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS0_RSS_VALID_M = BIT(4),
106 VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS0_L2TAG1P_M = BIT(5),
107 VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS0_XTRMD0_VALID_M = BIT(6),
108 VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS0_XTRMD1_VALID_M = BIT(7),
109};
110
111/* Bitmasks for splitq virtchnl2_rx_flex_desc_adv_nic_3 */
112enum virtchnl2_rx_flex_desc_adv_status_error_1_bits {
113 VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS1_RSVD_M = GENMASK(1, 0),
114 VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS1_ATRAEFAIL_M = BIT(2),
115 VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS1_L2TAG2P_M = BIT(3),
116 VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS1_XTRMD2_VALID_M = BIT(4),
117 VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS1_XTRMD3_VALID_M = BIT(5),
118 VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS1_XTRMD4_VALID_M = BIT(6),
119 VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS1_XTRMD5_VALID_M = BIT(7),
120};
121
122/* For singleq (flex) virtchnl2_rx_flex_desc fields
123 * For virtchnl2_rx_flex_desc.ptype_flex_flags0 member
124 */
125#define VIRTCHNL2_RX_FLEX_DESC_PTYPE_M GENMASK(9, 0)
126
127/* For virtchnl2_rx_flex_desc.pkt_len member */
128#define VIRTCHNL2_RX_FLEX_DESC_PKT_LEN_M GENMASK(13, 0)
129
130/* Bitmasks for singleq (flex) virtchnl2_rx_flex_desc */
131enum virtchnl2_rx_flex_desc_status_error_0_bits {
132 VIRTCHNL2_RX_FLEX_DESC_STATUS0_DD_M = BIT(0),
133 VIRTCHNL2_RX_FLEX_DESC_STATUS0_EOF_M = BIT(1),
134 VIRTCHNL2_RX_FLEX_DESC_STATUS0_HBO_M = BIT(2),
135 VIRTCHNL2_RX_FLEX_DESC_STATUS0_L3L4P_M = BIT(3),
136 VIRTCHNL2_RX_FLEX_DESC_STATUS0_XSUM_IPE_M = BIT(4),
137 VIRTCHNL2_RX_FLEX_DESC_STATUS0_XSUM_L4E_M = BIT(5),
138 VIRTCHNL2_RX_FLEX_DESC_STATUS0_XSUM_EIPE_M = BIT(6),
139 VIRTCHNL2_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_M = BIT(7),
140 VIRTCHNL2_RX_FLEX_DESC_STATUS0_LPBK_M = BIT(8),
141 VIRTCHNL2_RX_FLEX_DESC_STATUS0_IPV6EXADD_M = BIT(9),
142 VIRTCHNL2_RX_FLEX_DESC_STATUS0_RXE_M = BIT(10),
143 VIRTCHNL2_RX_FLEX_DESC_STATUS0_CRCP_M = BIT(11),
144 VIRTCHNL2_RX_FLEX_DESC_STATUS0_RSS_VALID_M = BIT(12),
145 VIRTCHNL2_RX_FLEX_DESC_STATUS0_L2TAG1P_M = BIT(13),
146 VIRTCHNL2_RX_FLEX_DESC_STATUS0_XTRMD0_VALID_M = BIT(14),
147 VIRTCHNL2_RX_FLEX_DESC_STATUS0_XTRMD1_VALID_M = BIT(15),
148};
149
150/* Bitmasks for singleq (flex) virtchnl2_rx_flex_desc */
151enum virtchnl2_rx_flex_desc_status_error_1_bits {
152 VIRTCHNL2_RX_FLEX_DESC_STATUS1_CPM_M = GENMASK(3, 0),
153 VIRTCHNL2_RX_FLEX_DESC_STATUS1_NAT_M = BIT(4),
154 VIRTCHNL2_RX_FLEX_DESC_STATUS1_CRYPTO_M = BIT(5),
155 /* [10:6] reserved */
156 VIRTCHNL2_RX_FLEX_DESC_STATUS1_L2TAG2P_M = BIT(11),
157 VIRTCHNL2_RX_FLEX_DESC_STATUS1_XTRMD2_VALID_M = BIT(12),
158 VIRTCHNL2_RX_FLEX_DESC_STATUS1_XTRMD3_VALID_M = BIT(13),
159 VIRTCHNL2_RX_FLEX_DESC_STATUS1_XTRMD4_VALID_M = BIT(14),
160 VIRTCHNL2_RX_FLEX_DESC_STATUS1_XTRMD5_VALID_M = BIT(15),
161};
162
163/* For virtchnl2_rx_flex_desc.ts_low member */
164#define VIRTCHNL2_RX_FLEX_TSTAMP_VALID BIT(0)
165
166/* For singleq (non flex) virtchnl2_singleq_base_rx_desc legacy desc members */
167#define VIRTCHNL2_RX_BASE_DESC_QW1_LEN_PBUF_M GENMASK_ULL(51, 38)
168#define VIRTCHNL2_RX_BASE_DESC_QW1_PTYPE_M GENMASK_ULL(37, 30)
169#define VIRTCHNL2_RX_BASE_DESC_QW1_ERROR_M GENMASK_ULL(26, 19)
170#define VIRTCHNL2_RX_BASE_DESC_QW1_STATUS_M GENMASK_ULL(18, 0)
171
172/* Bitmasks for singleq (base) virtchnl2_rx_base_desc */
173enum virtchnl2_rx_base_desc_status_bits {
174 VIRTCHNL2_RX_BASE_DESC_STATUS_DD_M = BIT(0),
175 VIRTCHNL2_RX_BASE_DESC_STATUS_EOF_M = BIT(1),
176 VIRTCHNL2_RX_BASE_DESC_STATUS_L2TAG1P_M = BIT(2),
177 VIRTCHNL2_RX_BASE_DESC_STATUS_L3L4P_M = BIT(3),
178 VIRTCHNL2_RX_BASE_DESC_STATUS_CRCP_M = BIT(4),
179 VIRTCHNL2_RX_BASE_DESC_STATUS_RSVD_M = GENMASK(7, 5),
180 VIRTCHNL2_RX_BASE_DESC_STATUS_EXT_UDP_0_M = BIT(8),
181 VIRTCHNL2_RX_BASE_DESC_STATUS_UMBCAST_M = GENMASK(10, 9),
182 VIRTCHNL2_RX_BASE_DESC_STATUS_FLM_M = BIT(11),
183 VIRTCHNL2_RX_BASE_DESC_STATUS_FLTSTAT_M = GENMASK(13, 12),
184 VIRTCHNL2_RX_BASE_DESC_STATUS_LPBK_M = BIT(14),
185 VIRTCHNL2_RX_BASE_DESC_STATUS_IPV6EXADD_M = BIT(15),
186 VIRTCHNL2_RX_BASE_DESC_STATUS_RSVD1_M = GENMASK(17, 16),
187 VIRTCHNL2_RX_BASE_DESC_STATUS_INT_UDP_0_M = BIT(18),
188};
189
190/* Bitmasks for singleq (base) virtchnl2_rx_base_desc */
191enum virtchnl2_rx_base_desc_error_bits {
192 VIRTCHNL2_RX_BASE_DESC_ERROR_RXE_M = BIT(0),
193 VIRTCHNL2_RX_BASE_DESC_ERROR_ATRAEFAIL_M = BIT(1),
194 VIRTCHNL2_RX_BASE_DESC_ERROR_HBO_M = BIT(2),
195 VIRTCHNL2_RX_BASE_DESC_ERROR_L3L4E_M = GENMASK(5, 3),
196 VIRTCHNL2_RX_BASE_DESC_ERROR_IPE_M = BIT(3),
197 VIRTCHNL2_RX_BASE_DESC_ERROR_L4E_M = BIT(4),
198 VIRTCHNL2_RX_BASE_DESC_ERROR_EIPE_M = BIT(5),
199 VIRTCHNL2_RX_BASE_DESC_ERROR_OVERSIZE_M = BIT(6),
200 VIRTCHNL2_RX_BASE_DESC_ERROR_PPRS_M = BIT(7),
201};
202
203/* Bitmasks for singleq (base) virtchnl2_rx_base_desc */
204#define VIRTCHNL2_RX_BASE_DESC_FLTSTAT_RSS_HASH_M GENMASK(13, 12)
205
206/**
207 * struct virtchnl2_splitq_rx_buf_desc - SplitQ RX buffer descriptor format
208 * @qword0: RX buffer struct.
209 * @qword0.buf_id: Buffer identifier.
210 * @qword0.rsvd0: Reserved.
211 * @qword0.rsvd1: Reserved.
212 * @pkt_addr: Packet buffer address.
213 * @hdr_addr: Header buffer address.
214 * @rsvd2: Rerserved.
215 *
216 * Receive Descriptors
217 * SplitQ buffer
218 * | 16| 0|
219 * ----------------------------------------------------------------
220 * | RSV | Buffer ID |
221 * ----------------------------------------------------------------
222 * | Rx packet buffer address |
223 * ----------------------------------------------------------------
224 * | Rx header buffer address |
225 * ----------------------------------------------------------------
226 * | RSV |
227 * ----------------------------------------------------------------
228 * | 0|
229 */
230struct virtchnl2_splitq_rx_buf_desc {
231 struct {
232 __le16 buf_id;
233 __le16 rsvd0;
234 __le32 rsvd1;
235 } qword0;
236 __le64 pkt_addr;
237 __le64 hdr_addr;
238 __le64 rsvd2;
239};
240
241/**
242 * struct virtchnl2_singleq_rx_buf_desc - SingleQ RX buffer descriptor format.
243 * @pkt_addr: Packet buffer address.
244 * @hdr_addr: Header buffer address.
245 * @rsvd1: Reserved.
246 * @rsvd2: Reserved.
247 *
248 * SingleQ buffer
249 * | 0|
250 * ----------------------------------------------------------------
251 * | Rx packet buffer address |
252 * ----------------------------------------------------------------
253 * | Rx header buffer address |
254 * ----------------------------------------------------------------
255 * | RSV |
256 * ----------------------------------------------------------------
257 * | RSV |
258 * ----------------------------------------------------------------
259 * | 0|
260 */
261struct virtchnl2_singleq_rx_buf_desc {
262 __le64 pkt_addr;
263 __le64 hdr_addr;
264 __le64 rsvd1;
265 __le64 rsvd2;
266};
267
268/**
269 * struct virtchnl2_singleq_base_rx_desc - RX descriptor writeback format.
270 * @qword0: First quad word struct.
271 * @qword0.lo_dword: Lower dual word struct.
272 * @qword0.lo_dword.mirroring_status: Mirrored packet status.
273 * @qword0.lo_dword.l2tag1: Stripped L2 tag from the received packet.
274 * @qword0.hi_dword: High dual word union.
275 * @qword0.hi_dword.rss: RSS hash.
276 * @qword0.hi_dword.fd_id: Flow director filter id.
277 * @qword1: Second quad word struct.
278 * @qword1.status_error_ptype_len: Status/error/PTYPE/length.
279 * @qword2: Third quad word struct.
280 * @qword2.ext_status: Extended status.
281 * @qword2.rsvd: Reserved.
282 * @qword2.l2tag2_1: Extracted L2 tag 2 from the packet.
283 * @qword2.l2tag2_2: Reserved.
284 * @qword3: Fourth quad word struct.
285 * @qword3.reserved: Reserved.
286 * @qword3.fd_id: Flow director filter id.
287 *
288 * Profile ID 0x1, SingleQ, base writeback format
289 */
290struct virtchnl2_singleq_base_rx_desc {
291 struct {
292 struct {
293 __le16 mirroring_status;
294 __le16 l2tag1;
295 } lo_dword;
296 union {
297 __le32 rss;
298 __le32 fd_id;
299 } hi_dword;
300 } qword0;
301 struct {
302 __le64 status_error_ptype_len;
303 } qword1;
304 struct {
305 __le16 ext_status;
306 __le16 rsvd;
307 __le16 l2tag2_1;
308 __le16 l2tag2_2;
309 } qword2;
310 struct {
311 __le32 reserved;
312 __le32 fd_id;
313 } qword3;
314};
315
316/**
317 * struct virtchnl2_rx_flex_desc_nic - RX descriptor writeback format.
318 *
319 * @rxdid: Descriptor builder profile id.
320 * @mir_id_umb_cast: umb_cast=[7:6], mirror=[5:0]
321 * @ptype_flex_flags0: ff0=[15:10], ptype=[9:0]
322 * @pkt_len: Packet length, [15:14] are reserved.
323 * @hdr_len_sph_flex_flags1: ff1/ext=[15:12], sph=[11], header=[10:0].
324 * @status_error0: Status/Error section 0.
325 * @l2tag1: Stripped L2 tag from the received packet
326 * @rss_hash: RSS hash.
327 * @status_error1: Status/Error section 1.
328 * @flexi_flags2: Flexible flags section 2.
329 * @ts_low: Lower word of timestamp value.
330 * @l2tag2_1st: First L2TAG2.
331 * @l2tag2_2nd: Second L2TAG2.
332 * @flow_id: Flow id.
333 * @flex_ts: Timestamp and flexible flow id union.
334 * @flex_ts.ts_high: Timestamp higher word of the timestamp value.
335 * @flex_ts.flex.rsvd: Reserved.
336 * @flex_ts.flex.flow_id_ipv6: IPv6 flow id.
337 *
338 * Profile ID 0x2, SingleQ, flex writeback format
339 */
340struct virtchnl2_rx_flex_desc_nic {
341 /* Qword 0 */
342 u8 rxdid;
343 u8 mir_id_umb_cast;
344 __le16 ptype_flex_flags0;
345 __le16 pkt_len;
346 __le16 hdr_len_sph_flex_flags1;
347 /* Qword 1 */
348 __le16 status_error0;
349 __le16 l2tag1;
350 __le32 rss_hash;
351 /* Qword 2 */
352 __le16 status_error1;
353 u8 flexi_flags2;
354 u8 ts_low;
355 __le16 l2tag2_1st;
356 __le16 l2tag2_2nd;
357 /* Qword 3 */
358 __le32 flow_id;
359 union {
360 struct {
361 __le16 rsvd;
362 __le16 flow_id_ipv6;
363 } flex;
364 __le32 ts_high;
365 } flex_ts;
366};
367
368/**
369 * struct virtchnl2_rx_flex_desc_adv_nic_3 - RX descriptor writeback format.
370 * @rxdid_ucast: ucast=[7:6], rsvd=[5:4], profile_id=[3:0].
371 * @status_err0_qw0: Status/Error section 0 in quad word 0.
372 * @ptype_err_fflags0: ff0=[15:12], udp_len_err=[11], ip_hdr_err=[10],
373 * ptype=[9:0].
374 * @pktlen_gen_bufq_id: bufq_id=[15] only in splitq, gen=[14] only in splitq,
375 * plen=[13:0].
376 * @hdrlen_flags: miss_prepend=[15], trunc_mirr=[14], int_udp_0=[13],
377 * ext_udp0=[12], sph=[11] only in splitq, rsc=[10]
378 * only in splitq, header=[9:0].
379 * @status_err0_qw1: Status/Error section 0 in quad word 1.
380 * @status_err1: Status/Error section 1.
381 * @fflags1: Flexible flags section 1.
382 * @ts_low: Lower word of timestamp value.
383 * @buf_id: Buffer identifier. Only in splitq mode.
384 * @misc: Union.
385 * @misc.raw_cs: Raw checksum.
386 * @misc.l2tag1: Stripped L2 tag from the received packet
387 * @misc.rscseglen:
388 * @hash1: Lower bits of Rx hash value.
389 * @ff2_mirrid_hash2: Union.
390 * @ff2_mirrid_hash2.fflags2: Flexible flags section 2.
391 * @ff2_mirrid_hash2.mirrorid: Mirror id.
392 * @ff2_mirrid_hash2.rscseglen: RSC segment length.
393 * @hash3: Upper bits of Rx hash value.
394 * @l2tag2: Extracted L2 tag 2 from the packet.
395 * @fmd4: Flexible metadata container 4.
396 * @l2tag1: Stripped L2 tag from the received packet
397 * @fmd6: Flexible metadata container 6.
398 * @ts_high: Timestamp higher word of the timestamp value.
399 *
400 * Profile ID 0x2, SplitQ, flex writeback format
401 *
402 * Flex-field 0: BufferID
403 * Flex-field 1: Raw checksum/L2TAG1/RSC Seg Len (determined by HW)
404 * Flex-field 2: Hash[15:0]
405 * Flex-flags 2: Hash[23:16]
406 * Flex-field 3: L2TAG2
407 * Flex-field 5: L2TAG1
408 * Flex-field 7: Timestamp (upper 32 bits)
409 */
410struct virtchnl2_rx_flex_desc_adv_nic_3 {
411 /* Qword 0 */
412 u8 rxdid_ucast;
413 u8 status_err0_qw0;
414 __le16 ptype_err_fflags0;
415 __le16 pktlen_gen_bufq_id;
416 __le16 hdrlen_flags;
417 /* Qword 1 */
418 u8 status_err0_qw1;
419 u8 status_err1;
420 u8 fflags1;
421 u8 ts_low;
422 __le16 buf_id;
423 union {
424 __le16 raw_cs;
425 __le16 l2tag1;
426 __le16 rscseglen;
427 } misc;
428 /* Qword 2 */
429 __le16 hash1;
430 union {
431 u8 fflags2;
432 u8 mirrorid;
433 u8 hash2;
434 } ff2_mirrid_hash2;
435 u8 hash3;
436 __le16 l2tag2;
437 __le16 fmd4;
438 /* Qword 3 */
439 __le16 l2tag1;
440 __le16 fmd6;
441 __le32 ts_high;
442};
443
444/* Common union for accessing descriptor format structs */
445union virtchnl2_rx_desc {
446 struct virtchnl2_singleq_base_rx_desc base_wb;
447 struct virtchnl2_rx_flex_desc_nic flex_nic_wb;
448 struct virtchnl2_rx_flex_desc_adv_nic_3 flex_adv_nic_3_wb;
449};
450
451#endif /* _VIRTCHNL_LAN_DESC_H_ */
452

source code of linux/drivers/net/ethernet/intel/idpf/virtchnl2_lan_desc.h