1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* Marvell RVU Admin Function driver |
3 | * |
4 | * Copyright (C) 2018 Marvell. |
5 | * |
6 | */ |
7 | |
8 | #ifndef RVU_STRUCT_H |
9 | #define RVU_STRUCT_H |
10 | |
11 | /* RVU Block revision IDs */ |
12 | #define RVU_BLK_RVUM_REVID 0x01 |
13 | |
14 | #define RVU_MULTI_BLK_VER 0x7ULL |
15 | |
16 | /* RVU Block Address Enumeration */ |
17 | enum rvu_block_addr_e { |
18 | BLKADDR_RVUM = 0x0ULL, |
19 | BLKADDR_LMT = 0x1ULL, |
20 | BLKADDR_MSIX = 0x2ULL, |
21 | BLKADDR_NPA = 0x3ULL, |
22 | BLKADDR_NIX0 = 0x4ULL, |
23 | BLKADDR_NIX1 = 0x5ULL, |
24 | BLKADDR_NPC = 0x6ULL, |
25 | BLKADDR_SSO = 0x7ULL, |
26 | BLKADDR_SSOW = 0x8ULL, |
27 | BLKADDR_TIM = 0x9ULL, |
28 | BLKADDR_CPT0 = 0xaULL, |
29 | BLKADDR_CPT1 = 0xbULL, |
30 | BLKADDR_NDC_NIX0_RX = 0xcULL, |
31 | BLKADDR_NDC_NIX0_TX = 0xdULL, |
32 | BLKADDR_NDC_NPA0 = 0xeULL, |
33 | BLKADDR_NDC_NIX1_RX = 0x10ULL, |
34 | BLKADDR_NDC_NIX1_TX = 0x11ULL, |
35 | BLKADDR_APR = 0x16ULL, |
36 | BLK_COUNT = 0x17ULL, |
37 | }; |
38 | |
39 | /* RVU Block Type Enumeration */ |
40 | enum rvu_block_type_e { |
41 | BLKTYPE_RVUM = 0x0, |
42 | BLKTYPE_MSIX = 0x1, |
43 | BLKTYPE_LMT = 0x2, |
44 | BLKTYPE_NIX = 0x3, |
45 | BLKTYPE_NPA = 0x4, |
46 | BLKTYPE_NPC = 0x5, |
47 | BLKTYPE_SSO = 0x6, |
48 | BLKTYPE_SSOW = 0x7, |
49 | BLKTYPE_TIM = 0x8, |
50 | BLKTYPE_CPT = 0x9, |
51 | BLKTYPE_NDC = 0xa, |
52 | BLKTYPE_MAX = 0xa, |
53 | }; |
54 | |
55 | /* RVU Admin function Interrupt Vector Enumeration */ |
56 | enum rvu_af_int_vec_e { |
57 | RVU_AF_INT_VEC_POISON = 0x0, |
58 | RVU_AF_INT_VEC_PFFLR = 0x1, |
59 | RVU_AF_INT_VEC_PFME = 0x2, |
60 | RVU_AF_INT_VEC_GEN = 0x3, |
61 | RVU_AF_INT_VEC_MBOX = 0x4, |
62 | RVU_AF_INT_VEC_CNT = 0x5, |
63 | }; |
64 | |
65 | /* CPT Admin function Interrupt Vector Enumeration */ |
66 | enum cpt_af_int_vec_e { |
67 | CPT_AF_INT_VEC_FLT0 = 0x0, |
68 | CPT_AF_INT_VEC_FLT1 = 0x1, |
69 | CPT_AF_INT_VEC_RVU = 0x2, |
70 | CPT_AF_INT_VEC_RAS = 0x3, |
71 | CPT_AF_INT_VEC_CNT = 0x4, |
72 | }; |
73 | |
74 | enum cpt_10k_af_int_vec_e { |
75 | CPT_10K_AF_INT_VEC_FLT0 = 0x0, |
76 | CPT_10K_AF_INT_VEC_FLT1 = 0x1, |
77 | CPT_10K_AF_INT_VEC_FLT2 = 0x2, |
78 | CPT_10K_AF_INT_VEC_RVU = 0x3, |
79 | CPT_10K_AF_INT_VEC_RAS = 0x4, |
80 | CPT_10K_AF_INT_VEC_CNT = 0x5, |
81 | }; |
82 | |
83 | /* NPA Admin function Interrupt Vector Enumeration */ |
84 | enum npa_af_int_vec_e { |
85 | NPA_AF_INT_VEC_RVU = 0x0, |
86 | NPA_AF_INT_VEC_GEN = 0x1, |
87 | NPA_AF_INT_VEC_AQ_DONE = 0x2, |
88 | NPA_AF_INT_VEC_AF_ERR = 0x3, |
89 | NPA_AF_INT_VEC_POISON = 0x4, |
90 | NPA_AF_INT_VEC_CNT = 0x5, |
91 | }; |
92 | |
93 | /* NIX Admin function Interrupt Vector Enumeration */ |
94 | enum nix_af_int_vec_e { |
95 | NIX_AF_INT_VEC_RVU = 0x0, |
96 | NIX_AF_INT_VEC_GEN = 0x1, |
97 | NIX_AF_INT_VEC_AQ_DONE = 0x2, |
98 | NIX_AF_INT_VEC_AF_ERR = 0x3, |
99 | NIX_AF_INT_VEC_POISON = 0x4, |
100 | NIX_AF_INT_VEC_CNT = 0x5, |
101 | }; |
102 | |
103 | /** |
104 | * RVU PF Interrupt Vector Enumeration |
105 | */ |
106 | enum rvu_pf_int_vec_e { |
107 | RVU_PF_INT_VEC_VFFLR0 = 0x0, |
108 | RVU_PF_INT_VEC_VFFLR1 = 0x1, |
109 | RVU_PF_INT_VEC_VFME0 = 0x2, |
110 | RVU_PF_INT_VEC_VFME1 = 0x3, |
111 | RVU_PF_INT_VEC_VFPF_MBOX0 = 0x4, |
112 | RVU_PF_INT_VEC_VFPF_MBOX1 = 0x5, |
113 | RVU_PF_INT_VEC_AFPF_MBOX = 0x6, |
114 | RVU_PF_INT_VEC_CNT = 0x7, |
115 | }; |
116 | |
117 | /* NPA admin queue completion enumeration */ |
118 | enum npa_aq_comp { |
119 | NPA_AQ_COMP_NOTDONE = 0x0, |
120 | NPA_AQ_COMP_GOOD = 0x1, |
121 | NPA_AQ_COMP_SWERR = 0x2, |
122 | NPA_AQ_COMP_CTX_POISON = 0x3, |
123 | NPA_AQ_COMP_CTX_FAULT = 0x4, |
124 | NPA_AQ_COMP_LOCKERR = 0x5, |
125 | }; |
126 | |
127 | /* NPA admin queue context types */ |
128 | enum npa_aq_ctype { |
129 | NPA_AQ_CTYPE_AURA = 0x0, |
130 | NPA_AQ_CTYPE_POOL = 0x1, |
131 | }; |
132 | |
133 | /* NPA admin queue instruction opcodes */ |
134 | enum npa_aq_instop { |
135 | NPA_AQ_INSTOP_NOP = 0x0, |
136 | NPA_AQ_INSTOP_INIT = 0x1, |
137 | NPA_AQ_INSTOP_WRITE = 0x2, |
138 | NPA_AQ_INSTOP_READ = 0x3, |
139 | NPA_AQ_INSTOP_LOCK = 0x4, |
140 | NPA_AQ_INSTOP_UNLOCK = 0x5, |
141 | }; |
142 | |
143 | /* ALLOC/FREE input queues Enumeration from coprocessors */ |
144 | enum npa_inpq { |
145 | NPA_INPQ_NIX0_RX = 0x0, |
146 | NPA_INPQ_NIX0_TX = 0x1, |
147 | NPA_INPQ_NIX1_RX = 0x2, |
148 | NPA_INPQ_NIX1_TX = 0x3, |
149 | NPA_INPQ_SSO = 0x4, |
150 | NPA_INPQ_TIM = 0x5, |
151 | NPA_INPQ_DPI = 0x6, |
152 | NPA_INPQ_AURA_OP = 0xe, |
153 | NPA_INPQ_INTERNAL_RSV = 0xf, |
154 | }; |
155 | |
156 | /* NPA admin queue instruction structure */ |
157 | struct npa_aq_inst_s { |
158 | u64 op : 4; /* W0 */ |
159 | u64 ctype : 4; |
160 | u64 lf : 9; |
161 | u64 reserved_17_23 : 7; |
162 | u64 cindex : 20; |
163 | u64 reserved_44_62 : 19; |
164 | u64 doneint : 1; |
165 | u64 res_addr; /* W1 */ |
166 | }; |
167 | |
168 | /* NPA admin queue result structure */ |
169 | struct npa_aq_res_s { |
170 | u64 op : 4; /* W0 */ |
171 | u64 ctype : 4; |
172 | u64 compcode : 8; |
173 | u64 doneint : 1; |
174 | u64 reserved_17_63 : 47; |
175 | u64 reserved_64_127; /* W1 */ |
176 | }; |
177 | |
178 | struct npa_aura_s { |
179 | u64 pool_addr; /* W0 */ |
180 | u64 ena : 1; /* W1 */ |
181 | u64 reserved_65 : 2; |
182 | u64 pool_caching : 1; |
183 | u64 pool_way_mask : 16; |
184 | u64 avg_con : 9; |
185 | u64 reserved_93 : 1; |
186 | u64 pool_drop_ena : 1; |
187 | u64 aura_drop_ena : 1; |
188 | u64 bp_ena : 2; |
189 | u64 reserved_98_103 : 6; |
190 | u64 aura_drop : 8; |
191 | u64 shift : 6; |
192 | u64 reserved_118_119 : 2; |
193 | u64 avg_level : 8; |
194 | u64 count : 36; /* W2 */ |
195 | u64 reserved_164_167 : 4; |
196 | u64 nix0_bpid : 9; |
197 | u64 reserved_177_179 : 3; |
198 | u64 nix1_bpid : 9; |
199 | u64 reserved_189_191 : 3; |
200 | u64 limit : 36; /* W3 */ |
201 | u64 reserved_228_231 : 4; |
202 | u64 bp : 8; |
203 | u64 reserved_241_243 : 3; |
204 | u64 fc_be : 1; |
205 | u64 fc_ena : 1; |
206 | u64 fc_up_crossing : 1; |
207 | u64 fc_stype : 2; |
208 | u64 fc_hyst_bits : 4; |
209 | u64 reserved_252_255 : 4; |
210 | u64 fc_addr; /* W4 */ |
211 | u64 pool_drop : 8; /* W5 */ |
212 | u64 update_time : 16; |
213 | u64 err_int : 8; |
214 | u64 err_int_ena : 8; |
215 | u64 thresh_int : 1; |
216 | u64 thresh_int_ena : 1; |
217 | u64 thresh_up : 1; |
218 | u64 reserved_363 : 1; |
219 | u64 thresh_qint_idx : 7; |
220 | u64 reserved_371 : 1; |
221 | u64 err_qint_idx : 7; |
222 | u64 reserved_379_383 : 5; |
223 | u64 thresh : 36; /* W6*/ |
224 | u64 rsvd_423_420 : 4; |
225 | u64 fc_msh_dst : 11; |
226 | u64 reserved_435_447 : 13; |
227 | u64 reserved_448_511; /* W7 */ |
228 | }; |
229 | |
230 | struct npa_pool_s { |
231 | u64 stack_base; /* W0 */ |
232 | u64 ena : 1; |
233 | u64 nat_align : 1; |
234 | u64 reserved_66_67 : 2; |
235 | u64 stack_caching : 1; |
236 | u64 reserved_70_71 : 3; |
237 | u64 stack_way_mask : 16; |
238 | u64 buf_offset : 12; |
239 | u64 reserved_100_103 : 4; |
240 | u64 buf_size : 11; |
241 | u64 reserved_115_127 : 13; |
242 | u64 stack_max_pages : 32; |
243 | u64 stack_pages : 32; |
244 | u64 op_pc : 48; |
245 | u64 reserved_240_255 : 16; |
246 | u64 stack_offset : 4; |
247 | u64 reserved_260_263 : 4; |
248 | u64 shift : 6; |
249 | u64 reserved_270_271 : 2; |
250 | u64 avg_level : 8; |
251 | u64 avg_con : 9; |
252 | u64 fc_ena : 1; |
253 | u64 fc_stype : 2; |
254 | u64 fc_hyst_bits : 4; |
255 | u64 fc_up_crossing : 1; |
256 | u64 fc_be : 1; |
257 | u64 reserved_298_299 : 2; |
258 | u64 update_time : 16; |
259 | u64 reserved_316_319 : 4; |
260 | u64 fc_addr; /* W5 */ |
261 | u64 ptr_start; /* W6 */ |
262 | u64 ptr_end; /* W7 */ |
263 | u64 reserved_512_535 : 24; |
264 | u64 err_int : 8; |
265 | u64 err_int_ena : 8; |
266 | u64 thresh_int : 1; |
267 | u64 thresh_int_ena : 1; |
268 | u64 thresh_up : 1; |
269 | u64 reserved_555 : 1; |
270 | u64 thresh_qint_idx : 7; |
271 | u64 reserved_563 : 1; |
272 | u64 err_qint_idx : 7; |
273 | u64 reserved_571_575 : 5; |
274 | u64 thresh : 36; |
275 | u64 rsvd_615_612 : 4; |
276 | u64 fc_msh_dst : 11; |
277 | u64 reserved_627_639 : 13; |
278 | u64 reserved_640_703; /* W10 */ |
279 | u64 reserved_704_767; /* W11 */ |
280 | u64 reserved_768_831; /* W12 */ |
281 | u64 reserved_832_895; /* W13 */ |
282 | u64 reserved_896_959; /* W14 */ |
283 | u64 reserved_960_1023; /* W15 */ |
284 | }; |
285 | |
286 | /* NIX admin queue completion status */ |
287 | enum nix_aq_comp { |
288 | NIX_AQ_COMP_NOTDONE = 0x0, |
289 | NIX_AQ_COMP_GOOD = 0x1, |
290 | NIX_AQ_COMP_SWERR = 0x2, |
291 | NIX_AQ_COMP_CTX_POISON = 0x3, |
292 | NIX_AQ_COMP_CTX_FAULT = 0x4, |
293 | NIX_AQ_COMP_LOCKERR = 0x5, |
294 | NIX_AQ_COMP_SQB_ALLOC_FAIL = 0x6, |
295 | }; |
296 | |
297 | /* NIX admin queue context types */ |
298 | enum nix_aq_ctype { |
299 | NIX_AQ_CTYPE_RQ = 0x0, |
300 | NIX_AQ_CTYPE_SQ = 0x1, |
301 | NIX_AQ_CTYPE_CQ = 0x2, |
302 | NIX_AQ_CTYPE_MCE = 0x3, |
303 | = 0x4, |
304 | NIX_AQ_CTYPE_DYNO = 0x5, |
305 | NIX_AQ_CTYPE_BANDPROF = 0x6, |
306 | }; |
307 | |
308 | /* NIX admin queue instruction opcodes */ |
309 | enum nix_aq_instop { |
310 | NIX_AQ_INSTOP_NOP = 0x0, |
311 | NIX_AQ_INSTOP_INIT = 0x1, |
312 | NIX_AQ_INSTOP_WRITE = 0x2, |
313 | NIX_AQ_INSTOP_READ = 0x3, |
314 | NIX_AQ_INSTOP_LOCK = 0x4, |
315 | NIX_AQ_INSTOP_UNLOCK = 0x5, |
316 | }; |
317 | |
318 | /* NIX admin queue instruction structure */ |
319 | struct nix_aq_inst_s { |
320 | u64 op : 4; |
321 | u64 ctype : 4; |
322 | u64 lf : 9; |
323 | u64 reserved_17_23 : 7; |
324 | u64 cindex : 20; |
325 | u64 reserved_44_62 : 19; |
326 | u64 doneint : 1; |
327 | u64 res_addr; /* W1 */ |
328 | }; |
329 | |
330 | /* NIX admin queue result structure */ |
331 | struct nix_aq_res_s { |
332 | u64 op : 4; |
333 | u64 ctype : 4; |
334 | u64 compcode : 8; |
335 | u64 doneint : 1; |
336 | u64 reserved_17_63 : 47; |
337 | u64 reserved_64_127; /* W1 */ |
338 | }; |
339 | |
340 | /* NIX Completion queue context structure */ |
341 | struct nix_cq_ctx_s { |
342 | u64 base; |
343 | u64 lbp_ena : 1; |
344 | u64 lbpid_low : 3; |
345 | u64 bp_ena : 1; |
346 | u64 lbpid_med : 3; |
347 | u64 bpid : 9; |
348 | u64 lbpid_high : 3; |
349 | u64 qint_idx : 7; |
350 | u64 cq_err : 1; |
351 | u64 cint_idx : 7; |
352 | u64 avg_con : 9; |
353 | u64 wrptr : 20; |
354 | u64 tail : 20; |
355 | u64 head : 20; |
356 | u64 avg_level : 8; |
357 | u64 update_time : 16; |
358 | u64 bp : 8; |
359 | u64 drop : 8; |
360 | u64 drop_ena : 1; |
361 | u64 ena : 1; |
362 | u64 cpt_drop_err_en : 1; |
363 | u64 rsvd_211 : 1; |
364 | u64 substream : 12; |
365 | u64 stash_thresh : 4; |
366 | u64 lbp_frac : 4; |
367 | u64 caching : 1; |
368 | u64 stashing : 1; |
369 | u64 rsvd_234_235 : 2; |
370 | u64 qsize : 4; |
371 | u64 cq_err_int : 8; |
372 | u64 cq_err_int_ena : 8; |
373 | }; |
374 | |
375 | /* CN10K NIX Receive queue context structure */ |
376 | struct nix_cn10k_rq_ctx_s { |
377 | u64 ena : 1; |
378 | u64 sso_ena : 1; |
379 | u64 ipsech_ena : 1; |
380 | u64 ena_wqwd : 1; |
381 | u64 cq : 20; |
382 | u64 rsvd_36_24 : 13; |
383 | u64 lenerr_dis : 1; |
384 | u64 csum_il4_dis : 1; |
385 | u64 csum_ol4_dis : 1; |
386 | u64 len_il4_dis : 1; |
387 | u64 len_il3_dis : 1; |
388 | u64 len_ol4_dis : 1; |
389 | u64 len_ol3_dis : 1; |
390 | u64 wqe_aura : 20; |
391 | u64 spb_aura : 20; |
392 | u64 lpb_aura : 20; |
393 | u64 sso_grp : 10; |
394 | u64 sso_tt : 2; |
395 | u64 pb_caching : 2; |
396 | u64 wqe_caching : 1; |
397 | u64 xqe_drop_ena : 1; |
398 | u64 spb_drop_ena : 1; |
399 | u64 lpb_drop_ena : 1; |
400 | u64 pb_stashing : 1; |
401 | u64 ipsecd_drop_ena : 1; |
402 | u64 chi_ena : 1; |
403 | u64 rsvd_127_125 : 3; |
404 | u64 band_prof_id : 10; /* W2 */ |
405 | u64 rsvd_138 : 1; |
406 | u64 policer_ena : 1; |
407 | u64 spb_sizem1 : 6; |
408 | u64 wqe_skip : 2; |
409 | u64 rsvd_150_148 : 3; |
410 | u64 spb_ena : 1; |
411 | u64 lpb_sizem1 : 12; |
412 | u64 first_skip : 7; |
413 | u64 rsvd_171 : 1; |
414 | u64 later_skip : 6; |
415 | u64 xqe_imm_size : 6; |
416 | u64 rsvd_189_184 : 6; |
417 | u64 xqe_imm_copy : 1; |
418 | u64 xqe_hdr_split : 1; |
419 | u64 xqe_drop : 8; /* W3 */ |
420 | u64 xqe_pass : 8; |
421 | u64 wqe_pool_drop : 8; |
422 | u64 wqe_pool_pass : 8; |
423 | u64 spb_aura_drop : 8; |
424 | u64 spb_aura_pass : 8; |
425 | u64 spb_pool_drop : 8; |
426 | u64 spb_pool_pass : 8; |
427 | u64 lpb_aura_drop : 8; /* W4 */ |
428 | u64 lpb_aura_pass : 8; |
429 | u64 lpb_pool_drop : 8; |
430 | u64 lpb_pool_pass : 8; |
431 | u64 rsvd_291_288 : 4; |
432 | u64 rq_int : 8; |
433 | u64 rq_int_ena : 8; |
434 | u64 qint_idx : 7; |
435 | u64 rsvd_319_315 : 5; |
436 | u64 ltag : 24; /* W5 */ |
437 | u64 good_utag : 8; |
438 | u64 bad_utag : 8; |
439 | u64 flow_tagw : 6; |
440 | u64 ipsec_vwqe : 1; |
441 | u64 vwqe_ena : 1; |
442 | u64 vwqe_wait : 8; |
443 | u64 max_vsize_exp : 4; |
444 | u64 vwqe_skip : 2; |
445 | u64 rsvd_383_382 : 2; |
446 | u64 octs : 48; /* W6 */ |
447 | u64 rsvd_447_432 : 16; |
448 | u64 pkts : 48; /* W7 */ |
449 | u64 rsvd_511_496 : 16; |
450 | u64 drop_octs : 48; /* W8 */ |
451 | u64 rsvd_575_560 : 16; |
452 | u64 drop_pkts : 48; /* W9 */ |
453 | u64 rsvd_639_624 : 16; |
454 | u64 re_pkts : 48; /* W10 */ |
455 | u64 rsvd_703_688 : 16; |
456 | u64 rsvd_767_704; /* W11 */ |
457 | u64 rsvd_831_768; /* W12 */ |
458 | u64 rsvd_895_832; /* W13 */ |
459 | u64 rsvd_959_896; /* W14 */ |
460 | u64 rsvd_1023_960; /* W15 */ |
461 | }; |
462 | |
463 | /* CN10K NIX Send queue context structure */ |
464 | struct nix_cn10k_sq_ctx_s { |
465 | u64 ena : 1; |
466 | u64 qint_idx : 6; |
467 | u64 substream : 20; |
468 | u64 sdp_mcast : 1; |
469 | u64 cq : 20; |
470 | u64 sqe_way_mask : 16; |
471 | u64 smq : 10; /* W1 */ |
472 | u64 cq_ena : 1; |
473 | u64 xoff : 1; |
474 | u64 sso_ena : 1; |
475 | u64 smq_rr_weight : 14; |
476 | u64 default_chan : 12; |
477 | u64 sqb_count : 16; |
478 | u64 rsvd_120_119 : 2; |
479 | u64 smq_rr_count_lb : 7; |
480 | u64 smq_rr_count_ub : 25; /* W2 */ |
481 | u64 sqb_aura : 20; |
482 | u64 sq_int : 8; |
483 | u64 sq_int_ena : 8; |
484 | u64 sqe_stype : 2; |
485 | u64 rsvd_191 : 1; |
486 | u64 max_sqe_size : 2; /* W3 */ |
487 | u64 cq_limit : 8; |
488 | u64 lmt_dis : 1; |
489 | u64 mnq_dis : 1; |
490 | u64 smq_next_sq : 20; |
491 | u64 smq_lso_segnum : 8; |
492 | u64 tail_offset : 6; |
493 | u64 smenq_offset : 6; |
494 | u64 head_offset : 6; |
495 | u64 smenq_next_sqb_vld : 1; |
496 | u64 smq_pend : 1; |
497 | u64 smq_next_sq_vld : 1; |
498 | u64 rsvd_255_253 : 3; |
499 | u64 next_sqb : 64; /* W4 */ |
500 | u64 tail_sqb : 64; /* W5 */ |
501 | u64 smenq_sqb : 64; /* W6 */ |
502 | u64 smenq_next_sqb : 64; /* W7 */ |
503 | u64 head_sqb : 64; /* W8 */ |
504 | u64 rsvd_583_576 : 8; /* W9 */ |
505 | u64 vfi_lso_total : 18; |
506 | u64 vfi_lso_sizem1 : 3; |
507 | u64 vfi_lso_sb : 8; |
508 | u64 vfi_lso_mps : 14; |
509 | u64 vfi_lso_vlan0_ins_ena : 1; |
510 | u64 vfi_lso_vlan1_ins_ena : 1; |
511 | u64 vfi_lso_vld : 1; |
512 | u64 rsvd_639_630 : 10; |
513 | u64 scm_lso_rem : 18; /* W10 */ |
514 | u64 rsvd_703_658 : 46; |
515 | u64 octs : 48; /* W11 */ |
516 | u64 rsvd_767_752 : 16; |
517 | u64 pkts : 48; /* W12 */ |
518 | u64 rsvd_831_816 : 16; |
519 | u64 rsvd_895_832 : 64; /* W13 */ |
520 | u64 dropped_octs : 48; |
521 | u64 rsvd_959_944 : 16; |
522 | u64 dropped_pkts : 48; |
523 | u64 rsvd_1023_1008 : 16; |
524 | }; |
525 | |
526 | /* NIX Receive queue context structure */ |
527 | struct nix_rq_ctx_s { |
528 | u64 ena : 1; |
529 | u64 sso_ena : 1; |
530 | u64 ipsech_ena : 1; |
531 | u64 ena_wqwd : 1; |
532 | u64 cq : 20; |
533 | u64 substream : 20; |
534 | u64 wqe_aura : 20; |
535 | u64 spb_aura : 20; |
536 | u64 lpb_aura : 20; |
537 | u64 sso_grp : 10; |
538 | u64 sso_tt : 2; |
539 | u64 pb_caching : 2; |
540 | u64 wqe_caching : 1; |
541 | u64 xqe_drop_ena : 1; |
542 | u64 spb_drop_ena : 1; |
543 | u64 lpb_drop_ena : 1; |
544 | u64 rsvd_127_122 : 6; |
545 | u64 rsvd_139_128 : 12; /* W2 */ |
546 | u64 spb_sizem1 : 6; |
547 | u64 wqe_skip : 2; |
548 | u64 rsvd_150_148 : 3; |
549 | u64 spb_ena : 1; |
550 | u64 lpb_sizem1 : 12; |
551 | u64 first_skip : 7; |
552 | u64 rsvd_171 : 1; |
553 | u64 later_skip : 6; |
554 | u64 xqe_imm_size : 6; |
555 | u64 rsvd_189_184 : 6; |
556 | u64 xqe_imm_copy : 1; |
557 | u64 xqe_hdr_split : 1; |
558 | u64 xqe_drop : 8; /* W3*/ |
559 | u64 xqe_pass : 8; |
560 | u64 wqe_pool_drop : 8; |
561 | u64 wqe_pool_pass : 8; |
562 | u64 spb_aura_drop : 8; |
563 | u64 spb_aura_pass : 8; |
564 | u64 spb_pool_drop : 8; |
565 | u64 spb_pool_pass : 8; |
566 | u64 lpb_aura_drop : 8; /* W4 */ |
567 | u64 lpb_aura_pass : 8; |
568 | u64 lpb_pool_drop : 8; |
569 | u64 lpb_pool_pass : 8; |
570 | u64 rsvd_291_288 : 4; |
571 | u64 rq_int : 8; |
572 | u64 rq_int_ena : 8; |
573 | u64 qint_idx : 7; |
574 | u64 rsvd_319_315 : 5; |
575 | u64 ltag : 24; /* W5 */ |
576 | u64 good_utag : 8; |
577 | u64 bad_utag : 8; |
578 | u64 flow_tagw : 6; |
579 | u64 rsvd_383_366 : 18; |
580 | u64 octs : 48; /* W6 */ |
581 | u64 rsvd_447_432 : 16; |
582 | u64 pkts : 48; /* W7 */ |
583 | u64 rsvd_511_496 : 16; |
584 | u64 drop_octs : 48; /* W8 */ |
585 | u64 rsvd_575_560 : 16; |
586 | u64 drop_pkts : 48; /* W9 */ |
587 | u64 rsvd_639_624 : 16; |
588 | u64 re_pkts : 48; /* W10 */ |
589 | u64 rsvd_703_688 : 16; |
590 | u64 rsvd_767_704; /* W11 */ |
591 | u64 rsvd_831_768; /* W12 */ |
592 | u64 rsvd_895_832; /* W13 */ |
593 | u64 rsvd_959_896; /* W14 */ |
594 | u64 rsvd_1023_960; /* W15 */ |
595 | }; |
596 | |
597 | /* NIX sqe sizes */ |
598 | enum nix_maxsqesz { |
599 | NIX_MAXSQESZ_W16 = 0x0, |
600 | NIX_MAXSQESZ_W8 = 0x1, |
601 | }; |
602 | |
603 | /* NIX SQB caching type */ |
604 | enum nix_stype { |
605 | NIX_STYPE_STF = 0x0, |
606 | NIX_STYPE_STT = 0x1, |
607 | NIX_STYPE_STP = 0x2, |
608 | }; |
609 | |
610 | /* NIX Send queue context structure */ |
611 | struct nix_sq_ctx_s { |
612 | u64 ena : 1; |
613 | u64 qint_idx : 6; |
614 | u64 substream : 20; |
615 | u64 sdp_mcast : 1; |
616 | u64 cq : 20; |
617 | u64 sqe_way_mask : 16; |
618 | u64 smq : 9; |
619 | u64 cq_ena : 1; |
620 | u64 xoff : 1; |
621 | u64 sso_ena : 1; |
622 | u64 smq_rr_quantum : 24; |
623 | u64 default_chan : 12; |
624 | u64 sqb_count : 16; |
625 | u64 smq_rr_count : 25; |
626 | u64 sqb_aura : 20; |
627 | u64 sq_int : 8; |
628 | u64 sq_int_ena : 8; |
629 | u64 sqe_stype : 2; |
630 | u64 rsvd_191 : 1; |
631 | u64 max_sqe_size : 2; |
632 | u64 cq_limit : 8; |
633 | u64 lmt_dis : 1; |
634 | u64 mnq_dis : 1; |
635 | u64 smq_next_sq : 20; |
636 | u64 smq_lso_segnum : 8; |
637 | u64 tail_offset : 6; |
638 | u64 smenq_offset : 6; |
639 | u64 head_offset : 6; |
640 | u64 smenq_next_sqb_vld : 1; |
641 | u64 smq_pend : 1; |
642 | u64 smq_next_sq_vld : 1; |
643 | u64 rsvd_255_253 : 3; |
644 | u64 next_sqb : 64;/* W4 */ |
645 | u64 tail_sqb : 64;/* W5 */ |
646 | u64 smenq_sqb : 64;/* W6 */ |
647 | u64 smenq_next_sqb : 64;/* W7 */ |
648 | u64 head_sqb : 64;/* W8 */ |
649 | u64 rsvd_583_576 : 8; |
650 | u64 vfi_lso_total : 18; |
651 | u64 vfi_lso_sizem1 : 3; |
652 | u64 vfi_lso_sb : 8; |
653 | u64 vfi_lso_mps : 14; |
654 | u64 vfi_lso_vlan0_ins_ena : 1; |
655 | u64 vfi_lso_vlan1_ins_ena : 1; |
656 | u64 vfi_lso_vld : 1; |
657 | u64 rsvd_639_630 : 10; |
658 | u64 scm_lso_rem : 18; |
659 | u64 rsvd_703_658 : 46; |
660 | u64 octs : 48; |
661 | u64 rsvd_767_752 : 16; |
662 | u64 pkts : 48; |
663 | u64 rsvd_831_816 : 16; |
664 | u64 rsvd_895_832 : 64;/* W13 */ |
665 | u64 dropped_octs : 48; |
666 | u64 rsvd_959_944 : 16; |
667 | u64 dropped_pkts : 48; |
668 | u64 rsvd_1023_1008 : 16; |
669 | }; |
670 | |
671 | /* NIX Receive side scaling entry structure*/ |
672 | struct { |
673 | uint32_t : 20; |
674 | uint32_t : 12; |
675 | |
676 | }; |
677 | |
678 | /* NIX receive multicast/mirror entry structure */ |
679 | struct nix_rx_mce_s { |
680 | uint64_t op : 2; |
681 | uint64_t rsvd_2 : 1; |
682 | uint64_t eol : 1; |
683 | uint64_t index : 20; |
684 | uint64_t rsvd_31_24 : 8; |
685 | uint64_t pf_func : 16; |
686 | uint64_t next : 16; |
687 | }; |
688 | |
689 | enum nix_band_prof_layers { |
690 | BAND_PROF_LEAF_LAYER = 0, |
691 | BAND_PROF_INVAL_LAYER = 1, |
692 | BAND_PROF_MID_LAYER = 2, |
693 | BAND_PROF_TOP_LAYER = 3, |
694 | BAND_PROF_NUM_LAYERS = 4, |
695 | }; |
696 | |
697 | enum NIX_RX_BAND_PROF_ACTIONRESULT_E { |
698 | NIX_RX_BAND_PROF_ACTIONRESULT_PASS = 0x0, |
699 | NIX_RX_BAND_PROF_ACTIONRESULT_DROP = 0x1, |
700 | NIX_RX_BAND_PROF_ACTIONRESULT_RED = 0x2, |
701 | }; |
702 | |
703 | enum nix_band_prof_pc_mode { |
704 | NIX_RX_PC_MODE_VLAN = 0, |
705 | NIX_RX_PC_MODE_DSCP = 1, |
706 | NIX_RX_PC_MODE_GEN = 2, |
707 | NIX_RX_PC_MODE_RSVD = 3, |
708 | }; |
709 | |
710 | /* NIX ingress policer bandwidth profile structure */ |
711 | struct nix_bandprof_s { |
712 | uint64_t pc_mode : 2; /* W0 */ |
713 | uint64_t icolor : 2; |
714 | uint64_t tnl_ena : 1; |
715 | uint64_t reserved_5_7 : 3; |
716 | uint64_t peir_exponent : 5; |
717 | uint64_t reserved_13_15 : 3; |
718 | uint64_t pebs_exponent : 5; |
719 | uint64_t reserved_21_23 : 3; |
720 | uint64_t cir_exponent : 5; |
721 | uint64_t reserved_29_31 : 3; |
722 | uint64_t cbs_exponent : 5; |
723 | uint64_t reserved_37_39 : 3; |
724 | uint64_t peir_mantissa : 8; |
725 | uint64_t pebs_mantissa : 8; |
726 | uint64_t cir_mantissa : 8; |
727 | uint64_t cbs_mantissa : 8; /* W1 */ |
728 | uint64_t lmode : 1; |
729 | uint64_t l_sellect : 3; |
730 | uint64_t rdiv : 4; |
731 | uint64_t adjust_exponent : 5; |
732 | uint64_t reserved_85_86 : 2; |
733 | uint64_t adjust_mantissa : 9; |
734 | uint64_t gc_action : 2; |
735 | uint64_t yc_action : 2; |
736 | uint64_t rc_action : 2; |
737 | uint64_t meter_algo : 2; |
738 | uint64_t band_prof_id : 7; |
739 | uint64_t reserved_111_118 : 8; |
740 | uint64_t hl_en : 1; |
741 | uint64_t reserved_120_127 : 8; |
742 | uint64_t ts : 48; /* W2 */ |
743 | uint64_t reserved_176_191 : 16; |
744 | uint64_t pe_accum : 32; /* W3 */ |
745 | uint64_t c_accum : 32; |
746 | uint64_t green_pkt_pass : 48; /* W4 */ |
747 | uint64_t reserved_304_319 : 16; |
748 | uint64_t yellow_pkt_pass : 48; /* W5 */ |
749 | uint64_t reserved_368_383 : 16; |
750 | uint64_t red_pkt_pass : 48; /* W6 */ |
751 | uint64_t reserved_432_447 : 16; |
752 | uint64_t green_octs_pass : 48; /* W7 */ |
753 | uint64_t reserved_496_511 : 16; |
754 | uint64_t yellow_octs_pass : 48; /* W8 */ |
755 | uint64_t reserved_560_575 : 16; |
756 | uint64_t red_octs_pass : 48; /* W9 */ |
757 | uint64_t reserved_624_639 : 16; |
758 | uint64_t green_pkt_drop : 48; /* W10 */ |
759 | uint64_t reserved_688_703 : 16; |
760 | uint64_t yellow_pkt_drop : 48; /* W11 */ |
761 | uint64_t reserved_752_767 : 16; |
762 | uint64_t red_pkt_drop : 48; /* W12 */ |
763 | uint64_t reserved_816_831 : 16; |
764 | uint64_t green_octs_drop : 48; /* W13 */ |
765 | uint64_t reserved_880_895 : 16; |
766 | uint64_t yellow_octs_drop : 48; /* W14 */ |
767 | uint64_t reserved_944_959 : 16; |
768 | uint64_t red_octs_drop : 48; /* W15 */ |
769 | uint64_t reserved_1008_1023 : 16; |
770 | }; |
771 | |
772 | enum nix_lsoalg { |
773 | NIX_LSOALG_NOP, |
774 | NIX_LSOALG_ADD_SEGNUM, |
775 | NIX_LSOALG_ADD_PAYLEN, |
776 | NIX_LSOALG_ADD_OFFSET, |
777 | NIX_LSOALG_TCP_FLAGS, |
778 | }; |
779 | |
780 | enum nix_txlayer { |
781 | NIX_TXLAYER_OL3, |
782 | NIX_TXLAYER_OL4, |
783 | NIX_TXLAYER_IL3, |
784 | NIX_TXLAYER_IL4, |
785 | }; |
786 | |
787 | struct nix_lso_format { |
788 | u64 offset : 8; |
789 | u64 layer : 2; |
790 | u64 rsvd_10_11 : 2; |
791 | u64 sizem1 : 2; |
792 | u64 rsvd_14_15 : 2; |
793 | u64 alg : 3; |
794 | u64 rsvd_19_63 : 45; |
795 | }; |
796 | |
797 | struct nix_rx_flowkey_alg { |
798 | u64 key_offset :6; |
799 | u64 ln_mask :1; |
800 | u64 fn_mask :1; |
801 | u64 hdr_offset :8; |
802 | u64 bytesm1 :5; |
803 | u64 lid :3; |
804 | u64 reserved_24_24 :1; |
805 | u64 ena :1; |
806 | u64 sel_chan :1; |
807 | u64 ltype_mask :4; |
808 | u64 ltype_match :4; |
809 | u64 reserved_35_63 :29; |
810 | }; |
811 | |
812 | /* NIX VTAG size */ |
813 | enum nix_vtag_size { |
814 | VTAGSIZE_T4 = 0x0, |
815 | VTAGSIZE_T8 = 0x1, |
816 | }; |
817 | |
818 | enum nix_tx_vtag_op { |
819 | NOP = 0x0, |
820 | VTAG_INSERT = 0x1, |
821 | VTAG_REPLACE = 0x2, |
822 | }; |
823 | |
824 | /* NIX RX VTAG actions */ |
825 | #define VTAG_STRIP BIT_ULL(4) |
826 | #define VTAG_CAPTURE BIT_ULL(5) |
827 | |
828 | #endif /* RVU_STRUCT_H */ |
829 | |