| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* Marvell RVU Ethernet driver |
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| 3 | * |
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| 4 | * Copyright (C) 2021 Marvell. |
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| 5 | * |
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| 6 | */ |
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| 7 | |
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| 8 | #ifndef CN10K_H |
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| 9 | #define CN10K_H |
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| 10 | |
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| 11 | #include "otx2_common.h" |
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| 12 | |
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| 13 | static inline int mtu_to_dwrr_weight(struct otx2_nic *pfvf, int mtu) |
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| 14 | { |
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| 15 | u32 weight; |
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| 16 | |
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| 17 | /* On OTx2, since AF returns DWRR_MTU as '1', this logic |
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| 18 | * will work on those silicons as well. |
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| 19 | */ |
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| 20 | weight = mtu / pfvf->hw.dwrr_mtu; |
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| 21 | if (mtu % pfvf->hw.dwrr_mtu) |
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| 22 | weight += 1; |
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| 23 | |
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| 24 | return weight; |
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| 25 | } |
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| 26 | |
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| 27 | int cn10k_refill_pool_ptrs(void *dev, struct otx2_cq_queue *cq); |
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| 28 | void cn10k_sqe_flush(void *dev, struct otx2_snd_queue *sq, int size, int qidx); |
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| 29 | int cn10k_sq_aq_init(void *dev, u16 qidx, u16 sqb_aura); |
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| 30 | int cn10k_lmtst_init(struct otx2_nic *pfvf); |
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| 31 | int cn10k_free_all_ipolicers(struct otx2_nic *pfvf); |
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| 32 | int cn10k_alloc_matchall_ipolicer(struct otx2_nic *pfvf); |
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| 33 | int cn10k_free_matchall_ipolicer(struct otx2_nic *pfvf); |
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| 34 | int cn10k_set_matchall_ipolicer_rate(struct otx2_nic *pfvf, |
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| 35 | u32 burst, u64 rate); |
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| 36 | int cn10k_map_unmap_rq_policer(struct otx2_nic *pfvf, int rq_idx, |
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| 37 | u16 policer, bool map); |
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| 38 | int cn10k_alloc_leaf_profile(struct otx2_nic *pfvf, u16 *leaf); |
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| 39 | int cn10k_set_ipolicer_rate(struct otx2_nic *pfvf, u16 profile, |
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| 40 | u32 burst, u64 rate, bool pps); |
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| 41 | int cn10k_free_leaf_profile(struct otx2_nic *pfvf, u16 leaf); |
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| 42 | #endif /* CN10K_H */ |
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| 43 | |
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