| 1 | /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ |
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| 2 | /* |
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| 3 | * Microsemi Ocelot Switch driver |
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| 4 | * |
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| 5 | * Copyright (c) 2017 Microsemi Corporation |
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| 6 | */ |
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| 7 | |
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| 8 | #ifndef _MSCC_OCELOT_REW_H_ |
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| 9 | #define _MSCC_OCELOT_REW_H_ |
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| 10 | |
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| 11 | #define REW_PORT_VLAN_CFG_GSZ 0x80 |
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| 12 | |
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| 13 | #define REW_PORT_VLAN_CFG_PORT_TPID(x) (((x) << 16) & GENMASK(31, 16)) |
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| 14 | #define REW_PORT_VLAN_CFG_PORT_TPID_M GENMASK(31, 16) |
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| 15 | #define REW_PORT_VLAN_CFG_PORT_TPID_X(x) (((x) & GENMASK(31, 16)) >> 16) |
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| 16 | #define REW_PORT_VLAN_CFG_PORT_DEI BIT(15) |
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| 17 | #define REW_PORT_VLAN_CFG_PORT_PCP(x) (((x) << 12) & GENMASK(14, 12)) |
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| 18 | #define REW_PORT_VLAN_CFG_PORT_PCP_M GENMASK(14, 12) |
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| 19 | #define REW_PORT_VLAN_CFG_PORT_PCP_X(x) (((x) & GENMASK(14, 12)) >> 12) |
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| 20 | #define REW_PORT_VLAN_CFG_PORT_VID(x) ((x) & GENMASK(11, 0)) |
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| 21 | #define REW_PORT_VLAN_CFG_PORT_VID_M GENMASK(11, 0) |
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| 22 | |
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| 23 | #define REW_TAG_CFG_GSZ 0x80 |
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| 24 | |
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| 25 | #define REW_TAG_CFG_TAG_CFG(x) (((x) << 7) & GENMASK(8, 7)) |
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| 26 | #define REW_TAG_CFG_TAG_CFG_M GENMASK(8, 7) |
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| 27 | #define REW_TAG_CFG_TAG_CFG_X(x) (((x) & GENMASK(8, 7)) >> 7) |
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| 28 | #define REW_TAG_CFG_TAG_TPID_CFG(x) (((x) << 5) & GENMASK(6, 5)) |
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| 29 | #define REW_TAG_CFG_TAG_TPID_CFG_M GENMASK(6, 5) |
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| 30 | #define REW_TAG_CFG_TAG_TPID_CFG_X(x) (((x) & GENMASK(6, 5)) >> 5) |
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| 31 | #define REW_TAG_CFG_TAG_VID_CFG BIT(4) |
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| 32 | #define REW_TAG_CFG_TAG_PCP_CFG(x) (((x) << 2) & GENMASK(3, 2)) |
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| 33 | #define REW_TAG_CFG_TAG_PCP_CFG_M GENMASK(3, 2) |
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| 34 | #define REW_TAG_CFG_TAG_PCP_CFG_X(x) (((x) & GENMASK(3, 2)) >> 2) |
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| 35 | #define REW_TAG_CFG_TAG_DEI_CFG(x) ((x) & GENMASK(1, 0)) |
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| 36 | #define REW_TAG_CFG_TAG_DEI_CFG_M GENMASK(1, 0) |
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| 37 | |
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| 38 | #define REW_PORT_CFG_GSZ 0x80 |
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| 39 | |
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| 40 | #define REW_PORT_CFG_ES0_EN BIT(5) |
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| 41 | #define REW_PORT_CFG_FCS_UPDATE_NONCPU_CFG(x) (((x) << 3) & GENMASK(4, 3)) |
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| 42 | #define REW_PORT_CFG_FCS_UPDATE_NONCPU_CFG_M GENMASK(4, 3) |
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| 43 | #define REW_PORT_CFG_FCS_UPDATE_NONCPU_CFG_X(x) (((x) & GENMASK(4, 3)) >> 3) |
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| 44 | #define REW_PORT_CFG_FCS_UPDATE_CPU_ENA BIT(2) |
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| 45 | #define REW_PORT_CFG_FLUSH_ENA BIT(1) |
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| 46 | #define REW_PORT_CFG_AGE_DIS BIT(0) |
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| 47 | |
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| 48 | #define REW_DSCP_CFG_GSZ 0x80 |
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| 49 | |
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| 50 | #define REW_PCP_DEI_QOS_MAP_CFG_GSZ 0x80 |
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| 51 | #define REW_PCP_DEI_QOS_MAP_CFG_RSZ 0x4 |
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| 52 | |
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| 53 | #define REW_PCP_DEI_QOS_MAP_CFG_DEI_QOS_VAL BIT(3) |
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| 54 | #define REW_PCP_DEI_QOS_MAP_CFG_PCP_QOS_VAL(x) ((x) & GENMASK(2, 0)) |
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| 55 | #define REW_PCP_DEI_QOS_MAP_CFG_PCP_QOS_VAL_M GENMASK(2, 0) |
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| 56 | |
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| 57 | #define REW_PTP_CFG_GSZ 0x80 |
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| 58 | |
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| 59 | #define REW_PTP_CFG_PTP_BACKPLANE_MODE BIT(7) |
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| 60 | #define REW_PTP_CFG_GP_CFG_UNUSED(x) (((x) << 3) & GENMASK(6, 3)) |
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| 61 | #define REW_PTP_CFG_GP_CFG_UNUSED_M GENMASK(6, 3) |
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| 62 | #define REW_PTP_CFG_GP_CFG_UNUSED_X(x) (((x) & GENMASK(6, 3)) >> 3) |
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| 63 | #define REW_PTP_CFG_PTP_1STEP_DIS BIT(2) |
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| 64 | #define REW_PTP_CFG_PTP_2STEP_DIS BIT(1) |
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| 65 | #define REW_PTP_CFG_PTP_UDP_KEEP BIT(0) |
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| 66 | |
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| 67 | #define REW_PTP_DLY1_CFG_GSZ 0x80 |
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| 68 | |
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| 69 | #define REW_RED_TAG_CFG_GSZ 0x80 |
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| 70 | |
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| 71 | #define REW_RED_TAG_CFG_RED_TAG_CFG BIT(0) |
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| 72 | |
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| 73 | #define REW_DSCP_REMAP_DP1_CFG_RSZ 0x4 |
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| 74 | |
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| 75 | #define REW_DSCP_REMAP_CFG_RSZ 0x4 |
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| 76 | |
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| 77 | #define REW_REW_STICKY_ES0_TAGB_PUSH_FAILED BIT(0) |
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| 78 | |
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| 79 | #define REW_PPT_RSZ 0x4 |
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| 80 | |
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| 81 | #endif |
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| 82 | |
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