1 | /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ |
2 | /* QLogic qed NIC Driver |
3 | * Copyright (c) 2015-2017 QLogic Corporation |
4 | * Copyright (c) 2019-2020 Marvell International Ltd. |
5 | */ |
6 | |
7 | #ifndef REG_ADDR_H |
8 | #define REG_ADDR_H |
9 | |
10 | #define CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE_SHIFT \ |
11 | 0 |
12 | |
13 | #define CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE ( \ |
14 | 0xfff << 0) |
15 | |
16 | #define CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE_SHIFT \ |
17 | 12 |
18 | |
19 | #define CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE ( \ |
20 | 0xfff << 12) |
21 | |
22 | #define CDU_REG_CID_ADDR_PARAMS_NCIB_SHIFT \ |
23 | 24 |
24 | |
25 | #define CDU_REG_CID_ADDR_PARAMS_NCIB ( \ |
26 | 0xff << 24) |
27 | |
28 | #define CDU_REG_SEGMENT0_PARAMS \ |
29 | 0x580904UL |
30 | #define CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK \ |
31 | (0xfff << 0) |
32 | #define CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK_SHIFT \ |
33 | 0 |
34 | #define CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE \ |
35 | (0xff << 16) |
36 | #define CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE_SHIFT \ |
37 | 16 |
38 | #define CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE \ |
39 | (0xff << 24) |
40 | #define CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE_SHIFT \ |
41 | 24 |
42 | #define CDU_REG_SEGMENT1_PARAMS \ |
43 | 0x580908UL |
44 | #define CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK \ |
45 | (0xfff << 0) |
46 | #define CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK_SHIFT \ |
47 | 0 |
48 | #define CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE \ |
49 | (0xff << 16) |
50 | #define CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE_SHIFT \ |
51 | 16 |
52 | #define CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE \ |
53 | (0xff << 24) |
54 | #define CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE_SHIFT \ |
55 | 24 |
56 | |
57 | #define XSDM_REG_OPERATION_GEN \ |
58 | 0xf80408UL |
59 | #define NIG_REG_RX_BRB_OUT_EN \ |
60 | 0x500e18UL |
61 | #define NIG_REG_STORM_OUT_EN \ |
62 | 0x500e08UL |
63 | #define PSWRQ2_REG_L2P_VALIDATE_VFID \ |
64 | 0x240c50UL |
65 | #define PGLUE_B_REG_USE_CLIENTID_IN_TAG \ |
66 | 0x2aae04UL |
67 | #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER \ |
68 | 0x2aa16cUL |
69 | #define PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR \ |
70 | 0x2aa118UL |
71 | #define PSWHST_REG_ZONE_PERMISSION_TABLE \ |
72 | 0x2a0800UL |
73 | #define BAR0_MAP_REG_MSDM_RAM \ |
74 | 0x1d00000UL |
75 | #define BAR0_MAP_REG_USDM_RAM \ |
76 | 0x1d80000UL |
77 | #define BAR0_MAP_REG_PSDM_RAM \ |
78 | 0x1f00000UL |
79 | #define BAR0_MAP_REG_TSDM_RAM \ |
80 | 0x1c80000UL |
81 | #define BAR0_MAP_REG_XSDM_RAM \ |
82 | 0x1e00000UL |
83 | #define BAR0_MAP_REG_YSDM_RAM \ |
84 | 0x1e80000UL |
85 | #define NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF \ |
86 | 0x5011f4UL |
87 | #define PRS_REG_SEARCH_RESP_INITIATOR_TYPE \ |
88 | 0x1f0164UL |
89 | #define PRS_REG_SEARCH_TCP \ |
90 | 0x1f0400UL |
91 | #define PRS_REG_SEARCH_UDP \ |
92 | 0x1f0404UL |
93 | #define PRS_REG_SEARCH_FCOE \ |
94 | 0x1f0408UL |
95 | #define PRS_REG_SEARCH_ROCE \ |
96 | 0x1f040cUL |
97 | #define PRS_REG_SEARCH_OPENFLOW \ |
98 | 0x1f0434UL |
99 | #define PRS_REG_SEARCH_TAG1 \ |
100 | 0x1f0444UL |
101 | #define PRS_REG_SEARCH_TENANT_ID \ |
102 | 0x1f044cUL |
103 | #define PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST \ |
104 | 0x1f0a0cUL |
105 | #define PRS_REG_SEARCH_TCP_FIRST_FRAG \ |
106 | 0x1f0410UL |
107 | #define TM_REG_PF_ENABLE_CONN \ |
108 | 0x2c043cUL |
109 | #define TM_REG_PF_ENABLE_TASK \ |
110 | 0x2c0444UL |
111 | #define TM_REG_PF_SCAN_ACTIVE_CONN \ |
112 | 0x2c04fcUL |
113 | #define TM_REG_PF_SCAN_ACTIVE_TASK \ |
114 | 0x2c0500UL |
115 | #define IGU_REG_LEADING_EDGE_LATCH \ |
116 | 0x18082cUL |
117 | #define IGU_REG_TRAILING_EDGE_LATCH \ |
118 | 0x180830UL |
119 | #define QM_REG_USG_CNT_PF_TX \ |
120 | 0x2f2eacUL |
121 | #define QM_REG_USG_CNT_PF_OTHER \ |
122 | 0x2f2eb0UL |
123 | #define DORQ_REG_PF_DB_ENABLE \ |
124 | 0x100508UL |
125 | #define DORQ_REG_VF_USAGE_CNT \ |
126 | 0x1009c4UL |
127 | #define QM_REG_PF_EN \ |
128 | 0x2f2ea4UL |
129 | #define QM_REG_RLGLBLUPPERBOUND \ |
130 | 0x2f3c00UL |
131 | #define TCFC_REG_WEAK_ENABLE_VF \ |
132 | 0x2d0704UL |
133 | #define TCFC_REG_STRONG_ENABLE_PF \ |
134 | 0x2d0708UL |
135 | #define TCFC_REG_STRONG_ENABLE_VF \ |
136 | 0x2d070cUL |
137 | #define CCFC_REG_WEAK_ENABLE_VF \ |
138 | 0x2e0704UL |
139 | #define CCFC_REG_STRONG_ENABLE_PF \ |
140 | 0x2e0708UL |
141 | #define PGLUE_B_REG_PGL_ADDR_88_F0_BB \ |
142 | 0x2aa404UL |
143 | #define PGLUE_B_REG_PGL_ADDR_8C_F0_BB \ |
144 | 0x2aa408UL |
145 | #define PGLUE_B_REG_PGL_ADDR_90_F0_BB \ |
146 | 0x2aa40cUL |
147 | #define PGLUE_B_REG_PGL_ADDR_94_F0_BB \ |
148 | 0x2aa410UL |
149 | #define PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR \ |
150 | 0x2aa138UL |
151 | #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ \ |
152 | 0x2aa174UL |
153 | #define MISC_REG_GEN_PURP_CR0 \ |
154 | 0x008c80UL |
155 | #define MCP_REG_SCRATCH \ |
156 | 0xe20000UL |
157 | #define MCP_REG_SCRATCH_SIZE \ |
158 | 57344 |
159 | #define CNIG_REG_NW_PORT_MODE_BB \ |
160 | 0x218200UL |
161 | #define MISCS_REG_CHIP_NUM \ |
162 | 0x00976cUL |
163 | #define MISCS_REG_CHIP_REV \ |
164 | 0x009770UL |
165 | #define MISCS_REG_CMT_ENABLED_FOR_PAIR \ |
166 | 0x00971cUL |
167 | #define MISCS_REG_CHIP_TEST_REG \ |
168 | 0x009778UL |
169 | #define MISCS_REG_CHIP_METAL \ |
170 | 0x009774UL |
171 | #define MISCS_REG_FUNCTION_HIDE \ |
172 | 0x0096f0UL |
173 | #define \ |
174 | 0x340804UL |
175 | #define \ |
176 | 0xdb0804UL |
177 | #define CAU_REG_LONG_TIMEOUT_THRESHOLD \ |
178 | 0x1c0708UL |
179 | #define CCFC_REG_ACTIVITY_COUNTER \ |
180 | 0x2e8800UL |
181 | #define CCFC_REG_STRONG_ENABLE_VF \ |
182 | 0x2e070cUL |
183 | #define CDU_REG_CCFC_CTX_VALID0 \ |
184 | 0x580400UL |
185 | #define CDU_REG_CCFC_CTX_VALID1 \ |
186 | 0x580404UL |
187 | #define CDU_REG_TCFC_CTX_VALID0 \ |
188 | 0x580408UL |
189 | #define CDU_REG_CID_ADDR_PARAMS \ |
190 | 0x580900UL |
191 | #define DBG_REG_CLIENT_ENABLE \ |
192 | 0x010004UL |
193 | #define DBG_REG_TIMESTAMP_VALID_EN \ |
194 | 0x010b58UL |
195 | #define DMAE_REG_INIT \ |
196 | 0x00c000UL |
197 | #define DORQ_REG_IFEN \ |
198 | 0x100040UL |
199 | #define DORQ_REG_TAG1_OVRD_MODE \ |
200 | 0x1008b4UL |
201 | #define DORQ_REG_PF_PCP_BB_K2 \ |
202 | 0x1008c4UL |
203 | #define DORQ_REG_PF_EXT_VID_BB_K2 \ |
204 | 0x1008c8UL |
205 | #define DORQ_REG_DB_DROP_REASON \ |
206 | 0x100a2cUL |
207 | #define DORQ_REG_DB_DROP_DETAILS \ |
208 | 0x100a24UL |
209 | #define DORQ_REG_DB_DROP_DETAILS_ADDRESS \ |
210 | 0x100a1cUL |
211 | #define GRC_REG_TIMEOUT_EN \ |
212 | 0x050404UL |
213 | #define GRC_REG_TIMEOUT_ATTN_ACCESS_VALID \ |
214 | 0x050054UL |
215 | #define GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_0 \ |
216 | 0x05004cUL |
217 | #define GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_1 \ |
218 | 0x050050UL |
219 | #define IGU_REG_BLOCK_CONFIGURATION \ |
220 | 0x180040UL |
221 | #define MCM_REG_INIT \ |
222 | 0x1200000UL |
223 | #define MCP2_REG_DBG_DWORD_ENABLE \ |
224 | 0x052404UL |
225 | #define MISC_REG_PORT_MODE \ |
226 | 0x008c00UL |
227 | #define MISCS_REG_CLK_100G_MODE \ |
228 | 0x009070UL |
229 | #define MSDM_REG_ENABLE_IN1 \ |
230 | 0xfc0004UL |
231 | #define MSEM_REG_ENABLE_IN \ |
232 | 0x1800004UL |
233 | #define NIG_REG_CM_HDR \ |
234 | 0x500840UL |
235 | #define NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR \ |
236 | 0x50196cUL |
237 | #define NIG_REG_LLH_PPFID2PFID_TBL_0 \ |
238 | 0x501970UL |
239 | #define NIG_REG_LLH_ENG_CLS_ROCE_QP_SEL \ |
240 | 0x50 |
241 | #define NIG_REG_LLH_CLS_TYPE_DUALMODE \ |
242 | 0x501964UL |
243 | #define NIG_REG_LLH_FUNC_TAG_EN 0x5019b0UL |
244 | #define NIG_REG_LLH_FUNC_TAG_VALUE 0x5019d0UL |
245 | #define NIG_REG_LLH_FUNC_FILTER_VALUE \ |
246 | 0x501a00UL |
247 | #define NIG_REG_LLH_FUNC_FILTER_VALUE_SIZE \ |
248 | 32 |
249 | #define NIG_REG_LLH_FUNC_FILTER_EN \ |
250 | 0x501a80UL |
251 | #define NIG_REG_LLH_FUNC_FILTER_EN_SIZE \ |
252 | 16 |
253 | #define NIG_REG_LLH_FUNC_FILTER_MODE \ |
254 | 0x501ac0UL |
255 | #define NIG_REG_LLH_FUNC_FILTER_MODE_SIZE \ |
256 | 16 |
257 | #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE \ |
258 | 0x501b00UL |
259 | #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_SIZE \ |
260 | 16 |
261 | #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL \ |
262 | 0x501b40UL |
263 | #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_SIZE \ |
264 | 16 |
265 | #define NCSI_REG_CONFIG \ |
266 | 0x040200UL |
267 | #define PBF_REG_INIT \ |
268 | 0xd80000UL |
269 | #define PBF_REG_NUM_BLOCKS_ALLOCATED_PROD_VOQ0 \ |
270 | 0xd806c8UL |
271 | #define PBF_REG_NUM_BLOCKS_ALLOCATED_CONS_VOQ0 \ |
272 | 0xd806ccUL |
273 | #define PTU_REG_ATC_INIT_ARRAY \ |
274 | 0x560000UL |
275 | #define PCM_REG_INIT \ |
276 | 0x1100000UL |
277 | #define PGLUE_B_REG_ADMIN_PER_PF_REGION \ |
278 | 0x2a9000UL |
279 | #define PGLUE_B_REG_TX_ERR_WR_DETAILS2 \ |
280 | 0x2aa150UL |
281 | #define PGLUE_B_REG_TX_ERR_WR_ADD_31_0 \ |
282 | 0x2aa144UL |
283 | #define PGLUE_B_REG_TX_ERR_WR_ADD_63_32 \ |
284 | 0x2aa148UL |
285 | #define PGLUE_B_REG_TX_ERR_WR_DETAILS \ |
286 | 0x2aa14cUL |
287 | #define PGLUE_B_REG_TX_ERR_RD_ADD_31_0 \ |
288 | 0x2aa154UL |
289 | #define PGLUE_B_REG_TX_ERR_RD_ADD_63_32 \ |
290 | 0x2aa158UL |
291 | #define PGLUE_B_REG_TX_ERR_RD_DETAILS \ |
292 | 0x2aa15cUL |
293 | #define PGLUE_B_REG_TX_ERR_RD_DETAILS2 \ |
294 | 0x2aa160UL |
295 | #define PGLUE_B_REG_TX_ERR_WR_DETAILS_ICPL \ |
296 | 0x2aa164UL |
297 | #define PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS \ |
298 | 0x2aa54cUL |
299 | #define PGLUE_B_REG_MASTER_ZLR_ERR_ADD_31_0 \ |
300 | 0x2aa544UL |
301 | #define PGLUE_B_REG_MASTER_ZLR_ERR_ADD_63_32 \ |
302 | 0x2aa548UL |
303 | #define PGLUE_B_REG_VF_ILT_ERR_ADD_31_0 \ |
304 | 0x2aae74UL |
305 | #define PGLUE_B_REG_VF_ILT_ERR_ADD_63_32 \ |
306 | 0x2aae78UL |
307 | #define PGLUE_B_REG_VF_ILT_ERR_DETAILS \ |
308 | 0x2aae7cUL |
309 | #define PGLUE_B_REG_VF_ILT_ERR_DETAILS2 \ |
310 | 0x2aae80UL |
311 | #define PGLUE_B_REG_LATCHED_ERRORS_CLR \ |
312 | 0x2aa3bcUL |
313 | #define PRM_REG_DISABLE_PRM \ |
314 | 0x230000UL |
315 | #define PRS_REG_SOFT_RST \ |
316 | 0x1f0000UL |
317 | #define PRS_REG_MSG_INFO \ |
318 | 0x1f0a1cUL |
319 | #define PRS_REG_ROCE_DEST_QP_MAX_PF \ |
320 | 0x1f0430UL |
321 | #define PRS_REG_USE_LIGHT_L2 \ |
322 | 0x1f096cUL |
323 | #define PSDM_REG_ENABLE_IN1 \ |
324 | 0xfa0004UL |
325 | #define PSEM_REG_ENABLE_IN \ |
326 | 0x1600004UL |
327 | #define PSWRQ_REG_DBG_SELECT \ |
328 | 0x280020UL |
329 | #define PSWRQ2_REG_CDUT_P_SIZE \ |
330 | 0x24000cUL |
331 | #define PSWRQ2_REG_ILT_MEMORY \ |
332 | 0x260000UL |
333 | #define PSWRQ2_REG_ILT_MEMORY_SIZE_BB \ |
334 | 15200 |
335 | #define PSWRQ2_REG_ILT_MEMORY_SIZE_K2 \ |
336 | 22000 |
337 | #define PSWHST_REG_DISCARD_INTERNAL_WRITES \ |
338 | 0x2a0040UL |
339 | #define PSWHST2_REG_DBGSYN_ALMOST_FULL_THR \ |
340 | 0x29e050UL |
341 | #define PSWHST_REG_INCORRECT_ACCESS_VALID \ |
342 | 0x2a0070UL |
343 | #define PSWHST_REG_INCORRECT_ACCESS_ADDRESS \ |
344 | 0x2a0074UL |
345 | #define PSWHST_REG_INCORRECT_ACCESS_DATA \ |
346 | 0x2a0068UL |
347 | #define PSWHST_REG_INCORRECT_ACCESS_LENGTH \ |
348 | 0x2a006cUL |
349 | #define PSWRD_REG_DBG_SELECT \ |
350 | 0x29c040UL |
351 | #define PSWRD2_REG_CONF11 \ |
352 | 0x29d064UL |
353 | #define PSWWR_REG_USDM_FULL_TH \ |
354 | 0x29a040UL |
355 | #define PSWWR2_REG_CDU_FULL_TH2 \ |
356 | 0x29b040UL |
357 | #define QM_REG_MAXPQSIZE_0 \ |
358 | 0x2f0434UL |
359 | #define \ |
360 | 0x238804UL |
361 | #define RDIF_REG_STOP_ON_ERROR \ |
362 | 0x300040UL |
363 | #define RDIF_REG_DEBUG_ERROR_INFO \ |
364 | 0x300400UL |
365 | #define RDIF_REG_DEBUG_ERROR_INFO_SIZE \ |
366 | 64 |
367 | #define SRC_REG_SOFT_RST \ |
368 | 0x23874cUL |
369 | #define TCFC_REG_ACTIVITY_COUNTER \ |
370 | 0x2d8800UL |
371 | #define TCM_REG_INIT \ |
372 | 0x1180000UL |
373 | #define TM_REG_PXP_READ_DATA_FIFO_INIT \ |
374 | 0x2c0014UL |
375 | #define TSDM_REG_ENABLE_IN1 \ |
376 | 0xfb0004UL |
377 | #define TSEM_REG_ENABLE_IN \ |
378 | 0x1700004UL |
379 | #define TDIF_REG_STOP_ON_ERROR \ |
380 | 0x310040UL |
381 | #define TDIF_REG_DEBUG_ERROR_INFO \ |
382 | 0x310400UL |
383 | #define TDIF_REG_DEBUG_ERROR_INFO_SIZE \ |
384 | 64 |
385 | #define UCM_REG_INIT \ |
386 | 0x1280000UL |
387 | #define UMAC_REG_IPG_HD_BKP_CNTL_BB_B0 \ |
388 | 0x051004UL |
389 | #define USDM_REG_ENABLE_IN1 \ |
390 | 0xfd0004UL |
391 | #define USEM_REG_ENABLE_IN \ |
392 | 0x1900004UL |
393 | #define XCM_REG_INIT \ |
394 | 0x1000000UL |
395 | #define XSDM_REG_ENABLE_IN1 \ |
396 | 0xf80004UL |
397 | #define XSEM_REG_ENABLE_IN \ |
398 | 0x1400004UL |
399 | #define YCM_REG_INIT \ |
400 | 0x1080000UL |
401 | #define YSDM_REG_ENABLE_IN1 \ |
402 | 0xf90004UL |
403 | #define YSEM_REG_ENABLE_IN \ |
404 | 0x1500004UL |
405 | #define XYLD_REG_SCBD_STRICT_PRIO \ |
406 | 0x4c0000UL |
407 | #define TMLD_REG_SCBD_STRICT_PRIO \ |
408 | 0x4d0000UL |
409 | #define MULD_REG_SCBD_STRICT_PRIO \ |
410 | 0x4e0000UL |
411 | #define YULD_REG_SCBD_STRICT_PRIO \ |
412 | 0x4c8000UL |
413 | #define MISC_REG_SHARED_MEM_ADDR \ |
414 | 0x008c20UL |
415 | #define DMAE_REG_GO_C0 \ |
416 | 0x00c048UL |
417 | #define DMAE_REG_GO_C1 \ |
418 | 0x00c04cUL |
419 | #define DMAE_REG_GO_C2 \ |
420 | 0x00c050UL |
421 | #define DMAE_REG_GO_C3 \ |
422 | 0x00c054UL |
423 | #define DMAE_REG_GO_C4 \ |
424 | 0x00c058UL |
425 | #define DMAE_REG_GO_C5 \ |
426 | 0x00c05cUL |
427 | #define DMAE_REG_GO_C6 \ |
428 | 0x00c060UL |
429 | #define DMAE_REG_GO_C7 \ |
430 | 0x00c064UL |
431 | #define DMAE_REG_GO_C8 \ |
432 | 0x00c068UL |
433 | #define DMAE_REG_GO_C9 \ |
434 | 0x00c06cUL |
435 | #define DMAE_REG_GO_C10 \ |
436 | 0x00c070UL |
437 | #define DMAE_REG_GO_C11 \ |
438 | 0x00c074UL |
439 | #define DMAE_REG_GO_C12 \ |
440 | 0x00c078UL |
441 | #define DMAE_REG_GO_C13 \ |
442 | 0x00c07cUL |
443 | #define DMAE_REG_GO_C14 \ |
444 | 0x00c080UL |
445 | #define DMAE_REG_GO_C15 \ |
446 | 0x00c084UL |
447 | #define DMAE_REG_GO_C16 \ |
448 | 0x00c088UL |
449 | #define DMAE_REG_GO_C17 \ |
450 | 0x00c08cUL |
451 | #define DMAE_REG_GO_C18 \ |
452 | 0x00c090UL |
453 | #define DMAE_REG_GO_C19 \ |
454 | 0x00c094UL |
455 | #define DMAE_REG_GO_C20 \ |
456 | 0x00c098UL |
457 | #define DMAE_REG_GO_C21 \ |
458 | 0x00c09cUL |
459 | #define DMAE_REG_GO_C22 \ |
460 | 0x00c0a0UL |
461 | #define DMAE_REG_GO_C23 \ |
462 | 0x00c0a4UL |
463 | #define DMAE_REG_GO_C24 \ |
464 | 0x00c0a8UL |
465 | #define DMAE_REG_GO_C25 \ |
466 | 0x00c0acUL |
467 | #define DMAE_REG_GO_C26 \ |
468 | 0x00c0b0UL |
469 | #define DMAE_REG_GO_C27 \ |
470 | 0x00c0b4UL |
471 | #define DMAE_REG_GO_C28 \ |
472 | 0x00c0b8UL |
473 | #define DMAE_REG_GO_C29 \ |
474 | 0x00c0bcUL |
475 | #define DMAE_REG_GO_C30 \ |
476 | 0x00c0c0UL |
477 | #define DMAE_REG_GO_C31 \ |
478 | 0x00c0c4UL |
479 | #define DMAE_REG_CMD_MEM \ |
480 | 0x00c800UL |
481 | #define QM_REG_MAXPQSIZETXSEL_0 \ |
482 | 0x2f0440UL |
483 | #define QM_REG_SDMCMDREADY \ |
484 | 0x2f1e10UL |
485 | #define QM_REG_SDMCMDADDR \ |
486 | 0x2f1e04UL |
487 | #define QM_REG_SDMCMDDATALSB \ |
488 | 0x2f1e08UL |
489 | #define QM_REG_SDMCMDDATAMSB \ |
490 | 0x2f1e0cUL |
491 | #define QM_REG_SDMCMDGO \ |
492 | 0x2f1e14UL |
493 | #define QM_REG_RLPFCRD \ |
494 | 0x2f4d80UL |
495 | #define QM_REG_RLPFINCVAL \ |
496 | 0x2f4c80UL |
497 | #define QM_REG_RLGLBLCRD \ |
498 | 0x2f4400UL |
499 | #define QM_REG_RLGLBLINCVAL \ |
500 | 0x2f3400UL |
501 | #define IGU_REG_ATTENTION_ENABLE \ |
502 | 0x18083cUL |
503 | #define IGU_REG_ATTN_MSG_ADDR_L \ |
504 | 0x180820UL |
505 | #define IGU_REG_ATTN_MSG_ADDR_H \ |
506 | 0x180824UL |
507 | #define MISC_REG_AEU_GENERAL_ATTN_0 \ |
508 | 0x008400UL |
509 | #define MISC_REG_AEU_GENERAL_ATTN_32 \ |
510 | 0x008480UL |
511 | #define MISC_REG_AEU_GENERAL_ATTN_35 \ |
512 | 0x00848cUL |
513 | #define CAU_REG_SB_ADDR_MEMORY \ |
514 | 0x1c8000UL |
515 | #define CAU_REG_SB_VAR_MEMORY \ |
516 | 0x1c6000UL |
517 | #define CAU_REG_PI_MEMORY \ |
518 | 0x1d0000UL |
519 | #define IGU_REG_PF_CONFIGURATION \ |
520 | 0x180800UL |
521 | #define IGU_REG_VF_CONFIGURATION \ |
522 | 0x180804UL |
523 | #define MISC_REG_AEU_ENABLE1_IGU_OUT_0 \ |
524 | 0x00849cUL |
525 | #define MISC_REG_AEU_ENABLE4_IGU_OUT_0 \ |
526 | 0x0084a8UL |
527 | #define MISC_REG_AEU_ENABLE4_IGU_OUT_0_GENERAL_ATTN32 \ |
528 | (0x1UL << 0) |
529 | #define MISC_REG_AEU_ENABLE4_IGU_OUT_0_GENERAL_ATTN32_SHIFT \ |
530 | 0 |
531 | #define MISC_REG_AEU_AFTER_INVERT_1_IGU \ |
532 | 0x0087b4UL |
533 | #define MISC_REG_AEU_MASK_ATTN_IGU \ |
534 | 0x008494UL |
535 | #define IGU_REG_CLEANUP_STATUS_0 \ |
536 | 0x180980UL |
537 | #define IGU_REG_CLEANUP_STATUS_1 \ |
538 | 0x180a00UL |
539 | #define IGU_REG_CLEANUP_STATUS_2 \ |
540 | 0x180a80UL |
541 | #define IGU_REG_CLEANUP_STATUS_3 \ |
542 | 0x180b00UL |
543 | #define IGU_REG_CLEANUP_STATUS_4 \ |
544 | 0x180b80UL |
545 | #define IGU_REG_COMMAND_REG_32LSB_DATA \ |
546 | 0x180840UL |
547 | #define IGU_REG_COMMAND_REG_CTRL \ |
548 | 0x180848UL |
549 | #define IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN ( \ |
550 | 0x1 << 1) |
551 | #define IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN ( \ |
552 | 0x1 << 0) |
553 | #define IGU_REG_PRODUCER_MEMORY 0x182000UL |
554 | #define IGU_REG_CONSUMER_MEM 0x183000UL |
555 | #define IGU_REG_MAPPING_MEMORY \ |
556 | 0x184000UL |
557 | #define IGU_REG_STATISTIC_NUM_VF_MSG_SENT \ |
558 | 0x180408UL |
559 | #define IGU_REG_WRITE_DONE_PENDING \ |
560 | 0x180900UL |
561 | #define MISCS_REG_GENERIC_POR_0 \ |
562 | 0x0096d4UL |
563 | #define MCP_REG_NVM_CFG4 \ |
564 | 0xe0642cUL |
565 | #define MCP_REG_NVM_CFG4_FLASH_SIZE ( \ |
566 | 0x7 << 0) |
567 | #define MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT \ |
568 | 0 |
569 | #define MCP_REG_CPU_STATE \ |
570 | 0xe05004UL |
571 | #define MCP_REG_CPU_STATE_SOFT_HALTED (0x1UL << 10) |
572 | #define MCP_REG_CPU_EVENT_MASK \ |
573 | 0xe05008UL |
574 | #define MCP_REG_CPU_PROGRAM_COUNTER 0xe0501cUL |
575 | #define PGLUE_B_REG_PF_BAR0_SIZE \ |
576 | 0x2aae60UL |
577 | #define PGLUE_B_REG_PF_BAR1_SIZE \ |
578 | 0x2aae64UL |
579 | #define PGLUE_B_REG_VF_BAR1_SIZE 0x2aae68UL |
580 | #define PRS_REG_ENCAPSULATION_TYPE_EN 0x1f0730UL |
581 | #define PRS_REG_GRE_PROTOCOL 0x1f0734UL |
582 | #define PRS_REG_VXLAN_PORT 0x1f0738UL |
583 | #define PRS_REG_OUTPUT_FORMAT_4_0 0x1f099cUL |
584 | #define NIG_REG_ENC_TYPE_ENABLE 0x501058UL |
585 | |
586 | #define NIG_REG_ENC_TYPE_ENABLE_ETH_OVER_GRE_ENABLE (0x1 << 0) |
587 | #define NIG_REG_ENC_TYPE_ENABLE_ETH_OVER_GRE_ENABLE_SHIFT 0 |
588 | #define NIG_REG_ENC_TYPE_ENABLE_IP_OVER_GRE_ENABLE (0x1 << 1) |
589 | #define NIG_REG_ENC_TYPE_ENABLE_IP_OVER_GRE_ENABLE_SHIFT 1 |
590 | #define NIG_REG_ENC_TYPE_ENABLE_VXLAN_ENABLE (0x1 << 2) |
591 | #define NIG_REG_ENC_TYPE_ENABLE_VXLAN_ENABLE_SHIFT 2 |
592 | |
593 | #define NIG_REG_VXLAN_CTRL 0x50105cUL |
594 | #define PBF_REG_VXLAN_PORT 0xd80518UL |
595 | #define PBF_REG_NGE_PORT 0xd8051cUL |
596 | #define PRS_REG_NGE_PORT 0x1f086cUL |
597 | #define NIG_REG_NGE_PORT 0x508b38UL |
598 | |
599 | #define DORQ_REG_L2_EDPM_TUNNEL_GRE_ETH_EN 0x10090cUL |
600 | #define DORQ_REG_L2_EDPM_TUNNEL_GRE_IP_EN 0x100910UL |
601 | #define DORQ_REG_L2_EDPM_TUNNEL_VXLAN_EN 0x100914UL |
602 | #define DORQ_REG_L2_EDPM_TUNNEL_NGE_IP_EN_K2 0x10092cUL |
603 | #define DORQ_REG_L2_EDPM_TUNNEL_NGE_ETH_EN_K2 0x100930UL |
604 | |
605 | #define NIG_REG_NGE_IP_ENABLE 0x508b28UL |
606 | #define NIG_REG_NGE_ETH_ENABLE 0x508b2cUL |
607 | #define NIG_REG_NGE_COMP_VER 0x508b30UL |
608 | #define PBF_REG_NGE_COMP_VER 0xd80524UL |
609 | #define PRS_REG_NGE_COMP_VER 0x1f0878UL |
610 | |
611 | #define QM_REG_WFQPFWEIGHT 0x2f4e80UL |
612 | #define QM_REG_WFQVPWEIGHT 0x2fa000UL |
613 | #define QM_REG_WFQVPUPPERBOUND \ |
614 | 0x2fb000UL |
615 | #define QM_REG_WFQVPCRD \ |
616 | 0x2fc000UL |
617 | #define PGLCS_REG_DBG_SELECT_K2_E5 \ |
618 | 0x001d14UL |
619 | #define PGLCS_REG_DBG_DWORD_ENABLE_K2_E5 \ |
620 | 0x001d18UL |
621 | #define PGLCS_REG_DBG_SHIFT_K2_E5 \ |
622 | 0x001d1cUL |
623 | #define PGLCS_REG_DBG_FORCE_VALID_K2_E5 \ |
624 | 0x001d20UL |
625 | #define PGLCS_REG_DBG_FORCE_FRAME_K2_E5 \ |
626 | 0x001d24UL |
627 | #define MISC_REG_RESET_PL_PDA_VMAIN_1 \ |
628 | 0x008070UL |
629 | #define MISC_REG_RESET_PL_PDA_VMAIN_2 \ |
630 | 0x008080UL |
631 | #define MISC_REG_RESET_PL_PDA_VAUX \ |
632 | 0x008090UL |
633 | #define MISCS_REG_RESET_PL_UA \ |
634 | 0x009050UL |
635 | #define MISCS_REG_RESET_PL_HV \ |
636 | 0x009060UL |
637 | #define MISCS_REG_RESET_PL_HV_2_K2_E5 \ |
638 | 0x009150UL |
639 | #define DMAE_REG_DBG_SELECT \ |
640 | 0x00c510UL |
641 | #define DMAE_REG_DBG_DWORD_ENABLE \ |
642 | 0x00c514UL |
643 | #define DMAE_REG_DBG_SHIFT \ |
644 | 0x00c518UL |
645 | #define DMAE_REG_DBG_FORCE_VALID \ |
646 | 0x00c51cUL |
647 | #define DMAE_REG_DBG_FORCE_FRAME \ |
648 | 0x00c520UL |
649 | #define NCSI_REG_DBG_SELECT \ |
650 | 0x040474UL |
651 | #define NCSI_REG_DBG_DWORD_ENABLE \ |
652 | 0x040478UL |
653 | #define NCSI_REG_DBG_SHIFT \ |
654 | 0x04047cUL |
655 | #define NCSI_REG_DBG_FORCE_VALID \ |
656 | 0x040480UL |
657 | #define NCSI_REG_DBG_FORCE_FRAME \ |
658 | 0x040484UL |
659 | #define GRC_REG_DBG_SELECT \ |
660 | 0x0500a4UL |
661 | #define GRC_REG_DBG_DWORD_ENABLE \ |
662 | 0x0500a8UL |
663 | #define GRC_REG_DBG_SHIFT \ |
664 | 0x0500acUL |
665 | #define GRC_REG_DBG_FORCE_VALID \ |
666 | 0x0500b0UL |
667 | #define GRC_REG_DBG_FORCE_FRAME \ |
668 | 0x0500b4UL |
669 | #define UMAC_REG_DBG_SELECT_K2_E5 \ |
670 | 0x051094UL |
671 | #define UMAC_REG_DBG_DWORD_ENABLE_K2_E5 \ |
672 | 0x051098UL |
673 | #define UMAC_REG_DBG_SHIFT_K2_E5 \ |
674 | 0x05109cUL |
675 | #define UMAC_REG_DBG_FORCE_VALID_K2_E5 \ |
676 | 0x0510a0UL |
677 | #define UMAC_REG_DBG_FORCE_FRAME_K2_E5 \ |
678 | 0x0510a4UL |
679 | #define MCP2_REG_DBG_SELECT \ |
680 | 0x052400UL |
681 | #define MCP2_REG_DBG_DWORD_ENABLE \ |
682 | 0x052404UL |
683 | #define MCP2_REG_DBG_SHIFT \ |
684 | 0x052408UL |
685 | #define MCP2_REG_DBG_FORCE_VALID \ |
686 | 0x052440UL |
687 | #define MCP2_REG_DBG_FORCE_FRAME \ |
688 | 0x052444UL |
689 | #define PCIE_REG_DBG_SELECT \ |
690 | 0x0547e8UL |
691 | #define PCIE_REG_DBG_DWORD_ENABLE \ |
692 | 0x0547ecUL |
693 | #define PCIE_REG_DBG_SHIFT \ |
694 | 0x0547f0UL |
695 | #define PCIE_REG_DBG_FORCE_VALID \ |
696 | 0x0547f4UL |
697 | #define PCIE_REG_DBG_FORCE_FRAME \ |
698 | 0x0547f8UL |
699 | #define DORQ_REG_DBG_SELECT \ |
700 | 0x100ad0UL |
701 | #define DORQ_REG_DBG_DWORD_ENABLE \ |
702 | 0x100ad4UL |
703 | #define DORQ_REG_DBG_SHIFT \ |
704 | 0x100ad8UL |
705 | #define DORQ_REG_DBG_FORCE_VALID \ |
706 | 0x100adcUL |
707 | #define DORQ_REG_DBG_FORCE_FRAME \ |
708 | 0x100ae0UL |
709 | #define IGU_REG_DBG_SELECT \ |
710 | 0x181578UL |
711 | #define IGU_REG_DBG_DWORD_ENABLE \ |
712 | 0x18157cUL |
713 | #define IGU_REG_DBG_SHIFT \ |
714 | 0x181580UL |
715 | #define IGU_REG_DBG_FORCE_VALID \ |
716 | 0x181584UL |
717 | #define IGU_REG_DBG_FORCE_FRAME \ |
718 | 0x181588UL |
719 | #define CAU_REG_DBG_SELECT \ |
720 | 0x1c0ea8UL |
721 | #define CAU_REG_DBG_DWORD_ENABLE \ |
722 | 0x1c0eacUL |
723 | #define CAU_REG_DBG_SHIFT \ |
724 | 0x1c0eb0UL |
725 | #define CAU_REG_DBG_FORCE_VALID \ |
726 | 0x1c0eb4UL |
727 | #define CAU_REG_DBG_FORCE_FRAME \ |
728 | 0x1c0eb8UL |
729 | #define PRS_REG_DBG_SELECT \ |
730 | 0x1f0b6cUL |
731 | #define PRS_REG_DBG_DWORD_ENABLE \ |
732 | 0x1f0b70UL |
733 | #define PRS_REG_DBG_SHIFT \ |
734 | 0x1f0b74UL |
735 | #define PRS_REG_DBG_FORCE_VALID \ |
736 | 0x1f0ba0UL |
737 | #define PRS_REG_DBG_FORCE_FRAME \ |
738 | 0x1f0ba4UL |
739 | #define CNIG_REG_DBG_SELECT_K2_E5 \ |
740 | 0x218254UL |
741 | #define CNIG_REG_DBG_DWORD_ENABLE_K2_E5 \ |
742 | 0x218258UL |
743 | #define CNIG_REG_DBG_SHIFT_K2_E5 \ |
744 | 0x21825cUL |
745 | #define CNIG_REG_DBG_FORCE_VALID_K2_E5 \ |
746 | 0x218260UL |
747 | #define CNIG_REG_DBG_FORCE_FRAME_K2_E5 \ |
748 | 0x218264UL |
749 | #define PRM_REG_DBG_SELECT \ |
750 | 0x2306a8UL |
751 | #define PRM_REG_DBG_DWORD_ENABLE \ |
752 | 0x2306acUL |
753 | #define PRM_REG_DBG_SHIFT \ |
754 | 0x2306b0UL |
755 | #define PRM_REG_DBG_FORCE_VALID \ |
756 | 0x2306b4UL |
757 | #define PRM_REG_DBG_FORCE_FRAME \ |
758 | 0x2306b8UL |
759 | #define SRC_REG_DBG_SELECT \ |
760 | 0x238700UL |
761 | #define SRC_REG_DBG_DWORD_ENABLE \ |
762 | 0x238704UL |
763 | #define SRC_REG_DBG_SHIFT \ |
764 | 0x238708UL |
765 | #define SRC_REG_DBG_FORCE_VALID \ |
766 | 0x23870cUL |
767 | #define SRC_REG_DBG_FORCE_FRAME \ |
768 | 0x238710UL |
769 | #define \ |
770 | 0x238c4cUL |
771 | #define \ |
772 | 0x238c50UL |
773 | #define \ |
774 | 0x238c54UL |
775 | #define \ |
776 | 0x238c58UL |
777 | #define \ |
778 | 0x238c5cUL |
779 | #define RPB_REG_DBG_SELECT \ |
780 | 0x23c728UL |
781 | #define RPB_REG_DBG_DWORD_ENABLE \ |
782 | 0x23c72cUL |
783 | #define RPB_REG_DBG_SHIFT \ |
784 | 0x23c730UL |
785 | #define RPB_REG_DBG_FORCE_VALID \ |
786 | 0x23c734UL |
787 | #define RPB_REG_DBG_FORCE_FRAME \ |
788 | 0x23c738UL |
789 | #define PSWRQ2_REG_DBG_SELECT \ |
790 | 0x240100UL |
791 | #define PSWRQ2_REG_DBG_DWORD_ENABLE \ |
792 | 0x240104UL |
793 | #define PSWRQ2_REG_DBG_SHIFT \ |
794 | 0x240108UL |
795 | #define PSWRQ2_REG_DBG_FORCE_VALID \ |
796 | 0x24010cUL |
797 | #define PSWRQ2_REG_DBG_FORCE_FRAME \ |
798 | 0x240110UL |
799 | #define PSWRQ_REG_DBG_SELECT \ |
800 | 0x280020UL |
801 | #define PSWRQ_REG_DBG_DWORD_ENABLE \ |
802 | 0x280024UL |
803 | #define PSWRQ_REG_DBG_SHIFT \ |
804 | 0x280028UL |
805 | #define PSWRQ_REG_DBG_FORCE_VALID \ |
806 | 0x28002cUL |
807 | #define PSWRQ_REG_DBG_FORCE_FRAME \ |
808 | 0x280030UL |
809 | #define PSWWR_REG_DBG_SELECT \ |
810 | 0x29a084UL |
811 | #define PSWWR_REG_DBG_DWORD_ENABLE \ |
812 | 0x29a088UL |
813 | #define PSWWR_REG_DBG_SHIFT \ |
814 | 0x29a08cUL |
815 | #define PSWWR_REG_DBG_FORCE_VALID \ |
816 | 0x29a090UL |
817 | #define PSWWR_REG_DBG_FORCE_FRAME \ |
818 | 0x29a094UL |
819 | #define PSWRD_REG_DBG_SELECT \ |
820 | 0x29c040UL |
821 | #define PSWRD_REG_DBG_DWORD_ENABLE \ |
822 | 0x29c044UL |
823 | #define PSWRD_REG_DBG_SHIFT \ |
824 | 0x29c048UL |
825 | #define PSWRD_REG_DBG_FORCE_VALID \ |
826 | 0x29c04cUL |
827 | #define PSWRD_REG_DBG_FORCE_FRAME \ |
828 | 0x29c050UL |
829 | #define PSWRD2_REG_DBG_SELECT \ |
830 | 0x29d400UL |
831 | #define PSWRD2_REG_DBG_DWORD_ENABLE \ |
832 | 0x29d404UL |
833 | #define PSWRD2_REG_DBG_SHIFT \ |
834 | 0x29d408UL |
835 | #define PSWRD2_REG_DBG_FORCE_VALID \ |
836 | 0x29d40cUL |
837 | #define PSWRD2_REG_DBG_FORCE_FRAME \ |
838 | 0x29d410UL |
839 | #define PSWHST2_REG_DBG_SELECT \ |
840 | 0x29e058UL |
841 | #define PSWHST2_REG_DBG_DWORD_ENABLE \ |
842 | 0x29e05cUL |
843 | #define PSWHST2_REG_DBG_SHIFT \ |
844 | 0x29e060UL |
845 | #define PSWHST2_REG_DBG_FORCE_VALID \ |
846 | 0x29e064UL |
847 | #define PSWHST2_REG_DBG_FORCE_FRAME \ |
848 | 0x29e068UL |
849 | #define PSWHST_REG_DBG_SELECT \ |
850 | 0x2a0100UL |
851 | #define PSWHST_REG_DBG_DWORD_ENABLE \ |
852 | 0x2a0104UL |
853 | #define PSWHST_REG_DBG_SHIFT \ |
854 | 0x2a0108UL |
855 | #define PSWHST_REG_DBG_FORCE_VALID \ |
856 | 0x2a010cUL |
857 | #define PSWHST_REG_DBG_FORCE_FRAME \ |
858 | 0x2a0110UL |
859 | #define PGLUE_B_REG_DBG_SELECT \ |
860 | 0x2a8400UL |
861 | #define PGLUE_B_REG_DBG_DWORD_ENABLE \ |
862 | 0x2a8404UL |
863 | #define PGLUE_B_REG_DBG_SHIFT \ |
864 | 0x2a8408UL |
865 | #define PGLUE_B_REG_DBG_FORCE_VALID \ |
866 | 0x2a840cUL |
867 | #define PGLUE_B_REG_DBG_FORCE_FRAME \ |
868 | 0x2a8410UL |
869 | #define TM_REG_DBG_SELECT \ |
870 | 0x2c07a8UL |
871 | #define TM_REG_DBG_DWORD_ENABLE \ |
872 | 0x2c07acUL |
873 | #define TM_REG_DBG_SHIFT \ |
874 | 0x2c07b0UL |
875 | #define TM_REG_DBG_FORCE_VALID \ |
876 | 0x2c07b4UL |
877 | #define TM_REG_DBG_FORCE_FRAME \ |
878 | 0x2c07b8UL |
879 | #define TCFC_REG_DBG_SELECT \ |
880 | 0x2d0500UL |
881 | #define TCFC_REG_DBG_DWORD_ENABLE \ |
882 | 0x2d0504UL |
883 | #define TCFC_REG_DBG_SHIFT \ |
884 | 0x2d0508UL |
885 | #define TCFC_REG_DBG_FORCE_VALID \ |
886 | 0x2d050cUL |
887 | #define TCFC_REG_DBG_FORCE_FRAME \ |
888 | 0x2d0510UL |
889 | #define CCFC_REG_DBG_SELECT \ |
890 | 0x2e0500UL |
891 | #define CCFC_REG_DBG_DWORD_ENABLE \ |
892 | 0x2e0504UL |
893 | #define CCFC_REG_DBG_SHIFT \ |
894 | 0x2e0508UL |
895 | #define CCFC_REG_DBG_FORCE_VALID \ |
896 | 0x2e050cUL |
897 | #define CCFC_REG_DBG_FORCE_FRAME \ |
898 | 0x2e0510UL |
899 | #define QM_REG_DBG_SELECT \ |
900 | 0x2f2e74UL |
901 | #define QM_REG_DBG_DWORD_ENABLE \ |
902 | 0x2f2e78UL |
903 | #define QM_REG_DBG_SHIFT \ |
904 | 0x2f2e7cUL |
905 | #define QM_REG_DBG_FORCE_VALID \ |
906 | 0x2f2e80UL |
907 | #define QM_REG_DBG_FORCE_FRAME \ |
908 | 0x2f2e84UL |
909 | #define RDIF_REG_DBG_SELECT \ |
910 | 0x300500UL |
911 | #define RDIF_REG_DBG_DWORD_ENABLE \ |
912 | 0x300504UL |
913 | #define RDIF_REG_DBG_SHIFT \ |
914 | 0x300508UL |
915 | #define RDIF_REG_DBG_FORCE_VALID \ |
916 | 0x30050cUL |
917 | #define RDIF_REG_DBG_FORCE_FRAME \ |
918 | 0x300510UL |
919 | #define TDIF_REG_DBG_SELECT \ |
920 | 0x310500UL |
921 | #define TDIF_REG_DBG_DWORD_ENABLE \ |
922 | 0x310504UL |
923 | #define TDIF_REG_DBG_SHIFT \ |
924 | 0x310508UL |
925 | #define TDIF_REG_DBG_FORCE_VALID \ |
926 | 0x31050cUL |
927 | #define TDIF_REG_DBG_FORCE_FRAME \ |
928 | 0x310510UL |
929 | #define BRB_REG_DBG_SELECT \ |
930 | 0x340ed0UL |
931 | #define BRB_REG_DBG_DWORD_ENABLE \ |
932 | 0x340ed4UL |
933 | #define BRB_REG_DBG_SHIFT \ |
934 | 0x340ed8UL |
935 | #define BRB_REG_DBG_FORCE_VALID \ |
936 | 0x340edcUL |
937 | #define BRB_REG_DBG_FORCE_FRAME \ |
938 | 0x340ee0UL |
939 | #define XYLD_REG_DBG_SELECT \ |
940 | 0x4c1600UL |
941 | #define XYLD_REG_DBG_DWORD_ENABLE \ |
942 | 0x4c1604UL |
943 | #define XYLD_REG_DBG_SHIFT \ |
944 | 0x4c1608UL |
945 | #define XYLD_REG_DBG_FORCE_VALID \ |
946 | 0x4c160cUL |
947 | #define XYLD_REG_DBG_FORCE_FRAME \ |
948 | 0x4c1610UL |
949 | #define YULD_REG_DBG_SELECT_BB_K2 \ |
950 | 0x4c9600UL |
951 | #define YULD_REG_DBG_DWORD_ENABLE_BB_K2 \ |
952 | 0x4c9604UL |
953 | #define YULD_REG_DBG_SHIFT_BB_K2 \ |
954 | 0x4c9608UL |
955 | #define YULD_REG_DBG_FORCE_VALID_BB_K2 \ |
956 | 0x4c960cUL |
957 | #define YULD_REG_DBG_FORCE_FRAME_BB_K2 \ |
958 | 0x4c9610UL |
959 | #define TMLD_REG_DBG_SELECT \ |
960 | 0x4d1600UL |
961 | #define TMLD_REG_DBG_DWORD_ENABLE \ |
962 | 0x4d1604UL |
963 | #define TMLD_REG_DBG_SHIFT \ |
964 | 0x4d1608UL |
965 | #define TMLD_REG_DBG_FORCE_VALID \ |
966 | 0x4d160cUL |
967 | #define TMLD_REG_DBG_FORCE_FRAME \ |
968 | 0x4d1610UL |
969 | #define MULD_REG_DBG_SELECT \ |
970 | 0x4e1600UL |
971 | #define MULD_REG_DBG_DWORD_ENABLE \ |
972 | 0x4e1604UL |
973 | #define MULD_REG_DBG_SHIFT \ |
974 | 0x4e1608UL |
975 | #define MULD_REG_DBG_FORCE_VALID \ |
976 | 0x4e160cUL |
977 | #define MULD_REG_DBG_FORCE_FRAME \ |
978 | 0x4e1610UL |
979 | #define NIG_REG_DBG_SELECT \ |
980 | 0x502140UL |
981 | #define NIG_REG_DBG_DWORD_ENABLE \ |
982 | 0x502144UL |
983 | #define NIG_REG_DBG_SHIFT \ |
984 | 0x502148UL |
985 | #define NIG_REG_DBG_FORCE_VALID \ |
986 | 0x50214cUL |
987 | #define NIG_REG_DBG_FORCE_FRAME \ |
988 | 0x502150UL |
989 | #define BMB_REG_DBG_SELECT \ |
990 | 0x540a7cUL |
991 | #define BMB_REG_DBG_DWORD_ENABLE \ |
992 | 0x540a80UL |
993 | #define BMB_REG_DBG_SHIFT \ |
994 | 0x540a84UL |
995 | #define BMB_REG_DBG_FORCE_VALID \ |
996 | 0x540a88UL |
997 | #define BMB_REG_DBG_FORCE_FRAME \ |
998 | 0x540a8cUL |
999 | #define PTU_REG_DBG_SELECT \ |
1000 | 0x560100UL |
1001 | #define PTU_REG_DBG_DWORD_ENABLE \ |
1002 | 0x560104UL |
1003 | #define PTU_REG_DBG_SHIFT \ |
1004 | 0x560108UL |
1005 | #define PTU_REG_DBG_FORCE_VALID \ |
1006 | 0x56010cUL |
1007 | #define PTU_REG_DBG_FORCE_FRAME \ |
1008 | 0x560110UL |
1009 | #define CDU_REG_DBG_SELECT \ |
1010 | 0x580704UL |
1011 | #define CDU_REG_DBG_DWORD_ENABLE \ |
1012 | 0x580708UL |
1013 | #define CDU_REG_DBG_SHIFT \ |
1014 | 0x58070cUL |
1015 | #define CDU_REG_DBG_FORCE_VALID \ |
1016 | 0x580710UL |
1017 | #define CDU_REG_DBG_FORCE_FRAME \ |
1018 | 0x580714UL |
1019 | #define WOL_REG_DBG_SELECT_K2_E5 \ |
1020 | 0x600140UL |
1021 | #define WOL_REG_DBG_DWORD_ENABLE_K2_E5 \ |
1022 | 0x600144UL |
1023 | #define WOL_REG_DBG_SHIFT_K2_E5 \ |
1024 | 0x600148UL |
1025 | #define WOL_REG_DBG_FORCE_VALID_K2_E5 \ |
1026 | 0x60014cUL |
1027 | #define WOL_REG_DBG_FORCE_FRAME_K2_E5 \ |
1028 | 0x600150UL |
1029 | #define BMBN_REG_DBG_SELECT_K2_E5 \ |
1030 | 0x610140UL |
1031 | #define BMBN_REG_DBG_DWORD_ENABLE_K2_E5 \ |
1032 | 0x610144UL |
1033 | #define BMBN_REG_DBG_SHIFT_K2_E5 \ |
1034 | 0x610148UL |
1035 | #define BMBN_REG_DBG_FORCE_VALID_K2_E5 \ |
1036 | 0x61014cUL |
1037 | #define BMBN_REG_DBG_FORCE_FRAME_K2_E5 \ |
1038 | 0x610150UL |
1039 | #define NWM_REG_DBG_SELECT_K2_E5 \ |
1040 | 0x8000ecUL |
1041 | #define NWM_REG_DBG_DWORD_ENABLE_K2_E5 \ |
1042 | 0x8000f0UL |
1043 | #define NWM_REG_DBG_SHIFT_K2_E5 \ |
1044 | 0x8000f4UL |
1045 | #define NWM_REG_DBG_FORCE_VALID_K2_E5 \ |
1046 | 0x8000f8UL |
1047 | #define NWM_REG_DBG_FORCE_FRAME_K2_E5 \ |
1048 | 0x8000fcUL |
1049 | #define PBF_REG_DBG_SELECT \ |
1050 | 0xd80060UL |
1051 | #define PBF_REG_DBG_DWORD_ENABLE \ |
1052 | 0xd80064UL |
1053 | #define PBF_REG_DBG_SHIFT \ |
1054 | 0xd80068UL |
1055 | #define PBF_REG_DBG_FORCE_VALID \ |
1056 | 0xd8006cUL |
1057 | #define PBF_REG_DBG_FORCE_FRAME \ |
1058 | 0xd80070UL |
1059 | #define PBF_PB1_REG_DBG_SELECT \ |
1060 | 0xda0728UL |
1061 | #define PBF_PB1_REG_DBG_DWORD_ENABLE \ |
1062 | 0xda072cUL |
1063 | #define PBF_PB1_REG_DBG_SHIFT \ |
1064 | 0xda0730UL |
1065 | #define PBF_PB1_REG_DBG_FORCE_VALID \ |
1066 | 0xda0734UL |
1067 | #define PBF_PB1_REG_DBG_FORCE_FRAME \ |
1068 | 0xda0738UL |
1069 | #define PBF_PB2_REG_DBG_SELECT \ |
1070 | 0xda4728UL |
1071 | #define PBF_PB2_REG_DBG_DWORD_ENABLE \ |
1072 | 0xda472cUL |
1073 | #define PBF_PB2_REG_DBG_SHIFT \ |
1074 | 0xda4730UL |
1075 | #define PBF_PB2_REG_DBG_FORCE_VALID \ |
1076 | 0xda4734UL |
1077 | #define PBF_PB2_REG_DBG_FORCE_FRAME \ |
1078 | 0xda4738UL |
1079 | #define BTB_REG_DBG_SELECT \ |
1080 | 0xdb08c8UL |
1081 | #define BTB_REG_DBG_DWORD_ENABLE \ |
1082 | 0xdb08ccUL |
1083 | #define BTB_REG_DBG_SHIFT \ |
1084 | 0xdb08d0UL |
1085 | #define BTB_REG_DBG_FORCE_VALID \ |
1086 | 0xdb08d4UL |
1087 | #define BTB_REG_DBG_FORCE_FRAME \ |
1088 | 0xdb08d8UL |
1089 | #define XSDM_REG_DBG_SELECT \ |
1090 | 0xf80e28UL |
1091 | #define XSDM_REG_DBG_DWORD_ENABLE \ |
1092 | 0xf80e2cUL |
1093 | #define XSDM_REG_DBG_SHIFT \ |
1094 | 0xf80e30UL |
1095 | #define XSDM_REG_DBG_FORCE_VALID \ |
1096 | 0xf80e34UL |
1097 | #define XSDM_REG_DBG_FORCE_FRAME \ |
1098 | 0xf80e38UL |
1099 | #define YSDM_REG_DBG_SELECT \ |
1100 | 0xf90e28UL |
1101 | #define YSDM_REG_DBG_DWORD_ENABLE \ |
1102 | 0xf90e2cUL |
1103 | #define YSDM_REG_DBG_SHIFT \ |
1104 | 0xf90e30UL |
1105 | #define YSDM_REG_DBG_FORCE_VALID \ |
1106 | 0xf90e34UL |
1107 | #define YSDM_REG_DBG_FORCE_FRAME \ |
1108 | 0xf90e38UL |
1109 | #define PSDM_REG_DBG_SELECT \ |
1110 | 0xfa0e28UL |
1111 | #define PSDM_REG_DBG_DWORD_ENABLE \ |
1112 | 0xfa0e2cUL |
1113 | #define PSDM_REG_DBG_SHIFT \ |
1114 | 0xfa0e30UL |
1115 | #define PSDM_REG_DBG_FORCE_VALID \ |
1116 | 0xfa0e34UL |
1117 | #define PSDM_REG_DBG_FORCE_FRAME \ |
1118 | 0xfa0e38UL |
1119 | #define TSDM_REG_DBG_SELECT \ |
1120 | 0xfb0e28UL |
1121 | #define TSDM_REG_DBG_DWORD_ENABLE \ |
1122 | 0xfb0e2cUL |
1123 | #define TSDM_REG_DBG_SHIFT \ |
1124 | 0xfb0e30UL |
1125 | #define TSDM_REG_DBG_FORCE_VALID \ |
1126 | 0xfb0e34UL |
1127 | #define TSDM_REG_DBG_FORCE_FRAME \ |
1128 | 0xfb0e38UL |
1129 | #define MSDM_REG_DBG_SELECT \ |
1130 | 0xfc0e28UL |
1131 | #define MSDM_REG_DBG_DWORD_ENABLE \ |
1132 | 0xfc0e2cUL |
1133 | #define MSDM_REG_DBG_SHIFT \ |
1134 | 0xfc0e30UL |
1135 | #define MSDM_REG_DBG_FORCE_VALID \ |
1136 | 0xfc0e34UL |
1137 | #define MSDM_REG_DBG_FORCE_FRAME \ |
1138 | 0xfc0e38UL |
1139 | #define USDM_REG_DBG_SELECT \ |
1140 | 0xfd0e28UL |
1141 | #define USDM_REG_DBG_DWORD_ENABLE \ |
1142 | 0xfd0e2cUL |
1143 | #define USDM_REG_DBG_SHIFT \ |
1144 | 0xfd0e30UL |
1145 | #define USDM_REG_DBG_FORCE_VALID \ |
1146 | 0xfd0e34UL |
1147 | #define USDM_REG_DBG_FORCE_FRAME \ |
1148 | 0xfd0e38UL |
1149 | #define XCM_REG_DBG_SELECT \ |
1150 | 0x1000040UL |
1151 | #define XCM_REG_DBG_DWORD_ENABLE \ |
1152 | 0x1000044UL |
1153 | #define XCM_REG_DBG_SHIFT \ |
1154 | 0x1000048UL |
1155 | #define XCM_REG_DBG_FORCE_VALID \ |
1156 | 0x100004cUL |
1157 | #define XCM_REG_DBG_FORCE_FRAME \ |
1158 | 0x1000050UL |
1159 | #define YCM_REG_DBG_SELECT \ |
1160 | 0x1080040UL |
1161 | #define YCM_REG_DBG_DWORD_ENABLE \ |
1162 | 0x1080044UL |
1163 | #define YCM_REG_DBG_SHIFT \ |
1164 | 0x1080048UL |
1165 | #define YCM_REG_DBG_FORCE_VALID \ |
1166 | 0x108004cUL |
1167 | #define YCM_REG_DBG_FORCE_FRAME \ |
1168 | 0x1080050UL |
1169 | #define PCM_REG_DBG_SELECT \ |
1170 | 0x1100040UL |
1171 | #define PCM_REG_DBG_DWORD_ENABLE \ |
1172 | 0x1100044UL |
1173 | #define PCM_REG_DBG_SHIFT \ |
1174 | 0x1100048UL |
1175 | #define PCM_REG_DBG_FORCE_VALID \ |
1176 | 0x110004cUL |
1177 | #define PCM_REG_DBG_FORCE_FRAME \ |
1178 | 0x1100050UL |
1179 | #define TCM_REG_DBG_SELECT \ |
1180 | 0x1180040UL |
1181 | #define TCM_REG_DBG_DWORD_ENABLE \ |
1182 | 0x1180044UL |
1183 | #define TCM_REG_DBG_SHIFT \ |
1184 | 0x1180048UL |
1185 | #define TCM_REG_DBG_FORCE_VALID \ |
1186 | 0x118004cUL |
1187 | #define TCM_REG_DBG_FORCE_FRAME \ |
1188 | 0x1180050UL |
1189 | #define MCM_REG_DBG_SELECT \ |
1190 | 0x1200040UL |
1191 | #define MCM_REG_DBG_DWORD_ENABLE \ |
1192 | 0x1200044UL |
1193 | #define MCM_REG_DBG_SHIFT \ |
1194 | 0x1200048UL |
1195 | #define MCM_REG_DBG_FORCE_VALID \ |
1196 | 0x120004cUL |
1197 | #define MCM_REG_DBG_FORCE_FRAME \ |
1198 | 0x1200050UL |
1199 | #define UCM_REG_DBG_SELECT \ |
1200 | 0x1280050UL |
1201 | #define UCM_REG_DBG_DWORD_ENABLE \ |
1202 | 0x1280054UL |
1203 | #define UCM_REG_DBG_SHIFT \ |
1204 | 0x1280058UL |
1205 | #define UCM_REG_DBG_FORCE_VALID \ |
1206 | 0x128005cUL |
1207 | #define UCM_REG_DBG_FORCE_FRAME \ |
1208 | 0x1280060UL |
1209 | #define XSEM_REG_DBG_SELECT \ |
1210 | 0x1401528UL |
1211 | #define XSEM_REG_DBG_DWORD_ENABLE \ |
1212 | 0x140152cUL |
1213 | #define XSEM_REG_DBG_SHIFT \ |
1214 | 0x1401530UL |
1215 | #define XSEM_REG_DBG_FORCE_VALID \ |
1216 | 0x1401534UL |
1217 | #define XSEM_REG_DBG_FORCE_FRAME \ |
1218 | 0x1401538UL |
1219 | #define YSEM_REG_DBG_SELECT \ |
1220 | 0x1501528UL |
1221 | #define YSEM_REG_DBG_DWORD_ENABLE \ |
1222 | 0x150152cUL |
1223 | #define YSEM_REG_DBG_SHIFT \ |
1224 | 0x1501530UL |
1225 | #define YSEM_REG_DBG_FORCE_VALID \ |
1226 | 0x1501534UL |
1227 | #define YSEM_REG_DBG_FORCE_FRAME \ |
1228 | 0x1501538UL |
1229 | #define PSEM_REG_DBG_SELECT \ |
1230 | 0x1601528UL |
1231 | #define PSEM_REG_DBG_DWORD_ENABLE \ |
1232 | 0x160152cUL |
1233 | #define PSEM_REG_DBG_SHIFT \ |
1234 | 0x1601530UL |
1235 | #define PSEM_REG_DBG_FORCE_VALID \ |
1236 | 0x1601534UL |
1237 | #define PSEM_REG_DBG_FORCE_FRAME \ |
1238 | 0x1601538UL |
1239 | #define TSEM_REG_DBG_SELECT \ |
1240 | 0x1701528UL |
1241 | #define TSEM_REG_DBG_DWORD_ENABLE \ |
1242 | 0x170152cUL |
1243 | #define TSEM_REG_DBG_SHIFT \ |
1244 | 0x1701530UL |
1245 | #define TSEM_REG_DBG_FORCE_VALID \ |
1246 | 0x1701534UL |
1247 | #define TSEM_REG_DBG_FORCE_FRAME \ |
1248 | 0x1701538UL |
1249 | #define DORQ_REG_PF_USAGE_CNT \ |
1250 | 0x1009c0UL |
1251 | #define DORQ_REG_PF_OVFL_STICKY \ |
1252 | 0x1009d0UL |
1253 | #define DORQ_REG_DPM_FORCE_ABORT \ |
1254 | 0x1009d8UL |
1255 | #define DORQ_REG_INT_STS \ |
1256 | 0x100180UL |
1257 | #define DORQ_REG_INT_STS_ADDRESS_ERROR \ |
1258 | (0x1UL << 0) |
1259 | #define DORQ_REG_INT_STS_WR \ |
1260 | 0x100188UL |
1261 | #define DORQ_REG_DB_DROP_DETAILS_REL \ |
1262 | 0x100a28UL |
1263 | #define DORQ_REG_INT_STS_ADDRESS_ERROR_SHIFT \ |
1264 | 0 |
1265 | #define DORQ_REG_INT_STS_DB_DROP \ |
1266 | (0x1UL << 1) |
1267 | #define DORQ_REG_INT_STS_DB_DROP_SHIFT \ |
1268 | 1 |
1269 | #define DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR \ |
1270 | (0x1UL << 2) |
1271 | #define DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR_SHIFT \ |
1272 | 2 |
1273 | #define DORQ_REG_INT_STS_DORQ_FIFO_AFULL\ |
1274 | (0x1UL << 3) |
1275 | #define DORQ_REG_INT_STS_DORQ_FIFO_AFULL_SHIFT \ |
1276 | 3 |
1277 | #define DORQ_REG_INT_STS_CFC_BYP_VALIDATION_ERR \ |
1278 | (0x1UL << 4) |
1279 | #define DORQ_REG_INT_STS_CFC_BYP_VALIDATION_ERR_SHIFT \ |
1280 | 4 |
1281 | #define DORQ_REG_INT_STS_CFC_LD_RESP_ERR \ |
1282 | (0x1UL << 5) |
1283 | #define DORQ_REG_INT_STS_CFC_LD_RESP_ERR_SHIFT \ |
1284 | 5 |
1285 | #define DORQ_REG_INT_STS_XCM_DONE_CNT_ERR \ |
1286 | (0x1UL << 6) |
1287 | #define DORQ_REG_INT_STS_XCM_DONE_CNT_ERR_SHIFT \ |
1288 | 6 |
1289 | #define DORQ_REG_INT_STS_CFC_LD_REQ_FIFO_OVFL_ERR \ |
1290 | (0x1UL << 7) |
1291 | #define DORQ_REG_INT_STS_CFC_LD_REQ_FIFO_OVFL_ERR_SHIFT \ |
1292 | 7 |
1293 | #define DORQ_REG_INT_STS_CFC_LD_REQ_FIFO_UNDER_ERR \ |
1294 | (0x1UL << 8) |
1295 | #define DORQ_REG_INT_STS_CFC_LD_REQ_FIFO_UNDER_ERR_SHIFT \ |
1296 | 8 |
1297 | #define DORQ_REG_DB_DROP_DETAILS_REASON \ |
1298 | 0x100a20UL |
1299 | #define MSEM_REG_DBG_SELECT \ |
1300 | 0x1801528UL |
1301 | #define MSEM_REG_DBG_DWORD_ENABLE \ |
1302 | 0x180152cUL |
1303 | #define MSEM_REG_DBG_SHIFT \ |
1304 | 0x1801530UL |
1305 | #define MSEM_REG_DBG_FORCE_VALID \ |
1306 | 0x1801534UL |
1307 | #define MSEM_REG_DBG_FORCE_FRAME \ |
1308 | 0x1801538UL |
1309 | #define USEM_REG_DBG_SELECT \ |
1310 | 0x1901528UL |
1311 | #define USEM_REG_DBG_DWORD_ENABLE \ |
1312 | 0x190152cUL |
1313 | #define USEM_REG_DBG_SHIFT \ |
1314 | 0x1901530UL |
1315 | #define USEM_REG_DBG_FORCE_VALID \ |
1316 | 0x1901534UL |
1317 | #define USEM_REG_DBG_FORCE_FRAME \ |
1318 | 0x1901538UL |
1319 | #define NWS_REG_DBG_SELECT_K2_E5 \ |
1320 | 0x700128UL |
1321 | #define NWS_REG_DBG_DWORD_ENABLE_K2_E5 \ |
1322 | 0x70012cUL |
1323 | #define NWS_REG_DBG_SHIFT_K2_E5 \ |
1324 | 0x700130UL |
1325 | #define NWS_REG_DBG_FORCE_VALID_K2_E5 \ |
1326 | 0x700134UL |
1327 | #define NWS_REG_DBG_FORCE_FRAME_K2_E5 \ |
1328 | 0x700138UL |
1329 | #define MS_REG_DBG_SELECT_K2_E5 \ |
1330 | 0x6a0228UL |
1331 | #define MS_REG_DBG_DWORD_ENABLE_K2_E5 \ |
1332 | 0x6a022cUL |
1333 | #define MS_REG_DBG_SHIFT_K2_E5 \ |
1334 | 0x6a0230UL |
1335 | #define MS_REG_DBG_FORCE_VALID_K2_E5 \ |
1336 | 0x6a0234UL |
1337 | #define MS_REG_DBG_FORCE_FRAME_K2_E5 \ |
1338 | 0x6a0238UL |
1339 | #define PCIE_REG_DBG_COMMON_SELECT_K2_E5 \ |
1340 | 0x054398UL |
1341 | #define PCIE_REG_DBG_COMMON_DWORD_ENABLE_K2_E5 \ |
1342 | 0x05439cUL |
1343 | #define PCIE_REG_DBG_COMMON_SHIFT_K2_E5 \ |
1344 | 0x0543a0UL |
1345 | #define PCIE_REG_DBG_COMMON_FORCE_VALID_K2_E5 \ |
1346 | 0x0543a4UL |
1347 | #define PCIE_REG_DBG_COMMON_FORCE_FRAME_K2_E5 \ |
1348 | 0x0543a8UL |
1349 | #define PTLD_REG_DBG_SELECT_E5 \ |
1350 | 0x5a1600UL |
1351 | #define PTLD_REG_DBG_DWORD_ENABLE_E5 \ |
1352 | 0x5a1604UL |
1353 | #define PTLD_REG_DBG_SHIFT_E5 \ |
1354 | 0x5a1608UL |
1355 | #define PTLD_REG_DBG_FORCE_VALID_E5 \ |
1356 | 0x5a160cUL |
1357 | #define PTLD_REG_DBG_FORCE_FRAME_E5 \ |
1358 | 0x5a1610UL |
1359 | #define YPLD_REG_DBG_SELECT_E5 \ |
1360 | 0x5c1600UL |
1361 | #define YPLD_REG_DBG_DWORD_ENABLE_E5 \ |
1362 | 0x5c1604UL |
1363 | #define YPLD_REG_DBG_SHIFT_E5 \ |
1364 | 0x5c1608UL |
1365 | #define YPLD_REG_DBG_FORCE_VALID_E5 \ |
1366 | 0x5c160cUL |
1367 | #define YPLD_REG_DBG_FORCE_FRAME_E5 \ |
1368 | 0x5c1610UL |
1369 | #define RGSRC_REG_DBG_SELECT_E5 \ |
1370 | 0x320040UL |
1371 | #define RGSRC_REG_DBG_DWORD_ENABLE_E5 \ |
1372 | 0x320044UL |
1373 | #define RGSRC_REG_DBG_SHIFT_E5 \ |
1374 | 0x320048UL |
1375 | #define RGSRC_REG_DBG_FORCE_VALID_E5 \ |
1376 | 0x32004cUL |
1377 | #define RGSRC_REG_DBG_FORCE_FRAME_E5 \ |
1378 | 0x320050UL |
1379 | #define TGSRC_REG_DBG_SELECT_E5 \ |
1380 | 0x322040UL |
1381 | #define TGSRC_REG_DBG_DWORD_ENABLE_E5 \ |
1382 | 0x322044UL |
1383 | #define TGSRC_REG_DBG_SHIFT_E5 \ |
1384 | 0x322048UL |
1385 | #define TGSRC_REG_DBG_FORCE_VALID_E5 \ |
1386 | 0x32204cUL |
1387 | #define TGSRC_REG_DBG_FORCE_FRAME_E5 \ |
1388 | 0x322050UL |
1389 | #define MISC_REG_RESET_PL_UA \ |
1390 | 0x008050UL |
1391 | #define MISC_REG_RESET_PL_HV \ |
1392 | 0x008060UL |
1393 | #define XCM_REG_CTX_RBC_ACCS \ |
1394 | 0x1001800UL |
1395 | #define XCM_REG_AGG_CON_CTX \ |
1396 | 0x1001804UL |
1397 | #define XCM_REG_SM_CON_CTX \ |
1398 | 0x1001808UL |
1399 | #define YCM_REG_CTX_RBC_ACCS \ |
1400 | 0x1081800UL |
1401 | #define YCM_REG_AGG_CON_CTX \ |
1402 | 0x1081804UL |
1403 | #define YCM_REG_AGG_TASK_CTX \ |
1404 | 0x1081808UL |
1405 | #define YCM_REG_SM_CON_CTX \ |
1406 | 0x108180cUL |
1407 | #define YCM_REG_SM_TASK_CTX \ |
1408 | 0x1081810UL |
1409 | #define PCM_REG_CTX_RBC_ACCS \ |
1410 | 0x1101440UL |
1411 | #define PCM_REG_SM_CON_CTX \ |
1412 | 0x1101444UL |
1413 | #define TCM_REG_CTX_RBC_ACCS \ |
1414 | 0x11814c0UL |
1415 | #define TCM_REG_AGG_CON_CTX \ |
1416 | 0x11814c4UL |
1417 | #define TCM_REG_AGG_TASK_CTX \ |
1418 | 0x11814c8UL |
1419 | #define TCM_REG_SM_CON_CTX \ |
1420 | 0x11814ccUL |
1421 | #define TCM_REG_SM_TASK_CTX \ |
1422 | 0x11814d0UL |
1423 | #define MCM_REG_CTX_RBC_ACCS \ |
1424 | 0x1201800UL |
1425 | #define MCM_REG_AGG_CON_CTX \ |
1426 | 0x1201804UL |
1427 | #define MCM_REG_AGG_TASK_CTX \ |
1428 | 0x1201808UL |
1429 | #define MCM_REG_SM_CON_CTX \ |
1430 | 0x120180cUL |
1431 | #define MCM_REG_SM_TASK_CTX \ |
1432 | 0x1201810UL |
1433 | #define UCM_REG_CTX_RBC_ACCS \ |
1434 | 0x1281700UL |
1435 | #define UCM_REG_AGG_CON_CTX \ |
1436 | 0x1281704UL |
1437 | #define UCM_REG_AGG_TASK_CTX \ |
1438 | 0x1281708UL |
1439 | #define UCM_REG_SM_CON_CTX \ |
1440 | 0x128170cUL |
1441 | #define UCM_REG_SM_TASK_CTX \ |
1442 | 0x1281710UL |
1443 | #define XSEM_REG_SLOW_DBG_EMPTY_BB_K2 \ |
1444 | 0x1401140UL |
1445 | #define XSEM_REG_SYNC_DBG_EMPTY \ |
1446 | 0x1401160UL |
1447 | #define XSEM_REG_SLOW_DBG_ACTIVE \ |
1448 | 0x1401400UL |
1449 | #define XSEM_REG_SLOW_DBG_MODE \ |
1450 | 0x1401404UL |
1451 | #define XSEM_REG_DBG_FRAME_MODE \ |
1452 | 0x1401408UL |
1453 | #define XSEM_REG_DBG_GPRE_VECT \ |
1454 | 0x1401410UL |
1455 | #define XSEM_REG_DBG_MODE1_CFG \ |
1456 | 0x1401420UL |
1457 | #define XSEM_REG_FAST_MEMORY \ |
1458 | 0x1440000UL |
1459 | #define YSEM_REG_SYNC_DBG_EMPTY \ |
1460 | 0x1501160UL |
1461 | #define YSEM_REG_SLOW_DBG_ACTIVE \ |
1462 | 0x1501400UL |
1463 | #define YSEM_REG_SLOW_DBG_MODE \ |
1464 | 0x1501404UL |
1465 | #define YSEM_REG_DBG_FRAME_MODE \ |
1466 | 0x1501408UL |
1467 | #define YSEM_REG_DBG_GPRE_VECT \ |
1468 | 0x1501410UL |
1469 | #define YSEM_REG_DBG_MODE1_CFG \ |
1470 | 0x1501420UL |
1471 | #define YSEM_REG_FAST_MEMORY \ |
1472 | 0x1540000UL |
1473 | #define PSEM_REG_SLOW_DBG_EMPTY_BB_K2 \ |
1474 | 0x1601140UL |
1475 | #define PSEM_REG_SYNC_DBG_EMPTY \ |
1476 | 0x1601160UL |
1477 | #define PSEM_REG_SLOW_DBG_ACTIVE \ |
1478 | 0x1601400UL |
1479 | #define PSEM_REG_SLOW_DBG_MODE \ |
1480 | 0x1601404UL |
1481 | #define PSEM_REG_DBG_FRAME_MODE \ |
1482 | 0x1601408UL |
1483 | #define PSEM_REG_DBG_GPRE_VECT \ |
1484 | 0x1601410UL |
1485 | #define PSEM_REG_DBG_MODE1_CFG \ |
1486 | 0x1601420UL |
1487 | #define PSEM_REG_FAST_MEMORY \ |
1488 | 0x1640000UL |
1489 | #define TSEM_REG_SLOW_DBG_EMPTY_BB_K2 \ |
1490 | 0x1701140UL |
1491 | #define TSEM_REG_SYNC_DBG_EMPTY \ |
1492 | 0x1701160UL |
1493 | #define TSEM_REG_SLOW_DBG_ACTIVE \ |
1494 | 0x1701400UL |
1495 | #define TSEM_REG_SLOW_DBG_MODE \ |
1496 | 0x1701404UL |
1497 | #define TSEM_REG_DBG_FRAME_MODE \ |
1498 | 0x1701408UL |
1499 | #define TSEM_REG_DBG_GPRE_VECT \ |
1500 | 0x1701410UL |
1501 | #define TSEM_REG_DBG_MODE1_CFG \ |
1502 | 0x1701420UL |
1503 | #define TSEM_REG_FAST_MEMORY \ |
1504 | 0x1740000UL |
1505 | #define MSEM_REG_SLOW_DBG_EMPTY_BB_K2 \ |
1506 | 0x1801140UL |
1507 | #define MSEM_REG_SYNC_DBG_EMPTY \ |
1508 | 0x1801160UL |
1509 | #define MSEM_REG_SLOW_DBG_ACTIVE \ |
1510 | 0x1801400UL |
1511 | #define MSEM_REG_SLOW_DBG_MODE \ |
1512 | 0x1801404UL |
1513 | #define MSEM_REG_DBG_FRAME_MODE \ |
1514 | 0x1801408UL |
1515 | #define MSEM_REG_DBG_GPRE_VECT \ |
1516 | 0x1801410UL |
1517 | #define MSEM_REG_DBG_MODE1_CFG \ |
1518 | 0x1801420UL |
1519 | #define MSEM_REG_FAST_MEMORY \ |
1520 | 0x1840000UL |
1521 | #define USEM_REG_SLOW_DBG_EMPTY_BB_K2 \ |
1522 | 0x1901140UL |
1523 | #define SEM_FAST_REG_INT_RAM_SIZE \ |
1524 | 20480 |
1525 | #define USEM_REG_SYNC_DBG_EMPTY \ |
1526 | 0x1901160UL |
1527 | #define USEM_REG_SLOW_DBG_ACTIVE \ |
1528 | 0x1901400UL |
1529 | #define USEM_REG_SLOW_DBG_MODE \ |
1530 | 0x1901404UL |
1531 | #define USEM_REG_DBG_FRAME_MODE \ |
1532 | 0x1901408UL |
1533 | #define USEM_REG_DBG_GPRE_VECT \ |
1534 | 0x1901410UL |
1535 | #define USEM_REG_DBG_MODE1_CFG \ |
1536 | 0x1901420UL |
1537 | #define USEM_REG_FAST_MEMORY \ |
1538 | 0x1940000UL |
1539 | #define SEM_FAST_REG_DBG_MODE23_SRC_DISABLE \ |
1540 | 0x000748UL |
1541 | #define SEM_FAST_REG_DBG_MODSRC_DISABLE \ |
1542 | 0x00074cUL |
1543 | #define SEM_FAST_REG_DBG_MODE6_SRC_DISABLE \ |
1544 | 0x000750UL |
1545 | #define SEM_FAST_REG_DEBUG_ACTIVE \ |
1546 | 0x000740UL |
1547 | #define SEM_FAST_REG_INT_RAM \ |
1548 | 0x020000UL |
1549 | #define SEM_FAST_REG_INT_RAM_SIZE_BB_K2 \ |
1550 | 20480 |
1551 | #define SEM_FAST_REG_RECORD_FILTER_ENABLE \ |
1552 | 0x000768UL |
1553 | #define GRC_REG_TRACE_FIFO_VALID_DATA \ |
1554 | 0x050064UL |
1555 | #define GRC_REG_NUMBER_VALID_OVERRIDE_WINDOW \ |
1556 | 0x05040cUL |
1557 | #define GRC_REG_PROTECTION_OVERRIDE_WINDOW \ |
1558 | 0x050500UL |
1559 | #define IGU_REG_ERROR_HANDLING_MEMORY \ |
1560 | 0x181520UL |
1561 | #define MCP_REG_CPU_MODE \ |
1562 | 0xe05000UL |
1563 | #define MCP_REG_CPU_MODE_SOFT_HALT \ |
1564 | (0x1 << 10) |
1565 | #define BRB_REG_BIG_RAM_ADDRESS \ |
1566 | 0x340800UL |
1567 | #define BRB_REG_BIG_RAM_DATA \ |
1568 | 0x341500UL |
1569 | #define BRB_REG_BIG_RAM_DATA_SIZE \ |
1570 | 64 |
1571 | #define SEM_FAST_REG_STALL_0 \ |
1572 | 0x000488UL |
1573 | #define SEM_FAST_REG_STALLED \ |
1574 | 0x000494UL |
1575 | #define BTB_REG_BIG_RAM_ADDRESS \ |
1576 | 0xdb0800UL |
1577 | #define BTB_REG_BIG_RAM_DATA \ |
1578 | 0xdb0c00UL |
1579 | #define BMB_REG_BIG_RAM_ADDRESS \ |
1580 | 0x540800UL |
1581 | #define BMB_REG_BIG_RAM_DATA \ |
1582 | 0x540f00UL |
1583 | #define SEM_FAST_REG_STORM_REG_FILE \ |
1584 | 0x008000UL |
1585 | #define \ |
1586 | 0x238c30UL |
1587 | #define MISCS_REG_BLOCK_256B_EN \ |
1588 | 0x009074UL |
1589 | #define MCP_REG_SCRATCH_SIZE_BB_K2 \ |
1590 | 57344 |
1591 | #define MCP_REG_CPU_REG_FILE \ |
1592 | 0xe05200UL |
1593 | #define MCP_REG_CPU_REG_FILE_SIZE \ |
1594 | 32 |
1595 | #define DBG_REG_DEBUG_TARGET \ |
1596 | 0x01005cUL |
1597 | #define DBG_REG_FULL_MODE \ |
1598 | 0x010060UL |
1599 | #define DBG_REG_CALENDAR_OUT_DATA \ |
1600 | 0x010480UL |
1601 | #define GRC_REG_TRACE_FIFO \ |
1602 | 0x050068UL |
1603 | #define IGU_REG_ERROR_HANDLING_DATA_VALID \ |
1604 | 0x181530UL |
1605 | #define DBG_REG_DBG_BLOCK_ON \ |
1606 | 0x010454UL |
1607 | #define DBG_REG_FILTER_ENABLE \ |
1608 | 0x0109d0UL |
1609 | #define DBG_REG_FRAMING_MODE \ |
1610 | 0x010058UL |
1611 | #define DBG_REG_TRIGGER_ENABLE \ |
1612 | 0x01054cUL |
1613 | #define SEM_FAST_REG_VFC_DATA_WR \ |
1614 | 0x000b40UL |
1615 | #define SEM_FAST_REG_VFC_ADDR \ |
1616 | 0x000b44UL |
1617 | #define SEM_FAST_REG_VFC_DATA_RD \ |
1618 | 0x000b48UL |
1619 | #define SEM_FAST_REG_VFC_STATUS \ |
1620 | 0x000b4cUL |
1621 | #define \ |
1622 | 0x238c20UL |
1623 | #define \ |
1624 | 4 |
1625 | #define MISC_REG_BLOCK_256B_EN \ |
1626 | 0x008c14UL |
1627 | #define NWS_REG_NWS_CMU_K2 \ |
1628 | 0x720000UL |
1629 | #define PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_7_0_K2 \ |
1630 | 0x000680UL |
1631 | #define PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_15_8_K2 \ |
1632 | 0x000684UL |
1633 | #define PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_7_0_K2 \ |
1634 | 0x0006c0UL |
1635 | #define PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_11_8_K2 \ |
1636 | 0x0006c4UL |
1637 | #define MS_REG_MS_CMU_K2 \ |
1638 | 0x6a4000UL |
1639 | #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X130_K2 \ |
1640 | 0x000208UL |
1641 | #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X131_K2 \ |
1642 | 0x00020cUL |
1643 | #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X132_K2 \ |
1644 | 0x000210UL |
1645 | #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X133_K2 \ |
1646 | 0x000214UL |
1647 | #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X130_K2 \ |
1648 | 0x000208UL |
1649 | #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X131_K2 \ |
1650 | 0x00020cUL |
1651 | #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X132_K2 \ |
1652 | 0x000210UL |
1653 | #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X133_K2 \ |
1654 | 0x000214UL |
1655 | #define PHY_PCIE_REG_PHY0_K2 \ |
1656 | 0x620000UL |
1657 | #define PHY_PCIE_REG_PHY1_K2 \ |
1658 | 0x624000UL |
1659 | #define NIG_REG_ROCE_DUPLICATE_TO_HOST 0x5088f0UL |
1660 | #define NIG_REG_PPF_TO_ENGINE_SEL 0x508900UL |
1661 | #define NIG_REG_PPF_TO_ENGINE_SEL_SIZE 8 |
1662 | #define PRS_REG_LIGHT_L2_ETHERTYPE_EN 0x1f0968UL |
1663 | #define NIG_REG_LLH_ENG_CLS_ENG_ID_TBL 0x501b90UL |
1664 | #define DORQ_REG_PF_DPM_ENABLE 0x100510UL |
1665 | #define DORQ_REG_PF_ICID_BIT_SHIFT_NORM 0x100448UL |
1666 | #define DORQ_REG_PF_MIN_ADDR_REG1 0x100400UL |
1667 | #define DORQ_REG_PF_DPI_BIT_SHIFT 0x100450UL |
1668 | #define NIG_REG_RX_PTP_EN 0x501900UL |
1669 | #define NIG_REG_TX_PTP_EN 0x501904UL |
1670 | #define NIG_REG_LLH_PTP_TO_HOST 0x501908UL |
1671 | #define NIG_REG_LLH_PTP_TO_MCP 0x50190cUL |
1672 | #define NIG_REG_PTP_SW_TXTSEN 0x501910UL |
1673 | #define NIG_REG_LLH_PTP_ETHERTYPE_1 0x501914UL |
1674 | #define NIG_REG_LLH_PTP_MAC_DA_2_LSB 0x501918UL |
1675 | #define NIG_REG_LLH_PTP_MAC_DA_2_MSB 0x50191cUL |
1676 | #define NIG_REG_LLH_PTP_PARAM_MASK 0x501920UL |
1677 | #define NIG_REG_LLH_PTP_RULE_MASK 0x501924UL |
1678 | #define NIG_REG_TX_LLH_PTP_PARAM_MASK 0x501928UL |
1679 | #define NIG_REG_TX_LLH_PTP_RULE_MASK 0x50192cUL |
1680 | #define NIG_REG_LLH_PTP_HOST_BUF_SEQID 0x501930UL |
1681 | #define NIG_REG_LLH_PTP_HOST_BUF_TS_LSB 0x501934UL |
1682 | #define NIG_REG_LLH_PTP_HOST_BUF_TS_MSB 0x501938UL |
1683 | #define NIG_REG_LLH_PTP_MCP_BUF_SEQID 0x50193cUL |
1684 | #define NIG_REG_LLH_PTP_MCP_BUF_TS_LSB 0x501940UL |
1685 | #define NIG_REG_LLH_PTP_MCP_BUF_TS_MSB 0x501944UL |
1686 | #define NIG_REG_TX_LLH_PTP_BUF_SEQID 0x501948UL |
1687 | #define NIG_REG_TX_LLH_PTP_BUF_TS_LSB 0x50194cUL |
1688 | #define NIG_REG_TX_LLH_PTP_BUF_TS_MSB 0x501950UL |
1689 | #define NIG_REG_RX_PTP_TS_MSB_ERR 0x501954UL |
1690 | #define NIG_REG_TX_PTP_TS_MSB_ERR 0x501958UL |
1691 | #define NIG_REG_TSGEN_SYNC_TIME_LSB 0x5088c0UL |
1692 | #define NIG_REG_TSGEN_SYNC_TIME_MSB 0x5088c4UL |
1693 | #define NIG_REG_TSGEN_RST_DRIFT_CNTR 0x5088d8UL |
1694 | #define NIG_REG_TSGEN_DRIFT_CNTR_CONF 0x5088dcUL |
1695 | #define NIG_REG_TS_OUTPUT_ENABLE_PDA 0x508870UL |
1696 | #define NIG_REG_TIMESYNC_GEN_REG_BB 0x500d00UL |
1697 | #define NIG_REG_TSGEN_FREE_CNT_VALUE_LSB 0x5088a8UL |
1698 | #define NIG_REG_TSGEN_FREE_CNT_VALUE_MSB 0x5088acUL |
1699 | #define NIG_REG_PTP_LATCH_OSTS_PKT_TIME 0x509040UL |
1700 | #define PSWRQ2_REG_WR_MBS0 0x240400UL |
1701 | |
1702 | #define PGLUE_B_REG_PGL_ADDR_E8_F0_K2 0x2aaf98UL |
1703 | #define PGLUE_B_REG_PGL_ADDR_EC_F0_K2 0x2aaf9cUL |
1704 | #define PGLUE_B_REG_PGL_ADDR_F0_F0_K2 0x2aafa0UL |
1705 | #define PGLUE_B_REG_PGL_ADDR_F4_F0_K2 0x2aafa4UL |
1706 | #define PGLUE_B_REG_MASTER_WRITE_PAD_ENABLE 0x2aae30UL |
1707 | #define NIG_REG_TSGEN_FREECNT_UPDATE_K2 0x509008UL |
1708 | #define CNIG_REG_NIG_PORT0_CONF_K2 0x218200UL |
1709 | |
1710 | #define NIG_REG_TX_EDPM_CTRL 0x501f0cUL |
1711 | #define NIG_REG_TX_EDPM_CTRL_TX_EDPM_EN (0x1 << 0) |
1712 | #define NIG_REG_TX_EDPM_CTRL_TX_EDPM_EN_SHIFT 0 |
1713 | #define NIG_REG_TX_EDPM_CTRL_TX_EDPM_TC_EN (0xff << 1) |
1714 | #define NIG_REG_TX_EDPM_CTRL_TX_EDPM_TC_EN_SHIFT 1 |
1715 | |
1716 | #define PRS_REG_SEARCH_GFT 0x1f11bcUL |
1717 | #define PRS_REG_SEARCH_NON_IP_AS_GFT 0x1f11c0UL |
1718 | #define PRS_REG_CM_HDR_GFT 0x1f11c8UL |
1719 | #define PRS_REG_GFT_CAM 0x1f1100UL |
1720 | #define PRS_REG_GFT_PROFILE_MASK_RAM 0x1f1000UL |
1721 | #define PRS_REG_CM_HDR_GFT_EVENT_ID_SHIFT 0 |
1722 | #define PRS_REG_CM_HDR_GFT_CM_HDR_SHIFT 8 |
1723 | #define PRS_REG_LOAD_L2_FILTER 0x1f0198UL |
1724 | |
1725 | #endif |
1726 | |