1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* |
3 | * linux/drivers/acorn/net/ether3.h |
4 | * |
5 | * Copyright (C) 1995-2000 Russell King |
6 | * |
7 | * network driver for Acorn/ANT Ether3 cards |
8 | */ |
9 | |
10 | #ifndef _LINUX_ether3_H |
11 | #define _LINUX_ether3_H |
12 | |
13 | /* use 0 for production, 1 for verification, >2 for debug. debug flags: */ |
14 | #define DEBUG_TX 2 |
15 | #define DEBUG_RX 4 |
16 | #define DEBUG_INT 8 |
17 | #define DEBUG_IC 16 |
18 | #ifndef NET_DEBUG |
19 | #define NET_DEBUG 0 |
20 | #endif |
21 | |
22 | #define priv(dev) ((struct dev_priv *)netdev_priv(dev)) |
23 | |
24 | /* Command register definitions & bits */ |
25 | #define REG_COMMAND (priv(dev)->seeq + 0x0000) |
26 | #define CMD_ENINTDMA 0x0001 |
27 | #define CMD_ENINTRX 0x0002 |
28 | #define CMD_ENINTTX 0x0004 |
29 | #define CMD_ENINTBUFWIN 0x0008 |
30 | #define CMD_ACKINTDMA 0x0010 |
31 | #define CMD_ACKINTRX 0x0020 |
32 | #define CMD_ACKINTTX 0x0040 |
33 | #define CMD_ACKINTBUFWIN 0x0080 |
34 | #define CMD_DMAON 0x0100 |
35 | #define CMD_RXON 0x0200 |
36 | #define CMD_TXON 0x0400 |
37 | #define CMD_DMAOFF 0x0800 |
38 | #define CMD_RXOFF 0x1000 |
39 | #define CMD_TXOFF 0x2000 |
40 | #define CMD_FIFOREAD 0x4000 |
41 | #define CMD_FIFOWRITE 0x8000 |
42 | |
43 | /* status register */ |
44 | #define REG_STATUS (priv(dev)->seeq + 0x0000) |
45 | #define STAT_ENINTSTAT 0x0001 |
46 | #define STAT_ENINTRX 0x0002 |
47 | #define STAT_ENINTTX 0x0004 |
48 | #define STAT_ENINTBUFWIN 0x0008 |
49 | #define STAT_INTDMA 0x0010 |
50 | #define STAT_INTRX 0x0020 |
51 | #define STAT_INTTX 0x0040 |
52 | #define STAT_INTBUFWIN 0x0080 |
53 | #define STAT_DMAON 0x0100 |
54 | #define STAT_RXON 0x0200 |
55 | #define STAT_TXON 0x0400 |
56 | #define STAT_FIFOFULL 0x2000 |
57 | #define STAT_FIFOEMPTY 0x4000 |
58 | #define STAT_FIFODIR 0x8000 |
59 | |
60 | /* configuration register 1 */ |
61 | #define REG_CONFIG1 (priv(dev)->seeq + 0x0040) |
62 | #define CFG1_BUFSELSTAT0 0x0000 |
63 | #define CFG1_BUFSELSTAT1 0x0001 |
64 | #define CFG1_BUFSELSTAT2 0x0002 |
65 | #define CFG1_BUFSELSTAT3 0x0003 |
66 | #define CFG1_BUFSELSTAT4 0x0004 |
67 | #define CFG1_BUFSELSTAT5 0x0005 |
68 | #define CFG1_ADDRPROM 0x0006 |
69 | #define CFG1_TRANSEND 0x0007 |
70 | #define CFG1_LOCBUFMEM 0x0008 |
71 | #define CFG1_INTVECTOR 0x0009 |
72 | #define CFG1_RECVSPECONLY 0x0000 |
73 | #define CFG1_RECVSPECBROAD 0x4000 |
74 | #define CFG1_RECVSPECBRMULTI 0x8000 |
75 | #define CFG1_RECVPROMISC 0xC000 |
76 | |
77 | /* The following aren't in 8004 */ |
78 | #define CFG1_DMABURSTCONT 0x0000 |
79 | #define CFG1_DMABURST800NS 0x0010 |
80 | #define CFG1_DMABURST1600NS 0x0020 |
81 | #define CFG1_DMABURST3200NS 0x0030 |
82 | #define CFG1_DMABURST1 0x0000 |
83 | #define CFG1_DMABURST4 0x0040 |
84 | #define CFG1_DMABURST8 0x0080 |
85 | #define CFG1_DMABURST16 0x00C0 |
86 | #define CFG1_RECVCOMPSTAT0 0x0100 |
87 | #define CFG1_RECVCOMPSTAT1 0x0200 |
88 | #define CFG1_RECVCOMPSTAT2 0x0400 |
89 | #define CFG1_RECVCOMPSTAT3 0x0800 |
90 | #define CFG1_RECVCOMPSTAT4 0x1000 |
91 | #define CFG1_RECVCOMPSTAT5 0x2000 |
92 | |
93 | /* configuration register 2 */ |
94 | #define REG_CONFIG2 (priv(dev)->seeq + 0x0080) |
95 | #define CFG2_BYTESWAP 0x0001 |
96 | #define CFG2_ERRENCRC 0x0008 |
97 | #define CFG2_ERRENDRIBBLE 0x0010 |
98 | #define CFG2_ERRSHORTFRAME 0x0020 |
99 | #define CFG2_SLOTSELECT 0x0040 |
100 | #define CFG2_PREAMSELECT 0x0080 |
101 | #define CFG2_ADDRLENGTH 0x0100 |
102 | #define CFG2_RECVCRC 0x0200 |
103 | #define CFG2_XMITNOCRC 0x0400 |
104 | #define CFG2_LOOPBACK 0x0800 |
105 | #define CFG2_CTRLO 0x1000 |
106 | #define CFG2_RESET 0x8000 |
107 | |
108 | #define REG_RECVEND (priv(dev)->seeq + 0x00c0) |
109 | |
110 | #define REG_BUFWIN (priv(dev)->seeq + 0x0100) |
111 | |
112 | #define REG_RECVPTR (priv(dev)->seeq + 0x0140) |
113 | |
114 | #define REG_TRANSMITPTR (priv(dev)->seeq + 0x0180) |
115 | |
116 | #define REG_DMAADDR (priv(dev)->seeq + 0x01c0) |
117 | |
118 | /* |
119 | * Cards transmit/receive headers |
120 | */ |
121 | #define TX_NEXT (0xffff) |
122 | #define TXHDR_ENBABBLEINT (1 << 16) |
123 | #define TXHDR_ENCOLLISIONINT (1 << 17) |
124 | #define TXHDR_EN16COLLISION (1 << 18) |
125 | #define TXHDR_ENSUCCESS (1 << 19) |
126 | #define TXHDR_DATAFOLLOWS (1 << 21) |
127 | #define TXHDR_CHAINCONTINUE (1 << 22) |
128 | #define TXHDR_TRANSMIT (1 << 23) |
129 | #define TXSTAT_BABBLED (1 << 24) |
130 | #define TXSTAT_COLLISION (1 << 25) |
131 | #define TXSTAT_16COLLISIONS (1 << 26) |
132 | #define TXSTAT_DONE (1 << 31) |
133 | |
134 | #define RX_NEXT (0xffff) |
135 | #define RXHDR_CHAINCONTINUE (1 << 6) |
136 | #define RXHDR_RECEIVE (1 << 7) |
137 | #define RXSTAT_OVERSIZE (1 << 8) |
138 | #define RXSTAT_CRCERROR (1 << 9) |
139 | #define RXSTAT_DRIBBLEERROR (1 << 10) |
140 | #define RXSTAT_SHORTPACKET (1 << 11) |
141 | #define RXSTAT_DONE (1 << 15) |
142 | |
143 | |
144 | #define TX_START 0x0000 |
145 | #define TX_END 0x6000 |
146 | #define RX_START 0x6000 |
147 | #define RX_LEN 0xA000 |
148 | #define RX_END 0x10000 |
149 | /* must be a power of 2 and greater than MAX_TX_BUFFERED */ |
150 | #define MAX_TXED 16 |
151 | #define MAX_TX_BUFFERED 10 |
152 | |
153 | struct dev_priv { |
154 | void __iomem *base; |
155 | void __iomem *seeq; |
156 | struct { |
157 | unsigned int command; |
158 | unsigned int config1; |
159 | unsigned int config2; |
160 | } regs; |
161 | unsigned char tx_head; /* buffer nr to insert next packet */ |
162 | unsigned char tx_tail; /* buffer nr of transmitting packet */ |
163 | unsigned int rx_head; /* address to fetch next packet from */ |
164 | struct timer_list timer; |
165 | struct net_device *dev; |
166 | int broken; /* 0 = ok, 1 = something went wrong */ |
167 | }; |
168 | |
169 | struct ether3_data { |
170 | const char name[8]; |
171 | unsigned long base_offset; |
172 | }; |
173 | |
174 | #endif |
175 | |