1/* SPDX-License-Identifier: GPL-2.0-only */
2/****************************************************************************
3 * Driver for Solarflare network controllers and boards
4 * Copyright 2009-2018 Solarflare Communications Inc.
5 * Copyright 2019-2020 Xilinx Inc.
6 */
7
8
9#ifndef MCDI_PCOL_H
10#define MCDI_PCOL_H
11
12/* Values to be written into FMCR_CZ_RESET_STATE_REG to control boot. */
13/* Power-on reset state */
14#define MC_FW_STATE_POR (1)
15/* If this is set in MC_RESET_STATE_REG then it should be
16 * possible to jump into IMEM without loading code from flash. */
17#define MC_FW_WARM_BOOT_OK (2)
18/* The MC main image has started to boot. */
19#define MC_FW_STATE_BOOTING (4)
20/* The Scheduler has started. */
21#define MC_FW_STATE_SCHED (8)
22/* If this is set in MC_RESET_STATE_REG then it should be
23 * possible to jump into IMEM without loading code from flash.
24 * Unlike a warm boot, assume DMEM has been reloaded, so that
25 * the MC persistent data must be reinitialised. */
26#define MC_FW_TEPID_BOOT_OK (16)
27/* We have entered the main firmware via recovery mode. This
28 * means that MC persistent data must be reinitialised, but that
29 * we shouldn't touch PCIe config. */
30#define MC_FW_RECOVERY_MODE_PCIE_INIT_OK (32)
31/* BIST state has been initialized */
32#define MC_FW_BIST_INIT_OK (128)
33
34/* Siena MC shared memmory offsets */
35/* The 'doorbell' addresses are hard-wired to alert the MC when written */
36#define MC_SMEM_P0_DOORBELL_OFST 0x000
37#define MC_SMEM_P1_DOORBELL_OFST 0x004
38/* The rest of these are firmware-defined */
39#define MC_SMEM_P0_PDU_OFST 0x008
40#define MC_SMEM_P1_PDU_OFST 0x108
41#define MC_SMEM_PDU_LEN 0x100
42#define MC_SMEM_P0_PTP_TIME_OFST 0x7f0
43#define MC_SMEM_P0_STATUS_OFST 0x7f8
44#define MC_SMEM_P1_STATUS_OFST 0x7fc
45
46/* Values to be written to the per-port status dword in shared
47 * memory on reboot and assert */
48#define MC_STATUS_DWORD_REBOOT (0xb007b007)
49#define MC_STATUS_DWORD_ASSERT (0xdeaddead)
50
51/* Check whether an mcfw version (in host order) belongs to a bootloader */
52#define MC_FW_VERSION_IS_BOOTLOADER(_v) (((_v) >> 16) == 0xb007)
53
54/* The current version of the MCDI protocol.
55 *
56 * Note that the ROM burnt into the card only talks V0, so at the very
57 * least every driver must support version 0 and MCDI_PCOL_VERSION
58 */
59#define MCDI_PCOL_VERSION 2
60
61/* Unused commands: 0x23, 0x27, 0x30, 0x31 */
62
63/* MCDI version 1
64 *
65 * Each MCDI request starts with an MCDI_HEADER, which is a 32bit
66 * structure, filled in by the client.
67 *
68 * 0 7 8 16 20 22 23 24 31
69 * | CODE | R | LEN | SEQ | Rsvd | E | R | XFLAGS |
70 * | | |
71 * | | \--- Response
72 * | \------- Error
73 * \------------------------------ Resync (always set)
74 *
75 * The client writes it's request into MC shared memory, and rings the
76 * doorbell. Each request is completed by either by the MC writing
77 * back into shared memory, or by writing out an event.
78 *
79 * All MCDI commands support completion by shared memory response. Each
80 * request may also contain additional data (accounted for by HEADER.LEN),
81 * and some response's may also contain additional data (again, accounted
82 * for by HEADER.LEN).
83 *
84 * Some MCDI commands support completion by event, in which any associated
85 * response data is included in the event.
86 *
87 * The protocol requires one response to be delivered for every request, a
88 * request should not be sent unless the response for the previous request
89 * has been received (either by polling shared memory, or by receiving
90 * an event).
91 */
92
93/** Request/Response structure */
94#define MCDI_HEADER_OFST 0
95#define MCDI_HEADER_CODE_LBN 0
96#define MCDI_HEADER_CODE_WIDTH 7
97#define MCDI_HEADER_RESYNC_LBN 7
98#define MCDI_HEADER_RESYNC_WIDTH 1
99#define MCDI_HEADER_DATALEN_LBN 8
100#define MCDI_HEADER_DATALEN_WIDTH 8
101#define MCDI_HEADER_SEQ_LBN 16
102#define MCDI_HEADER_SEQ_WIDTH 4
103#define MCDI_HEADER_RSVD_LBN 20
104#define MCDI_HEADER_RSVD_WIDTH 1
105#define MCDI_HEADER_NOT_EPOCH_LBN 21
106#define MCDI_HEADER_NOT_EPOCH_WIDTH 1
107#define MCDI_HEADER_ERROR_LBN 22
108#define MCDI_HEADER_ERROR_WIDTH 1
109#define MCDI_HEADER_RESPONSE_LBN 23
110#define MCDI_HEADER_RESPONSE_WIDTH 1
111#define MCDI_HEADER_XFLAGS_LBN 24
112#define MCDI_HEADER_XFLAGS_WIDTH 8
113/* Request response using event */
114#define MCDI_HEADER_XFLAGS_EVREQ 0x01
115/* Request (and signal) early doorbell return */
116#define MCDI_HEADER_XFLAGS_DBRET 0x02
117
118/* Maximum number of payload bytes */
119#define MCDI_CTL_SDU_LEN_MAX_V1 0xfc
120#define MCDI_CTL_SDU_LEN_MAX_V2 0x400
121
122#define MCDI_CTL_SDU_LEN_MAX MCDI_CTL_SDU_LEN_MAX_V2
123
124
125/* The MC can generate events for two reasons:
126 * - To advance a shared memory request if XFLAGS_EVREQ was set
127 * - As a notification (link state, i2c event), controlled
128 * via MC_CMD_LOG_CTRL
129 *
130 * Both events share a common structure:
131 *
132 * 0 32 33 36 44 52 60
133 * | Data | Cont | Level | Src | Code | Rsvd |
134 * |
135 * \ There is another event pending in this notification
136 *
137 * If Code==CMDDONE, then the fields are further interpreted as:
138 *
139 * - LEVEL==INFO Command succeeded
140 * - LEVEL==ERR Command failed
141 *
142 * 0 8 16 24 32
143 * | Seq | Datalen | Errno | Rsvd |
144 *
145 * These fields are taken directly out of the standard MCDI header, i.e.,
146 * LEVEL==ERR, Datalen == 0 => Reboot
147 *
148 * Events can be squirted out of the UART (using LOG_CTRL) without a
149 * MCDI header. An event can be distinguished from a MCDI response by
150 * examining the first byte which is 0xc0. This corresponds to the
151 * non-existent MCDI command MC_CMD_DEBUG_LOG.
152 *
153 * 0 7 8
154 * | command | Resync | = 0xc0
155 *
156 * Since the event is written in big-endian byte order, this works
157 * providing bits 56-63 of the event are 0xc0.
158 *
159 * 56 60 63
160 * | Rsvd | Code | = 0xc0
161 *
162 * Which means for convenience the event code is 0xc for all MC
163 * generated events.
164 */
165#define FSE_AZ_EV_CODE_MCDI_EVRESPONSE 0xc
166
167
168#define MC_CMD_ERR_CODE_OFST 0
169#define MC_CMD_ERR_PROXY_PENDING_HANDLE_OFST 4
170
171/* We define 8 "escape" commands to allow
172 for command number space extension */
173
174#define MC_CMD_CMD_SPACE_ESCAPE_0 0x78
175#define MC_CMD_CMD_SPACE_ESCAPE_1 0x79
176#define MC_CMD_CMD_SPACE_ESCAPE_2 0x7A
177#define MC_CMD_CMD_SPACE_ESCAPE_3 0x7B
178#define MC_CMD_CMD_SPACE_ESCAPE_4 0x7C
179#define MC_CMD_CMD_SPACE_ESCAPE_5 0x7D
180#define MC_CMD_CMD_SPACE_ESCAPE_6 0x7E
181#define MC_CMD_CMD_SPACE_ESCAPE_7 0x7F
182
183/* Vectors in the boot ROM */
184/* Point to the copycode entry point. */
185#define SIENA_MC_BOOTROM_COPYCODE_VEC (0x800 - 3 * 0x4)
186#define HUNT_MC_BOOTROM_COPYCODE_VEC (0x8000 - 3 * 0x4)
187#define MEDFORD_MC_BOOTROM_COPYCODE_VEC (0x10000 - 3 * 0x4)
188/* Points to the recovery mode entry point. Misnamed but kept for compatibility. */
189#define SIENA_MC_BOOTROM_NOFLASH_VEC (0x800 - 2 * 0x4)
190#define HUNT_MC_BOOTROM_NOFLASH_VEC (0x8000 - 2 * 0x4)
191#define MEDFORD_MC_BOOTROM_NOFLASH_VEC (0x10000 - 2 * 0x4)
192/* Points to the recovery mode entry point. Same as above, but the right name. */
193#define SIENA_MC_BOOTROM_RECOVERY_VEC (0x800 - 2 * 0x4)
194#define HUNT_MC_BOOTROM_RECOVERY_VEC (0x8000 - 2 * 0x4)
195#define MEDFORD_MC_BOOTROM_RECOVERY_VEC (0x10000 - 2 * 0x4)
196
197/* Points to noflash mode entry point. */
198#define MEDFORD_MC_BOOTROM_REAL_NOFLASH_VEC (0x10000 - 4 * 0x4)
199
200/* The command set exported by the boot ROM (MCDI v0) */
201#define MC_CMD_GET_VERSION_V0_SUPPORTED_FUNCS { \
202 (1 << MC_CMD_READ32) | \
203 (1 << MC_CMD_WRITE32) | \
204 (1 << MC_CMD_COPYCODE) | \
205 (1 << MC_CMD_GET_VERSION), \
206 0, 0, 0 }
207
208#define MC_CMD_SENSOR_INFO_OUT_OFFSET_OFST(_x) \
209 (MC_CMD_SENSOR_ENTRY_OFST + (_x))
210
211#define MC_CMD_DBI_WRITE_IN_ADDRESS_OFST(n) \
212 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \
213 MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST + \
214 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN)
215
216#define MC_CMD_DBI_WRITE_IN_BYTE_MASK_OFST(n) \
217 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \
218 MC_CMD_DBIWROP_TYPEDEF_BYTE_MASK_OFST + \
219 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN)
220
221#define MC_CMD_DBI_WRITE_IN_VALUE_OFST(n) \
222 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \
223 MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST + \
224 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN)
225
226/* This may be ORed with an EVB_PORT_ID_xxx constant to pass a non-default
227 * stack ID (which must be in the range 1-255) along with an EVB port ID.
228 */
229#define EVB_STACK_ID(n) (((n) & 0xff) << 16)
230
231
232/* Version 2 adds an optional argument to error returns: the errno value
233 * may be followed by the (0-based) number of the first argument that
234 * could not be processed.
235 */
236#define MC_CMD_ERR_ARG_OFST 4
237
238/* MC_CMD_ERR enum: Public MCDI error codes. Error codes that correspond to
239 * POSIX errnos should use the same numeric values that linux does. Error codes
240 * specific to Solarflare firmware should use values in the range 0x1000 -
241 * 0x10ff. The range 0x2000 - 0x20ff is reserved for private error codes (see
242 * MC_CMD_ERR_PRIV below).
243 */
244/* enum: Operation not permitted. */
245#define MC_CMD_ERR_EPERM 0x1
246/* enum: Non-existent command target */
247#define MC_CMD_ERR_ENOENT 0x2
248/* enum: assert() has killed the MC */
249#define MC_CMD_ERR_EINTR 0x4
250/* enum: I/O failure */
251#define MC_CMD_ERR_EIO 0x5
252/* enum: Already exists */
253#define MC_CMD_ERR_EEXIST 0x6
254/* enum: Try again */
255#define MC_CMD_ERR_EAGAIN 0xb
256/* enum: Out of memory */
257#define MC_CMD_ERR_ENOMEM 0xc
258/* enum: Caller does not hold required locks */
259#define MC_CMD_ERR_EACCES 0xd
260/* enum: Resource is currently unavailable (e.g. lock contention) */
261#define MC_CMD_ERR_EBUSY 0x10
262/* enum: No such device */
263#define MC_CMD_ERR_ENODEV 0x13
264/* enum: Invalid argument to target */
265#define MC_CMD_ERR_EINVAL 0x16
266/* enum: No space */
267#define MC_CMD_ERR_ENOSPC 0x1c
268/* enum: Read-only */
269#define MC_CMD_ERR_EROFS 0x1e
270/* enum: Broken pipe */
271#define MC_CMD_ERR_EPIPE 0x20
272/* enum: Out of range */
273#define MC_CMD_ERR_ERANGE 0x22
274/* enum: Non-recursive resource is already acquired */
275#define MC_CMD_ERR_EDEADLK 0x23
276/* enum: Operation not implemented */
277#define MC_CMD_ERR_ENOSYS 0x26
278/* enum: Operation timed out */
279#define MC_CMD_ERR_ETIME 0x3e
280/* enum: Link has been severed */
281#define MC_CMD_ERR_ENOLINK 0x43
282/* enum: Protocol error */
283#define MC_CMD_ERR_EPROTO 0x47
284/* enum: Bad message */
285#define MC_CMD_ERR_EBADMSG 0x4a
286/* enum: Operation not supported */
287#define MC_CMD_ERR_ENOTSUP 0x5f
288/* enum: Address not available */
289#define MC_CMD_ERR_EADDRNOTAVAIL 0x63
290/* enum: Not connected */
291#define MC_CMD_ERR_ENOTCONN 0x6b
292/* enum: Operation already in progress */
293#define MC_CMD_ERR_EALREADY 0x72
294/* enum: Stale handle. The handle references a resource that no longer exists.
295 */
296#define MC_CMD_ERR_ESTALE 0x74
297/* enum: Resource allocation failed. */
298#define MC_CMD_ERR_ALLOC_FAIL 0x1000
299/* enum: V-adaptor not found. */
300#define MC_CMD_ERR_NO_VADAPTOR 0x1001
301/* enum: EVB port not found. */
302#define MC_CMD_ERR_NO_EVB_PORT 0x1002
303/* enum: V-switch not found. */
304#define MC_CMD_ERR_NO_VSWITCH 0x1003
305/* enum: Too many VLAN tags. */
306#define MC_CMD_ERR_VLAN_LIMIT 0x1004
307/* enum: Bad PCI function number. */
308#define MC_CMD_ERR_BAD_PCI_FUNC 0x1005
309/* enum: Invalid VLAN mode. */
310#define MC_CMD_ERR_BAD_VLAN_MODE 0x1006
311/* enum: Invalid v-switch type. */
312#define MC_CMD_ERR_BAD_VSWITCH_TYPE 0x1007
313/* enum: Invalid v-port type. */
314#define MC_CMD_ERR_BAD_VPORT_TYPE 0x1008
315/* enum: MAC address exists. */
316#define MC_CMD_ERR_MAC_EXIST 0x1009
317/* enum: Slave core not present */
318#define MC_CMD_ERR_SLAVE_NOT_PRESENT 0x100a
319/* enum: The datapath is disabled. */
320#define MC_CMD_ERR_DATAPATH_DISABLED 0x100b
321/* enum: The requesting client is not a function */
322#define MC_CMD_ERR_CLIENT_NOT_FN 0x100c
323/* enum: The requested operation might require the command to be passed between
324 * MCs, and thetransport doesn't support that. Should only ever been seen over
325 * the UART.
326 */
327#define MC_CMD_ERR_TRANSPORT_NOPROXY 0x100d
328/* enum: VLAN tag(s) exists */
329#define MC_CMD_ERR_VLAN_EXIST 0x100e
330/* enum: No MAC address assigned to an EVB port */
331#define MC_CMD_ERR_NO_MAC_ADDR 0x100f
332/* enum: Notifies the driver that the request has been relayed to an admin
333 * function for authorization. The driver should wait for a PROXY_RESPONSE
334 * event and then resend its request. This error code is followed by a 32-bit
335 * handle that helps matching it with the respective PROXY_RESPONSE event.
336 */
337#define MC_CMD_ERR_PROXY_PENDING 0x1010
338/* enum: The request cannot be passed for authorization because another request
339 * from the same function is currently being authorized. The drvier should try
340 * again later.
341 */
342#define MC_CMD_ERR_PROXY_INPROGRESS 0x1011
343/* enum: Returned by MC_CMD_PROXY_COMPLETE if the caller is not the function
344 * that has enabled proxying or BLOCK_INDEX points to a function that doesn't
345 * await an authorization.
346 */
347#define MC_CMD_ERR_PROXY_UNEXPECTED 0x1012
348/* enum: This code is currently only used internally in FW. Its meaning is that
349 * an operation failed due to lack of SR-IOV privilege. Normally it is
350 * translated to EPERM by send_cmd_err(), but it may also be used to trigger
351 * some special mechanism for handling such case, e.g. to relay the failed
352 * request to a designated admin function for authorization.
353 */
354#define MC_CMD_ERR_NO_PRIVILEGE 0x1013
355/* enum: Workaround 26807 could not be turned on/off because some functions
356 * have already installed filters. See the comment at
357 * MC_CMD_WORKAROUND_BUG26807. May also returned for other operations such as
358 * sub-variant switching.
359 */
360#define MC_CMD_ERR_FILTERS_PRESENT 0x1014
361/* enum: The clock whose frequency you've attempted to set set doesn't exist on
362 * this NIC
363 */
364#define MC_CMD_ERR_NO_CLOCK 0x1015
365/* enum: Returned by MC_CMD_TESTASSERT if the action that should have caused an
366 * assertion failed to do so.
367 */
368#define MC_CMD_ERR_UNREACHABLE 0x1016
369/* enum: This command needs to be processed in the background but there were no
370 * resources to do so. Send it again after a command has completed.
371 */
372#define MC_CMD_ERR_QUEUE_FULL 0x1017
373/* enum: The operation could not be completed because the PCIe link has gone
374 * away. This error code is never expected to be returned over the TLP
375 * transport.
376 */
377#define MC_CMD_ERR_NO_PCIE 0x1018
378/* enum: The operation could not be completed because the datapath has gone
379 * away. This is distinct from MC_CMD_ERR_DATAPATH_DISABLED in that the
380 * datapath absence may be temporary
381 */
382#define MC_CMD_ERR_NO_DATAPATH 0x1019
383/* enum: The operation could not complete because some VIs are allocated */
384#define MC_CMD_ERR_VIS_PRESENT 0x101a
385/* enum: The operation could not complete because some PIO buffers are
386 * allocated
387 */
388#define MC_CMD_ERR_PIOBUFS_PRESENT 0x101b
389
390/* MC_CMD_RESOURCE_SPECIFIER enum */
391/* enum: Any */
392#define MC_CMD_RESOURCE_INSTANCE_ANY 0xffffffff
393#define MC_CMD_RESOURCE_INSTANCE_NONE 0xfffffffe /* enum */
394
395/* MC_CMD_FPGA_FLASH_INDEX enum */
396#define MC_CMD_FPGA_FLASH_PRIMARY 0x0 /* enum */
397#define MC_CMD_FPGA_FLASH_SECONDARY 0x1 /* enum */
398
399/* MC_CMD_EXTERNAL_MAE_LINK_MODE enum */
400/* enum: Legacy mode as described in XN-200039-TC. */
401#define MC_CMD_EXTERNAL_MAE_LINK_MODE_LEGACY 0x0
402/* enum: Switchdev mode as described in XN-200039-TC. */
403#define MC_CMD_EXTERNAL_MAE_LINK_MODE_SWITCHDEV 0x1
404/* enum: Bootstrap mode as described in XN-200039-TC. */
405#define MC_CMD_EXTERNAL_MAE_LINK_MODE_BOOTSTRAP 0x2
406/* enum: Link-mode change is in-progress as described in XN-200039-TC. */
407#define MC_CMD_EXTERNAL_MAE_LINK_MODE_PENDING 0xf
408
409/* PCIE_INTERFACE enum: From EF100 onwards, SFC products can have multiple PCIe
410 * interfaces. There is a need to refer to interfaces explicitly from drivers
411 * (for example, a management driver on one interface administering a function
412 * on another interface). This enumeration provides stable identifiers to all
413 * interfaces present on a product. Product documentation will specify which
414 * interfaces exist and their associated identifier. In general, drivers,
415 * should not assign special meanings to specific values. Instead, behaviour
416 * should be determined by NIC configuration, which will identify interfaces
417 * where appropriate.
418 */
419/* enum: Primary host interfaces. Typically (i.e. for all known SFC products)
420 * the interface exposed on the edge connector (or form factor equivalent).
421 */
422#define PCIE_INTERFACE_HOST_PRIMARY 0x0
423/* enum: Riverhead and keystone products have a second PCIe interface to which
424 * an on-NIC ARM module is expected to be connected.
425 */
426#define PCIE_INTERFACE_NIC_EMBEDDED 0x1
427/* enum: For MCDI commands issued over a PCIe interface, this value is
428 * translated into the interface over which the command was issued. Not
429 * meaningful for other MCDI transports.
430 */
431#define PCIE_INTERFACE_CALLER 0xffffffff
432
433/* MC_CLIENT_ID_SPECIFIER enum */
434/* enum: Equivalent to the caller's client ID */
435#define MC_CMD_CLIENT_ID_SELF 0xffffffff
436
437/* MAE_FIELD_SUPPORT_STATUS enum */
438/* enum: The NIC does not support this field. The driver must ensure that any
439 * mask associated with this field in a match rule is zeroed. The NIC may
440 * either reject requests with an invalid mask for such a field, or may assume
441 * that the mask is zero. (This category only exists to describe behaviour for
442 * fields that a newer driver might know about but that older firmware does
443 * not. It is recommended that firmware report MAE_FIELD_FIELD_MATCH_NEVER for
444 * all match fields defined at the time of its compilation. If a driver see a
445 * field support status value that it does not recognise, it must treat that
446 * field as thought the field was reported as MAE_FIELD_SUPPORTED_MATCH_NEVER,
447 * and must never set a non-zero mask value for this field.
448 */
449#define MAE_FIELD_UNSUPPORTED 0x0
450/* enum: The NIC supports this field, but cannot use it in a match rule. The
451 * driver must ensure that any mask for such a field in a match rule is zeroed.
452 * The NIC will reject requests with an invalid mask for such a field.
453 */
454#define MAE_FIELD_SUPPORTED_MATCH_NEVER 0x1
455/* enum: The NIC supports this field, and must use it in all match rules. The
456 * driver must ensure that any mask for such a field is all ones. The NIC will
457 * reject requests with an invalid mask for such a field.
458 */
459#define MAE_FIELD_SUPPORTED_MATCH_ALWAYS 0x2
460/* enum: The NIC supports this field, and may optionally use it in match rules.
461 * The driver must ensure that any mask for such a field is either all zeroes
462 * or all ones. The NIC will reject requests with an invalid mask for such a
463 * field.
464 */
465#define MAE_FIELD_SUPPORTED_MATCH_OPTIONAL 0x3
466/* enum: The NIC supports this field, and may optionally use it in match rules.
467 * The driver must ensure that any mask for such a field is either all zeroes
468 * or a consecutive set of ones following by all zeroes (starting from MSB).
469 * The NIC will reject requests with an invalid mask for such a field.
470 */
471#define MAE_FIELD_SUPPORTED_MATCH_PREFIX 0x4
472/* enum: The NIC supports this field, and may optionally use it in match rules.
473 * The driver may provide an arbitrary mask for such a field.
474 */
475#define MAE_FIELD_SUPPORTED_MATCH_MASK 0x5
476
477/* MAE_CT_VNI_MODE enum: Controls the layout of the VNI input to the conntrack
478 * lookup. (Values are not arbitrary - constrained by table access ABI.)
479 */
480/* enum: The VNI input to the conntrack lookup will be zero. */
481#define MAE_CT_VNI_MODE_ZERO 0x0
482/* enum: The VNI input to the conntrack lookup will be the VNI (VXLAN/Geneve)
483 * or VSID (NVGRE) field from the packet.
484 */
485#define MAE_CT_VNI_MODE_VNI 0x1
486/* enum: The VNI input to the conntrack lookup will be the VLAN ID from the
487 * outermost VLAN tag (in bottom 12 bits; top 12 bits zero).
488 */
489#define MAE_CT_VNI_MODE_1VLAN 0x2
490/* enum: The VNI input to the conntrack lookup will be the VLAN IDs from both
491 * VLAN tags (outermost in bottom 12 bits, innermost in top 12 bits).
492 */
493#define MAE_CT_VNI_MODE_2VLAN 0x3
494
495/* MAE_FIELD enum: NB: this enum shares namespace with the support status enum.
496 */
497/* enum: Source mport upon entering the MAE. */
498#define MAE_FIELD_INGRESS_PORT 0x0
499#define MAE_FIELD_MARK 0x1 /* enum */
500/* enum: Table ID used in action rule. Initially zero, can be changed in action
501 * rule response.
502 */
503#define MAE_FIELD_RECIRC_ID 0x2
504#define MAE_FIELD_IS_IP_FRAG 0x3 /* enum */
505#define MAE_FIELD_DO_CT 0x4 /* enum */
506#define MAE_FIELD_CT_HIT 0x5 /* enum */
507/* enum: Undefined unless CT_HIT=1. */
508#define MAE_FIELD_CT_MARK 0x6
509/* enum: Undefined unless DO_CT=1. */
510#define MAE_FIELD_CT_DOMAIN 0x7
511/* enum: Undefined unless CT_HIT=1. */
512#define MAE_FIELD_CT_PRIVATE_FLAGS 0x8
513/* enum: 1 if the packet ingressed the NIC from one of the MACs, else 0. */
514#define MAE_FIELD_IS_FROM_NETWORK 0x9
515/* enum: 1 if the packet has 1 or more VLAN tags, else 0. */
516#define MAE_FIELD_HAS_OVLAN 0xa
517/* enum: 1 if the packet has 2 or more VLAN tags, else 0. */
518#define MAE_FIELD_HAS_IVLAN 0xb
519/* enum: 1 if the outer packet has 1 or more VLAN tags, else 0; only present
520 * when encap
521 */
522#define MAE_FIELD_ENC_HAS_OVLAN 0xc
523/* enum: 1 if the outer packet has 2 or more VLAN tags, else 0; only present
524 * when encap
525 */
526#define MAE_FIELD_ENC_HAS_IVLAN 0xd
527/* enum: Packet is IP fragment */
528#define MAE_FIELD_ENC_IP_FRAG 0xe
529#define MAE_FIELD_ETHER_TYPE 0x21 /* enum */
530#define MAE_FIELD_VLAN0_TCI 0x22 /* enum */
531#define MAE_FIELD_VLAN0_PROTO 0x23 /* enum */
532#define MAE_FIELD_VLAN1_TCI 0x24 /* enum */
533#define MAE_FIELD_VLAN1_PROTO 0x25 /* enum */
534/* enum: Inner when encap */
535#define MAE_FIELD_ETH_SADDR 0x28
536/* enum: Inner when encap */
537#define MAE_FIELD_ETH_DADDR 0x29
538/* enum: Inner when encap. NB: IPv4 and IPv6 fields are mutually exclusive. */
539#define MAE_FIELD_SRC_IP4 0x2a
540/* enum: Inner when encap */
541#define MAE_FIELD_SRC_IP6 0x2b
542/* enum: Inner when encap */
543#define MAE_FIELD_DST_IP4 0x2c
544/* enum: Inner when encap */
545#define MAE_FIELD_DST_IP6 0x2d
546/* enum: Inner when encap */
547#define MAE_FIELD_IP_PROTO 0x2e
548/* enum: Inner when encap */
549#define MAE_FIELD_IP_TOS 0x2f
550/* enum: Inner when encap */
551#define MAE_FIELD_IP_TTL 0x30
552/* enum: Inner when encap TODO: how this is defined? The raw flags +
553 * frag_offset from the packet, or some derived value more amenable to ternary
554 * matching? TODO: there was a proposal for driver-allocation fields. The
555 * driver would provide some instruction for how to extract given field values,
556 * and would be given a field id in return. It could then use that field id in
557 * its matches. This feels like it would be extremely hard to implement in
558 * hardware, but I mention it for completeness.
559 */
560#define MAE_FIELD_IP_FLAGS 0x31
561/* enum: Ports (UDP, TCP) Inner when encap */
562#define MAE_FIELD_L4_SPORT 0x32
563/* enum: Ports (UDP, TCP) Inner when encap */
564#define MAE_FIELD_L4_DPORT 0x33
565/* enum: Inner when encap */
566#define MAE_FIELD_TCP_FLAGS 0x34
567/* enum: TCP packet with any of SYN, FIN or RST flag set */
568#define MAE_FIELD_TCP_SYN_FIN_RST 0x35
569/* enum: Packet is IP fragment with fragment offset 0 */
570#define MAE_FIELD_IP_FIRST_FRAG 0x36
571/* enum: The type of encapsulated used for this packet. Value as per
572 * ENCAP_TYPE_*.
573 */
574#define MAE_FIELD_ENCAP_TYPE 0x3f
575/* enum: The ID of the outer rule that marked this packet as encapsulated.
576 * Useful for implicitly matching on outer fields.
577 */
578#define MAE_FIELD_OUTER_RULE_ID 0x40
579/* enum: Outer; only present when encap */
580#define MAE_FIELD_ENC_ETHER_TYPE 0x41
581/* enum: Outer; only present when encap */
582#define MAE_FIELD_ENC_VLAN0_TCI 0x42
583/* enum: Outer; only present when encap */
584#define MAE_FIELD_ENC_VLAN0_PROTO 0x43
585/* enum: Outer; only present when encap */
586#define MAE_FIELD_ENC_VLAN1_TCI 0x44
587/* enum: Outer; only present when encap */
588#define MAE_FIELD_ENC_VLAN1_PROTO 0x45
589/* enum: Outer; only present when encap */
590#define MAE_FIELD_ENC_ETH_SADDR 0x48
591/* enum: Outer; only present when encap */
592#define MAE_FIELD_ENC_ETH_DADDR 0x49
593/* enum: Outer; only present when encap */
594#define MAE_FIELD_ENC_SRC_IP4 0x4a
595/* enum: Outer; only present when encap */
596#define MAE_FIELD_ENC_SRC_IP6 0x4b
597/* enum: Outer; only present when encap */
598#define MAE_FIELD_ENC_DST_IP4 0x4c
599/* enum: Outer; only present when encap */
600#define MAE_FIELD_ENC_DST_IP6 0x4d
601/* enum: Outer; only present when encap */
602#define MAE_FIELD_ENC_IP_PROTO 0x4e
603/* enum: Outer; only present when encap */
604#define MAE_FIELD_ENC_IP_TOS 0x4f
605/* enum: Outer; only present when encap */
606#define MAE_FIELD_ENC_IP_TTL 0x50
607/* enum: Outer; only present when encap */
608#define MAE_FIELD_ENC_IP_FLAGS 0x51
609/* enum: Outer; only present when encap */
610#define MAE_FIELD_ENC_L4_SPORT 0x52
611/* enum: Outer; only present when encap */
612#define MAE_FIELD_ENC_L4_DPORT 0x53
613/* enum: VNI (when VXLAN or GENEVE) VSID (when NVGRE) Bottom 24 bits of Key
614 * (when L2GRE) Outer; only present when encap
615 */
616#define MAE_FIELD_ENC_VNET_ID 0x54
617
618/* MAE_MCDI_ENCAP_TYPE enum: Encapsulation type. Defines how the payload will
619 * be parsed to an inner frame. Other values are reserved. Unknown values
620 * should be treated same as NONE. (Values are not arbitrary - constrained by
621 * table access ABI.)
622 */
623#define MAE_MCDI_ENCAP_TYPE_NONE 0x0 /* enum */
624/* enum: Don't assume enum aligns with support bitmask... */
625#define MAE_MCDI_ENCAP_TYPE_VXLAN 0x1
626#define MAE_MCDI_ENCAP_TYPE_NVGRE 0x2 /* enum */
627#define MAE_MCDI_ENCAP_TYPE_GENEVE 0x3 /* enum */
628#define MAE_MCDI_ENCAP_TYPE_L2GRE 0x4 /* enum */
629
630/* MAE_MPORT_END enum: Selects which end of the logical link identified by an
631 * MPORT_SELECTOR is targeted by an operation.
632 */
633/* enum: Selects the port on the MAE virtual switch */
634#define MAE_MPORT_END_MAE 0x1
635/* enum: Selects the virtual NIC plugged into the MAE switch */
636#define MAE_MPORT_END_VNIC 0x2
637
638/* MAE_COUNTER_TYPE enum: The datapath maintains several sets of counters, each
639 * being associated with a different table. Note that the same counter ID may
640 * be allocated by different counter blocks, so e.g. AR counter 42 is different
641 * from CT counter 42. Generation counts are also type-specific. This value is
642 * also present in the header of streaming counter packets, in the IDENTIFIER
643 * field (see packetiser packet format definitions).
644 */
645/* enum: Action Rule counters - can be referenced in AR response. */
646#define MAE_COUNTER_TYPE_AR 0x0
647/* enum: Conntrack counters - can be referenced in CT response. */
648#define MAE_COUNTER_TYPE_CT 0x1
649/* enum: Outer Rule counters - can be referenced in OR response. */
650#define MAE_COUNTER_TYPE_OR 0x2
651
652/* TABLE_ID enum: Unique IDs for tables. The 32-bit ID values have been
653 * structured with bits [31:24] reserved (0), [23:16] indicating which major
654 * block the tables belongs to (0=VNIC TX, none currently; 1=MAE; 2=VNIC RX),
655 * [15:8] a unique ID within the block, and [7:0] reserved for future
656 * variations of the same table. (All of the tables currently defined within
657 * the streaming engines are listed here, but this does not imply that they are
658 * all supported - MC_CMD_TABLE_LIST returns the list of actually supported
659 * tables.)
660 */
661/* enum: Outer_Rule_Table in the MAE - refer to SF-123102-TC. */
662#define TABLE_ID_OUTER_RULE_TABLE 0x10000
663/* enum: Outer_Rule_No_CT_Table in the MAE - refer to SF-123102-TC. */
664#define TABLE_ID_OUTER_RULE_NO_CT_TABLE 0x10100
665/* enum: Mgmt_Filter_Table in the MAE - refer to SF-123102-TC. */
666#define TABLE_ID_MGMT_FILTER_TABLE 0x10200
667/* enum: Conntrack_Table in the MAE - refer to SF-123102-TC. */
668#define TABLE_ID_CONNTRACK_TABLE 0x10300
669/* enum: Action_Rule_Table in the MAE - refer to SF-123102-TC. */
670#define TABLE_ID_ACTION_RULE_TABLE 0x10400
671/* enum: Mgroup_Default_Action_Set_Table in the MAE - refer to SF-123102-TC. */
672#define TABLE_ID_MGROUP_DEFAULT_ACTION_SET_TABLE 0x10500
673/* enum: Encap_Hdr_Part1_Table in the MAE - refer to SF-123102-TC. */
674#define TABLE_ID_ENCAP_HDR_PART1_TABLE 0x10600
675/* enum: Encap_Hdr_Part2_Table in the MAE - refer to SF-123102-TC. */
676#define TABLE_ID_ENCAP_HDR_PART2_TABLE 0x10700
677/* enum: Replace_Src_MAC_Table in the MAE - refer to SF-123102-TC. */
678#define TABLE_ID_REPLACE_SRC_MAC_TABLE 0x10800
679/* enum: Replace_Dst_MAC_Table in the MAE - refer to SF-123102-TC. */
680#define TABLE_ID_REPLACE_DST_MAC_TABLE 0x10900
681/* enum: Dst_Mport_VC_Table in the MAE - refer to SF-123102-TC. */
682#define TABLE_ID_DST_MPORT_VC_TABLE 0x10a00
683/* enum: LACP_LAG_Config_Table in the MAE - refer to SF-123102-TC. */
684#define TABLE_ID_LACP_LAG_CONFIG_TABLE 0x10b00
685/* enum: LACP_Balance_Table in the MAE - refer to SF-123102-TC. */
686#define TABLE_ID_LACP_BALANCE_TABLE 0x10c00
687/* enum: Dst_Mport_Host_Chan_Table in the MAE - refer to SF-123102-TC. */
688#define TABLE_ID_DST_MPORT_HOST_CHAN_TABLE 0x10d00
689/* enum: VNIC_Rx_Encap_Table in VNIC Rx - refer to SF-123102-TC. */
690#define TABLE_ID_VNIC_RX_ENCAP_TABLE 0x20000
691/* enum: Steering_Table in VNIC Rx - refer to SF-123102-TC. */
692#define TABLE_ID_STEERING_TABLE 0x20100
693/* enum: RSS_Context_Table in VNIC Rx - refer to SF-123102-TC. */
694#define TABLE_ID_RSS_CONTEXT_TABLE 0x20200
695/* enum: Indirection_Table in VNIC Rx - refer to SF-123102-TC. */
696#define TABLE_ID_INDIRECTION_TABLE 0x20300
697
698/* TABLE_COMPRESSED_VLAN enum: Compressed VLAN TPID as used by some field
699 * types; can be calculated by (((ether_type_msb >> 2) & 0x4) ^ 0x4) |
700 * (ether_type_msb & 0x3);
701 */
702#define TABLE_COMPRESSED_VLAN_TPID_8100 0x5 /* enum */
703#define TABLE_COMPRESSED_VLAN_TPID_88A8 0x4 /* enum */
704#define TABLE_COMPRESSED_VLAN_TPID_9100 0x1 /* enum */
705#define TABLE_COMPRESSED_VLAN_TPID_9200 0x2 /* enum */
706#define TABLE_COMPRESSED_VLAN_TPID_9300 0x3 /* enum */
707
708/* TABLE_NAT_DIR enum: NAT direction. */
709#define TABLE_NAT_DIR_SOURCE 0x0 /* enum */
710#define TABLE_NAT_DIR_DEST 0x1 /* enum */
711
712/* TABLE_RSS_KEY_MODE enum: Defines how the value for Toeplitz hashing for RSS
713 * is constructed as a concatenation (indicated here by "++") of packet header
714 * fields.
715 */
716/* enum: IP src addr ++ IP dst addr */
717#define TABLE_RSS_KEY_MODE_SA_DA 0x0
718/* enum: IP src addr ++ IP dst addr ++ TCP/UDP src port ++ TCP/UDP dst port */
719#define TABLE_RSS_KEY_MODE_SA_DA_SP_DP 0x1
720/* enum: IP src addr */
721#define TABLE_RSS_KEY_MODE_SA 0x2
722/* enum: IP dst addr */
723#define TABLE_RSS_KEY_MODE_DA 0x3
724/* enum: IP src addr ++ TCP/UDP src port */
725#define TABLE_RSS_KEY_MODE_SA_SP 0x4
726/* enum: IP dest addr ++ TCP dest port */
727#define TABLE_RSS_KEY_MODE_DA_DP 0x5
728/* enum: Nothing (produces input of 0, resulting in output hash of 0) */
729#define TABLE_RSS_KEY_MODE_NONE 0x7
730
731/* TABLE_RSS_SPREAD_MODE enum: RSS spreading mode. */
732/* enum: RSS uses Indirection_Table lookup. */
733#define TABLE_RSS_SPREAD_MODE_INDIRECTION 0x0
734/* enum: RSS uses even spreading calculation. */
735#define TABLE_RSS_SPREAD_MODE_EVEN 0x1
736
737/* TABLE_FIELD_ID enum: Unique IDs for fields. Related concepts have been
738 * loosely grouped together into blocks with gaps for expansion, but the values
739 * are arbitrary. Field IDs are not specific to particular tables, and in some
740 * cases this sharing means that they are not used with the exact names of the
741 * corresponding table definitions in SF-123102-TC; however, the mapping should
742 * still be clear. The intent is that a list of fields, with their associated
743 * bit widths and semantics version code, unambiguously defines the semantics
744 * of the fields in a key or response. (Again, this list includes all of the
745 * fields currently defined within the streaming engines, but only a subset may
746 * actually be used by the supported list of tables.)
747 */
748/* enum: May appear multiple times within a key or response, and indicates that
749 * the field is unused and should be set to 0 (or masked out if permitted by
750 * the MASK_VALUE for this field).
751 */
752#define TABLE_FIELD_ID_UNUSED 0x0
753/* enum: Source m-port (a full m-port label). */
754#define TABLE_FIELD_ID_SRC_MPORT 0x1
755/* enum: Destination m-port (a full m-port label). */
756#define TABLE_FIELD_ID_DST_MPORT 0x2
757/* enum: Source m-group ID. */
758#define TABLE_FIELD_ID_SRC_MGROUP_ID 0x3
759/* enum: Physical network port ID (or m-port ID; same thing, for physical
760 * network ports).
761 */
762#define TABLE_FIELD_ID_NETWORK_PORT_ID 0x4
763/* enum: True if packet arrived via network port, false if it arrived via host.
764 */
765#define TABLE_FIELD_ID_IS_FROM_NETWORK 0x5
766/* enum: Full virtual channel from capsule header. */
767#define TABLE_FIELD_ID_CH_VC 0x6
768/* enum: Low bits of virtual channel from capsule header. */
769#define TABLE_FIELD_ID_CH_VC_LOW 0x7
770/* enum: User mark value in metadata and packet prefix. */
771#define TABLE_FIELD_ID_USER_MARK 0x8
772/* enum: User flag value in metadata and packet prefix. */
773#define TABLE_FIELD_ID_USER_FLAG 0x9
774/* enum: Counter ID associated with a response. All-bits-1 is a null value to
775 * suppress counting.
776 */
777#define TABLE_FIELD_ID_COUNTER_ID 0xa
778/* enum: Discriminator which may be set by plugins in some lookup keys; this
779 * allows plugins to make a reinterpretation of packet fields in these keys
780 * without clashing with the normal interpretation.
781 */
782#define TABLE_FIELD_ID_DISCRIM 0xb
783/* enum: Destination MAC address. The mapping from bytes in a frame to the
784 * 48-bit value for this field is in network order, i.e. a MAC address of
785 * AA:BB:CC:DD:EE:FF becomes a 48-bit value of 0xAABBCCDDEEFF.
786 */
787#define TABLE_FIELD_ID_DST_MAC 0x14
788/* enum: Source MAC address (see notes for DST_MAC). */
789#define TABLE_FIELD_ID_SRC_MAC 0x15
790/* enum: Outer VLAN tag TPID, compressed to an enumeration. */
791#define TABLE_FIELD_ID_OVLAN_TPID_COMPRESSED 0x16
792/* enum: Full outer VLAN tag TCI (16 bits). */
793#define TABLE_FIELD_ID_OVLAN 0x17
794/* enum: Outer VLAN ID (least significant 12 bits of full 16-bit TCI) only. */
795#define TABLE_FIELD_ID_OVLAN_VID 0x18
796/* enum: Inner VLAN tag TPID, compressed to an enumeration. */
797#define TABLE_FIELD_ID_IVLAN_TPID_COMPRESSED 0x19
798/* enum: Full inner VLAN tag TCI (16 bits). */
799#define TABLE_FIELD_ID_IVLAN 0x1a
800/* enum: Inner VLAN ID (least significant 12 bits of full 16-bit TCI) only. */
801#define TABLE_FIELD_ID_IVLAN_VID 0x1b
802/* enum: Ethertype. */
803#define TABLE_FIELD_ID_ETHER_TYPE 0x1c
804/* enum: Source IP address, either IPv4 or IPv6. The mapping from bytes in a
805 * frame to the 128-bit value for this field is in network order, with IPv4
806 * addresses assumed to have 12 bytes of trailing zeroes. i.e. the IPv6 address
807 * [2345::6789:ABCD] is 0x2345000000000000000000006789ABCD; the IPv4 address
808 * 192.168.1.2 is 0xC0A80102000000000000000000000000.
809 */
810#define TABLE_FIELD_ID_SRC_IP 0x1d
811/* enum: Destination IP address (see notes for SRC_IP). */
812#define TABLE_FIELD_ID_DST_IP 0x1e
813/* enum: IPv4 Type-of-Service or IPv6 Traffic Class field. */
814#define TABLE_FIELD_ID_IP_TOS 0x1f
815/* enum: IP Protocol. */
816#define TABLE_FIELD_ID_IP_PROTO 0x20
817/* enum: Layer 4 source port. */
818#define TABLE_FIELD_ID_SRC_PORT 0x21
819/* enum: Layer 4 destination port. */
820#define TABLE_FIELD_ID_DST_PORT 0x22
821/* enum: TCP flags. */
822#define TABLE_FIELD_ID_TCP_FLAGS 0x23
823/* enum: Virtual Network Identifier (VXLAN) or Virtual Session ID (NVGRE). */
824#define TABLE_FIELD_ID_VNI 0x24
825/* enum: True if packet has any tunnel encapsulation header. */
826#define TABLE_FIELD_ID_HAS_ENCAP 0x32
827/* enum: True if encap header has an outer VLAN tag. */
828#define TABLE_FIELD_ID_HAS_ENC_OVLAN 0x33
829/* enum: True if encap header has an inner VLAN tag. */
830#define TABLE_FIELD_ID_HAS_ENC_IVLAN 0x34
831/* enum: True if encap header is some sort of IP. */
832#define TABLE_FIELD_ID_HAS_ENC_IP 0x35
833/* enum: True if encap header is specifically IPv4. */
834#define TABLE_FIELD_ID_HAS_ENC_IP4 0x36
835/* enum: True if encap header is UDP. */
836#define TABLE_FIELD_ID_HAS_ENC_UDP 0x37
837/* enum: True if only/inner frame has an outer VLAN tag. */
838#define TABLE_FIELD_ID_HAS_OVLAN 0x38
839/* enum: True if only/inner frame has an inner VLAN tag. */
840#define TABLE_FIELD_ID_HAS_IVLAN 0x39
841/* enum: True if only/inner frame is some sort of IP. */
842#define TABLE_FIELD_ID_HAS_IP 0x3a
843/* enum: True if only/inner frame has a recognised L4 IP protocol (TCP or UDP).
844 */
845#define TABLE_FIELD_ID_HAS_L4 0x3b
846/* enum: True if only/inner frame is an IP fragment. */
847#define TABLE_FIELD_ID_IP_FRAG 0x3c
848/* enum: True if only/inner frame is the first IP fragment (fragment offset 0).
849 */
850#define TABLE_FIELD_ID_IP_FIRST_FRAG 0x3d
851/* enum: True if only/inner frame has an IP Time-To-Live of <= 1. (Note: the
852 * implementation calls this "ip_ttl_is_one" but does in fact match packets
853 * with TTL=0 - which we shouldn't be seeing! - as well.)
854 */
855#define TABLE_FIELD_ID_IP_TTL_LE_ONE 0x3e
856/* enum: True if only/inner frame has any of TCP SYN, FIN or RST flags set. */
857#define TABLE_FIELD_ID_TCP_INTERESTING_FLAGS 0x3f
858/* enum: Plugin channel selection. */
859#define TABLE_FIELD_ID_RDP_PL_CHAN 0x50
860/* enum: Enable update of CH_ROUTE_RDP_C_PL route bit. */
861#define TABLE_FIELD_ID_RDP_C_PL_EN 0x51
862/* enum: New value of CH_ROUTE_RDP_C_PL route bit. */
863#define TABLE_FIELD_ID_RDP_C_PL 0x52
864/* enum: Enable update of CH_ROUTE_RDP_D_PL route bit. */
865#define TABLE_FIELD_ID_RDP_D_PL_EN 0x53
866/* enum: New value of CH_ROUTE_RDP_D_PL route bit. */
867#define TABLE_FIELD_ID_RDP_D_PL 0x54
868/* enum: Enable update of CH_ROUTE_RDP_OUT_HOST_CHAN route bit. */
869#define TABLE_FIELD_ID_RDP_OUT_HOST_CHAN_EN 0x55
870/* enum: New value of CH_ROUTE_RDP_OUT_HOST_CHAN route bit. */
871#define TABLE_FIELD_ID_RDP_OUT_HOST_CHAN 0x56
872/* enum: Recirculation ID for lookup sequences with two action rule lookups. */
873#define TABLE_FIELD_ID_RECIRC_ID 0x64
874/* enum: Domain ID passed to conntrack and action rule lookups. */
875#define TABLE_FIELD_ID_DOMAIN 0x65
876/* enum: Construction mode for encap_tunnel_id - see MAE_CT_VNI_MODE enum. */
877#define TABLE_FIELD_ID_CT_VNI_MODE 0x66
878/* enum: True to inhibit conntrack lookup if TCP SYN, FIN or RST flag is set.
879 */
880#define TABLE_FIELD_ID_CT_TCP_FLAGS_INHIBIT 0x67
881/* enum: True to do conntrack lookups for IPv4 TCP packets. */
882#define TABLE_FIELD_ID_DO_CT_IP4_TCP 0x68
883/* enum: True to do conntrack lookups for IPv4 UDP packets. */
884#define TABLE_FIELD_ID_DO_CT_IP4_UDP 0x69
885/* enum: True to do conntrack lookups for IPv6 TCP packets. */
886#define TABLE_FIELD_ID_DO_CT_IP6_TCP 0x6a
887/* enum: True to do conntrack lookups for IPv6 UDP packets. */
888#define TABLE_FIELD_ID_DO_CT_IP6_UDP 0x6b
889/* enum: Outer rule identifier. */
890#define TABLE_FIELD_ID_OUTER_RULE_ID 0x6c
891/* enum: Encapsulation type - see MAE_MCDI_ENCAP_TYPE enum. */
892#define TABLE_FIELD_ID_ENCAP_TYPE 0x6d
893/* enum: Encap tunnel ID for conntrack lookups from VNI, VLAN tag(s), or 0,
894 * depending on CT_VNI_MODE.
895 */
896#define TABLE_FIELD_ID_ENCAP_TUNNEL_ID 0x78
897/* enum: A conntrack entry identifier, passed to plugins. */
898#define TABLE_FIELD_ID_CT_ENTRY_ID 0x79
899/* enum: Either source or destination NAT replacement port. */
900#define TABLE_FIELD_ID_NAT_PORT 0x7a
901/* enum: Either source or destination NAT replacement IPv4 address. Note that
902 * this is specifically an IPv4 address (IPv6 is not supported for NAT), with
903 * byte mapped to a 32-bit value in network order, i.e. the IPv4 address
904 * 192.168.1.2 is the value 0xC0A80102.
905 */
906#define TABLE_FIELD_ID_NAT_IP 0x7b
907/* enum: NAT direction: 0=>source, 1=>destination. */
908#define TABLE_FIELD_ID_NAT_DIR 0x7c
909/* enum: Conntrack mark value, passed to action rule lookup. Note that this is
910 * not related to the "user mark" in the metadata / packet prefix.
911 */
912#define TABLE_FIELD_ID_CT_MARK 0x7d
913/* enum: Private flags for conntrack, passed to action rule lookup. */
914#define TABLE_FIELD_ID_CT_PRIV_FLAGS 0x7e
915/* enum: True if the conntrack lookup resulted in a hit. */
916#define TABLE_FIELD_ID_CT_HIT 0x7f
917/* enum: True to suppress delivery when source and destination m-ports match.
918 */
919#define TABLE_FIELD_ID_SUPPRESS_SELF_DELIVERY 0x8c
920/* enum: True to perform tunnel decapsulation. */
921#define TABLE_FIELD_ID_DO_DECAP 0x8d
922/* enum: True to copy outer frame DSCP to inner on decap. */
923#define TABLE_FIELD_ID_DECAP_DSCP_COPY 0x8e
924/* enum: True to map outer frame ECN to inner on decap, by RFC 6040 rules. */
925#define TABLE_FIELD_ID_DECAP_ECN_RFC6040 0x8f
926/* enum: True to replace DSCP field. */
927#define TABLE_FIELD_ID_DO_REPLACE_DSCP 0x90
928/* enum: True to replace ECN field. */
929#define TABLE_FIELD_ID_DO_REPLACE_ECN 0x91
930/* enum: True to decrement IP Time-To-Live. */
931#define TABLE_FIELD_ID_DO_DECR_IP_TTL 0x92
932/* enum: True to replace source MAC address. */
933#define TABLE_FIELD_ID_DO_SRC_MAC 0x93
934/* enum: True to replace destination MAC address. */
935#define TABLE_FIELD_ID_DO_DST_MAC 0x94
936/* enum: Number of VLAN tags to pop. Valid values are 0, 1, or 2. */
937#define TABLE_FIELD_ID_DO_VLAN_POP 0x95
938/* enum: Number of VLANs tags to push. Valid values are 0, 1, or 2. */
939#define TABLE_FIELD_ID_DO_VLAN_PUSH 0x96
940/* enum: True to count this packet. */
941#define TABLE_FIELD_ID_DO_COUNT 0x97
942/* enum: True to perform tunnel encapsulation. */
943#define TABLE_FIELD_ID_DO_ENCAP 0x98
944/* enum: True to copy inner frame DSCP to outer on encap. */
945#define TABLE_FIELD_ID_ENCAP_DSCP_COPY 0x99
946/* enum: True to copy inner frame ECN to outer on encap. */
947#define TABLE_FIELD_ID_ENCAP_ECN_COPY 0x9a
948/* enum: True to deliver the packet (otherwise it is dropped). */
949#define TABLE_FIELD_ID_DO_DELIVER 0x9b
950/* enum: True to set the user flag in the metadata. */
951#define TABLE_FIELD_ID_DO_FLAG 0x9c
952/* enum: True to update the user mark in the metadata. */
953#define TABLE_FIELD_ID_DO_MARK 0x9d
954/* enum: True to override the capsule virtual channel for network deliveries.
955 */
956#define TABLE_FIELD_ID_DO_SET_NET_CHAN 0x9e
957/* enum: True to override the reported source m-port for host deliveries. */
958#define TABLE_FIELD_ID_DO_SET_SRC_MPORT 0x9f
959/* enum: Encap header ID for DO_ENCAP, indexing Encap_Hdr_Part1/2_Table. */
960#define TABLE_FIELD_ID_ENCAP_HDR_ID 0xaa
961/* enum: New DSCP value for DO_REPLACE_DSCP. */
962#define TABLE_FIELD_ID_DSCP_VALUE 0xab
963/* enum: If DO_REPLACE_ECN is set, the new value for the ECN field. If
964 * DO_REPLACE_ECN is not set, ECN_CONTROL[0] and ECN_CONTROL[1] are set to
965 * request remapping of ECT0 and ECT1 ECN codepoints respectively to CE.
966 */
967#define TABLE_FIELD_ID_ECN_CONTROL 0xac
968/* enum: Source MAC ID for DO_SRC_MAC, indexing Replace_Src_MAC_Table. */
969#define TABLE_FIELD_ID_SRC_MAC_ID 0xad
970/* enum: Destination MAC ID for DO_DST_MAC, indexing Replace_Dst_MAC_Table. */
971#define TABLE_FIELD_ID_DST_MAC_ID 0xae
972/* enum: Parameter for either DO_SET_NET_CHAN (only bottom 6 bits used in this
973 * case) or DO_SET_SRC_MPORT.
974 */
975#define TABLE_FIELD_ID_REPORTED_SRC_MPORT_OR_NET_CHAN 0xaf
976/* enum: 64-byte chunk of added encapsulation header. */
977#define TABLE_FIELD_ID_CHUNK64 0xb4
978/* enum: 32-byte chunk of added encapsulation header. */
979#define TABLE_FIELD_ID_CHUNK32 0xb5
980/* enum: 16-byte chunk of added encapsulation header. */
981#define TABLE_FIELD_ID_CHUNK16 0xb6
982/* enum: 8-byte chunk of added encapsulation header. */
983#define TABLE_FIELD_ID_CHUNK8 0xb7
984/* enum: 4-byte chunk of added encapsulation header. */
985#define TABLE_FIELD_ID_CHUNK4 0xb8
986/* enum: 2-byte chunk of added encapsulation header. */
987#define TABLE_FIELD_ID_CHUNK2 0xb9
988/* enum: Added encapsulation header length in words. */
989#define TABLE_FIELD_ID_HDR_LEN_W 0xba
990/* enum: Static value for layer 2/3 LACP hash of the encapsulation header. */
991#define TABLE_FIELD_ID_ENC_LACP_HASH_L23 0xbb
992/* enum: Static value for layer 4 LACP hash of the encapsulation header. */
993#define TABLE_FIELD_ID_ENC_LACP_HASH_L4 0xbc
994/* enum: True to use the static ENC_LACP_HASH values for the encap header
995 * instead of the calculated values for the inner frame when delivering a newly
996 * encapsulated packet to a LAG m-port.
997 */
998#define TABLE_FIELD_ID_USE_ENC_LACP_HASHES 0xbd
999/* enum: True to trigger conntrack from first action rule lookup (AR=>CT=>AR
1000 * sequence).
1001 */
1002#define TABLE_FIELD_ID_DO_CT 0xc8
1003/* enum: True to perform NAT using parameters from conntrack lookup response.
1004 */
1005#define TABLE_FIELD_ID_DO_NAT 0xc9
1006/* enum: True to trigger recirculated action rule lookup (AR=>AR sequence). */
1007#define TABLE_FIELD_ID_DO_RECIRC 0xca
1008/* enum: Next action set payload ID for replay. The null value is all-1-bits.
1009 */
1010#define TABLE_FIELD_ID_NEXT_ACTION_SET_PAYLOAD 0xcb
1011/* enum: Next action set row ID for replay. The null value is all-1-bits. */
1012#define TABLE_FIELD_ID_NEXT_ACTION_SET_ROW 0xcc
1013/* enum: Action set payload ID for additional delivery to management CPU. The
1014 * null value is all-1-bits.
1015 */
1016#define TABLE_FIELD_ID_MC_ACTION_SET_PAYLOAD 0xcd
1017/* enum: Action set row ID for additional delivery to management CPU. The null
1018 * value is all-1-bits.
1019 */
1020#define TABLE_FIELD_ID_MC_ACTION_SET_ROW 0xce
1021/* enum: True to include layer 4 in LACP hash on delivery to a LAG m-port. */
1022#define TABLE_FIELD_ID_LACP_INC_L4 0xdc
1023/* enum: True to request that LACP is performed by a plugin. */
1024#define TABLE_FIELD_ID_LACP_PLUGIN 0xdd
1025/* enum: LACP_Balance_Table base address divided by 64. */
1026#define TABLE_FIELD_ID_BAL_TBL_BASE_DIV64 0xde
1027/* enum: Length of balance table region: 0=>64, 1=>128, 2=>256. */
1028#define TABLE_FIELD_ID_BAL_TBL_LEN_ID 0xdf
1029/* enum: UDP port to match for UDP-based encapsulations; required to be 0 for
1030 * other encapsulation types.
1031 */
1032#define TABLE_FIELD_ID_UDP_PORT 0xe6
1033/* enum: True to perform RSS based on outer fields rather than inner fields. */
1034#define TABLE_FIELD_ID_RSS_ON_OUTER 0xe7
1035/* enum: True to perform steering table lookup on outer fields rather than
1036 * inner fields.
1037 */
1038#define TABLE_FIELD_ID_STEER_ON_OUTER 0xe8
1039/* enum: Destination queue ID for host delivery. */
1040#define TABLE_FIELD_ID_DST_QID 0xf0
1041/* enum: True to drop this packet. */
1042#define TABLE_FIELD_ID_DROP 0xf1
1043/* enum: True to strip outer VLAN tag from this packet. */
1044#define TABLE_FIELD_ID_VLAN_STRIP 0xf2
1045/* enum: True to override the user mark field with the supplied USER_MARK, or
1046 * false to bitwise-OR the USER_MARK into it.
1047 */
1048#define TABLE_FIELD_ID_MARK_OVERRIDE 0xf3
1049/* enum: True to override the user flag field with the supplied USER_FLAG, or
1050 * false to bitwise-OR the USER_FLAG into it.
1051 */
1052#define TABLE_FIELD_ID_FLAG_OVERRIDE 0xf4
1053/* enum: RSS context ID, indexing the RSS_Context_Table. */
1054#define TABLE_FIELD_ID_RSS_CTX_ID 0xfa
1055/* enum: True to enable RSS. */
1056#define TABLE_FIELD_ID_RSS_EN 0xfb
1057/* enum: Toeplitz hash key. */
1058#define TABLE_FIELD_ID_KEY 0xfc
1059/* enum: Key mode for IPv4 TCP packets - see TABLE_RSS_KEY_MODE enum. */
1060#define TABLE_FIELD_ID_TCP_V4_KEY_MODE 0xfd
1061/* enum: Key mode for IPv6 TCP packets - see TABLE_RSS_KEY_MODE enum. */
1062#define TABLE_FIELD_ID_TCP_V6_KEY_MODE 0xfe
1063/* enum: Key mode for IPv4 UDP packets - see TABLE_RSS_KEY_MODE enum. */
1064#define TABLE_FIELD_ID_UDP_V4_KEY_MODE 0xff
1065/* enum: Key mode for IPv6 UDP packets - see TABLE_RSS_KEY_MODE enum. */
1066#define TABLE_FIELD_ID_UDP_V6_KEY_MODE 0x100
1067/* enum: Key mode for other IPv4 packets - see TABLE_RSS_KEY_MODE enum. */
1068#define TABLE_FIELD_ID_OTHER_V4_KEY_MODE 0x101
1069/* enum: Key mode for other IPv6 packets - see TABLE_RSS_KEY_MODE enum. */
1070#define TABLE_FIELD_ID_OTHER_V6_KEY_MODE 0x102
1071/* enum: Spreading mode - 0=>indirection; 1=>even. */
1072#define TABLE_FIELD_ID_SPREAD_MODE 0x103
1073/* enum: For indirection spreading mode, the base address of a region within
1074 * the Indirection_Table. For even spreading mode, the number of queues to
1075 * spread across (only values 1-255 are valid for this mode).
1076 */
1077#define TABLE_FIELD_ID_INDIR_TBL_BASE 0x104
1078/* enum: For indirection spreading mode, identifies the length of a region
1079 * within the Indirection_Table, where length = 32 << len_id. Must be set to 0
1080 * for even spreading mode.
1081 */
1082#define TABLE_FIELD_ID_INDIR_TBL_LEN_ID 0x105
1083/* enum: An offset to be applied to the base destination queue ID. */
1084#define TABLE_FIELD_ID_INDIR_OFFSET 0x106
1085
1086/* MCDI_EVENT structuredef: The structure of an MCDI_EVENT on Siena/EF10/EF100
1087 * platforms
1088 */
1089#define MCDI_EVENT_LEN 8
1090#define MCDI_EVENT_CONT_LBN 32
1091#define MCDI_EVENT_CONT_WIDTH 1
1092#define MCDI_EVENT_LEVEL_LBN 33
1093#define MCDI_EVENT_LEVEL_WIDTH 3
1094/* enum: Info. */
1095#define MCDI_EVENT_LEVEL_INFO 0x0
1096/* enum: Warning. */
1097#define MCDI_EVENT_LEVEL_WARN 0x1
1098/* enum: Error. */
1099#define MCDI_EVENT_LEVEL_ERR 0x2
1100/* enum: Fatal. */
1101#define MCDI_EVENT_LEVEL_FATAL 0x3
1102#define MCDI_EVENT_DATA_OFST 0
1103#define MCDI_EVENT_DATA_LEN 4
1104#define MCDI_EVENT_CMDDONE_SEQ_OFST 0
1105#define MCDI_EVENT_CMDDONE_SEQ_LBN 0
1106#define MCDI_EVENT_CMDDONE_SEQ_WIDTH 8
1107#define MCDI_EVENT_CMDDONE_DATALEN_OFST 0
1108#define MCDI_EVENT_CMDDONE_DATALEN_LBN 8
1109#define MCDI_EVENT_CMDDONE_DATALEN_WIDTH 8
1110#define MCDI_EVENT_CMDDONE_ERRNO_OFST 0
1111#define MCDI_EVENT_CMDDONE_ERRNO_LBN 16
1112#define MCDI_EVENT_CMDDONE_ERRNO_WIDTH 8
1113#define MCDI_EVENT_LINKCHANGE_LP_CAP_OFST 0
1114#define MCDI_EVENT_LINKCHANGE_LP_CAP_LBN 0
1115#define MCDI_EVENT_LINKCHANGE_LP_CAP_WIDTH 16
1116#define MCDI_EVENT_LINKCHANGE_SPEED_OFST 0
1117#define MCDI_EVENT_LINKCHANGE_SPEED_LBN 16
1118#define MCDI_EVENT_LINKCHANGE_SPEED_WIDTH 4
1119/* enum: Link is down or link speed could not be determined */
1120#define MCDI_EVENT_LINKCHANGE_SPEED_UNKNOWN 0x0
1121/* enum: 100Mbs */
1122#define MCDI_EVENT_LINKCHANGE_SPEED_100M 0x1
1123/* enum: 1Gbs */
1124#define MCDI_EVENT_LINKCHANGE_SPEED_1G 0x2
1125/* enum: 10Gbs */
1126#define MCDI_EVENT_LINKCHANGE_SPEED_10G 0x3
1127/* enum: 40Gbs */
1128#define MCDI_EVENT_LINKCHANGE_SPEED_40G 0x4
1129/* enum: 25Gbs */
1130#define MCDI_EVENT_LINKCHANGE_SPEED_25G 0x5
1131/* enum: 50Gbs */
1132#define MCDI_EVENT_LINKCHANGE_SPEED_50G 0x6
1133/* enum: 100Gbs */
1134#define MCDI_EVENT_LINKCHANGE_SPEED_100G 0x7
1135#define MCDI_EVENT_LINKCHANGE_FCNTL_OFST 0
1136#define MCDI_EVENT_LINKCHANGE_FCNTL_LBN 20
1137#define MCDI_EVENT_LINKCHANGE_FCNTL_WIDTH 4
1138#define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_OFST 0
1139#define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_LBN 24
1140#define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_WIDTH 8
1141#define MCDI_EVENT_SENSOREVT_MONITOR_OFST 0
1142#define MCDI_EVENT_SENSOREVT_MONITOR_LBN 0
1143#define MCDI_EVENT_SENSOREVT_MONITOR_WIDTH 8
1144#define MCDI_EVENT_SENSOREVT_STATE_OFST 0
1145#define MCDI_EVENT_SENSOREVT_STATE_LBN 8
1146#define MCDI_EVENT_SENSOREVT_STATE_WIDTH 8
1147#define MCDI_EVENT_SENSOREVT_VALUE_OFST 0
1148#define MCDI_EVENT_SENSOREVT_VALUE_LBN 16
1149#define MCDI_EVENT_SENSOREVT_VALUE_WIDTH 16
1150#define MCDI_EVENT_FWALERT_DATA_OFST 0
1151#define MCDI_EVENT_FWALERT_DATA_LBN 8
1152#define MCDI_EVENT_FWALERT_DATA_WIDTH 24
1153#define MCDI_EVENT_FWALERT_REASON_OFST 0
1154#define MCDI_EVENT_FWALERT_REASON_LBN 0
1155#define MCDI_EVENT_FWALERT_REASON_WIDTH 8
1156/* enum: SRAM Access. */
1157#define MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS 0x1
1158#define MCDI_EVENT_FLR_VF_OFST 0
1159#define MCDI_EVENT_FLR_VF_LBN 0
1160#define MCDI_EVENT_FLR_VF_WIDTH 8
1161#define MCDI_EVENT_TX_ERR_TXQ_OFST 0
1162#define MCDI_EVENT_TX_ERR_TXQ_LBN 0
1163#define MCDI_EVENT_TX_ERR_TXQ_WIDTH 12
1164#define MCDI_EVENT_TX_ERR_TYPE_OFST 0
1165#define MCDI_EVENT_TX_ERR_TYPE_LBN 12
1166#define MCDI_EVENT_TX_ERR_TYPE_WIDTH 4
1167/* enum: Descriptor loader reported failure. Specific to EF10-family NICs. */
1168#define MCDI_EVENT_TX_ERR_DL_FAIL 0x1
1169/* enum: Descriptor ring empty and no EOP seen for packet. Specific to
1170 * EF10-family NICs
1171 */
1172#define MCDI_EVENT_TX_ERR_NO_EOP 0x2
1173/* enum: Overlength packet. Specific to EF10-family NICs. */
1174#define MCDI_EVENT_TX_ERR_2BIG 0x3
1175/* enum: Malformed option descriptor. Specific to EF10-family NICs. */
1176#define MCDI_EVENT_TX_BAD_OPTDESC 0x5
1177/* enum: Option descriptor part way through a packet. Specific to EF10-family
1178 * NICs.
1179 */
1180#define MCDI_EVENT_TX_OPT_IN_PKT 0x8
1181/* enum: DMA or PIO data access error. Specific to EF10-family NICs */
1182#define MCDI_EVENT_TX_ERR_BAD_DMA_OR_PIO 0x9
1183#define MCDI_EVENT_TX_ERR_INFO_OFST 0
1184#define MCDI_EVENT_TX_ERR_INFO_LBN 16
1185#define MCDI_EVENT_TX_ERR_INFO_WIDTH 16
1186#define MCDI_EVENT_TX_FLUSH_TO_DRIVER_OFST 0
1187#define MCDI_EVENT_TX_FLUSH_TO_DRIVER_LBN 12
1188#define MCDI_EVENT_TX_FLUSH_TO_DRIVER_WIDTH 1
1189#define MCDI_EVENT_TX_FLUSH_TXQ_OFST 0
1190#define MCDI_EVENT_TX_FLUSH_TXQ_LBN 0
1191#define MCDI_EVENT_TX_FLUSH_TXQ_WIDTH 12
1192#define MCDI_EVENT_PTP_ERR_TYPE_OFST 0
1193#define MCDI_EVENT_PTP_ERR_TYPE_LBN 0
1194#define MCDI_EVENT_PTP_ERR_TYPE_WIDTH 8
1195/* enum: PLL lost lock */
1196#define MCDI_EVENT_PTP_ERR_PLL_LOST 0x1
1197/* enum: Filter overflow (PDMA) */
1198#define MCDI_EVENT_PTP_ERR_FILTER 0x2
1199/* enum: FIFO overflow (FPGA) */
1200#define MCDI_EVENT_PTP_ERR_FIFO 0x3
1201/* enum: Merge queue overflow */
1202#define MCDI_EVENT_PTP_ERR_QUEUE 0x4
1203#define MCDI_EVENT_AOE_ERR_TYPE_OFST 0
1204#define MCDI_EVENT_AOE_ERR_TYPE_LBN 0
1205#define MCDI_EVENT_AOE_ERR_TYPE_WIDTH 8
1206/* enum: AOE failed to load - no valid image? */
1207#define MCDI_EVENT_AOE_NO_LOAD 0x1
1208/* enum: AOE FC reported an exception */
1209#define MCDI_EVENT_AOE_FC_ASSERT 0x2
1210/* enum: AOE FC watchdogged */
1211#define MCDI_EVENT_AOE_FC_WATCHDOG 0x3
1212/* enum: AOE FC failed to start */
1213#define MCDI_EVENT_AOE_FC_NO_START 0x4
1214/* enum: Generic AOE fault - likely to have been reported via other means too
1215 * but intended for use by aoex driver.
1216 */
1217#define MCDI_EVENT_AOE_FAULT 0x5
1218/* enum: Results of reprogramming the CPLD (status in AOE_ERR_DATA) */
1219#define MCDI_EVENT_AOE_CPLD_REPROGRAMMED 0x6
1220/* enum: AOE loaded successfully */
1221#define MCDI_EVENT_AOE_LOAD 0x7
1222/* enum: AOE DMA operation completed (LSB of HOST_HANDLE in AOE_ERR_DATA) */
1223#define MCDI_EVENT_AOE_DMA 0x8
1224/* enum: AOE byteblaster connected/disconnected (Connection status in
1225 * AOE_ERR_DATA)
1226 */
1227#define MCDI_EVENT_AOE_BYTEBLASTER 0x9
1228/* enum: DDR ECC status update */
1229#define MCDI_EVENT_AOE_DDR_ECC_STATUS 0xa
1230/* enum: PTP status update */
1231#define MCDI_EVENT_AOE_PTP_STATUS 0xb
1232/* enum: FPGA header incorrect */
1233#define MCDI_EVENT_AOE_FPGA_LOAD_HEADER_ERR 0xc
1234/* enum: FPGA Powered Off due to error in powering up FPGA */
1235#define MCDI_EVENT_AOE_FPGA_POWER_OFF 0xd
1236/* enum: AOE FPGA load failed due to MC to MUM communication failure */
1237#define MCDI_EVENT_AOE_FPGA_LOAD_FAILED 0xe
1238/* enum: Notify that invalid flash type detected */
1239#define MCDI_EVENT_AOE_INVALID_FPGA_FLASH_TYPE 0xf
1240/* enum: Notify that the attempt to run FPGA Controller firmware timedout */
1241#define MCDI_EVENT_AOE_FC_RUN_TIMEDOUT 0x10
1242/* enum: Failure to probe one or more FPGA boot flash chips */
1243#define MCDI_EVENT_AOE_FPGA_BOOT_FLASH_INVALID 0x11
1244/* enum: FPGA boot-flash contains an invalid image header */
1245#define MCDI_EVENT_AOE_FPGA_BOOT_FLASH_HDR_INVALID 0x12
1246/* enum: Failed to program clocks required by the FPGA */
1247#define MCDI_EVENT_AOE_FPGA_CLOCKS_PROGRAM_FAILED 0x13
1248/* enum: Notify that FPGA Controller is alive to serve MCDI requests */
1249#define MCDI_EVENT_AOE_FC_RUNNING 0x14
1250#define MCDI_EVENT_AOE_ERR_DATA_OFST 0
1251#define MCDI_EVENT_AOE_ERR_DATA_LBN 8
1252#define MCDI_EVENT_AOE_ERR_DATA_WIDTH 8
1253#define MCDI_EVENT_AOE_ERR_FC_ASSERT_INFO_OFST 0
1254#define MCDI_EVENT_AOE_ERR_FC_ASSERT_INFO_LBN 8
1255#define MCDI_EVENT_AOE_ERR_FC_ASSERT_INFO_WIDTH 8
1256/* enum: FC Assert happened, but the register information is not available */
1257#define MCDI_EVENT_AOE_ERR_FC_ASSERT_SEEN 0x0
1258/* enum: The register information for FC Assert is ready for readinng by driver
1259 */
1260#define MCDI_EVENT_AOE_ERR_FC_ASSERT_DATA_READY 0x1
1261#define MCDI_EVENT_AOE_ERR_CODE_FPGA_HEADER_VERIFY_FAILED_OFST 0
1262#define MCDI_EVENT_AOE_ERR_CODE_FPGA_HEADER_VERIFY_FAILED_LBN 8
1263#define MCDI_EVENT_AOE_ERR_CODE_FPGA_HEADER_VERIFY_FAILED_WIDTH 8
1264/* enum: Reading from NV failed */
1265#define MCDI_EVENT_AOE_ERR_FPGA_HEADER_NV_READ_FAIL 0x0
1266/* enum: Invalid Magic Number if FPGA header */
1267#define MCDI_EVENT_AOE_ERR_FPGA_HEADER_MAGIC_FAIL 0x1
1268/* enum: Invalid Silicon type detected in header */
1269#define MCDI_EVENT_AOE_ERR_FPGA_HEADER_SILICON_TYPE 0x2
1270/* enum: Unsupported VRatio */
1271#define MCDI_EVENT_AOE_ERR_FPGA_HEADER_VRATIO 0x3
1272/* enum: Unsupported DDR Type */
1273#define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_TYPE 0x4
1274/* enum: DDR Voltage out of supported range */
1275#define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_VOLTAGE 0x5
1276/* enum: Unsupported DDR speed */
1277#define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_SPEED 0x6
1278/* enum: Unsupported DDR size */
1279#define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_SIZE 0x7
1280/* enum: Unsupported DDR rank */
1281#define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_RANK 0x8
1282#define MCDI_EVENT_AOE_ERR_CODE_INVALID_FPGA_FLASH_TYPE_INFO_OFST 0
1283#define MCDI_EVENT_AOE_ERR_CODE_INVALID_FPGA_FLASH_TYPE_INFO_LBN 8
1284#define MCDI_EVENT_AOE_ERR_CODE_INVALID_FPGA_FLASH_TYPE_INFO_WIDTH 8
1285/* enum: Primary boot flash */
1286#define MCDI_EVENT_AOE_FLASH_TYPE_BOOT_PRIMARY 0x0
1287/* enum: Secondary boot flash */
1288#define MCDI_EVENT_AOE_FLASH_TYPE_BOOT_SECONDARY 0x1
1289#define MCDI_EVENT_AOE_ERR_CODE_FPGA_POWER_OFF_OFST 0
1290#define MCDI_EVENT_AOE_ERR_CODE_FPGA_POWER_OFF_LBN 8
1291#define MCDI_EVENT_AOE_ERR_CODE_FPGA_POWER_OFF_WIDTH 8
1292#define MCDI_EVENT_AOE_ERR_CODE_FPGA_LOAD_FAILED_OFST 0
1293#define MCDI_EVENT_AOE_ERR_CODE_FPGA_LOAD_FAILED_LBN 8
1294#define MCDI_EVENT_AOE_ERR_CODE_FPGA_LOAD_FAILED_WIDTH 8
1295#define MCDI_EVENT_RX_ERR_RXQ_OFST 0
1296#define MCDI_EVENT_RX_ERR_RXQ_LBN 0
1297#define MCDI_EVENT_RX_ERR_RXQ_WIDTH 12
1298#define MCDI_EVENT_RX_ERR_TYPE_OFST 0
1299#define MCDI_EVENT_RX_ERR_TYPE_LBN 12
1300#define MCDI_EVENT_RX_ERR_TYPE_WIDTH 4
1301#define MCDI_EVENT_RX_ERR_INFO_OFST 0
1302#define MCDI_EVENT_RX_ERR_INFO_LBN 16
1303#define MCDI_EVENT_RX_ERR_INFO_WIDTH 16
1304#define MCDI_EVENT_RX_FLUSH_TO_DRIVER_OFST 0
1305#define MCDI_EVENT_RX_FLUSH_TO_DRIVER_LBN 12
1306#define MCDI_EVENT_RX_FLUSH_TO_DRIVER_WIDTH 1
1307#define MCDI_EVENT_RX_FLUSH_RXQ_OFST 0
1308#define MCDI_EVENT_RX_FLUSH_RXQ_LBN 0
1309#define MCDI_EVENT_RX_FLUSH_RXQ_WIDTH 12
1310#define MCDI_EVENT_MC_REBOOT_COUNT_OFST 0
1311#define MCDI_EVENT_MC_REBOOT_COUNT_LBN 0
1312#define MCDI_EVENT_MC_REBOOT_COUNT_WIDTH 16
1313#define MCDI_EVENT_MUM_ERR_TYPE_OFST 0
1314#define MCDI_EVENT_MUM_ERR_TYPE_LBN 0
1315#define MCDI_EVENT_MUM_ERR_TYPE_WIDTH 8
1316/* enum: MUM failed to load - no valid image? */
1317#define MCDI_EVENT_MUM_NO_LOAD 0x1
1318/* enum: MUM f/w reported an exception */
1319#define MCDI_EVENT_MUM_ASSERT 0x2
1320/* enum: MUM not kicking watchdog */
1321#define MCDI_EVENT_MUM_WATCHDOG 0x3
1322#define MCDI_EVENT_MUM_ERR_DATA_OFST 0
1323#define MCDI_EVENT_MUM_ERR_DATA_LBN 8
1324#define MCDI_EVENT_MUM_ERR_DATA_WIDTH 8
1325#define MCDI_EVENT_DBRET_SEQ_OFST 0
1326#define MCDI_EVENT_DBRET_SEQ_LBN 0
1327#define MCDI_EVENT_DBRET_SEQ_WIDTH 8
1328#define MCDI_EVENT_SUC_ERR_TYPE_OFST 0
1329#define MCDI_EVENT_SUC_ERR_TYPE_LBN 0
1330#define MCDI_EVENT_SUC_ERR_TYPE_WIDTH 8
1331/* enum: Corrupted or bad SUC application. */
1332#define MCDI_EVENT_SUC_BAD_APP 0x1
1333/* enum: SUC application reported an assert. */
1334#define MCDI_EVENT_SUC_ASSERT 0x2
1335/* enum: SUC application reported an exception. */
1336#define MCDI_EVENT_SUC_EXCEPTION 0x3
1337/* enum: SUC watchdog timer expired. */
1338#define MCDI_EVENT_SUC_WATCHDOG 0x4
1339#define MCDI_EVENT_SUC_ERR_ADDRESS_OFST 0
1340#define MCDI_EVENT_SUC_ERR_ADDRESS_LBN 8
1341#define MCDI_EVENT_SUC_ERR_ADDRESS_WIDTH 24
1342#define MCDI_EVENT_SUC_ERR_DATA_OFST 0
1343#define MCDI_EVENT_SUC_ERR_DATA_LBN 8
1344#define MCDI_EVENT_SUC_ERR_DATA_WIDTH 24
1345#define MCDI_EVENT_LINKCHANGE_V2_LP_CAP_OFST 0
1346#define MCDI_EVENT_LINKCHANGE_V2_LP_CAP_LBN 0
1347#define MCDI_EVENT_LINKCHANGE_V2_LP_CAP_WIDTH 24
1348#define MCDI_EVENT_LINKCHANGE_V2_SPEED_OFST 0
1349#define MCDI_EVENT_LINKCHANGE_V2_SPEED_LBN 24
1350#define MCDI_EVENT_LINKCHANGE_V2_SPEED_WIDTH 4
1351/* Enum values, see field(s): */
1352/* MCDI_EVENT/LINKCHANGE_SPEED */
1353#define MCDI_EVENT_LINKCHANGE_V2_FLAGS_LINK_UP_OFST 0
1354#define MCDI_EVENT_LINKCHANGE_V2_FLAGS_LINK_UP_LBN 28
1355#define MCDI_EVENT_LINKCHANGE_V2_FLAGS_LINK_UP_WIDTH 1
1356#define MCDI_EVENT_LINKCHANGE_V2_FCNTL_OFST 0
1357#define MCDI_EVENT_LINKCHANGE_V2_FCNTL_LBN 29
1358#define MCDI_EVENT_LINKCHANGE_V2_FCNTL_WIDTH 3
1359/* Enum values, see field(s): */
1360/* MC_CMD_SET_MAC/MC_CMD_SET_MAC_IN/FCNTL */
1361#define MCDI_EVENT_MODULECHANGE_LD_CAP_OFST 0
1362#define MCDI_EVENT_MODULECHANGE_LD_CAP_LBN 0
1363#define MCDI_EVENT_MODULECHANGE_LD_CAP_WIDTH 30
1364#define MCDI_EVENT_MODULECHANGE_SEQ_OFST 0
1365#define MCDI_EVENT_MODULECHANGE_SEQ_LBN 30
1366#define MCDI_EVENT_MODULECHANGE_SEQ_WIDTH 2
1367#define MCDI_EVENT_DATA_LBN 0
1368#define MCDI_EVENT_DATA_WIDTH 32
1369/* Alias for PTP_DATA. */
1370#define MCDI_EVENT_SRC_LBN 36
1371#define MCDI_EVENT_SRC_WIDTH 8
1372/* Data associated with PTP events which doesn't fit into the main DATA field
1373 */
1374#define MCDI_EVENT_PTP_DATA_LBN 36
1375#define MCDI_EVENT_PTP_DATA_WIDTH 8
1376/* EF100 specific. Defined by QDMA. The phase bit, changes each time round the
1377 * event ring
1378 */
1379#define MCDI_EVENT_EV_EVQ_PHASE_LBN 59
1380#define MCDI_EVENT_EV_EVQ_PHASE_WIDTH 1
1381#define MCDI_EVENT_EV_CODE_LBN 60
1382#define MCDI_EVENT_EV_CODE_WIDTH 4
1383#define MCDI_EVENT_CODE_LBN 44
1384#define MCDI_EVENT_CODE_WIDTH 8
1385/* enum: Event generated by host software */
1386#define MCDI_EVENT_SW_EVENT 0x0
1387/* enum: Bad assert. */
1388#define MCDI_EVENT_CODE_BADSSERT 0x1
1389/* enum: PM Notice. */
1390#define MCDI_EVENT_CODE_PMNOTICE 0x2
1391/* enum: Command done. */
1392#define MCDI_EVENT_CODE_CMDDONE 0x3
1393/* enum: Link change. */
1394#define MCDI_EVENT_CODE_LINKCHANGE 0x4
1395/* enum: Sensor Event. */
1396#define MCDI_EVENT_CODE_SENSOREVT 0x5
1397/* enum: Schedule error. */
1398#define MCDI_EVENT_CODE_SCHEDERR 0x6
1399/* enum: Reboot. */
1400#define MCDI_EVENT_CODE_REBOOT 0x7
1401/* enum: Mac stats DMA. */
1402#define MCDI_EVENT_CODE_MAC_STATS_DMA 0x8
1403/* enum: Firmware alert. */
1404#define MCDI_EVENT_CODE_FWALERT 0x9
1405/* enum: Function level reset. */
1406#define MCDI_EVENT_CODE_FLR 0xa
1407/* enum: Transmit error */
1408#define MCDI_EVENT_CODE_TX_ERR 0xb
1409/* enum: Tx flush has completed */
1410#define MCDI_EVENT_CODE_TX_FLUSH 0xc
1411/* enum: PTP packet received timestamp */
1412#define MCDI_EVENT_CODE_PTP_RX 0xd
1413/* enum: PTP NIC failure */
1414#define MCDI_EVENT_CODE_PTP_FAULT 0xe
1415/* enum: PTP PPS event */
1416#define MCDI_EVENT_CODE_PTP_PPS 0xf
1417/* enum: Rx flush has completed */
1418#define MCDI_EVENT_CODE_RX_FLUSH 0x10
1419/* enum: Receive error */
1420#define MCDI_EVENT_CODE_RX_ERR 0x11
1421/* enum: AOE fault */
1422#define MCDI_EVENT_CODE_AOE 0x12
1423/* enum: Network port calibration failed (VCAL). */
1424#define MCDI_EVENT_CODE_VCAL_FAIL 0x13
1425/* enum: HW PPS event */
1426#define MCDI_EVENT_CODE_HW_PPS 0x14
1427/* enum: The MC has rebooted (huntington and later, siena uses CODE_REBOOT and
1428 * a different format)
1429 */
1430#define MCDI_EVENT_CODE_MC_REBOOT 0x15
1431/* enum: the MC has detected a parity error */
1432#define MCDI_EVENT_CODE_PAR_ERR 0x16
1433/* enum: the MC has detected a correctable error */
1434#define MCDI_EVENT_CODE_ECC_CORR_ERR 0x17
1435/* enum: the MC has detected an uncorrectable error */
1436#define MCDI_EVENT_CODE_ECC_FATAL_ERR 0x18
1437/* enum: The MC has entered offline BIST mode */
1438#define MCDI_EVENT_CODE_MC_BIST 0x19
1439/* enum: PTP tick event providing current NIC time */
1440#define MCDI_EVENT_CODE_PTP_TIME 0x1a
1441/* enum: MUM fault */
1442#define MCDI_EVENT_CODE_MUM 0x1b
1443/* enum: notify the designated PF of a new authorization request */
1444#define MCDI_EVENT_CODE_PROXY_REQUEST 0x1c
1445/* enum: notify a function that awaits an authorization that its request has
1446 * been processed and it may now resend the command
1447 */
1448#define MCDI_EVENT_CODE_PROXY_RESPONSE 0x1d
1449/* enum: MCDI command accepted. New commands can be issued but this command is
1450 * not done yet.
1451 */
1452#define MCDI_EVENT_CODE_DBRET 0x1e
1453/* enum: The MC has detected a fault on the SUC */
1454#define MCDI_EVENT_CODE_SUC 0x1f
1455/* enum: Link change. This event is sent instead of LINKCHANGE if
1456 * WANT_V2_LINKCHANGES was set on driver attach.
1457 */
1458#define MCDI_EVENT_CODE_LINKCHANGE_V2 0x20
1459/* enum: This event is sent if WANT_V2_LINKCHANGES was set on driver attach
1460 * when the local device capabilities changes. This will usually correspond to
1461 * a module change.
1462 */
1463#define MCDI_EVENT_CODE_MODULECHANGE 0x21
1464/* enum: Notification that the sensors have been added and/or removed from the
1465 * sensor table. This event includes the new sensor table generation count, if
1466 * this does not match the driver's local copy it is expected to call
1467 * DYNAMIC_SENSORS_LIST to refresh it.
1468 */
1469#define MCDI_EVENT_CODE_DYNAMIC_SENSORS_CHANGE 0x22
1470/* enum: Notification that a sensor has changed state as a result of a reading
1471 * crossing a threshold. This is sent as two events, the first event contains
1472 * the handle and the sensor's state (in the SRC field), and the second
1473 * contains the value.
1474 */
1475#define MCDI_EVENT_CODE_DYNAMIC_SENSORS_STATE_CHANGE 0x23
1476/* enum: Notification that a descriptor proxy function configuration has been
1477 * pushed to "live" status (visible to host). SRC field contains the handle of
1478 * the affected descriptor proxy function. DATA field contains the generation
1479 * count of configuration set applied. See MC_CMD_DESC_PROXY_FUNC_CONFIG_SET /
1480 * MC_CMD_DESC_PROXY_FUNC_CONFIG_COMMIT and SF-122927-TC for details.
1481 */
1482#define MCDI_EVENT_CODE_DESC_PROXY_FUNC_CONFIG_COMMITTED 0x24
1483/* enum: Notification that a descriptor proxy function has been reset. SRC
1484 * field contains the handle of the affected descriptor proxy function. See
1485 * SF-122927-TC for details.
1486 */
1487#define MCDI_EVENT_CODE_DESC_PROXY_FUNC_RESET 0x25
1488/* enum: Notification that a driver attached to a descriptor proxy function.
1489 * SRC field contains the handle of the affected descriptor proxy function. For
1490 * Virtio proxy functions this message consists of two MCDI events, where the
1491 * first event's (CONT=1) DATA field carries negotiated virtio feature bits 0
1492 * to 31 and the second (CONT=0) carries bits 32 to 63. For EF100 proxy
1493 * functions event length and meaning of DATA field is not yet defined. See
1494 * SF-122927-TC for details.
1495 */
1496#define MCDI_EVENT_CODE_DESC_PROXY_FUNC_DRIVER_ATTACH 0x26
1497/* enum: Notification that the mport journal has changed since it was last read
1498 * and updates can be read using the MC_CMD_MAE_MPORT_READ_JOURNAL command. The
1499 * firmware may moderate the events so that an event is not sent for every
1500 * change to the journal.
1501 */
1502#define MCDI_EVENT_CODE_MPORT_JOURNAL_CHANGE 0x27
1503/* enum: Artificial event generated by host and posted via MC for test
1504 * purposes.
1505 */
1506#define MCDI_EVENT_CODE_TESTGEN 0xfa
1507#define MCDI_EVENT_CMDDONE_DATA_OFST 0
1508#define MCDI_EVENT_CMDDONE_DATA_LEN 4
1509#define MCDI_EVENT_CMDDONE_DATA_LBN 0
1510#define MCDI_EVENT_CMDDONE_DATA_WIDTH 32
1511#define MCDI_EVENT_LINKCHANGE_DATA_OFST 0
1512#define MCDI_EVENT_LINKCHANGE_DATA_LEN 4
1513#define MCDI_EVENT_LINKCHANGE_DATA_LBN 0
1514#define MCDI_EVENT_LINKCHANGE_DATA_WIDTH 32
1515#define MCDI_EVENT_SENSOREVT_DATA_OFST 0
1516#define MCDI_EVENT_SENSOREVT_DATA_LEN 4
1517#define MCDI_EVENT_SENSOREVT_DATA_LBN 0
1518#define MCDI_EVENT_SENSOREVT_DATA_WIDTH 32
1519#define MCDI_EVENT_MAC_STATS_DMA_GENERATION_OFST 0
1520#define MCDI_EVENT_MAC_STATS_DMA_GENERATION_LEN 4
1521#define MCDI_EVENT_MAC_STATS_DMA_GENERATION_LBN 0
1522#define MCDI_EVENT_MAC_STATS_DMA_GENERATION_WIDTH 32
1523#define MCDI_EVENT_TX_ERR_DATA_OFST 0
1524#define MCDI_EVENT_TX_ERR_DATA_LEN 4
1525#define MCDI_EVENT_TX_ERR_DATA_LBN 0
1526#define MCDI_EVENT_TX_ERR_DATA_WIDTH 32
1527/* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the seconds field of
1528 * timestamp
1529 */
1530#define MCDI_EVENT_PTP_SECONDS_OFST 0
1531#define MCDI_EVENT_PTP_SECONDS_LEN 4
1532#define MCDI_EVENT_PTP_SECONDS_LBN 0
1533#define MCDI_EVENT_PTP_SECONDS_WIDTH 32
1534/* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the major field of
1535 * timestamp
1536 */
1537#define MCDI_EVENT_PTP_MAJOR_OFST 0
1538#define MCDI_EVENT_PTP_MAJOR_LEN 4
1539#define MCDI_EVENT_PTP_MAJOR_LBN 0
1540#define MCDI_EVENT_PTP_MAJOR_WIDTH 32
1541/* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the nanoseconds field
1542 * of timestamp
1543 */
1544#define MCDI_EVENT_PTP_NANOSECONDS_OFST 0
1545#define MCDI_EVENT_PTP_NANOSECONDS_LEN 4
1546#define MCDI_EVENT_PTP_NANOSECONDS_LBN 0
1547#define MCDI_EVENT_PTP_NANOSECONDS_WIDTH 32
1548/* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the minor field of
1549 * timestamp
1550 */
1551#define MCDI_EVENT_PTP_MINOR_OFST 0
1552#define MCDI_EVENT_PTP_MINOR_LEN 4
1553#define MCDI_EVENT_PTP_MINOR_LBN 0
1554#define MCDI_EVENT_PTP_MINOR_WIDTH 32
1555/* For CODE_PTP_RX events, the lowest four bytes of sourceUUID from PTP packet
1556 */
1557#define MCDI_EVENT_PTP_UUID_OFST 0
1558#define MCDI_EVENT_PTP_UUID_LEN 4
1559#define MCDI_EVENT_PTP_UUID_LBN 0
1560#define MCDI_EVENT_PTP_UUID_WIDTH 32
1561#define MCDI_EVENT_RX_ERR_DATA_OFST 0
1562#define MCDI_EVENT_RX_ERR_DATA_LEN 4
1563#define MCDI_EVENT_RX_ERR_DATA_LBN 0
1564#define MCDI_EVENT_RX_ERR_DATA_WIDTH 32
1565#define MCDI_EVENT_PAR_ERR_DATA_OFST 0
1566#define MCDI_EVENT_PAR_ERR_DATA_LEN 4
1567#define MCDI_EVENT_PAR_ERR_DATA_LBN 0
1568#define MCDI_EVENT_PAR_ERR_DATA_WIDTH 32
1569#define MCDI_EVENT_ECC_CORR_ERR_DATA_OFST 0
1570#define MCDI_EVENT_ECC_CORR_ERR_DATA_LEN 4
1571#define MCDI_EVENT_ECC_CORR_ERR_DATA_LBN 0
1572#define MCDI_EVENT_ECC_CORR_ERR_DATA_WIDTH 32
1573#define MCDI_EVENT_ECC_FATAL_ERR_DATA_OFST 0
1574#define MCDI_EVENT_ECC_FATAL_ERR_DATA_LEN 4
1575#define MCDI_EVENT_ECC_FATAL_ERR_DATA_LBN 0
1576#define MCDI_EVENT_ECC_FATAL_ERR_DATA_WIDTH 32
1577/* For CODE_PTP_TIME events, the major value of the PTP clock */
1578#define MCDI_EVENT_PTP_TIME_MAJOR_OFST 0
1579#define MCDI_EVENT_PTP_TIME_MAJOR_LEN 4
1580#define MCDI_EVENT_PTP_TIME_MAJOR_LBN 0
1581#define MCDI_EVENT_PTP_TIME_MAJOR_WIDTH 32
1582/* For CODE_PTP_TIME events, bits 19-26 of the minor value of the PTP clock */
1583#define MCDI_EVENT_PTP_TIME_MINOR_26_19_LBN 36
1584#define MCDI_EVENT_PTP_TIME_MINOR_26_19_WIDTH 8
1585/* For CODE_PTP_TIME events, most significant bits of the minor value of the
1586 * PTP clock. This is a more generic equivalent of PTP_TIME_MINOR_26_19.
1587 */
1588#define MCDI_EVENT_PTP_TIME_MINOR_MS_8BITS_LBN 36
1589#define MCDI_EVENT_PTP_TIME_MINOR_MS_8BITS_WIDTH 8
1590/* For CODE_PTP_TIME events where report sync status is enabled, indicates
1591 * whether the NIC clock has ever been set
1592 */
1593#define MCDI_EVENT_PTP_TIME_NIC_CLOCK_VALID_LBN 36
1594#define MCDI_EVENT_PTP_TIME_NIC_CLOCK_VALID_WIDTH 1
1595/* For CODE_PTP_TIME events where report sync status is enabled, indicates
1596 * whether the NIC and System clocks are in sync
1597 */
1598#define MCDI_EVENT_PTP_TIME_HOST_NIC_IN_SYNC_LBN 37
1599#define MCDI_EVENT_PTP_TIME_HOST_NIC_IN_SYNC_WIDTH 1
1600/* For CODE_PTP_TIME events where report sync status is enabled, bits 21-26 of
1601 * the minor value of the PTP clock
1602 */
1603#define MCDI_EVENT_PTP_TIME_MINOR_26_21_LBN 38
1604#define MCDI_EVENT_PTP_TIME_MINOR_26_21_WIDTH 6
1605/* For CODE_PTP_TIME events, most significant bits of the minor value of the
1606 * PTP clock. This is a more generic equivalent of PTP_TIME_MINOR_26_21.
1607 */
1608#define MCDI_EVENT_PTP_TIME_MINOR_MS_6BITS_LBN 38
1609#define MCDI_EVENT_PTP_TIME_MINOR_MS_6BITS_WIDTH 6
1610#define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_OFST 0
1611#define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_LEN 4
1612#define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_LBN 0
1613#define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_WIDTH 32
1614#define MCDI_EVENT_PROXY_RESPONSE_HANDLE_OFST 0
1615#define MCDI_EVENT_PROXY_RESPONSE_HANDLE_LEN 4
1616#define MCDI_EVENT_PROXY_RESPONSE_HANDLE_LBN 0
1617#define MCDI_EVENT_PROXY_RESPONSE_HANDLE_WIDTH 32
1618/* Zero means that the request has been completed or authorized, and the driver
1619 * should resend it. A non-zero value means that the authorization has been
1620 * denied, and gives the reason. Typically it will be EPERM.
1621 */
1622#define MCDI_EVENT_PROXY_RESPONSE_RC_LBN 36
1623#define MCDI_EVENT_PROXY_RESPONSE_RC_WIDTH 8
1624#define MCDI_EVENT_DBRET_DATA_OFST 0
1625#define MCDI_EVENT_DBRET_DATA_LEN 4
1626#define MCDI_EVENT_DBRET_DATA_LBN 0
1627#define MCDI_EVENT_DBRET_DATA_WIDTH 32
1628#define MCDI_EVENT_LINKCHANGE_V2_DATA_OFST 0
1629#define MCDI_EVENT_LINKCHANGE_V2_DATA_LEN 4
1630#define MCDI_EVENT_LINKCHANGE_V2_DATA_LBN 0
1631#define MCDI_EVENT_LINKCHANGE_V2_DATA_WIDTH 32
1632#define MCDI_EVENT_MODULECHANGE_DATA_OFST 0
1633#define MCDI_EVENT_MODULECHANGE_DATA_LEN 4
1634#define MCDI_EVENT_MODULECHANGE_DATA_LBN 0
1635#define MCDI_EVENT_MODULECHANGE_DATA_WIDTH 32
1636/* The new generation count after a sensor has been added or deleted. */
1637#define MCDI_EVENT_DYNAMIC_SENSORS_GENERATION_OFST 0
1638#define MCDI_EVENT_DYNAMIC_SENSORS_GENERATION_LEN 4
1639#define MCDI_EVENT_DYNAMIC_SENSORS_GENERATION_LBN 0
1640#define MCDI_EVENT_DYNAMIC_SENSORS_GENERATION_WIDTH 32
1641/* The handle of a dynamic sensor. */
1642#define MCDI_EVENT_DYNAMIC_SENSORS_HANDLE_OFST 0
1643#define MCDI_EVENT_DYNAMIC_SENSORS_HANDLE_LEN 4
1644#define MCDI_EVENT_DYNAMIC_SENSORS_HANDLE_LBN 0
1645#define MCDI_EVENT_DYNAMIC_SENSORS_HANDLE_WIDTH 32
1646/* The current values of a sensor. */
1647#define MCDI_EVENT_DYNAMIC_SENSORS_VALUE_OFST 0
1648#define MCDI_EVENT_DYNAMIC_SENSORS_VALUE_LEN 4
1649#define MCDI_EVENT_DYNAMIC_SENSORS_VALUE_LBN 0
1650#define MCDI_EVENT_DYNAMIC_SENSORS_VALUE_WIDTH 32
1651/* The current state of a sensor. */
1652#define MCDI_EVENT_DYNAMIC_SENSORS_STATE_LBN 36
1653#define MCDI_EVENT_DYNAMIC_SENSORS_STATE_WIDTH 8
1654#define MCDI_EVENT_DESC_PROXY_DATA_OFST 0
1655#define MCDI_EVENT_DESC_PROXY_DATA_LEN 4
1656#define MCDI_EVENT_DESC_PROXY_DATA_LBN 0
1657#define MCDI_EVENT_DESC_PROXY_DATA_WIDTH 32
1658/* Generation count of applied configuration set */
1659#define MCDI_EVENT_DESC_PROXY_GENERATION_OFST 0
1660#define MCDI_EVENT_DESC_PROXY_GENERATION_LEN 4
1661#define MCDI_EVENT_DESC_PROXY_GENERATION_LBN 0
1662#define MCDI_EVENT_DESC_PROXY_GENERATION_WIDTH 32
1663/* Virtio features negotiated with the host driver. First event (CONT=1)
1664 * carries bits 0 to 31. Second event (CONT=0) carries bits 32 to 63.
1665 */
1666#define MCDI_EVENT_DESC_PROXY_VIRTIO_FEATURES_OFST 0
1667#define MCDI_EVENT_DESC_PROXY_VIRTIO_FEATURES_LEN 4
1668#define MCDI_EVENT_DESC_PROXY_VIRTIO_FEATURES_LBN 0
1669#define MCDI_EVENT_DESC_PROXY_VIRTIO_FEATURES_WIDTH 32
1670
1671/* FCDI_EVENT structuredef */
1672#define FCDI_EVENT_LEN 8
1673#define FCDI_EVENT_CONT_LBN 32
1674#define FCDI_EVENT_CONT_WIDTH 1
1675#define FCDI_EVENT_LEVEL_LBN 33
1676#define FCDI_EVENT_LEVEL_WIDTH 3
1677/* enum: Info. */
1678#define FCDI_EVENT_LEVEL_INFO 0x0
1679/* enum: Warning. */
1680#define FCDI_EVENT_LEVEL_WARN 0x1
1681/* enum: Error. */
1682#define FCDI_EVENT_LEVEL_ERR 0x2
1683/* enum: Fatal. */
1684#define FCDI_EVENT_LEVEL_FATAL 0x3
1685#define FCDI_EVENT_DATA_OFST 0
1686#define FCDI_EVENT_DATA_LEN 4
1687#define FCDI_EVENT_LINK_STATE_STATUS_OFST 0
1688#define FCDI_EVENT_LINK_STATE_STATUS_LBN 0
1689#define FCDI_EVENT_LINK_STATE_STATUS_WIDTH 1
1690#define FCDI_EVENT_LINK_DOWN 0x0 /* enum */
1691#define FCDI_EVENT_LINK_UP 0x1 /* enum */
1692#define FCDI_EVENT_DATA_LBN 0
1693#define FCDI_EVENT_DATA_WIDTH 32
1694#define FCDI_EVENT_SRC_LBN 36
1695#define FCDI_EVENT_SRC_WIDTH 8
1696#define FCDI_EVENT_EV_CODE_LBN 60
1697#define FCDI_EVENT_EV_CODE_WIDTH 4
1698#define FCDI_EVENT_CODE_LBN 44
1699#define FCDI_EVENT_CODE_WIDTH 8
1700/* enum: The FC was rebooted. */
1701#define FCDI_EVENT_CODE_REBOOT 0x1
1702/* enum: Bad assert. */
1703#define FCDI_EVENT_CODE_ASSERT 0x2
1704/* enum: DDR3 test result. */
1705#define FCDI_EVENT_CODE_DDR_TEST_RESULT 0x3
1706/* enum: Link status. */
1707#define FCDI_EVENT_CODE_LINK_STATE 0x4
1708/* enum: A timed read is ready to be serviced. */
1709#define FCDI_EVENT_CODE_TIMED_READ 0x5
1710/* enum: One or more PPS IN events */
1711#define FCDI_EVENT_CODE_PPS_IN 0x6
1712/* enum: Tick event from PTP clock */
1713#define FCDI_EVENT_CODE_PTP_TICK 0x7
1714/* enum: ECC error counters */
1715#define FCDI_EVENT_CODE_DDR_ECC_STATUS 0x8
1716/* enum: Current status of PTP */
1717#define FCDI_EVENT_CODE_PTP_STATUS 0x9
1718/* enum: Port id config to map MC-FC port idx */
1719#define FCDI_EVENT_CODE_PORT_CONFIG 0xa
1720/* enum: Boot result or error code */
1721#define FCDI_EVENT_CODE_BOOT_RESULT 0xb
1722#define FCDI_EVENT_REBOOT_SRC_LBN 36
1723#define FCDI_EVENT_REBOOT_SRC_WIDTH 8
1724#define FCDI_EVENT_REBOOT_FC_FW 0x0 /* enum */
1725#define FCDI_EVENT_REBOOT_FC_BOOTLOADER 0x1 /* enum */
1726#define FCDI_EVENT_ASSERT_INSTR_ADDRESS_OFST 0
1727#define FCDI_EVENT_ASSERT_INSTR_ADDRESS_LEN 4
1728#define FCDI_EVENT_ASSERT_INSTR_ADDRESS_LBN 0
1729#define FCDI_EVENT_ASSERT_INSTR_ADDRESS_WIDTH 32
1730#define FCDI_EVENT_ASSERT_TYPE_LBN 36
1731#define FCDI_EVENT_ASSERT_TYPE_WIDTH 8
1732#define FCDI_EVENT_DDR_TEST_RESULT_STATUS_CODE_LBN 36
1733#define FCDI_EVENT_DDR_TEST_RESULT_STATUS_CODE_WIDTH 8
1734#define FCDI_EVENT_DDR_TEST_RESULT_RESULT_OFST 0
1735#define FCDI_EVENT_DDR_TEST_RESULT_RESULT_LEN 4
1736#define FCDI_EVENT_DDR_TEST_RESULT_RESULT_LBN 0
1737#define FCDI_EVENT_DDR_TEST_RESULT_RESULT_WIDTH 32
1738#define FCDI_EVENT_LINK_STATE_DATA_OFST 0
1739#define FCDI_EVENT_LINK_STATE_DATA_LEN 4
1740#define FCDI_EVENT_LINK_STATE_DATA_LBN 0
1741#define FCDI_EVENT_LINK_STATE_DATA_WIDTH 32
1742#define FCDI_EVENT_PTP_STATE_OFST 0
1743#define FCDI_EVENT_PTP_STATE_LEN 4
1744#define FCDI_EVENT_PTP_UNDEFINED 0x0 /* enum */
1745#define FCDI_EVENT_PTP_SETUP_FAILED 0x1 /* enum */
1746#define FCDI_EVENT_PTP_OPERATIONAL 0x2 /* enum */
1747#define FCDI_EVENT_PTP_STATE_LBN 0
1748#define FCDI_EVENT_PTP_STATE_WIDTH 32
1749#define FCDI_EVENT_DDR_ECC_STATUS_BANK_ID_LBN 36
1750#define FCDI_EVENT_DDR_ECC_STATUS_BANK_ID_WIDTH 8
1751#define FCDI_EVENT_DDR_ECC_STATUS_STATUS_OFST 0
1752#define FCDI_EVENT_DDR_ECC_STATUS_STATUS_LEN 4
1753#define FCDI_EVENT_DDR_ECC_STATUS_STATUS_LBN 0
1754#define FCDI_EVENT_DDR_ECC_STATUS_STATUS_WIDTH 32
1755/* Index of MC port being referred to */
1756#define FCDI_EVENT_PORT_CONFIG_SRC_LBN 36
1757#define FCDI_EVENT_PORT_CONFIG_SRC_WIDTH 8
1758/* FC Port index that matches the MC port index in SRC */
1759#define FCDI_EVENT_PORT_CONFIG_DATA_OFST 0
1760#define FCDI_EVENT_PORT_CONFIG_DATA_LEN 4
1761#define FCDI_EVENT_PORT_CONFIG_DATA_LBN 0
1762#define FCDI_EVENT_PORT_CONFIG_DATA_WIDTH 32
1763#define FCDI_EVENT_BOOT_RESULT_OFST 0
1764#define FCDI_EVENT_BOOT_RESULT_LEN 4
1765/* Enum values, see field(s): */
1766/* MC_CMD_AOE/MC_CMD_AOE_OUT_INFO/FC_BOOT_RESULT */
1767#define FCDI_EVENT_BOOT_RESULT_LBN 0
1768#define FCDI_EVENT_BOOT_RESULT_WIDTH 32
1769
1770/* FCDI_EXTENDED_EVENT_PPS structuredef: Extended FCDI event to send PPS events
1771 * to the MC. Note that this structure | is overlayed over a normal FCDI event
1772 * such that bits 32-63 containing | event code, level, source etc remain the
1773 * same. In this case the data | field of the header is defined to be the
1774 * number of timestamps
1775 */
1776#define FCDI_EXTENDED_EVENT_PPS_LENMIN 16
1777#define FCDI_EXTENDED_EVENT_PPS_LENMAX 248
1778#define FCDI_EXTENDED_EVENT_PPS_LENMAX_MCDI2 1016
1779#define FCDI_EXTENDED_EVENT_PPS_LEN(num) (8+8*(num))
1780#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_NUM(len) (((len)-8)/8)
1781/* Number of timestamps following */
1782#define FCDI_EXTENDED_EVENT_PPS_COUNT_OFST 0
1783#define FCDI_EXTENDED_EVENT_PPS_COUNT_LEN 4
1784#define FCDI_EXTENDED_EVENT_PPS_COUNT_LBN 0
1785#define FCDI_EXTENDED_EVENT_PPS_COUNT_WIDTH 32
1786/* Seconds field of a timestamp record */
1787#define FCDI_EXTENDED_EVENT_PPS_SECONDS_OFST 8
1788#define FCDI_EXTENDED_EVENT_PPS_SECONDS_LEN 4
1789#define FCDI_EXTENDED_EVENT_PPS_SECONDS_LBN 64
1790#define FCDI_EXTENDED_EVENT_PPS_SECONDS_WIDTH 32
1791/* Nanoseconds field of a timestamp record */
1792#define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_OFST 12
1793#define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_LEN 4
1794#define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_LBN 96
1795#define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_WIDTH 32
1796/* Timestamp records comprising the event */
1797#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_OFST 8
1798#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LEN 8
1799#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LO_OFST 8
1800#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LO_LEN 4
1801#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LO_LBN 64
1802#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LO_WIDTH 32
1803#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_HI_OFST 12
1804#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_HI_LEN 4
1805#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_HI_LBN 96
1806#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_HI_WIDTH 32
1807#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MINNUM 1
1808#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MAXNUM 30
1809#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MAXNUM_MCDI2 126
1810#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LBN 64
1811#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_WIDTH 64
1812
1813/* MUM_EVENT structuredef */
1814#define MUM_EVENT_LEN 8
1815#define MUM_EVENT_CONT_LBN 32
1816#define MUM_EVENT_CONT_WIDTH 1
1817#define MUM_EVENT_LEVEL_LBN 33
1818#define MUM_EVENT_LEVEL_WIDTH 3
1819/* enum: Info. */
1820#define MUM_EVENT_LEVEL_INFO 0x0
1821/* enum: Warning. */
1822#define MUM_EVENT_LEVEL_WARN 0x1
1823/* enum: Error. */
1824#define MUM_EVENT_LEVEL_ERR 0x2
1825/* enum: Fatal. */
1826#define MUM_EVENT_LEVEL_FATAL 0x3
1827#define MUM_EVENT_DATA_OFST 0
1828#define MUM_EVENT_DATA_LEN 4
1829#define MUM_EVENT_SENSOR_ID_OFST 0
1830#define MUM_EVENT_SENSOR_ID_LBN 0
1831#define MUM_EVENT_SENSOR_ID_WIDTH 8
1832/* Enum values, see field(s): */
1833/* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */
1834#define MUM_EVENT_SENSOR_STATE_OFST 0
1835#define MUM_EVENT_SENSOR_STATE_LBN 8
1836#define MUM_EVENT_SENSOR_STATE_WIDTH 8
1837#define MUM_EVENT_PORT_PHY_READY_OFST 0
1838#define MUM_EVENT_PORT_PHY_READY_LBN 0
1839#define MUM_EVENT_PORT_PHY_READY_WIDTH 1
1840#define MUM_EVENT_PORT_PHY_LINK_UP_OFST 0
1841#define MUM_EVENT_PORT_PHY_LINK_UP_LBN 1
1842#define MUM_EVENT_PORT_PHY_LINK_UP_WIDTH 1
1843#define MUM_EVENT_PORT_PHY_TX_LOL_OFST 0
1844#define MUM_EVENT_PORT_PHY_TX_LOL_LBN 2
1845#define MUM_EVENT_PORT_PHY_TX_LOL_WIDTH 1
1846#define MUM_EVENT_PORT_PHY_RX_LOL_OFST 0
1847#define MUM_EVENT_PORT_PHY_RX_LOL_LBN 3
1848#define MUM_EVENT_PORT_PHY_RX_LOL_WIDTH 1
1849#define MUM_EVENT_PORT_PHY_TX_LOS_OFST 0
1850#define MUM_EVENT_PORT_PHY_TX_LOS_LBN 4
1851#define MUM_EVENT_PORT_PHY_TX_LOS_WIDTH 1
1852#define MUM_EVENT_PORT_PHY_RX_LOS_OFST 0
1853#define MUM_EVENT_PORT_PHY_RX_LOS_LBN 5
1854#define MUM_EVENT_PORT_PHY_RX_LOS_WIDTH 1
1855#define MUM_EVENT_PORT_PHY_TX_FAULT_OFST 0
1856#define MUM_EVENT_PORT_PHY_TX_FAULT_LBN 6
1857#define MUM_EVENT_PORT_PHY_TX_FAULT_WIDTH 1
1858#define MUM_EVENT_DATA_LBN 0
1859#define MUM_EVENT_DATA_WIDTH 32
1860#define MUM_EVENT_SRC_LBN 36
1861#define MUM_EVENT_SRC_WIDTH 8
1862#define MUM_EVENT_EV_CODE_LBN 60
1863#define MUM_EVENT_EV_CODE_WIDTH 4
1864#define MUM_EVENT_CODE_LBN 44
1865#define MUM_EVENT_CODE_WIDTH 8
1866/* enum: The MUM was rebooted. */
1867#define MUM_EVENT_CODE_REBOOT 0x1
1868/* enum: Bad assert. */
1869#define MUM_EVENT_CODE_ASSERT 0x2
1870/* enum: Sensor failure. */
1871#define MUM_EVENT_CODE_SENSOR 0x3
1872/* enum: Link fault has been asserted, or has cleared. */
1873#define MUM_EVENT_CODE_QSFP_LASI_INTERRUPT 0x4
1874#define MUM_EVENT_SENSOR_DATA_OFST 0
1875#define MUM_EVENT_SENSOR_DATA_LEN 4
1876#define MUM_EVENT_SENSOR_DATA_LBN 0
1877#define MUM_EVENT_SENSOR_DATA_WIDTH 32
1878#define MUM_EVENT_PORT_PHY_FLAGS_OFST 0
1879#define MUM_EVENT_PORT_PHY_FLAGS_LEN 4
1880#define MUM_EVENT_PORT_PHY_FLAGS_LBN 0
1881#define MUM_EVENT_PORT_PHY_FLAGS_WIDTH 32
1882#define MUM_EVENT_PORT_PHY_COPPER_LEN_OFST 0
1883#define MUM_EVENT_PORT_PHY_COPPER_LEN_LEN 4
1884#define MUM_EVENT_PORT_PHY_COPPER_LEN_LBN 0
1885#define MUM_EVENT_PORT_PHY_COPPER_LEN_WIDTH 32
1886#define MUM_EVENT_PORT_PHY_CAPS_OFST 0
1887#define MUM_EVENT_PORT_PHY_CAPS_LEN 4
1888#define MUM_EVENT_PORT_PHY_CAPS_LBN 0
1889#define MUM_EVENT_PORT_PHY_CAPS_WIDTH 32
1890#define MUM_EVENT_PORT_PHY_TECH_OFST 0
1891#define MUM_EVENT_PORT_PHY_TECH_LEN 4
1892#define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_UNKNOWN 0x0 /* enum */
1893#define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_OPTICAL 0x1 /* enum */
1894#define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_PASSIVE 0x2 /* enum */
1895#define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_PASSIVE_EQUALIZED 0x3 /* enum */
1896#define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_ACTIVE_LIMITING 0x4 /* enum */
1897#define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_ACTIVE_LINEAR 0x5 /* enum */
1898#define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_BASE_T 0x6 /* enum */
1899#define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_LOOPBACK_PASSIVE 0x7 /* enum */
1900#define MUM_EVENT_PORT_PHY_TECH_LBN 0
1901#define MUM_EVENT_PORT_PHY_TECH_WIDTH 32
1902#define MUM_EVENT_PORT_PHY_SRC_DATA_ID_LBN 36
1903#define MUM_EVENT_PORT_PHY_SRC_DATA_ID_WIDTH 4
1904#define MUM_EVENT_PORT_PHY_SRC_DATA_ID_FLAGS 0x0 /* enum */
1905#define MUM_EVENT_PORT_PHY_SRC_DATA_ID_COPPER_LEN 0x1 /* enum */
1906#define MUM_EVENT_PORT_PHY_SRC_DATA_ID_CAPS 0x2 /* enum */
1907#define MUM_EVENT_PORT_PHY_SRC_DATA_ID_TECH 0x3 /* enum */
1908#define MUM_EVENT_PORT_PHY_SRC_DATA_ID_MAX 0x4 /* enum */
1909#define MUM_EVENT_PORT_PHY_SRC_PORT_NO_LBN 40
1910#define MUM_EVENT_PORT_PHY_SRC_PORT_NO_WIDTH 4
1911
1912
1913/***********************************/
1914/* MC_CMD_READ32
1915 * Read multiple 32byte words from MC memory. Note - this command really
1916 * belongs to INSECURE category but is required by shmboot. The command handler
1917 * has additional checks to reject insecure calls.
1918 */
1919#define MC_CMD_READ32 0x1
1920#undef MC_CMD_0x1_PRIVILEGE_CTG
1921
1922#define MC_CMD_0x1_PRIVILEGE_CTG SRIOV_CTG_ADMIN
1923
1924/* MC_CMD_READ32_IN msgrequest */
1925#define MC_CMD_READ32_IN_LEN 8
1926#define MC_CMD_READ32_IN_ADDR_OFST 0
1927#define MC_CMD_READ32_IN_ADDR_LEN 4
1928#define MC_CMD_READ32_IN_NUMWORDS_OFST 4
1929#define MC_CMD_READ32_IN_NUMWORDS_LEN 4
1930
1931/* MC_CMD_READ32_OUT msgresponse */
1932#define MC_CMD_READ32_OUT_LENMIN 4
1933#define MC_CMD_READ32_OUT_LENMAX 252
1934#define MC_CMD_READ32_OUT_LENMAX_MCDI2 1020
1935#define MC_CMD_READ32_OUT_LEN(num) (0+4*(num))
1936#define MC_CMD_READ32_OUT_BUFFER_NUM(len) (((len)-0)/4)
1937#define MC_CMD_READ32_OUT_BUFFER_OFST 0
1938#define MC_CMD_READ32_OUT_BUFFER_LEN 4
1939#define MC_CMD_READ32_OUT_BUFFER_MINNUM 1
1940#define MC_CMD_READ32_OUT_BUFFER_MAXNUM 63
1941#define MC_CMD_READ32_OUT_BUFFER_MAXNUM_MCDI2 255
1942
1943
1944/***********************************/
1945/* MC_CMD_WRITE32
1946 * Write multiple 32byte words to MC memory.
1947 */
1948#define MC_CMD_WRITE32 0x2
1949#undef MC_CMD_0x2_PRIVILEGE_CTG
1950
1951#define MC_CMD_0x2_PRIVILEGE_CTG SRIOV_CTG_INSECURE
1952
1953/* MC_CMD_WRITE32_IN msgrequest */
1954#define MC_CMD_WRITE32_IN_LENMIN 8
1955#define MC_CMD_WRITE32_IN_LENMAX 252
1956#define MC_CMD_WRITE32_IN_LENMAX_MCDI2 1020
1957#define MC_CMD_WRITE32_IN_LEN(num) (4+4*(num))
1958#define MC_CMD_WRITE32_IN_BUFFER_NUM(len) (((len)-4)/4)
1959#define MC_CMD_WRITE32_IN_ADDR_OFST 0
1960#define MC_CMD_WRITE32_IN_ADDR_LEN 4
1961#define MC_CMD_WRITE32_IN_BUFFER_OFST 4
1962#define MC_CMD_WRITE32_IN_BUFFER_LEN 4
1963#define MC_CMD_WRITE32_IN_BUFFER_MINNUM 1
1964#define MC_CMD_WRITE32_IN_BUFFER_MAXNUM 62
1965#define MC_CMD_WRITE32_IN_BUFFER_MAXNUM_MCDI2 254
1966
1967/* MC_CMD_WRITE32_OUT msgresponse */
1968#define MC_CMD_WRITE32_OUT_LEN 0
1969
1970
1971/***********************************/
1972/* MC_CMD_COPYCODE
1973 * Copy MC code between two locations and jump. Note - this command really
1974 * belongs to INSECURE category but is required by shmboot. The command handler
1975 * has additional checks to reject insecure calls.
1976 */
1977#define MC_CMD_COPYCODE 0x3
1978#undef MC_CMD_0x3_PRIVILEGE_CTG
1979
1980#define MC_CMD_0x3_PRIVILEGE_CTG SRIOV_CTG_ADMIN
1981
1982/* MC_CMD_COPYCODE_IN msgrequest */
1983#define MC_CMD_COPYCODE_IN_LEN 16
1984/* Source address
1985 *
1986 * The main image should be entered via a copy of a single word from and to a
1987 * magic address, which controls various aspects of the boot. The magic address
1988 * is a bitfield, with each bit as documented below.
1989 */
1990#define MC_CMD_COPYCODE_IN_SRC_ADDR_OFST 0
1991#define MC_CMD_COPYCODE_IN_SRC_ADDR_LEN 4
1992/* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT (see below) */
1993#define MC_CMD_COPYCODE_HUNT_NO_MAGIC_ADDR 0x10000
1994/* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT and
1995 * BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED (see below)
1996 */
1997#define MC_CMD_COPYCODE_HUNT_NO_DATAPATH_MAGIC_ADDR 0x1d0d0
1998/* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT,
1999 * BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED and BOOT_MAGIC_IGNORE_CONFIG (see
2000 * below)
2001 */
2002#define MC_CMD_COPYCODE_HUNT_IGNORE_CONFIG_MAGIC_ADDR 0x1badc
2003#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_PRESENT_OFST 0
2004#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_PRESENT_LBN 17
2005#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_PRESENT_WIDTH 1
2006#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED_OFST 0
2007#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED_LBN 2
2008#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED_WIDTH 1
2009#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_IGNORE_CONFIG_OFST 0
2010#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_IGNORE_CONFIG_LBN 3
2011#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_IGNORE_CONFIG_WIDTH 1
2012#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_OFST 0
2013#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_LBN 4
2014#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_WIDTH 1
2015#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_FORCE_STANDALONE_OFST 0
2016#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_FORCE_STANDALONE_LBN 5
2017#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_FORCE_STANDALONE_WIDTH 1
2018#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_DISABLE_XIP_OFST 0
2019#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_DISABLE_XIP_LBN 6
2020#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_DISABLE_XIP_WIDTH 1
2021/* Destination address */
2022#define MC_CMD_COPYCODE_IN_DEST_ADDR_OFST 4
2023#define MC_CMD_COPYCODE_IN_DEST_ADDR_LEN 4
2024#define MC_CMD_COPYCODE_IN_NUMWORDS_OFST 8
2025#define MC_CMD_COPYCODE_IN_NUMWORDS_LEN 4
2026/* Address of where to jump after copy. */
2027#define MC_CMD_COPYCODE_IN_JUMP_OFST 12
2028#define MC_CMD_COPYCODE_IN_JUMP_LEN 4
2029/* enum: Control should return to the caller rather than jumping */
2030#define MC_CMD_COPYCODE_JUMP_NONE 0x1
2031
2032/* MC_CMD_COPYCODE_OUT msgresponse */
2033#define MC_CMD_COPYCODE_OUT_LEN 0
2034
2035
2036/***********************************/
2037/* MC_CMD_SET_FUNC
2038 * Select function for function-specific commands.
2039 */
2040#define MC_CMD_SET_FUNC 0x4
2041#undef MC_CMD_0x4_PRIVILEGE_CTG
2042
2043#define MC_CMD_0x4_PRIVILEGE_CTG SRIOV_CTG_INSECURE
2044
2045/* MC_CMD_SET_FUNC_IN msgrequest */
2046#define MC_CMD_SET_FUNC_IN_LEN 4
2047/* Set function */
2048#define MC_CMD_SET_FUNC_IN_FUNC_OFST 0
2049#define MC_CMD_SET_FUNC_IN_FUNC_LEN 4
2050
2051/* MC_CMD_SET_FUNC_OUT msgresponse */
2052#define MC_CMD_SET_FUNC_OUT_LEN 0
2053
2054
2055/***********************************/
2056/* MC_CMD_GET_BOOT_STATUS
2057 * Get the instruction address from which the MC booted.
2058 */
2059#define MC_CMD_GET_BOOT_STATUS 0x5
2060#undef MC_CMD_0x5_PRIVILEGE_CTG
2061
2062#define MC_CMD_0x5_PRIVILEGE_CTG SRIOV_CTG_GENERAL
2063
2064/* MC_CMD_GET_BOOT_STATUS_IN msgrequest */
2065#define MC_CMD_GET_BOOT_STATUS_IN_LEN 0
2066
2067/* MC_CMD_GET_BOOT_STATUS_OUT msgresponse */
2068#define MC_CMD_GET_BOOT_STATUS_OUT_LEN 8
2069/* ?? */
2070#define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_OFST 0
2071#define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_LEN 4
2072/* enum: indicates that the MC wasn't flash booted */
2073#define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_NULL 0xdeadbeef
2074#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_OFST 4
2075#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_LEN 4
2076#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_OFST 4
2077#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_LBN 0
2078#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_WIDTH 1
2079#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_OFST 4
2080#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_LBN 1
2081#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_WIDTH 1
2082#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_OFST 4
2083#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_LBN 2
2084#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_WIDTH 1
2085
2086
2087/***********************************/
2088/* MC_CMD_GET_ASSERTS
2089 * Get (and optionally clear) the current assertion status. Only
2090 * OUT.GLOBAL_FLAGS is guaranteed to exist in the completion payload. The other
2091 * fields will only be present if OUT.GLOBAL_FLAGS != NO_FAILS
2092 */
2093#define MC_CMD_GET_ASSERTS 0x6
2094#undef MC_CMD_0x6_PRIVILEGE_CTG
2095
2096#define MC_CMD_0x6_PRIVILEGE_CTG SRIOV_CTG_ADMIN
2097
2098/* MC_CMD_GET_ASSERTS_IN msgrequest */
2099#define MC_CMD_GET_ASSERTS_IN_LEN 4
2100/* Set to clear assertion */
2101#define MC_CMD_GET_ASSERTS_IN_CLEAR_OFST 0
2102#define MC_CMD_GET_ASSERTS_IN_CLEAR_LEN 4
2103
2104/* MC_CMD_GET_ASSERTS_OUT msgresponse */
2105#define MC_CMD_GET_ASSERTS_OUT_LEN 140
2106/* Assertion status flag. */
2107#define MC_CMD_GET_ASSERTS_OUT_GLOBAL_FLAGS_OFST 0
2108#define MC_CMD_GET_ASSERTS_OUT_GLOBAL_FLAGS_LEN 4
2109/* enum: No assertions have failed. */
2110#define MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x1
2111/* enum: A system-level assertion has failed. */
2112#define MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 0x2
2113/* enum: A thread-level assertion has failed. */
2114#define MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 0x3
2115/* enum: The system was reset by the watchdog. */
2116#define MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 0x4
2117/* enum: An illegal address trap stopped the system (huntington and later) */
2118#define MC_CMD_GET_ASSERTS_FLAGS_ADDR_TRAP 0x5
2119/* Failing PC value */
2120#define MC_CMD_GET_ASSERTS_OUT_SAVED_PC_OFFS_OFST 4
2121#define MC_CMD_GET_ASSERTS_OUT_SAVED_PC_OFFS_LEN 4
2122/* Saved GP regs */
2123#define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_OFST 8
2124#define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_LEN 4
2125#define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_NUM 31
2126/* enum: A magic value hinting that the value in this register at the time of
2127 * the failure has likely been lost.
2128 */
2129#define MC_CMD_GET_ASSERTS_REG_NO_DATA 0xda7a1057
2130/* Failing thread address */
2131#define MC_CMD_GET_ASSERTS_OUT_THREAD_OFFS_OFST 132
2132#define MC_CMD_GET_ASSERTS_OUT_THREAD_OFFS_LEN 4
2133#define MC_CMD_GET_ASSERTS_OUT_RESERVED_OFST 136
2134#define MC_CMD_GET_ASSERTS_OUT_RESERVED_LEN 4
2135
2136/* MC_CMD_GET_ASSERTS_OUT_V2 msgresponse: Extended response for MicroBlaze CPUs
2137 * found on Riverhead designs
2138 */
2139#define MC_CMD_GET_ASSERTS_OUT_V2_LEN 240
2140/* Assertion status flag. */
2141#define MC_CMD_GET_ASSERTS_OUT_V2_GLOBAL_FLAGS_OFST 0
2142#define MC_CMD_GET_ASSERTS_OUT_V2_GLOBAL_FLAGS_LEN 4
2143/* enum: No assertions have failed. */
2144/* MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x1 */
2145/* enum: A system-level assertion has failed. */
2146/* MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 0x2 */
2147/* enum: A thread-level assertion has failed. */
2148/* MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 0x3 */
2149/* enum: The system was reset by the watchdog. */
2150/* MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 0x4 */
2151/* enum: An illegal address trap stopped the system (huntington and later) */
2152/* MC_CMD_GET_ASSERTS_FLAGS_ADDR_TRAP 0x5 */
2153/* Failing PC value */
2154#define MC_CMD_GET_ASSERTS_OUT_V2_SAVED_PC_OFFS_OFST 4
2155#define MC_CMD_GET_ASSERTS_OUT_V2_SAVED_PC_OFFS_LEN 4
2156/* Saved GP regs */
2157#define MC_CMD_GET_ASSERTS_OUT_V2_GP_REGS_OFFS_OFST 8
2158#define MC_CMD_GET_ASSERTS_OUT_V2_GP_REGS_OFFS_LEN 4
2159#define MC_CMD_GET_ASSERTS_OUT_V2_GP_REGS_OFFS_NUM 31
2160/* enum: A magic value hinting that the value in this register at the time of
2161 * the failure has likely been lost.
2162 */
2163/* MC_CMD_GET_ASSERTS_REG_NO_DATA 0xda7a1057 */
2164/* Failing thread address */
2165#define MC_CMD_GET_ASSERTS_OUT_V2_THREAD_OFFS_OFST 132
2166#define MC_CMD_GET_ASSERTS_OUT_V2_THREAD_OFFS_LEN 4
2167#define MC_CMD_GET_ASSERTS_OUT_V2_RESERVED_OFST 136
2168#define MC_CMD_GET_ASSERTS_OUT_V2_RESERVED_LEN 4
2169/* Saved Special Function Registers */
2170#define MC_CMD_GET_ASSERTS_OUT_V2_SF_REGS_OFFS_OFST 136
2171#define MC_CMD_GET_ASSERTS_OUT_V2_SF_REGS_OFFS_LEN 4
2172#define MC_CMD_GET_ASSERTS_OUT_V2_SF_REGS_OFFS_NUM 26
2173
2174/* MC_CMD_GET_ASSERTS_OUT_V3 msgresponse: Extended response with asserted
2175 * firmware version information
2176 */
2177#define MC_CMD_GET_ASSERTS_OUT_V3_LEN 360
2178/* Assertion status flag. */
2179#define MC_CMD_GET_ASSERTS_OUT_V3_GLOBAL_FLAGS_OFST 0
2180#define MC_CMD_GET_ASSERTS_OUT_V3_GLOBAL_FLAGS_LEN 4
2181/* enum: No assertions have failed. */
2182/* MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x1 */
2183/* enum: A system-level assertion has failed. */
2184/* MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 0x2 */
2185/* enum: A thread-level assertion has failed. */
2186/* MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 0x3 */
2187/* enum: The system was reset by the watchdog. */
2188/* MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 0x4 */
2189/* enum: An illegal address trap stopped the system (huntington and later) */
2190/* MC_CMD_GET_ASSERTS_FLAGS_ADDR_TRAP 0x5 */
2191/* Failing PC value */
2192#define MC_CMD_GET_ASSERTS_OUT_V3_SAVED_PC_OFFS_OFST 4
2193#define MC_CMD_GET_ASSERTS_OUT_V3_SAVED_PC_OFFS_LEN 4
2194/* Saved GP regs */
2195#define MC_CMD_GET_ASSERTS_OUT_V3_GP_REGS_OFFS_OFST 8
2196#define MC_CMD_GET_ASSERTS_OUT_V3_GP_REGS_OFFS_LEN 4
2197#define MC_CMD_GET_ASSERTS_OUT_V3_GP_REGS_OFFS_NUM 31
2198/* enum: A magic value hinting that the value in this register at the time of
2199 * the failure has likely been lost.
2200 */
2201/* MC_CMD_GET_ASSERTS_REG_NO_DATA 0xda7a1057 */
2202/* Failing thread address */
2203#define MC_CMD_GET_ASSERTS_OUT_V3_THREAD_OFFS_OFST 132
2204#define MC_CMD_GET_ASSERTS_OUT_V3_THREAD_OFFS_LEN 4
2205#define MC_CMD_GET_ASSERTS_OUT_V3_RESERVED_OFST 136
2206#define MC_CMD_GET_ASSERTS_OUT_V3_RESERVED_LEN 4
2207/* Saved Special Function Registers */
2208#define MC_CMD_GET_ASSERTS_OUT_V3_SF_REGS_OFFS_OFST 136
2209#define MC_CMD_GET_ASSERTS_OUT_V3_SF_REGS_OFFS_LEN 4
2210#define MC_CMD_GET_ASSERTS_OUT_V3_SF_REGS_OFFS_NUM 26
2211/* MC firmware unique build ID (as binary SHA-1 value) */
2212#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_ID_OFST 240
2213#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_ID_LEN 20
2214/* MC firmware build date (as Unix timestamp) */
2215#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_OFST 260
2216#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_LEN 8
2217#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_LO_OFST 260
2218#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_LO_LEN 4
2219#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_LO_LBN 2080
2220#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_LO_WIDTH 32
2221#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_HI_OFST 264
2222#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_HI_LEN 4
2223#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_HI_LBN 2112
2224#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_HI_WIDTH 32
2225/* MC firmware version number */
2226#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_OFST 268
2227#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_LEN 8
2228#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_LO_OFST 268
2229#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_LO_LEN 4
2230#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_LO_LBN 2144
2231#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_LO_WIDTH 32
2232#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_HI_OFST 272
2233#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_HI_LEN 4
2234#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_HI_LBN 2176
2235#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_HI_WIDTH 32
2236/* MC firmware security level */
2237#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_SECURITY_LEVEL_OFST 276
2238#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_SECURITY_LEVEL_LEN 4
2239/* MC firmware extra version info (as null-terminated US-ASCII string) */
2240#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_EXTRA_INFO_OFST 280
2241#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_EXTRA_INFO_LEN 16
2242/* MC firmware build name (as null-terminated US-ASCII string) */
2243#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_NAME_OFST 296
2244#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_NAME_LEN 64
2245
2246
2247/***********************************/
2248/* MC_CMD_LOG_CTRL
2249 * Configure the output stream for log events such as link state changes,
2250 * sensor notifications and MCDI completions
2251 */
2252#define MC_CMD_LOG_CTRL 0x7
2253#undef MC_CMD_0x7_PRIVILEGE_CTG
2254
2255#define MC_CMD_0x7_PRIVILEGE_CTG SRIOV_CTG_GENERAL
2256
2257/* MC_CMD_LOG_CTRL_IN msgrequest */
2258#define MC_CMD_LOG_CTRL_IN_LEN 8
2259/* Log destination */
2260#define MC_CMD_LOG_CTRL_IN_LOG_DEST_OFST 0
2261#define MC_CMD_LOG_CTRL_IN_LOG_DEST_LEN 4
2262/* enum: UART. */
2263#define MC_CMD_LOG_CTRL_IN_LOG_DEST_UART 0x1
2264/* enum: Event queue. */
2265#define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ 0x2
2266/* Legacy argument. Must be zero. */
2267#define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ_OFST 4
2268#define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ_LEN 4
2269
2270/* MC_CMD_LOG_CTRL_OUT msgresponse */
2271#define MC_CMD_LOG_CTRL_OUT_LEN 0
2272
2273
2274/***********************************/
2275/* MC_CMD_GET_VERSION
2276 * Get version information about adapter components.
2277 */
2278#define MC_CMD_GET_VERSION 0x8
2279#undef MC_CMD_0x8_PRIVILEGE_CTG
2280
2281#define MC_CMD_0x8_PRIVILEGE_CTG SRIOV_CTG_GENERAL
2282
2283/* MC_CMD_GET_VERSION_IN msgrequest */
2284#define MC_CMD_GET_VERSION_IN_LEN 0
2285
2286/* MC_CMD_GET_VERSION_EXT_IN msgrequest: Asks for the extended version */
2287#define MC_CMD_GET_VERSION_EXT_IN_LEN 4
2288/* placeholder, set to 0 */
2289#define MC_CMD_GET_VERSION_EXT_IN_EXT_FLAGS_OFST 0
2290#define MC_CMD_GET_VERSION_EXT_IN_EXT_FLAGS_LEN 4
2291
2292/* MC_CMD_GET_VERSION_V0_OUT msgresponse: deprecated version format */
2293#define MC_CMD_GET_VERSION_V0_OUT_LEN 4
2294#define MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0
2295#define MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4
2296/* enum: Reserved version number to indicate "any" version. */
2297#define MC_CMD_GET_VERSION_OUT_FIRMWARE_ANY 0xffffffff
2298/* enum: Bootrom version value for Siena. */
2299#define MC_CMD_GET_VERSION_OUT_FIRMWARE_SIENA_BOOTROM 0xb0070000
2300/* enum: Bootrom version value for Huntington. */
2301#define MC_CMD_GET_VERSION_OUT_FIRMWARE_HUNT_BOOTROM 0xb0070001
2302/* enum: Bootrom version value for Medford2. */
2303#define MC_CMD_GET_VERSION_OUT_FIRMWARE_MEDFORD2_BOOTROM 0xb0070002
2304
2305/* MC_CMD_GET_VERSION_OUT msgresponse */
2306#define MC_CMD_GET_VERSION_OUT_LEN 32
2307/* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */
2308/* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */
2309/* Enum values, see field(s): */
2310/* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */
2311#define MC_CMD_GET_VERSION_OUT_PCOL_OFST 4
2312#define MC_CMD_GET_VERSION_OUT_PCOL_LEN 4
2313/* 128bit mask of functions supported by the current firmware */
2314#define MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_OFST 8
2315#define MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_LEN 16
2316#define MC_CMD_GET_VERSION_OUT_VERSION_OFST 24
2317#define MC_CMD_GET_VERSION_OUT_VERSION_LEN 8
2318#define MC_CMD_GET_VERSION_OUT_VERSION_LO_OFST 24
2319#define MC_CMD_GET_VERSION_OUT_VERSION_LO_LEN 4
2320#define MC_CMD_GET_VERSION_OUT_VERSION_LO_LBN 192
2321#define MC_CMD_GET_VERSION_OUT_VERSION_LO_WIDTH 32
2322#define MC_CMD_GET_VERSION_OUT_VERSION_HI_OFST 28
2323#define MC_CMD_GET_VERSION_OUT_VERSION_HI_LEN 4
2324#define MC_CMD_GET_VERSION_OUT_VERSION_HI_LBN 224
2325#define MC_CMD_GET_VERSION_OUT_VERSION_HI_WIDTH 32
2326
2327/* MC_CMD_GET_VERSION_EXT_OUT msgresponse */
2328#define MC_CMD_GET_VERSION_EXT_OUT_LEN 48
2329/* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */
2330/* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */
2331/* Enum values, see field(s): */
2332/* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */
2333#define MC_CMD_GET_VERSION_EXT_OUT_PCOL_OFST 4
2334#define MC_CMD_GET_VERSION_EXT_OUT_PCOL_LEN 4
2335/* 128bit mask of functions supported by the current firmware */
2336#define MC_CMD_GET_VERSION_EXT_OUT_SUPPORTED_FUNCS_OFST 8
2337#define MC_CMD_GET_VERSION_EXT_OUT_SUPPORTED_FUNCS_LEN 16
2338#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_OFST 24
2339#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LEN 8
2340#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LO_OFST 24
2341#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LO_LEN 4
2342#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LO_LBN 192
2343#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LO_WIDTH 32
2344#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_HI_OFST 28
2345#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_HI_LEN 4
2346#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_HI_LBN 224
2347#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_HI_WIDTH 32
2348/* extra info */
2349#define MC_CMD_GET_VERSION_EXT_OUT_EXTRA_OFST 32
2350#define MC_CMD_GET_VERSION_EXT_OUT_EXTRA_LEN 16
2351
2352/* MC_CMD_GET_VERSION_V2_OUT msgresponse: Extended response providing version
2353 * information for all adapter components. For Riverhead based designs, base MC
2354 * firmware version fields refer to NMC firmware, while CMC firmware data is in
2355 * dedicated CMC fields. Flags indicate which data is present in the response
2356 * (depending on which components exist on a particular adapter)
2357 */
2358#define MC_CMD_GET_VERSION_V2_OUT_LEN 304
2359/* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */
2360/* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */
2361/* Enum values, see field(s): */
2362/* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */
2363#define MC_CMD_GET_VERSION_V2_OUT_PCOL_OFST 4
2364#define MC_CMD_GET_VERSION_V2_OUT_PCOL_LEN 4
2365/* 128bit mask of functions supported by the current firmware */
2366#define MC_CMD_GET_VERSION_V2_OUT_SUPPORTED_FUNCS_OFST 8
2367#define MC_CMD_GET_VERSION_V2_OUT_SUPPORTED_FUNCS_LEN 16
2368#define MC_CMD_GET_VERSION_V2_OUT_VERSION_OFST 24
2369#define MC_CMD_GET_VERSION_V2_OUT_VERSION_LEN 8
2370#define MC_CMD_GET_VERSION_V2_OUT_VERSION_LO_OFST 24
2371#define MC_CMD_GET_VERSION_V2_OUT_VERSION_LO_LEN 4
2372#define MC_CMD_GET_VERSION_V2_OUT_VERSION_LO_LBN 192
2373#define MC_CMD_GET_VERSION_V2_OUT_VERSION_LO_WIDTH 32
2374#define MC_CMD_GET_VERSION_V2_OUT_VERSION_HI_OFST 28
2375#define MC_CMD_GET_VERSION_V2_OUT_VERSION_HI_LEN 4
2376#define MC_CMD_GET_VERSION_V2_OUT_VERSION_HI_LBN 224
2377#define MC_CMD_GET_VERSION_V2_OUT_VERSION_HI_WIDTH 32
2378/* extra info */
2379#define MC_CMD_GET_VERSION_V2_OUT_EXTRA_OFST 32
2380#define MC_CMD_GET_VERSION_V2_OUT_EXTRA_LEN 16
2381/* Flags indicating which extended fields are valid */
2382#define MC_CMD_GET_VERSION_V2_OUT_FLAGS_OFST 48
2383#define MC_CMD_GET_VERSION_V2_OUT_FLAGS_LEN 4
2384#define MC_CMD_GET_VERSION_V2_OUT_MCFW_EXT_INFO_PRESENT_OFST 48
2385#define MC_CMD_GET_VERSION_V2_OUT_MCFW_EXT_INFO_PRESENT_LBN 0
2386#define MC_CMD_GET_VERSION_V2_OUT_MCFW_EXT_INFO_PRESENT_WIDTH 1
2387#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_EXT_INFO_PRESENT_OFST 48
2388#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_EXT_INFO_PRESENT_LBN 1
2389#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_EXT_INFO_PRESENT_WIDTH 1
2390#define MC_CMD_GET_VERSION_V2_OUT_CMC_EXT_INFO_PRESENT_OFST 48
2391#define MC_CMD_GET_VERSION_V2_OUT_CMC_EXT_INFO_PRESENT_LBN 2
2392#define MC_CMD_GET_VERSION_V2_OUT_CMC_EXT_INFO_PRESENT_WIDTH 1
2393#define MC_CMD_GET_VERSION_V2_OUT_FPGA_EXT_INFO_PRESENT_OFST 48
2394#define MC_CMD_GET_VERSION_V2_OUT_FPGA_EXT_INFO_PRESENT_LBN 3
2395#define MC_CMD_GET_VERSION_V2_OUT_FPGA_EXT_INFO_PRESENT_WIDTH 1
2396#define MC_CMD_GET_VERSION_V2_OUT_BOARD_EXT_INFO_PRESENT_OFST 48
2397#define MC_CMD_GET_VERSION_V2_OUT_BOARD_EXT_INFO_PRESENT_LBN 4
2398#define MC_CMD_GET_VERSION_V2_OUT_BOARD_EXT_INFO_PRESENT_WIDTH 1
2399#define MC_CMD_GET_VERSION_V2_OUT_DATAPATH_HW_VERSION_PRESENT_OFST 48
2400#define MC_CMD_GET_VERSION_V2_OUT_DATAPATH_HW_VERSION_PRESENT_LBN 5
2401#define MC_CMD_GET_VERSION_V2_OUT_DATAPATH_HW_VERSION_PRESENT_WIDTH 1
2402#define MC_CMD_GET_VERSION_V2_OUT_DATAPATH_FW_VERSION_PRESENT_OFST 48
2403#define MC_CMD_GET_VERSION_V2_OUT_DATAPATH_FW_VERSION_PRESENT_LBN 6
2404#define MC_CMD_GET_VERSION_V2_OUT_DATAPATH_FW_VERSION_PRESENT_WIDTH 1
2405#define MC_CMD_GET_VERSION_V2_OUT_SOC_BOOT_VERSION_PRESENT_OFST 48
2406#define MC_CMD_GET_VERSION_V2_OUT_SOC_BOOT_VERSION_PRESENT_LBN 7
2407#define MC_CMD_GET_VERSION_V2_OUT_SOC_BOOT_VERSION_PRESENT_WIDTH 1
2408#define MC_CMD_GET_VERSION_V2_OUT_SOC_UBOOT_VERSION_PRESENT_OFST 48
2409#define MC_CMD_GET_VERSION_V2_OUT_SOC_UBOOT_VERSION_PRESENT_LBN 8
2410#define MC_CMD_GET_VERSION_V2_OUT_SOC_UBOOT_VERSION_PRESENT_WIDTH 1
2411#define MC_CMD_GET_VERSION_V2_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_OFST 48
2412#define MC_CMD_GET_VERSION_V2_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_LBN 9
2413#define MC_CMD_GET_VERSION_V2_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_WIDTH 1
2414#define MC_CMD_GET_VERSION_V2_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_OFST 48
2415#define MC_CMD_GET_VERSION_V2_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_LBN 10
2416#define MC_CMD_GET_VERSION_V2_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_WIDTH 1
2417#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_VERSION_PRESENT_OFST 48
2418#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_VERSION_PRESENT_LBN 11
2419#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_VERSION_PRESENT_WIDTH 1
2420#define MC_CMD_GET_VERSION_V2_OUT_BOARD_VERSION_PRESENT_OFST 48
2421#define MC_CMD_GET_VERSION_V2_OUT_BOARD_VERSION_PRESENT_LBN 12
2422#define MC_CMD_GET_VERSION_V2_OUT_BOARD_VERSION_PRESENT_WIDTH 1
2423#define MC_CMD_GET_VERSION_V2_OUT_BUNDLE_VERSION_PRESENT_OFST 48
2424#define MC_CMD_GET_VERSION_V2_OUT_BUNDLE_VERSION_PRESENT_LBN 13
2425#define MC_CMD_GET_VERSION_V2_OUT_BUNDLE_VERSION_PRESENT_WIDTH 1
2426/* MC firmware unique build ID (as binary SHA-1 value) */
2427#define MC_CMD_GET_VERSION_V2_OUT_MCFW_BUILD_ID_OFST 52
2428#define MC_CMD_GET_VERSION_V2_OUT_MCFW_BUILD_ID_LEN 20
2429/* MC firmware security level */
2430#define MC_CMD_GET_VERSION_V2_OUT_MCFW_SECURITY_LEVEL_OFST 72
2431#define MC_CMD_GET_VERSION_V2_OUT_MCFW_SECURITY_LEVEL_LEN 4
2432/* MC firmware build name (as null-terminated US-ASCII string) */
2433#define MC_CMD_GET_VERSION_V2_OUT_MCFW_BUILD_NAME_OFST 76
2434#define MC_CMD_GET_VERSION_V2_OUT_MCFW_BUILD_NAME_LEN 64
2435/* The SUC firmware version as four numbers - a.b.c.d */
2436#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_VERSION_OFST 140
2437#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_VERSION_LEN 4
2438#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_VERSION_NUM 4
2439/* SUC firmware build date (as 64-bit Unix timestamp) */
2440#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_OFST 156
2441#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_LEN 8
2442#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_LO_OFST 156
2443#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_LO_LEN 4
2444#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_LO_LBN 1248
2445#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_LO_WIDTH 32
2446#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_HI_OFST 160
2447#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_HI_LEN 4
2448#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_HI_LBN 1280
2449#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_HI_WIDTH 32
2450/* The ID of the SUC chip. This is specific to the platform but typically
2451 * indicates family, memory sizes etc. See SF-116728-SW for further details.
2452 */
2453#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_CHIP_ID_OFST 164
2454#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_CHIP_ID_LEN 4
2455/* The CMC firmware version as four numbers - a.b.c.d */
2456#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_VERSION_OFST 168
2457#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_VERSION_LEN 4
2458#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_VERSION_NUM 4
2459/* CMC firmware build date (as 64-bit Unix timestamp) */
2460#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_OFST 184
2461#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_LEN 8
2462#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_LO_OFST 184
2463#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_LO_LEN 4
2464#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_LO_LBN 1472
2465#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_LO_WIDTH 32
2466#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_HI_OFST 188
2467#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_HI_LEN 4
2468#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_HI_LBN 1504
2469#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_HI_WIDTH 32
2470/* FPGA version as three numbers. On Riverhead based systems this field uses
2471 * the same encoding as hardware version ID registers (MC_FPGA_BUILD_HWRD_REG):
2472 * FPGA_VERSION[0]: x => Image H{x} FPGA_VERSION[1]: Revision letter (0 => A, 1
2473 * => B, ...) FPGA_VERSION[2]: Sub-revision number
2474 */
2475#define MC_CMD_GET_VERSION_V2_OUT_FPGA_VERSION_OFST 192
2476#define MC_CMD_GET_VERSION_V2_OUT_FPGA_VERSION_LEN 4
2477#define MC_CMD_GET_VERSION_V2_OUT_FPGA_VERSION_NUM 3
2478/* Extra FPGA revision information (as null-terminated US-ASCII string) */
2479#define MC_CMD_GET_VERSION_V2_OUT_FPGA_EXTRA_OFST 204
2480#define MC_CMD_GET_VERSION_V2_OUT_FPGA_EXTRA_LEN 16
2481/* Board name / adapter model (as null-terminated US-ASCII string) */
2482#define MC_CMD_GET_VERSION_V2_OUT_BOARD_NAME_OFST 220
2483#define MC_CMD_GET_VERSION_V2_OUT_BOARD_NAME_LEN 16
2484/* Board revision number */
2485#define MC_CMD_GET_VERSION_V2_OUT_BOARD_REVISION_OFST 236
2486#define MC_CMD_GET_VERSION_V2_OUT_BOARD_REVISION_LEN 4
2487/* Board serial number (as null-terminated US-ASCII string) */
2488#define MC_CMD_GET_VERSION_V2_OUT_BOARD_SERIAL_OFST 240
2489#define MC_CMD_GET_VERSION_V2_OUT_BOARD_SERIAL_LEN 64
2490
2491/* MC_CMD_GET_VERSION_V3_OUT msgresponse: Extended response providing version
2492 * information for all adapter components. For Riverhead based designs, base MC
2493 * firmware version fields refer to NMC firmware, while CMC firmware data is in
2494 * dedicated CMC fields. Flags indicate which data is present in the response
2495 * (depending on which components exist on a particular adapter)
2496 */
2497#define MC_CMD_GET_VERSION_V3_OUT_LEN 328
2498/* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */
2499/* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */
2500/* Enum values, see field(s): */
2501/* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */
2502#define MC_CMD_GET_VERSION_V3_OUT_PCOL_OFST 4
2503#define MC_CMD_GET_VERSION_V3_OUT_PCOL_LEN 4
2504/* 128bit mask of functions supported by the current firmware */
2505#define MC_CMD_GET_VERSION_V3_OUT_SUPPORTED_FUNCS_OFST 8
2506#define MC_CMD_GET_VERSION_V3_OUT_SUPPORTED_FUNCS_LEN 16
2507#define MC_CMD_GET_VERSION_V3_OUT_VERSION_OFST 24
2508#define MC_CMD_GET_VERSION_V3_OUT_VERSION_LEN 8
2509#define MC_CMD_GET_VERSION_V3_OUT_VERSION_LO_OFST 24
2510#define MC_CMD_GET_VERSION_V3_OUT_VERSION_LO_LEN 4
2511#define MC_CMD_GET_VERSION_V3_OUT_VERSION_LO_LBN 192
2512#define MC_CMD_GET_VERSION_V3_OUT_VERSION_LO_WIDTH 32
2513#define MC_CMD_GET_VERSION_V3_OUT_VERSION_HI_OFST 28
2514#define MC_CMD_GET_VERSION_V3_OUT_VERSION_HI_LEN 4
2515#define MC_CMD_GET_VERSION_V3_OUT_VERSION_HI_LBN 224
2516#define MC_CMD_GET_VERSION_V3_OUT_VERSION_HI_WIDTH 32
2517/* extra info */
2518#define MC_CMD_GET_VERSION_V3_OUT_EXTRA_OFST 32
2519#define MC_CMD_GET_VERSION_V3_OUT_EXTRA_LEN 16
2520/* Flags indicating which extended fields are valid */
2521#define MC_CMD_GET_VERSION_V3_OUT_FLAGS_OFST 48
2522#define MC_CMD_GET_VERSION_V3_OUT_FLAGS_LEN 4
2523#define MC_CMD_GET_VERSION_V3_OUT_MCFW_EXT_INFO_PRESENT_OFST 48
2524#define MC_CMD_GET_VERSION_V3_OUT_MCFW_EXT_INFO_PRESENT_LBN 0
2525#define MC_CMD_GET_VERSION_V3_OUT_MCFW_EXT_INFO_PRESENT_WIDTH 1
2526#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_EXT_INFO_PRESENT_OFST 48
2527#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_EXT_INFO_PRESENT_LBN 1
2528#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_EXT_INFO_PRESENT_WIDTH 1
2529#define MC_CMD_GET_VERSION_V3_OUT_CMC_EXT_INFO_PRESENT_OFST 48
2530#define MC_CMD_GET_VERSION_V3_OUT_CMC_EXT_INFO_PRESENT_LBN 2
2531#define MC_CMD_GET_VERSION_V3_OUT_CMC_EXT_INFO_PRESENT_WIDTH 1
2532#define MC_CMD_GET_VERSION_V3_OUT_FPGA_EXT_INFO_PRESENT_OFST 48
2533#define MC_CMD_GET_VERSION_V3_OUT_FPGA_EXT_INFO_PRESENT_LBN 3
2534#define MC_CMD_GET_VERSION_V3_OUT_FPGA_EXT_INFO_PRESENT_WIDTH 1
2535#define MC_CMD_GET_VERSION_V3_OUT_BOARD_EXT_INFO_PRESENT_OFST 48
2536#define MC_CMD_GET_VERSION_V3_OUT_BOARD_EXT_INFO_PRESENT_LBN 4
2537#define MC_CMD_GET_VERSION_V3_OUT_BOARD_EXT_INFO_PRESENT_WIDTH 1
2538#define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_HW_VERSION_PRESENT_OFST 48
2539#define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_HW_VERSION_PRESENT_LBN 5
2540#define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_HW_VERSION_PRESENT_WIDTH 1
2541#define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_FW_VERSION_PRESENT_OFST 48
2542#define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_FW_VERSION_PRESENT_LBN 6
2543#define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_FW_VERSION_PRESENT_WIDTH 1
2544#define MC_CMD_GET_VERSION_V3_OUT_SOC_BOOT_VERSION_PRESENT_OFST 48
2545#define MC_CMD_GET_VERSION_V3_OUT_SOC_BOOT_VERSION_PRESENT_LBN 7
2546#define MC_CMD_GET_VERSION_V3_OUT_SOC_BOOT_VERSION_PRESENT_WIDTH 1
2547#define MC_CMD_GET_VERSION_V3_OUT_SOC_UBOOT_VERSION_PRESENT_OFST 48
2548#define MC_CMD_GET_VERSION_V3_OUT_SOC_UBOOT_VERSION_PRESENT_LBN 8
2549#define MC_CMD_GET_VERSION_V3_OUT_SOC_UBOOT_VERSION_PRESENT_WIDTH 1
2550#define MC_CMD_GET_VERSION_V3_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_OFST 48
2551#define MC_CMD_GET_VERSION_V3_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_LBN 9
2552#define MC_CMD_GET_VERSION_V3_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_WIDTH 1
2553#define MC_CMD_GET_VERSION_V3_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_OFST 48
2554#define MC_CMD_GET_VERSION_V3_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_LBN 10
2555#define MC_CMD_GET_VERSION_V3_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_WIDTH 1
2556#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_VERSION_PRESENT_OFST 48
2557#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_VERSION_PRESENT_LBN 11
2558#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_VERSION_PRESENT_WIDTH 1
2559#define MC_CMD_GET_VERSION_V3_OUT_BOARD_VERSION_PRESENT_OFST 48
2560#define MC_CMD_GET_VERSION_V3_OUT_BOARD_VERSION_PRESENT_LBN 12
2561#define MC_CMD_GET_VERSION_V3_OUT_BOARD_VERSION_PRESENT_WIDTH 1
2562#define MC_CMD_GET_VERSION_V3_OUT_BUNDLE_VERSION_PRESENT_OFST 48
2563#define MC_CMD_GET_VERSION_V3_OUT_BUNDLE_VERSION_PRESENT_LBN 13
2564#define MC_CMD_GET_VERSION_V3_OUT_BUNDLE_VERSION_PRESENT_WIDTH 1
2565/* MC firmware unique build ID (as binary SHA-1 value) */
2566#define MC_CMD_GET_VERSION_V3_OUT_MCFW_BUILD_ID_OFST 52
2567#define MC_CMD_GET_VERSION_V3_OUT_MCFW_BUILD_ID_LEN 20
2568/* MC firmware security level */
2569#define MC_CMD_GET_VERSION_V3_OUT_MCFW_SECURITY_LEVEL_OFST 72
2570#define MC_CMD_GET_VERSION_V3_OUT_MCFW_SECURITY_LEVEL_LEN 4
2571/* MC firmware build name (as null-terminated US-ASCII string) */
2572#define MC_CMD_GET_VERSION_V3_OUT_MCFW_BUILD_NAME_OFST 76
2573#define MC_CMD_GET_VERSION_V3_OUT_MCFW_BUILD_NAME_LEN 64
2574/* The SUC firmware version as four numbers - a.b.c.d */
2575#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_VERSION_OFST 140
2576#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_VERSION_LEN 4
2577#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_VERSION_NUM 4
2578/* SUC firmware build date (as 64-bit Unix timestamp) */
2579#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_OFST 156
2580#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_LEN 8
2581#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_LO_OFST 156
2582#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_LO_LEN 4
2583#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_LO_LBN 1248
2584#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_LO_WIDTH 32
2585#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_HI_OFST 160
2586#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_HI_LEN 4
2587#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_HI_LBN 1280
2588#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_HI_WIDTH 32
2589/* The ID of the SUC chip. This is specific to the platform but typically
2590 * indicates family, memory sizes etc. See SF-116728-SW for further details.
2591 */
2592#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_CHIP_ID_OFST 164
2593#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_CHIP_ID_LEN 4
2594/* The CMC firmware version as four numbers - a.b.c.d */
2595#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_VERSION_OFST 168
2596#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_VERSION_LEN 4
2597#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_VERSION_NUM 4
2598/* CMC firmware build date (as 64-bit Unix timestamp) */
2599#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_OFST 184
2600#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_LEN 8
2601#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_LO_OFST 184
2602#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_LO_LEN 4
2603#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_LO_LBN 1472
2604#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_LO_WIDTH 32
2605#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_HI_OFST 188
2606#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_HI_LEN 4
2607#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_HI_LBN 1504
2608#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_HI_WIDTH 32
2609/* FPGA version as three numbers. On Riverhead based systems this field uses
2610 * the same encoding as hardware version ID registers (MC_FPGA_BUILD_HWRD_REG):
2611 * FPGA_VERSION[0]: x => Image H{x} FPGA_VERSION[1]: Revision letter (0 => A, 1
2612 * => B, ...) FPGA_VERSION[2]: Sub-revision number
2613 */
2614#define MC_CMD_GET_VERSION_V3_OUT_FPGA_VERSION_OFST 192
2615#define MC_CMD_GET_VERSION_V3_OUT_FPGA_VERSION_LEN 4
2616#define MC_CMD_GET_VERSION_V3_OUT_FPGA_VERSION_NUM 3
2617/* Extra FPGA revision information (as null-terminated US-ASCII string) */
2618#define MC_CMD_GET_VERSION_V3_OUT_FPGA_EXTRA_OFST 204
2619#define MC_CMD_GET_VERSION_V3_OUT_FPGA_EXTRA_LEN 16
2620/* Board name / adapter model (as null-terminated US-ASCII string) */
2621#define MC_CMD_GET_VERSION_V3_OUT_BOARD_NAME_OFST 220
2622#define MC_CMD_GET_VERSION_V3_OUT_BOARD_NAME_LEN 16
2623/* Board revision number */
2624#define MC_CMD_GET_VERSION_V3_OUT_BOARD_REVISION_OFST 236
2625#define MC_CMD_GET_VERSION_V3_OUT_BOARD_REVISION_LEN 4
2626/* Board serial number (as null-terminated US-ASCII string) */
2627#define MC_CMD_GET_VERSION_V3_OUT_BOARD_SERIAL_OFST 240
2628#define MC_CMD_GET_VERSION_V3_OUT_BOARD_SERIAL_LEN 64
2629/* The version of the datapath hardware design as three number - a.b.c */
2630#define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_HW_VERSION_OFST 304
2631#define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_HW_VERSION_LEN 4
2632#define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_HW_VERSION_NUM 3
2633/* The version of the firmware library used to control the datapath as three
2634 * number - a.b.c
2635 */
2636#define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_FW_VERSION_OFST 316
2637#define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_FW_VERSION_LEN 4
2638#define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_FW_VERSION_NUM 3
2639
2640/* MC_CMD_GET_VERSION_V4_OUT msgresponse: Extended response providing SoC
2641 * version information
2642 */
2643#define MC_CMD_GET_VERSION_V4_OUT_LEN 392
2644/* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */
2645/* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */
2646/* Enum values, see field(s): */
2647/* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */
2648#define MC_CMD_GET_VERSION_V4_OUT_PCOL_OFST 4
2649#define MC_CMD_GET_VERSION_V4_OUT_PCOL_LEN 4
2650/* 128bit mask of functions supported by the current firmware */
2651#define MC_CMD_GET_VERSION_V4_OUT_SUPPORTED_FUNCS_OFST 8
2652#define MC_CMD_GET_VERSION_V4_OUT_SUPPORTED_FUNCS_LEN 16
2653#define MC_CMD_GET_VERSION_V4_OUT_VERSION_OFST 24
2654#define MC_CMD_GET_VERSION_V4_OUT_VERSION_LEN 8
2655#define MC_CMD_GET_VERSION_V4_OUT_VERSION_LO_OFST 24
2656#define MC_CMD_GET_VERSION_V4_OUT_VERSION_LO_LEN 4
2657#define MC_CMD_GET_VERSION_V4_OUT_VERSION_LO_LBN 192
2658#define MC_CMD_GET_VERSION_V4_OUT_VERSION_LO_WIDTH 32
2659#define MC_CMD_GET_VERSION_V4_OUT_VERSION_HI_OFST 28
2660#define MC_CMD_GET_VERSION_V4_OUT_VERSION_HI_LEN 4
2661#define MC_CMD_GET_VERSION_V4_OUT_VERSION_HI_LBN 224
2662#define MC_CMD_GET_VERSION_V4_OUT_VERSION_HI_WIDTH 32
2663/* extra info */
2664#define MC_CMD_GET_VERSION_V4_OUT_EXTRA_OFST 32
2665#define MC_CMD_GET_VERSION_V4_OUT_EXTRA_LEN 16
2666/* Flags indicating which extended fields are valid */
2667#define MC_CMD_GET_VERSION_V4_OUT_FLAGS_OFST 48
2668#define MC_CMD_GET_VERSION_V4_OUT_FLAGS_LEN 4
2669#define MC_CMD_GET_VERSION_V4_OUT_MCFW_EXT_INFO_PRESENT_OFST 48
2670#define MC_CMD_GET_VERSION_V4_OUT_MCFW_EXT_INFO_PRESENT_LBN 0
2671#define MC_CMD_GET_VERSION_V4_OUT_MCFW_EXT_INFO_PRESENT_WIDTH 1
2672#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_EXT_INFO_PRESENT_OFST 48
2673#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_EXT_INFO_PRESENT_LBN 1
2674#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_EXT_INFO_PRESENT_WIDTH 1
2675#define MC_CMD_GET_VERSION_V4_OUT_CMC_EXT_INFO_PRESENT_OFST 48
2676#define MC_CMD_GET_VERSION_V4_OUT_CMC_EXT_INFO_PRESENT_LBN 2
2677#define MC_CMD_GET_VERSION_V4_OUT_CMC_EXT_INFO_PRESENT_WIDTH 1
2678#define MC_CMD_GET_VERSION_V4_OUT_FPGA_EXT_INFO_PRESENT_OFST 48
2679#define MC_CMD_GET_VERSION_V4_OUT_FPGA_EXT_INFO_PRESENT_LBN 3
2680#define MC_CMD_GET_VERSION_V4_OUT_FPGA_EXT_INFO_PRESENT_WIDTH 1
2681#define MC_CMD_GET_VERSION_V4_OUT_BOARD_EXT_INFO_PRESENT_OFST 48
2682#define MC_CMD_GET_VERSION_V4_OUT_BOARD_EXT_INFO_PRESENT_LBN 4
2683#define MC_CMD_GET_VERSION_V4_OUT_BOARD_EXT_INFO_PRESENT_WIDTH 1
2684#define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_HW_VERSION_PRESENT_OFST 48
2685#define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_HW_VERSION_PRESENT_LBN 5
2686#define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_HW_VERSION_PRESENT_WIDTH 1
2687#define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_FW_VERSION_PRESENT_OFST 48
2688#define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_FW_VERSION_PRESENT_LBN 6
2689#define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_FW_VERSION_PRESENT_WIDTH 1
2690#define MC_CMD_GET_VERSION_V4_OUT_SOC_BOOT_VERSION_PRESENT_OFST 48
2691#define MC_CMD_GET_VERSION_V4_OUT_SOC_BOOT_VERSION_PRESENT_LBN 7
2692#define MC_CMD_GET_VERSION_V4_OUT_SOC_BOOT_VERSION_PRESENT_WIDTH 1
2693#define MC_CMD_GET_VERSION_V4_OUT_SOC_UBOOT_VERSION_PRESENT_OFST 48
2694#define MC_CMD_GET_VERSION_V4_OUT_SOC_UBOOT_VERSION_PRESENT_LBN 8
2695#define MC_CMD_GET_VERSION_V4_OUT_SOC_UBOOT_VERSION_PRESENT_WIDTH 1
2696#define MC_CMD_GET_VERSION_V4_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_OFST 48
2697#define MC_CMD_GET_VERSION_V4_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_LBN 9
2698#define MC_CMD_GET_VERSION_V4_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_WIDTH 1
2699#define MC_CMD_GET_VERSION_V4_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_OFST 48
2700#define MC_CMD_GET_VERSION_V4_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_LBN 10
2701#define MC_CMD_GET_VERSION_V4_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_WIDTH 1
2702#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_VERSION_PRESENT_OFST 48
2703#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_VERSION_PRESENT_LBN 11
2704#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_VERSION_PRESENT_WIDTH 1
2705#define MC_CMD_GET_VERSION_V4_OUT_BOARD_VERSION_PRESENT_OFST 48
2706#define MC_CMD_GET_VERSION_V4_OUT_BOARD_VERSION_PRESENT_LBN 12
2707#define MC_CMD_GET_VERSION_V4_OUT_BOARD_VERSION_PRESENT_WIDTH 1
2708#define MC_CMD_GET_VERSION_V4_OUT_BUNDLE_VERSION_PRESENT_OFST 48
2709#define MC_CMD_GET_VERSION_V4_OUT_BUNDLE_VERSION_PRESENT_LBN 13
2710#define MC_CMD_GET_VERSION_V4_OUT_BUNDLE_VERSION_PRESENT_WIDTH 1
2711/* MC firmware unique build ID (as binary SHA-1 value) */
2712#define MC_CMD_GET_VERSION_V4_OUT_MCFW_BUILD_ID_OFST 52
2713#define MC_CMD_GET_VERSION_V4_OUT_MCFW_BUILD_ID_LEN 20
2714/* MC firmware security level */
2715#define MC_CMD_GET_VERSION_V4_OUT_MCFW_SECURITY_LEVEL_OFST 72
2716#define MC_CMD_GET_VERSION_V4_OUT_MCFW_SECURITY_LEVEL_LEN 4
2717/* MC firmware build name (as null-terminated US-ASCII string) */
2718#define MC_CMD_GET_VERSION_V4_OUT_MCFW_BUILD_NAME_OFST 76
2719#define MC_CMD_GET_VERSION_V4_OUT_MCFW_BUILD_NAME_LEN 64
2720/* The SUC firmware version as four numbers - a.b.c.d */
2721#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_VERSION_OFST 140
2722#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_VERSION_LEN 4
2723#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_VERSION_NUM 4
2724/* SUC firmware build date (as 64-bit Unix timestamp) */
2725#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_OFST 156
2726#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_LEN 8
2727#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_LO_OFST 156
2728#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_LO_LEN 4
2729#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_LO_LBN 1248
2730#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_LO_WIDTH 32
2731#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_HI_OFST 160
2732#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_HI_LEN 4
2733#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_HI_LBN 1280
2734#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_HI_WIDTH 32
2735/* The ID of the SUC chip. This is specific to the platform but typically
2736 * indicates family, memory sizes etc. See SF-116728-SW for further details.
2737 */
2738#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_CHIP_ID_OFST 164
2739#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_CHIP_ID_LEN 4
2740/* The CMC firmware version as four numbers - a.b.c.d */
2741#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_VERSION_OFST 168
2742#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_VERSION_LEN 4
2743#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_VERSION_NUM 4
2744/* CMC firmware build date (as 64-bit Unix timestamp) */
2745#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_OFST 184
2746#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_LEN 8
2747#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_LO_OFST 184
2748#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_LO_LEN 4
2749#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_LO_LBN 1472
2750#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_LO_WIDTH 32
2751#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_HI_OFST 188
2752#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_HI_LEN 4
2753#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_HI_LBN 1504
2754#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_HI_WIDTH 32
2755/* FPGA version as three numbers. On Riverhead based systems this field uses
2756 * the same encoding as hardware version ID registers (MC_FPGA_BUILD_HWRD_REG):
2757 * FPGA_VERSION[0]: x => Image H{x} FPGA_VERSION[1]: Revision letter (0 => A, 1
2758 * => B, ...) FPGA_VERSION[2]: Sub-revision number
2759 */
2760#define MC_CMD_GET_VERSION_V4_OUT_FPGA_VERSION_OFST 192
2761#define MC_CMD_GET_VERSION_V4_OUT_FPGA_VERSION_LEN 4
2762#define MC_CMD_GET_VERSION_V4_OUT_FPGA_VERSION_NUM 3
2763/* Extra FPGA revision information (as null-terminated US-ASCII string) */
2764#define MC_CMD_GET_VERSION_V4_OUT_FPGA_EXTRA_OFST 204
2765#define MC_CMD_GET_VERSION_V4_OUT_FPGA_EXTRA_LEN 16
2766/* Board name / adapter model (as null-terminated US-ASCII string) */
2767#define MC_CMD_GET_VERSION_V4_OUT_BOARD_NAME_OFST 220
2768#define MC_CMD_GET_VERSION_V4_OUT_BOARD_NAME_LEN 16
2769/* Board revision number */
2770#define MC_CMD_GET_VERSION_V4_OUT_BOARD_REVISION_OFST 236
2771#define MC_CMD_GET_VERSION_V4_OUT_BOARD_REVISION_LEN 4
2772/* Board serial number (as null-terminated US-ASCII string) */
2773#define MC_CMD_GET_VERSION_V4_OUT_BOARD_SERIAL_OFST 240
2774#define MC_CMD_GET_VERSION_V4_OUT_BOARD_SERIAL_LEN 64
2775/* The version of the datapath hardware design as three number - a.b.c */
2776#define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_HW_VERSION_OFST 304
2777#define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_HW_VERSION_LEN 4
2778#define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_HW_VERSION_NUM 3
2779/* The version of the firmware library used to control the datapath as three
2780 * number - a.b.c
2781 */
2782#define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_FW_VERSION_OFST 316
2783#define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_FW_VERSION_LEN 4
2784#define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_FW_VERSION_NUM 3
2785/* The SOC boot version as four numbers - a.b.c.d */
2786#define MC_CMD_GET_VERSION_V4_OUT_SOC_BOOT_VERSION_OFST 328
2787#define MC_CMD_GET_VERSION_V4_OUT_SOC_BOOT_VERSION_LEN 4
2788#define MC_CMD_GET_VERSION_V4_OUT_SOC_BOOT_VERSION_NUM 4
2789/* The SOC uboot version as four numbers - a.b.c.d */
2790#define MC_CMD_GET_VERSION_V4_OUT_SOC_UBOOT_VERSION_OFST 344
2791#define MC_CMD_GET_VERSION_V4_OUT_SOC_UBOOT_VERSION_LEN 4
2792#define MC_CMD_GET_VERSION_V4_OUT_SOC_UBOOT_VERSION_NUM 4
2793/* The SOC main rootfs version as four numbers - a.b.c.d */
2794#define MC_CMD_GET_VERSION_V4_OUT_SOC_MAIN_ROOTFS_VERSION_OFST 360
2795#define MC_CMD_GET_VERSION_V4_OUT_SOC_MAIN_ROOTFS_VERSION_LEN 4
2796#define MC_CMD_GET_VERSION_V4_OUT_SOC_MAIN_ROOTFS_VERSION_NUM 4
2797/* The SOC recovery buildroot version as four numbers - a.b.c.d */
2798#define MC_CMD_GET_VERSION_V4_OUT_SOC_RECOVERY_BUILDROOT_VERSION_OFST 376
2799#define MC_CMD_GET_VERSION_V4_OUT_SOC_RECOVERY_BUILDROOT_VERSION_LEN 4
2800#define MC_CMD_GET_VERSION_V4_OUT_SOC_RECOVERY_BUILDROOT_VERSION_NUM 4
2801
2802/* MC_CMD_GET_VERSION_V5_OUT msgresponse: Extended response providing bundle
2803 * and board version information
2804 */
2805#define MC_CMD_GET_VERSION_V5_OUT_LEN 424
2806/* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */
2807/* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */
2808/* Enum values, see field(s): */
2809/* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */
2810#define MC_CMD_GET_VERSION_V5_OUT_PCOL_OFST 4
2811#define MC_CMD_GET_VERSION_V5_OUT_PCOL_LEN 4
2812/* 128bit mask of functions supported by the current firmware */
2813#define MC_CMD_GET_VERSION_V5_OUT_SUPPORTED_FUNCS_OFST 8
2814#define MC_CMD_GET_VERSION_V5_OUT_SUPPORTED_FUNCS_LEN 16
2815#define MC_CMD_GET_VERSION_V5_OUT_VERSION_OFST 24
2816#define MC_CMD_GET_VERSION_V5_OUT_VERSION_LEN 8
2817#define MC_CMD_GET_VERSION_V5_OUT_VERSION_LO_OFST 24
2818#define MC_CMD_GET_VERSION_V5_OUT_VERSION_LO_LEN 4
2819#define MC_CMD_GET_VERSION_V5_OUT_VERSION_LO_LBN 192
2820#define MC_CMD_GET_VERSION_V5_OUT_VERSION_LO_WIDTH 32
2821#define MC_CMD_GET_VERSION_V5_OUT_VERSION_HI_OFST 28
2822#define MC_CMD_GET_VERSION_V5_OUT_VERSION_HI_LEN 4
2823#define MC_CMD_GET_VERSION_V5_OUT_VERSION_HI_LBN 224
2824#define MC_CMD_GET_VERSION_V5_OUT_VERSION_HI_WIDTH 32
2825/* extra info */
2826#define MC_CMD_GET_VERSION_V5_OUT_EXTRA_OFST 32
2827#define MC_CMD_GET_VERSION_V5_OUT_EXTRA_LEN 16
2828/* Flags indicating which extended fields are valid */
2829#define MC_CMD_GET_VERSION_V5_OUT_FLAGS_OFST 48
2830#define MC_CMD_GET_VERSION_V5_OUT_FLAGS_LEN 4
2831#define MC_CMD_GET_VERSION_V5_OUT_MCFW_EXT_INFO_PRESENT_OFST 48
2832#define MC_CMD_GET_VERSION_V5_OUT_MCFW_EXT_INFO_PRESENT_LBN 0
2833#define MC_CMD_GET_VERSION_V5_OUT_MCFW_EXT_INFO_PRESENT_WIDTH 1
2834#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_EXT_INFO_PRESENT_OFST 48
2835#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_EXT_INFO_PRESENT_LBN 1
2836#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_EXT_INFO_PRESENT_WIDTH 1
2837#define MC_CMD_GET_VERSION_V5_OUT_CMC_EXT_INFO_PRESENT_OFST 48
2838#define MC_CMD_GET_VERSION_V5_OUT_CMC_EXT_INFO_PRESENT_LBN 2
2839#define MC_CMD_GET_VERSION_V5_OUT_CMC_EXT_INFO_PRESENT_WIDTH 1
2840#define MC_CMD_GET_VERSION_V5_OUT_FPGA_EXT_INFO_PRESENT_OFST 48
2841#define MC_CMD_GET_VERSION_V5_OUT_FPGA_EXT_INFO_PRESENT_LBN 3
2842#define MC_CMD_GET_VERSION_V5_OUT_FPGA_EXT_INFO_PRESENT_WIDTH 1
2843#define MC_CMD_GET_VERSION_V5_OUT_BOARD_EXT_INFO_PRESENT_OFST 48
2844#define MC_CMD_GET_VERSION_V5_OUT_BOARD_EXT_INFO_PRESENT_LBN 4
2845#define MC_CMD_GET_VERSION_V5_OUT_BOARD_EXT_INFO_PRESENT_WIDTH 1
2846#define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_HW_VERSION_PRESENT_OFST 48
2847#define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_HW_VERSION_PRESENT_LBN 5
2848#define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_HW_VERSION_PRESENT_WIDTH 1
2849#define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_FW_VERSION_PRESENT_OFST 48
2850#define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_FW_VERSION_PRESENT_LBN 6
2851#define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_FW_VERSION_PRESENT_WIDTH 1
2852#define MC_CMD_GET_VERSION_V5_OUT_SOC_BOOT_VERSION_PRESENT_OFST 48
2853#define MC_CMD_GET_VERSION_V5_OUT_SOC_BOOT_VERSION_PRESENT_LBN 7
2854#define MC_CMD_GET_VERSION_V5_OUT_SOC_BOOT_VERSION_PRESENT_WIDTH 1
2855#define MC_CMD_GET_VERSION_V5_OUT_SOC_UBOOT_VERSION_PRESENT_OFST 48
2856#define MC_CMD_GET_VERSION_V5_OUT_SOC_UBOOT_VERSION_PRESENT_LBN 8
2857#define MC_CMD_GET_VERSION_V5_OUT_SOC_UBOOT_VERSION_PRESENT_WIDTH 1
2858#define MC_CMD_GET_VERSION_V5_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_OFST 48
2859#define MC_CMD_GET_VERSION_V5_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_LBN 9
2860#define MC_CMD_GET_VERSION_V5_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_WIDTH 1
2861#define MC_CMD_GET_VERSION_V5_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_OFST 48
2862#define MC_CMD_GET_VERSION_V5_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_LBN 10
2863#define MC_CMD_GET_VERSION_V5_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_WIDTH 1
2864#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_VERSION_PRESENT_OFST 48
2865#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_VERSION_PRESENT_LBN 11
2866#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_VERSION_PRESENT_WIDTH 1
2867#define MC_CMD_GET_VERSION_V5_OUT_BOARD_VERSION_PRESENT_OFST 48
2868#define MC_CMD_GET_VERSION_V5_OUT_BOARD_VERSION_PRESENT_LBN 12
2869#define MC_CMD_GET_VERSION_V5_OUT_BOARD_VERSION_PRESENT_WIDTH 1
2870#define MC_CMD_GET_VERSION_V5_OUT_BUNDLE_VERSION_PRESENT_OFST 48
2871#define MC_CMD_GET_VERSION_V5_OUT_BUNDLE_VERSION_PRESENT_LBN 13
2872#define MC_CMD_GET_VERSION_V5_OUT_BUNDLE_VERSION_PRESENT_WIDTH 1
2873/* MC firmware unique build ID (as binary SHA-1 value) */
2874#define MC_CMD_GET_VERSION_V5_OUT_MCFW_BUILD_ID_OFST 52
2875#define MC_CMD_GET_VERSION_V5_OUT_MCFW_BUILD_ID_LEN 20
2876/* MC firmware security level */
2877#define MC_CMD_GET_VERSION_V5_OUT_MCFW_SECURITY_LEVEL_OFST 72
2878#define MC_CMD_GET_VERSION_V5_OUT_MCFW_SECURITY_LEVEL_LEN 4
2879/* MC firmware build name (as null-terminated US-ASCII string) */
2880#define MC_CMD_GET_VERSION_V5_OUT_MCFW_BUILD_NAME_OFST 76
2881#define MC_CMD_GET_VERSION_V5_OUT_MCFW_BUILD_NAME_LEN 64
2882/* The SUC firmware version as four numbers - a.b.c.d */
2883#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_VERSION_OFST 140
2884#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_VERSION_LEN 4
2885#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_VERSION_NUM 4
2886/* SUC firmware build date (as 64-bit Unix timestamp) */
2887#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_OFST 156
2888#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_LEN 8
2889#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_LO_OFST 156
2890#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_LO_LEN 4
2891#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_LO_LBN 1248
2892#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_LO_WIDTH 32
2893#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_HI_OFST 160
2894#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_HI_LEN 4
2895#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_HI_LBN 1280
2896#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_HI_WIDTH 32
2897/* The ID of the SUC chip. This is specific to the platform but typically
2898 * indicates family, memory sizes etc. See SF-116728-SW for further details.
2899 */
2900#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_CHIP_ID_OFST 164
2901#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_CHIP_ID_LEN 4
2902/* The CMC firmware version as four numbers - a.b.c.d */
2903#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_VERSION_OFST 168
2904#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_VERSION_LEN 4
2905#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_VERSION_NUM 4
2906/* CMC firmware build date (as 64-bit Unix timestamp) */
2907#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_OFST 184
2908#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_LEN 8
2909#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_LO_OFST 184
2910#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_LO_LEN 4
2911#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_LO_LBN 1472
2912#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_LO_WIDTH 32
2913#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_HI_OFST 188
2914#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_HI_LEN 4
2915#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_HI_LBN 1504
2916#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_HI_WIDTH 32
2917/* FPGA version as three numbers. On Riverhead based systems this field uses
2918 * the same encoding as hardware version ID registers (MC_FPGA_BUILD_HWRD_REG):
2919 * FPGA_VERSION[0]: x => Image H{x} FPGA_VERSION[1]: Revision letter (0 => A, 1
2920 * => B, ...) FPGA_VERSION[2]: Sub-revision number
2921 */
2922#define MC_CMD_GET_VERSION_V5_OUT_FPGA_VERSION_OFST 192
2923#define MC_CMD_GET_VERSION_V5_OUT_FPGA_VERSION_LEN 4
2924#define MC_CMD_GET_VERSION_V5_OUT_FPGA_VERSION_NUM 3
2925/* Extra FPGA revision information (as null-terminated US-ASCII string) */
2926#define MC_CMD_GET_VERSION_V5_OUT_FPGA_EXTRA_OFST 204
2927#define MC_CMD_GET_VERSION_V5_OUT_FPGA_EXTRA_LEN 16
2928/* Board name / adapter model (as null-terminated US-ASCII string) */
2929#define MC_CMD_GET_VERSION_V5_OUT_BOARD_NAME_OFST 220
2930#define MC_CMD_GET_VERSION_V5_OUT_BOARD_NAME_LEN 16
2931/* Board revision number */
2932#define MC_CMD_GET_VERSION_V5_OUT_BOARD_REVISION_OFST 236
2933#define MC_CMD_GET_VERSION_V5_OUT_BOARD_REVISION_LEN 4
2934/* Board serial number (as null-terminated US-ASCII string) */
2935#define MC_CMD_GET_VERSION_V5_OUT_BOARD_SERIAL_OFST 240
2936#define MC_CMD_GET_VERSION_V5_OUT_BOARD_SERIAL_LEN 64
2937/* The version of the datapath hardware design as three number - a.b.c */
2938#define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_HW_VERSION_OFST 304
2939#define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_HW_VERSION_LEN 4
2940#define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_HW_VERSION_NUM 3
2941/* The version of the firmware library used to control the datapath as three
2942 * number - a.b.c
2943 */
2944#define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_FW_VERSION_OFST 316
2945#define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_FW_VERSION_LEN 4
2946#define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_FW_VERSION_NUM 3
2947/* The SOC boot version as four numbers - a.b.c.d */
2948#define MC_CMD_GET_VERSION_V5_OUT_SOC_BOOT_VERSION_OFST 328
2949#define MC_CMD_GET_VERSION_V5_OUT_SOC_BOOT_VERSION_LEN 4
2950#define MC_CMD_GET_VERSION_V5_OUT_SOC_BOOT_VERSION_NUM 4
2951/* The SOC uboot version as four numbers - a.b.c.d */
2952#define MC_CMD_GET_VERSION_V5_OUT_SOC_UBOOT_VERSION_OFST 344
2953#define MC_CMD_GET_VERSION_V5_OUT_SOC_UBOOT_VERSION_LEN 4
2954#define MC_CMD_GET_VERSION_V5_OUT_SOC_UBOOT_VERSION_NUM 4
2955/* The SOC main rootfs version as four numbers - a.b.c.d */
2956#define MC_CMD_GET_VERSION_V5_OUT_SOC_MAIN_ROOTFS_VERSION_OFST 360
2957#define MC_CMD_GET_VERSION_V5_OUT_SOC_MAIN_ROOTFS_VERSION_LEN 4
2958#define MC_CMD_GET_VERSION_V5_OUT_SOC_MAIN_ROOTFS_VERSION_NUM 4
2959/* The SOC recovery buildroot version as four numbers - a.b.c.d */
2960#define MC_CMD_GET_VERSION_V5_OUT_SOC_RECOVERY_BUILDROOT_VERSION_OFST 376
2961#define MC_CMD_GET_VERSION_V5_OUT_SOC_RECOVERY_BUILDROOT_VERSION_LEN 4
2962#define MC_CMD_GET_VERSION_V5_OUT_SOC_RECOVERY_BUILDROOT_VERSION_NUM 4
2963/* Board version as four numbers - a.b.c.d. BOARD_VERSION[0] duplicates the
2964 * BOARD_REVISION field
2965 */
2966#define MC_CMD_GET_VERSION_V5_OUT_BOARD_VERSION_OFST 392
2967#define MC_CMD_GET_VERSION_V5_OUT_BOARD_VERSION_LEN 4
2968#define MC_CMD_GET_VERSION_V5_OUT_BOARD_VERSION_NUM 4
2969/* Bundle version as four numbers - a.b.c.d */
2970#define MC_CMD_GET_VERSION_V5_OUT_BUNDLE_VERSION_OFST 408
2971#define MC_CMD_GET_VERSION_V5_OUT_BUNDLE_VERSION_LEN 4
2972#define MC_CMD_GET_VERSION_V5_OUT_BUNDLE_VERSION_NUM 4
2973
2974
2975/***********************************/
2976/* MC_CMD_PTP
2977 * Perform PTP operation
2978 */
2979#define MC_CMD_PTP 0xb
2980#undef MC_CMD_0xb_PRIVILEGE_CTG
2981
2982#define MC_CMD_0xb_PRIVILEGE_CTG SRIOV_CTG_GENERAL
2983
2984/* MC_CMD_PTP_IN msgrequest */
2985#define MC_CMD_PTP_IN_LEN 1
2986/* PTP operation code */
2987#define MC_CMD_PTP_IN_OP_OFST 0
2988#define MC_CMD_PTP_IN_OP_LEN 1
2989/* enum: Enable PTP packet timestamping operation. */
2990#define MC_CMD_PTP_OP_ENABLE 0x1
2991/* enum: Disable PTP packet timestamping operation. */
2992#define MC_CMD_PTP_OP_DISABLE 0x2
2993/* enum: Send a PTP packet. This operation is used on Siena and Huntington.
2994 * From Medford onwards it is not supported: on those platforms PTP transmit
2995 * timestamping is done using the fast path.
2996 */
2997#define MC_CMD_PTP_OP_TRANSMIT 0x3
2998/* enum: Read the current NIC time. */
2999#define MC_CMD_PTP_OP_READ_NIC_TIME 0x4
3000/* enum: Get the current PTP status. Note that the clock frequency returned (in
3001 * Hz) is rounded to the nearest MHz (e.g. 666000000 for 666666666).
3002 */
3003#define MC_CMD_PTP_OP_STATUS 0x5
3004/* enum: Adjust the PTP NIC's time. */
3005#define MC_CMD_PTP_OP_ADJUST 0x6
3006/* enum: Synchronize host and NIC time. */
3007#define MC_CMD_PTP_OP_SYNCHRONIZE 0x7
3008/* enum: Basic manufacturing tests. Siena PTP adapters only. */
3009#define MC_CMD_PTP_OP_MANFTEST_BASIC 0x8
3010/* enum: Packet based manufacturing tests. Siena PTP adapters only. */
3011#define MC_CMD_PTP_OP_MANFTEST_PACKET 0x9
3012/* enum: Reset some of the PTP related statistics */
3013#define MC_CMD_PTP_OP_RESET_STATS 0xa
3014/* enum: Debug operations to MC. */
3015#define MC_CMD_PTP_OP_DEBUG 0xb
3016/* enum: Read an FPGA register. Siena PTP adapters only. */
3017#define MC_CMD_PTP_OP_FPGAREAD 0xc
3018/* enum: Write an FPGA register. Siena PTP adapters only. */
3019#define MC_CMD_PTP_OP_FPGAWRITE 0xd
3020/* enum: Apply an offset to the NIC clock */
3021#define MC_CMD_PTP_OP_CLOCK_OFFSET_ADJUST 0xe
3022/* enum: Change the frequency correction applied to the NIC clock */
3023#define MC_CMD_PTP_OP_CLOCK_FREQ_ADJUST 0xf
3024/* enum: Set the MC packet filter VLAN tags for received PTP packets.
3025 * Deprecated for Huntington onwards.
3026 */
3027#define MC_CMD_PTP_OP_RX_SET_VLAN_FILTER 0x10
3028/* enum: Set the MC packet filter UUID for received PTP packets. Deprecated for
3029 * Huntington onwards.
3030 */
3031#define MC_CMD_PTP_OP_RX_SET_UUID_FILTER 0x11
3032/* enum: Set the MC packet filter Domain for received PTP packets. Deprecated
3033 * for Huntington onwards.
3034 */
3035#define MC_CMD_PTP_OP_RX_SET_DOMAIN_FILTER 0x12
3036/* enum: Set the clock source. Required for snapper tests on Huntington and
3037 * Medford. Not implemented for Siena or Medford2.
3038 */
3039#define MC_CMD_PTP_OP_SET_CLK_SRC 0x13
3040/* enum: Reset value of Timer Reg. Not implemented. */
3041#define MC_CMD_PTP_OP_RST_CLK 0x14
3042/* enum: Enable the forwarding of PPS events to the host */
3043#define MC_CMD_PTP_OP_PPS_ENABLE 0x15
3044/* enum: Get the time format used by this NIC for PTP operations */
3045#define MC_CMD_PTP_OP_GET_TIME_FORMAT 0x16
3046/* enum: Get the clock attributes. NOTE- extended version of
3047 * MC_CMD_PTP_OP_GET_TIME_FORMAT
3048 */
3049#define MC_CMD_PTP_OP_GET_ATTRIBUTES 0x16
3050/* enum: Get corrections that should be applied to the various different
3051 * timestamps
3052 */
3053#define MC_CMD_PTP_OP_GET_TIMESTAMP_CORRECTIONS 0x17
3054/* enum: Subscribe to receive periodic time events indicating the current NIC
3055 * time
3056 */
3057#define MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE 0x18
3058/* enum: Unsubscribe to stop receiving time events */
3059#define MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE 0x19
3060/* enum: PPS based manfacturing tests. Requires PPS output to be looped to PPS
3061 * input on the same NIC. Siena PTP adapters only.
3062 */
3063#define MC_CMD_PTP_OP_MANFTEST_PPS 0x1a
3064/* enum: Set the PTP sync status. Status is used by firmware to report to event
3065 * subscribers.
3066 */
3067#define MC_CMD_PTP_OP_SET_SYNC_STATUS 0x1b
3068/* enum: Above this for future use. */
3069#define MC_CMD_PTP_OP_MAX 0x1c
3070
3071/* MC_CMD_PTP_IN_ENABLE msgrequest */
3072#define MC_CMD_PTP_IN_ENABLE_LEN 16
3073#define MC_CMD_PTP_IN_CMD_OFST 0
3074#define MC_CMD_PTP_IN_CMD_LEN 4
3075#define MC_CMD_PTP_IN_PERIPH_ID_OFST 4
3076#define MC_CMD_PTP_IN_PERIPH_ID_LEN 4
3077/* Not used, initialize to 0. Events are always sent to function relative queue
3078 * 0.
3079 */
3080#define MC_CMD_PTP_IN_ENABLE_QUEUE_OFST 8
3081#define MC_CMD_PTP_IN_ENABLE_QUEUE_LEN 4
3082/* PTP timestamping mode. Not used from Huntington onwards. */
3083#define MC_CMD_PTP_IN_ENABLE_MODE_OFST 12
3084#define MC_CMD_PTP_IN_ENABLE_MODE_LEN 4
3085/* enum: PTP, version 1 */
3086#define MC_CMD_PTP_MODE_V1 0x0
3087/* enum: PTP, version 1, with VLAN headers - deprecated */
3088#define MC_CMD_PTP_MODE_V1_VLAN 0x1
3089/* enum: PTP, version 2 */
3090#define MC_CMD_PTP_MODE_V2 0x2
3091/* enum: PTP, version 2, with VLAN headers - deprecated */
3092#define MC_CMD_PTP_MODE_V2_VLAN 0x3
3093/* enum: PTP, version 2, with improved UUID filtering */
3094#define MC_CMD_PTP_MODE_V2_ENHANCED 0x4
3095/* enum: FCoE (seconds and microseconds) */
3096#define MC_CMD_PTP_MODE_FCOE 0x5
3097
3098/* MC_CMD_PTP_IN_DISABLE msgrequest */
3099#define MC_CMD_PTP_IN_DISABLE_LEN 8
3100/* MC_CMD_PTP_IN_CMD_OFST 0 */
3101/* MC_CMD_PTP_IN_CMD_LEN 4 */
3102/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3103/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3104
3105/* MC_CMD_PTP_IN_TRANSMIT msgrequest */
3106#define MC_CMD_PTP_IN_TRANSMIT_LENMIN 13
3107#define MC_CMD_PTP_IN_TRANSMIT_LENMAX 252
3108#define MC_CMD_PTP_IN_TRANSMIT_LENMAX_MCDI2 1020
3109#define MC_CMD_PTP_IN_TRANSMIT_LEN(num) (12+1*(num))
3110#define MC_CMD_PTP_IN_TRANSMIT_PACKET_NUM(len) (((len)-12)/1)
3111/* MC_CMD_PTP_IN_CMD_OFST 0 */
3112/* MC_CMD_PTP_IN_CMD_LEN 4 */
3113/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3114/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3115/* Transmit packet length */
3116#define MC_CMD_PTP_IN_TRANSMIT_LENGTH_OFST 8
3117#define MC_CMD_PTP_IN_TRANSMIT_LENGTH_LEN 4
3118/* Transmit packet data */
3119#define MC_CMD_PTP_IN_TRANSMIT_PACKET_OFST 12
3120#define MC_CMD_PTP_IN_TRANSMIT_PACKET_LEN 1
3121#define MC_CMD_PTP_IN_TRANSMIT_PACKET_MINNUM 1
3122#define MC_CMD_PTP_IN_TRANSMIT_PACKET_MAXNUM 240
3123#define MC_CMD_PTP_IN_TRANSMIT_PACKET_MAXNUM_MCDI2 1008
3124
3125/* MC_CMD_PTP_IN_READ_NIC_TIME msgrequest */
3126#define MC_CMD_PTP_IN_READ_NIC_TIME_LEN 8
3127/* MC_CMD_PTP_IN_CMD_OFST 0 */
3128/* MC_CMD_PTP_IN_CMD_LEN 4 */
3129/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3130/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3131
3132/* MC_CMD_PTP_IN_READ_NIC_TIME_V2 msgrequest */
3133#define MC_CMD_PTP_IN_READ_NIC_TIME_V2_LEN 8
3134/* MC_CMD_PTP_IN_CMD_OFST 0 */
3135/* MC_CMD_PTP_IN_CMD_LEN 4 */
3136/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3137/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3138
3139/* MC_CMD_PTP_IN_STATUS msgrequest */
3140#define MC_CMD_PTP_IN_STATUS_LEN 8
3141/* MC_CMD_PTP_IN_CMD_OFST 0 */
3142/* MC_CMD_PTP_IN_CMD_LEN 4 */
3143/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3144/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3145
3146/* MC_CMD_PTP_IN_ADJUST msgrequest */
3147#define MC_CMD_PTP_IN_ADJUST_LEN 24
3148/* MC_CMD_PTP_IN_CMD_OFST 0 */
3149/* MC_CMD_PTP_IN_CMD_LEN 4 */
3150/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3151/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3152/* Frequency adjustment 40 bit fixed point ns */
3153#define MC_CMD_PTP_IN_ADJUST_FREQ_OFST 8
3154#define MC_CMD_PTP_IN_ADJUST_FREQ_LEN 8
3155#define MC_CMD_PTP_IN_ADJUST_FREQ_LO_OFST 8
3156#define MC_CMD_PTP_IN_ADJUST_FREQ_LO_LEN 4
3157#define MC_CMD_PTP_IN_ADJUST_FREQ_LO_LBN 64
3158#define MC_CMD_PTP_IN_ADJUST_FREQ_LO_WIDTH 32
3159#define MC_CMD_PTP_IN_ADJUST_FREQ_HI_OFST 12
3160#define MC_CMD_PTP_IN_ADJUST_FREQ_HI_LEN 4
3161#define MC_CMD_PTP_IN_ADJUST_FREQ_HI_LBN 96
3162#define MC_CMD_PTP_IN_ADJUST_FREQ_HI_WIDTH 32
3163/* enum: Number of fractional bits in frequency adjustment */
3164#define MC_CMD_PTP_IN_ADJUST_BITS 0x28
3165/* enum: Number of fractional bits in frequency adjustment when FP44_FREQ_ADJ
3166 * is indicated in the MC_CMD_PTP_OUT_GET_ATTRIBUTES command CAPABILITIES
3167 * field.
3168 */
3169#define MC_CMD_PTP_IN_ADJUST_BITS_FP44 0x2c
3170/* Time adjustment in seconds */
3171#define MC_CMD_PTP_IN_ADJUST_SECONDS_OFST 16
3172#define MC_CMD_PTP_IN_ADJUST_SECONDS_LEN 4
3173/* Time adjustment major value */
3174#define MC_CMD_PTP_IN_ADJUST_MAJOR_OFST 16
3175#define MC_CMD_PTP_IN_ADJUST_MAJOR_LEN 4
3176/* Time adjustment in nanoseconds */
3177#define MC_CMD_PTP_IN_ADJUST_NANOSECONDS_OFST 20
3178#define MC_CMD_PTP_IN_ADJUST_NANOSECONDS_LEN 4
3179/* Time adjustment minor value */
3180#define MC_CMD_PTP_IN_ADJUST_MINOR_OFST 20
3181#define MC_CMD_PTP_IN_ADJUST_MINOR_LEN 4
3182
3183/* MC_CMD_PTP_IN_ADJUST_V2 msgrequest */
3184#define MC_CMD_PTP_IN_ADJUST_V2_LEN 28
3185/* MC_CMD_PTP_IN_CMD_OFST 0 */
3186/* MC_CMD_PTP_IN_CMD_LEN 4 */
3187/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3188/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3189/* Frequency adjustment 40 bit fixed point ns */
3190#define MC_CMD_PTP_IN_ADJUST_V2_FREQ_OFST 8
3191#define MC_CMD_PTP_IN_ADJUST_V2_FREQ_LEN 8
3192#define MC_CMD_PTP_IN_ADJUST_V2_FREQ_LO_OFST 8
3193#define MC_CMD_PTP_IN_ADJUST_V2_FREQ_LO_LEN 4
3194#define MC_CMD_PTP_IN_ADJUST_V2_FREQ_LO_LBN 64
3195#define MC_CMD_PTP_IN_ADJUST_V2_FREQ_LO_WIDTH 32
3196#define MC_CMD_PTP_IN_ADJUST_V2_FREQ_HI_OFST 12
3197#define MC_CMD_PTP_IN_ADJUST_V2_FREQ_HI_LEN 4
3198#define MC_CMD_PTP_IN_ADJUST_V2_FREQ_HI_LBN 96
3199#define MC_CMD_PTP_IN_ADJUST_V2_FREQ_HI_WIDTH 32
3200/* enum: Number of fractional bits in frequency adjustment */
3201/* MC_CMD_PTP_IN_ADJUST_BITS 0x28 */
3202/* enum: Number of fractional bits in frequency adjustment when FP44_FREQ_ADJ
3203 * is indicated in the MC_CMD_PTP_OUT_GET_ATTRIBUTES command CAPABILITIES
3204 * field.
3205 */
3206/* MC_CMD_PTP_IN_ADJUST_BITS_FP44 0x2c */
3207/* Time adjustment in seconds */
3208#define MC_CMD_PTP_IN_ADJUST_V2_SECONDS_OFST 16
3209#define MC_CMD_PTP_IN_ADJUST_V2_SECONDS_LEN 4
3210/* Time adjustment major value */
3211#define MC_CMD_PTP_IN_ADJUST_V2_MAJOR_OFST 16
3212#define MC_CMD_PTP_IN_ADJUST_V2_MAJOR_LEN 4
3213/* Time adjustment in nanoseconds */
3214#define MC_CMD_PTP_IN_ADJUST_V2_NANOSECONDS_OFST 20
3215#define MC_CMD_PTP_IN_ADJUST_V2_NANOSECONDS_LEN 4
3216/* Time adjustment minor value */
3217#define MC_CMD_PTP_IN_ADJUST_V2_MINOR_OFST 20
3218#define MC_CMD_PTP_IN_ADJUST_V2_MINOR_LEN 4
3219/* Upper 32bits of major time offset adjustment */
3220#define MC_CMD_PTP_IN_ADJUST_V2_MAJOR_HI_OFST 24
3221#define MC_CMD_PTP_IN_ADJUST_V2_MAJOR_HI_LEN 4
3222
3223/* MC_CMD_PTP_IN_SYNCHRONIZE msgrequest */
3224#define MC_CMD_PTP_IN_SYNCHRONIZE_LEN 20
3225/* MC_CMD_PTP_IN_CMD_OFST 0 */
3226/* MC_CMD_PTP_IN_CMD_LEN 4 */
3227/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3228/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3229/* Number of time readings to capture */
3230#define MC_CMD_PTP_IN_SYNCHRONIZE_NUMTIMESETS_OFST 8
3231#define MC_CMD_PTP_IN_SYNCHRONIZE_NUMTIMESETS_LEN 4
3232/* Host address in which to write "synchronization started" indication (64
3233 * bits)
3234 */
3235#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_OFST 12
3236#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LEN 8
3237#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LO_OFST 12
3238#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LO_LEN 4
3239#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LO_LBN 96
3240#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LO_WIDTH 32
3241#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_HI_OFST 16
3242#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_HI_LEN 4
3243#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_HI_LBN 128
3244#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_HI_WIDTH 32
3245
3246/* MC_CMD_PTP_IN_MANFTEST_BASIC msgrequest */
3247#define MC_CMD_PTP_IN_MANFTEST_BASIC_LEN 8
3248/* MC_CMD_PTP_IN_CMD_OFST 0 */
3249/* MC_CMD_PTP_IN_CMD_LEN 4 */
3250/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3251/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3252
3253/* MC_CMD_PTP_IN_MANFTEST_PACKET msgrequest */
3254#define MC_CMD_PTP_IN_MANFTEST_PACKET_LEN 12
3255/* MC_CMD_PTP_IN_CMD_OFST 0 */
3256/* MC_CMD_PTP_IN_CMD_LEN 4 */
3257/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3258/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3259/* Enable or disable packet testing */
3260#define MC_CMD_PTP_IN_MANFTEST_PACKET_TEST_ENABLE_OFST 8
3261#define MC_CMD_PTP_IN_MANFTEST_PACKET_TEST_ENABLE_LEN 4
3262
3263/* MC_CMD_PTP_IN_RESET_STATS msgrequest: Reset PTP statistics */
3264#define MC_CMD_PTP_IN_RESET_STATS_LEN 8
3265/* MC_CMD_PTP_IN_CMD_OFST 0 */
3266/* MC_CMD_PTP_IN_CMD_LEN 4 */
3267/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3268/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3269
3270/* MC_CMD_PTP_IN_DEBUG msgrequest */
3271#define MC_CMD_PTP_IN_DEBUG_LEN 12
3272/* MC_CMD_PTP_IN_CMD_OFST 0 */
3273/* MC_CMD_PTP_IN_CMD_LEN 4 */
3274/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3275/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3276/* Debug operations */
3277#define MC_CMD_PTP_IN_DEBUG_DEBUG_PARAM_OFST 8
3278#define MC_CMD_PTP_IN_DEBUG_DEBUG_PARAM_LEN 4
3279
3280/* MC_CMD_PTP_IN_FPGAREAD msgrequest */
3281#define MC_CMD_PTP_IN_FPGAREAD_LEN 16
3282/* MC_CMD_PTP_IN_CMD_OFST 0 */
3283/* MC_CMD_PTP_IN_CMD_LEN 4 */
3284/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3285/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3286#define MC_CMD_PTP_IN_FPGAREAD_ADDR_OFST 8
3287#define MC_CMD_PTP_IN_FPGAREAD_ADDR_LEN 4
3288#define MC_CMD_PTP_IN_FPGAREAD_NUMBYTES_OFST 12
3289#define MC_CMD_PTP_IN_FPGAREAD_NUMBYTES_LEN 4
3290
3291/* MC_CMD_PTP_IN_FPGAWRITE msgrequest */
3292#define MC_CMD_PTP_IN_FPGAWRITE_LENMIN 13
3293#define MC_CMD_PTP_IN_FPGAWRITE_LENMAX 252
3294#define MC_CMD_PTP_IN_FPGAWRITE_LENMAX_MCDI2 1020
3295#define MC_CMD_PTP_IN_FPGAWRITE_LEN(num) (12+1*(num))
3296#define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_NUM(len) (((len)-12)/1)
3297/* MC_CMD_PTP_IN_CMD_OFST 0 */
3298/* MC_CMD_PTP_IN_CMD_LEN 4 */
3299/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3300/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3301#define MC_CMD_PTP_IN_FPGAWRITE_ADDR_OFST 8
3302#define MC_CMD_PTP_IN_FPGAWRITE_ADDR_LEN 4
3303#define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_OFST 12
3304#define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_LEN 1
3305#define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MINNUM 1
3306#define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MAXNUM 240
3307#define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MAXNUM_MCDI2 1008
3308
3309/* MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST msgrequest */
3310#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_LEN 16
3311/* MC_CMD_PTP_IN_CMD_OFST 0 */
3312/* MC_CMD_PTP_IN_CMD_LEN 4 */
3313/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3314/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3315/* Time adjustment in seconds */
3316#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_SECONDS_OFST 8
3317#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_SECONDS_LEN 4
3318/* Time adjustment major value */
3319#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MAJOR_OFST 8
3320#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MAJOR_LEN 4
3321/* Time adjustment in nanoseconds */
3322#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_NANOSECONDS_OFST 12
3323#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_NANOSECONDS_LEN 4
3324/* Time adjustment minor value */
3325#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MINOR_OFST 12
3326#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MINOR_LEN 4
3327
3328/* MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2 msgrequest */
3329#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_LEN 20
3330/* MC_CMD_PTP_IN_CMD_OFST 0 */
3331/* MC_CMD_PTP_IN_CMD_LEN 4 */
3332/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3333/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3334/* Time adjustment in seconds */
3335#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_SECONDS_OFST 8
3336#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_SECONDS_LEN 4
3337/* Time adjustment major value */
3338#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MAJOR_OFST 8
3339#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MAJOR_LEN 4
3340/* Time adjustment in nanoseconds */
3341#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_NANOSECONDS_OFST 12
3342#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_NANOSECONDS_LEN 4
3343/* Time adjustment minor value */
3344#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MINOR_OFST 12
3345#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MINOR_LEN 4
3346/* Upper 32bits of major time offset adjustment */
3347#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MAJOR_HI_OFST 16
3348#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MAJOR_HI_LEN 4
3349
3350/* MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST msgrequest */
3351#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_LEN 16
3352/* MC_CMD_PTP_IN_CMD_OFST 0 */
3353/* MC_CMD_PTP_IN_CMD_LEN 4 */
3354/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3355/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3356/* Frequency adjustment 40 bit fixed point ns */
3357#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_OFST 8
3358#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LEN 8
3359#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LO_OFST 8
3360#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LO_LEN 4
3361#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LO_LBN 64
3362#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LO_WIDTH 32
3363#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_HI_OFST 12
3364#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_HI_LEN 4
3365#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_HI_LBN 96
3366#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_HI_WIDTH 32
3367/* Enum values, see field(s): */
3368/* MC_CMD_PTP/MC_CMD_PTP_IN_ADJUST/FREQ */
3369
3370/* MC_CMD_PTP_IN_RX_SET_VLAN_FILTER msgrequest */
3371#define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_LEN 24
3372/* MC_CMD_PTP_IN_CMD_OFST 0 */
3373/* MC_CMD_PTP_IN_CMD_LEN 4 */
3374/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3375/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3376/* Number of VLAN tags, 0 if not VLAN */
3377#define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_NUM_VLAN_TAGS_OFST 8
3378#define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_NUM_VLAN_TAGS_LEN 4
3379/* Set of VLAN tags to filter against */
3380#define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_OFST 12
3381#define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_LEN 4
3382#define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_NUM 3
3383
3384/* MC_CMD_PTP_IN_RX_SET_UUID_FILTER msgrequest */
3385#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_LEN 20
3386/* MC_CMD_PTP_IN_CMD_OFST 0 */
3387/* MC_CMD_PTP_IN_CMD_LEN 4 */
3388/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3389/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3390/* 1 to enable UUID filtering, 0 to disable */
3391#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_ENABLE_OFST 8
3392#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_ENABLE_LEN 4
3393/* UUID to filter against */
3394#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_OFST 12
3395#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LEN 8
3396#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LO_OFST 12
3397#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LO_LEN 4
3398#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LO_LBN 96
3399#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LO_WIDTH 32
3400#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_HI_OFST 16
3401#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_HI_LEN 4
3402#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_HI_LBN 128
3403#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_HI_WIDTH 32
3404
3405/* MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER msgrequest */
3406#define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_LEN 16
3407/* MC_CMD_PTP_IN_CMD_OFST 0 */
3408/* MC_CMD_PTP_IN_CMD_LEN 4 */
3409/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3410/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3411/* 1 to enable Domain filtering, 0 to disable */
3412#define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_ENABLE_OFST 8
3413#define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_ENABLE_LEN 4
3414/* Domain number to filter against */
3415#define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_DOMAIN_OFST 12
3416#define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_DOMAIN_LEN 4
3417
3418/* MC_CMD_PTP_IN_SET_CLK_SRC msgrequest */
3419#define MC_CMD_PTP_IN_SET_CLK_SRC_LEN 12
3420/* MC_CMD_PTP_IN_CMD_OFST 0 */
3421/* MC_CMD_PTP_IN_CMD_LEN 4 */
3422/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3423/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3424/* Set the clock source. */
3425#define MC_CMD_PTP_IN_SET_CLK_SRC_CLK_OFST 8
3426#define MC_CMD_PTP_IN_SET_CLK_SRC_CLK_LEN 4
3427/* enum: Internal. */
3428#define MC_CMD_PTP_CLK_SRC_INTERNAL 0x0
3429/* enum: External. */
3430#define MC_CMD_PTP_CLK_SRC_EXTERNAL 0x1
3431
3432/* MC_CMD_PTP_IN_RST_CLK msgrequest: Reset value of Timer Reg. */
3433#define MC_CMD_PTP_IN_RST_CLK_LEN 8
3434/* MC_CMD_PTP_IN_CMD_OFST 0 */
3435/* MC_CMD_PTP_IN_CMD_LEN 4 */
3436/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3437/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3438
3439/* MC_CMD_PTP_IN_PPS_ENABLE msgrequest */
3440#define MC_CMD_PTP_IN_PPS_ENABLE_LEN 12
3441/* MC_CMD_PTP_IN_CMD_OFST 0 */
3442/* MC_CMD_PTP_IN_CMD_LEN 4 */
3443/* Enable or disable */
3444#define MC_CMD_PTP_IN_PPS_ENABLE_OP_OFST 4
3445#define MC_CMD_PTP_IN_PPS_ENABLE_OP_LEN 4
3446/* enum: Enable */
3447#define MC_CMD_PTP_ENABLE_PPS 0x0
3448/* enum: Disable */
3449#define MC_CMD_PTP_DISABLE_PPS 0x1
3450/* Not used, initialize to 0. Events are always sent to function relative queue
3451 * 0.
3452 */
3453#define MC_CMD_PTP_IN_PPS_ENABLE_QUEUE_ID_OFST 8
3454#define MC_CMD_PTP_IN_PPS_ENABLE_QUEUE_ID_LEN 4
3455
3456/* MC_CMD_PTP_IN_GET_TIME_FORMAT msgrequest */
3457#define MC_CMD_PTP_IN_GET_TIME_FORMAT_LEN 8
3458/* MC_CMD_PTP_IN_CMD_OFST 0 */
3459/* MC_CMD_PTP_IN_CMD_LEN 4 */
3460/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3461/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3462
3463/* MC_CMD_PTP_IN_GET_ATTRIBUTES msgrequest */
3464#define MC_CMD_PTP_IN_GET_ATTRIBUTES_LEN 8
3465/* MC_CMD_PTP_IN_CMD_OFST 0 */
3466/* MC_CMD_PTP_IN_CMD_LEN 4 */
3467/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3468/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3469
3470/* MC_CMD_PTP_IN_GET_TIMESTAMP_CORRECTIONS msgrequest */
3471#define MC_CMD_PTP_IN_GET_TIMESTAMP_CORRECTIONS_LEN 8
3472/* MC_CMD_PTP_IN_CMD_OFST 0 */
3473/* MC_CMD_PTP_IN_CMD_LEN 4 */
3474/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3475/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3476
3477/* MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE msgrequest */
3478#define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN 12
3479/* MC_CMD_PTP_IN_CMD_OFST 0 */
3480/* MC_CMD_PTP_IN_CMD_LEN 4 */
3481/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3482/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3483/* Original field containing queue ID. Now extended to include flags. */
3484#define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_OFST 8
3485#define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_LEN 4
3486#define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_ID_OFST 8
3487#define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_ID_LBN 0
3488#define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_ID_WIDTH 16
3489#define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_REPORT_SYNC_STATUS_OFST 8
3490#define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_REPORT_SYNC_STATUS_LBN 31
3491#define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_REPORT_SYNC_STATUS_WIDTH 1
3492
3493/* MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE msgrequest */
3494#define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN 16
3495/* MC_CMD_PTP_IN_CMD_OFST 0 */
3496/* MC_CMD_PTP_IN_CMD_LEN 4 */
3497/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3498/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3499/* Unsubscribe options */
3500#define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL_OFST 8
3501#define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL_LEN 4
3502/* enum: Unsubscribe a single queue */
3503#define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE 0x0
3504/* enum: Unsubscribe all queues */
3505#define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_ALL 0x1
3506/* Event queue ID */
3507#define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE_OFST 12
3508#define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE_LEN 4
3509
3510/* MC_CMD_PTP_IN_MANFTEST_PPS msgrequest */
3511#define MC_CMD_PTP_IN_MANFTEST_PPS_LEN 12
3512/* MC_CMD_PTP_IN_CMD_OFST 0 */
3513/* MC_CMD_PTP_IN_CMD_LEN 4 */
3514/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3515/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3516/* 1 to enable PPS test mode, 0 to disable and return result. */
3517#define MC_CMD_PTP_IN_MANFTEST_PPS_TEST_ENABLE_OFST 8
3518#define MC_CMD_PTP_IN_MANFTEST_PPS_TEST_ENABLE_LEN 4
3519
3520/* MC_CMD_PTP_IN_SET_SYNC_STATUS msgrequest */
3521#define MC_CMD_PTP_IN_SET_SYNC_STATUS_LEN 24
3522/* MC_CMD_PTP_IN_CMD_OFST 0 */
3523/* MC_CMD_PTP_IN_CMD_LEN 4 */
3524/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3525/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3526/* NIC - Host System Clock Synchronization status */
3527#define MC_CMD_PTP_IN_SET_SYNC_STATUS_STATUS_OFST 8
3528#define MC_CMD_PTP_IN_SET_SYNC_STATUS_STATUS_LEN 4
3529/* enum: Host System clock and NIC clock are not in sync */
3530#define MC_CMD_PTP_IN_SET_SYNC_STATUS_NOT_IN_SYNC 0x0
3531/* enum: Host System clock and NIC clock are synchronized */
3532#define MC_CMD_PTP_IN_SET_SYNC_STATUS_IN_SYNC 0x1
3533/* If synchronized, number of seconds until clocks should be considered to be
3534 * no longer in sync.
3535 */
3536#define MC_CMD_PTP_IN_SET_SYNC_STATUS_TIMEOUT_OFST 12
3537#define MC_CMD_PTP_IN_SET_SYNC_STATUS_TIMEOUT_LEN 4
3538#define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED0_OFST 16
3539#define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED0_LEN 4
3540#define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED1_OFST 20
3541#define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED1_LEN 4
3542
3543/* MC_CMD_PTP_OUT msgresponse */
3544#define MC_CMD_PTP_OUT_LEN 0
3545
3546/* MC_CMD_PTP_OUT_TRANSMIT msgresponse */
3547#define MC_CMD_PTP_OUT_TRANSMIT_LEN 8
3548/* Value of seconds timestamp */
3549#define MC_CMD_PTP_OUT_TRANSMIT_SECONDS_OFST 0
3550#define MC_CMD_PTP_OUT_TRANSMIT_SECONDS_LEN 4
3551/* Timestamp major value */
3552#define MC_CMD_PTP_OUT_TRANSMIT_MAJOR_OFST 0
3553#define MC_CMD_PTP_OUT_TRANSMIT_MAJOR_LEN 4
3554/* Value of nanoseconds timestamp */
3555#define MC_CMD_PTP_OUT_TRANSMIT_NANOSECONDS_OFST 4
3556#define MC_CMD_PTP_OUT_TRANSMIT_NANOSECONDS_LEN 4
3557/* Timestamp minor value */
3558#define MC_CMD_PTP_OUT_TRANSMIT_MINOR_OFST 4
3559#define MC_CMD_PTP_OUT_TRANSMIT_MINOR_LEN 4
3560
3561/* MC_CMD_PTP_OUT_TIME_EVENT_SUBSCRIBE msgresponse */
3562#define MC_CMD_PTP_OUT_TIME_EVENT_SUBSCRIBE_LEN 0
3563
3564/* MC_CMD_PTP_OUT_TIME_EVENT_UNSUBSCRIBE msgresponse */
3565#define MC_CMD_PTP_OUT_TIME_EVENT_UNSUBSCRIBE_LEN 0
3566
3567/* MC_CMD_PTP_OUT_READ_NIC_TIME msgresponse */
3568#define MC_CMD_PTP_OUT_READ_NIC_TIME_LEN 8
3569/* Value of seconds timestamp */
3570#define MC_CMD_PTP_OUT_READ_NIC_TIME_SECONDS_OFST 0
3571#define MC_CMD_PTP_OUT_READ_NIC_TIME_SECONDS_LEN 4
3572/* Timestamp major value */
3573#define MC_CMD_PTP_OUT_READ_NIC_TIME_MAJOR_OFST 0
3574#define MC_CMD_PTP_OUT_READ_NIC_TIME_MAJOR_LEN 4
3575/* Value of nanoseconds timestamp */
3576#define MC_CMD_PTP_OUT_READ_NIC_TIME_NANOSECONDS_OFST 4
3577#define MC_CMD_PTP_OUT_READ_NIC_TIME_NANOSECONDS_LEN 4
3578/* Timestamp minor value */
3579#define MC_CMD_PTP_OUT_READ_NIC_TIME_MINOR_OFST 4
3580#define MC_CMD_PTP_OUT_READ_NIC_TIME_MINOR_LEN 4
3581
3582/* MC_CMD_PTP_OUT_READ_NIC_TIME_V2 msgresponse */
3583#define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_LEN 12
3584/* Value of seconds timestamp */
3585#define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_SECONDS_OFST 0
3586#define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_SECONDS_LEN 4
3587/* Timestamp major value */
3588#define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_OFST 0
3589#define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_LEN 4
3590/* Value of nanoseconds timestamp */
3591#define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_NANOSECONDS_OFST 4
3592#define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_NANOSECONDS_LEN 4
3593/* Timestamp minor value */
3594#define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MINOR_OFST 4
3595#define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MINOR_LEN 4
3596/* Upper 32bits of major timestamp value */
3597#define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_HI_OFST 8
3598#define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_HI_LEN 4
3599
3600/* MC_CMD_PTP_OUT_STATUS msgresponse */
3601#define MC_CMD_PTP_OUT_STATUS_LEN 64
3602/* Frequency of NIC's hardware clock */
3603#define MC_CMD_PTP_OUT_STATUS_CLOCK_FREQ_OFST 0
3604#define MC_CMD_PTP_OUT_STATUS_CLOCK_FREQ_LEN 4
3605/* Number of packets transmitted and timestamped */
3606#define MC_CMD_PTP_OUT_STATUS_STATS_TX_OFST 4
3607#define MC_CMD_PTP_OUT_STATUS_STATS_TX_LEN 4
3608/* Number of packets received and timestamped */
3609#define MC_CMD_PTP_OUT_STATUS_STATS_RX_OFST 8
3610#define MC_CMD_PTP_OUT_STATUS_STATS_RX_LEN 4
3611/* Number of packets timestamped by the FPGA */
3612#define MC_CMD_PTP_OUT_STATUS_STATS_TS_OFST 12
3613#define MC_CMD_PTP_OUT_STATUS_STATS_TS_LEN 4
3614/* Number of packets filter matched */
3615#define MC_CMD_PTP_OUT_STATUS_STATS_FM_OFST 16
3616#define MC_CMD_PTP_OUT_STATUS_STATS_FM_LEN 4
3617/* Number of packets not filter matched */
3618#define MC_CMD_PTP_OUT_STATUS_STATS_NFM_OFST 20
3619#define MC_CMD_PTP_OUT_STATUS_STATS_NFM_LEN 4
3620/* Number of PPS overflows (noise on input?) */
3621#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFLOW_OFST 24
3622#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFLOW_LEN 4
3623/* Number of PPS bad periods */
3624#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_BAD_OFST 28
3625#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_BAD_LEN 4
3626/* Minimum period of PPS pulse in nanoseconds */
3627#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MIN_OFST 32
3628#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MIN_LEN 4
3629/* Maximum period of PPS pulse in nanoseconds */
3630#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MAX_OFST 36
3631#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MAX_LEN 4
3632/* Last period of PPS pulse in nanoseconds */
3633#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_LAST_OFST 40
3634#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_LAST_LEN 4
3635/* Mean period of PPS pulse in nanoseconds */
3636#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MEAN_OFST 44
3637#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MEAN_LEN 4
3638/* Minimum offset of PPS pulse in nanoseconds (signed) */
3639#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MIN_OFST 48
3640#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MIN_LEN 4
3641/* Maximum offset of PPS pulse in nanoseconds (signed) */
3642#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MAX_OFST 52
3643#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MAX_LEN 4
3644/* Last offset of PPS pulse in nanoseconds (signed) */
3645#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_LAST_OFST 56
3646#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_LAST_LEN 4
3647/* Mean offset of PPS pulse in nanoseconds (signed) */
3648#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MEAN_OFST 60
3649#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MEAN_LEN 4
3650
3651/* MC_CMD_PTP_OUT_SYNCHRONIZE msgresponse */
3652#define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMIN 20
3653#define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMAX 240
3654#define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMAX_MCDI2 1020
3655#define MC_CMD_PTP_OUT_SYNCHRONIZE_LEN(num) (0+20*(num))
3656#define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_NUM(len) (((len)-0)/20)
3657/* A set of host and NIC times */
3658#define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_OFST 0
3659#define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_LEN 20
3660#define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MINNUM 1
3661#define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MAXNUM 12
3662#define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MAXNUM_MCDI2 51
3663/* Host time immediately before NIC's hardware clock read */
3664#define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTSTART_OFST 0
3665#define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTSTART_LEN 4
3666/* Value of seconds timestamp */
3667#define MC_CMD_PTP_OUT_SYNCHRONIZE_SECONDS_OFST 4
3668#define MC_CMD_PTP_OUT_SYNCHRONIZE_SECONDS_LEN 4
3669/* Timestamp major value */
3670#define MC_CMD_PTP_OUT_SYNCHRONIZE_MAJOR_OFST 4
3671#define MC_CMD_PTP_OUT_SYNCHRONIZE_MAJOR_LEN 4
3672/* Value of nanoseconds timestamp */
3673#define MC_CMD_PTP_OUT_SYNCHRONIZE_NANOSECONDS_OFST 8
3674#define MC_CMD_PTP_OUT_SYNCHRONIZE_NANOSECONDS_LEN 4
3675/* Timestamp minor value */
3676#define MC_CMD_PTP_OUT_SYNCHRONIZE_MINOR_OFST 8
3677#define MC_CMD_PTP_OUT_SYNCHRONIZE_MINOR_LEN 4
3678/* Host time immediately after NIC's hardware clock read */
3679#define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTEND_OFST 12
3680#define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTEND_LEN 4
3681/* Number of nanoseconds waited after reading NIC's hardware clock */
3682#define MC_CMD_PTP_OUT_SYNCHRONIZE_WAITNS_OFST 16
3683#define MC_CMD_PTP_OUT_SYNCHRONIZE_WAITNS_LEN 4
3684
3685/* MC_CMD_PTP_OUT_MANFTEST_BASIC msgresponse */
3686#define MC_CMD_PTP_OUT_MANFTEST_BASIC_LEN 8
3687/* Results of testing */
3688#define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_RESULT_OFST 0
3689#define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_RESULT_LEN 4
3690/* enum: Successful test */
3691#define MC_CMD_PTP_MANF_SUCCESS 0x0
3692/* enum: FPGA load failed */
3693#define MC_CMD_PTP_MANF_FPGA_LOAD 0x1
3694/* enum: FPGA version invalid */
3695#define MC_CMD_PTP_MANF_FPGA_VERSION 0x2
3696/* enum: FPGA registers incorrect */
3697#define MC_CMD_PTP_MANF_FPGA_REGISTERS 0x3
3698/* enum: Oscillator possibly not working? */
3699#define MC_CMD_PTP_MANF_OSCILLATOR 0x4
3700/* enum: Timestamps not increasing */
3701#define MC_CMD_PTP_MANF_TIMESTAMPS 0x5
3702/* enum: Mismatched packet count */
3703#define MC_CMD_PTP_MANF_PACKET_COUNT 0x6
3704/* enum: Mismatched packet count (Siena filter and FPGA) */
3705#define MC_CMD_PTP_MANF_FILTER_COUNT 0x7
3706/* enum: Not enough packets to perform timestamp check */
3707#define MC_CMD_PTP_MANF_PACKET_ENOUGH 0x8
3708/* enum: Timestamp trigger GPIO not working */
3709#define MC_CMD_PTP_MANF_GPIO_TRIGGER 0x9
3710/* enum: Insufficient PPS events to perform checks */
3711#define MC_CMD_PTP_MANF_PPS_ENOUGH 0xa
3712/* enum: PPS time event period not sufficiently close to 1s. */
3713#define MC_CMD_PTP_MANF_PPS_PERIOD 0xb
3714/* enum: PPS time event nS reading not sufficiently close to zero. */
3715#define MC_CMD_PTP_MANF_PPS_NS 0xc
3716/* enum: PTP peripheral registers incorrect */
3717#define MC_CMD_PTP_MANF_REGISTERS 0xd
3718/* enum: Failed to read time from PTP peripheral */
3719#define MC_CMD_PTP_MANF_CLOCK_READ 0xe
3720/* Presence of external oscillator */
3721#define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_EXTOSC_OFST 4
3722#define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_EXTOSC_LEN 4
3723
3724/* MC_CMD_PTP_OUT_MANFTEST_PACKET msgresponse */
3725#define MC_CMD_PTP_OUT_MANFTEST_PACKET_LEN 12
3726/* Results of testing */
3727#define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_RESULT_OFST 0
3728#define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_RESULT_LEN 4
3729/* Number of packets received by FPGA */
3730#define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FPGACOUNT_OFST 4
3731#define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FPGACOUNT_LEN 4
3732/* Number of packets received by Siena filters */
3733#define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FILTERCOUNT_OFST 8
3734#define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FILTERCOUNT_LEN 4
3735
3736/* MC_CMD_PTP_OUT_FPGAREAD msgresponse */
3737#define MC_CMD_PTP_OUT_FPGAREAD_LENMIN 1
3738#define MC_CMD_PTP_OUT_FPGAREAD_LENMAX 252
3739#define MC_CMD_PTP_OUT_FPGAREAD_LENMAX_MCDI2 1020
3740#define MC_CMD_PTP_OUT_FPGAREAD_LEN(num) (0+1*(num))
3741#define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_NUM(len) (((len)-0)/1)
3742#define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_OFST 0
3743#define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_LEN 1
3744#define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MINNUM 1
3745#define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MAXNUM 252
3746#define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MAXNUM_MCDI2 1020
3747
3748/* MC_CMD_PTP_OUT_GET_TIME_FORMAT msgresponse */
3749#define MC_CMD_PTP_OUT_GET_TIME_FORMAT_LEN 4
3750/* Time format required/used by for this NIC. Applies to all PTP MCDI
3751 * operations that pass times between the host and firmware. If this operation
3752 * is not supported (older firmware) a format of seconds and nanoseconds should
3753 * be assumed. Note this enum is deprecated. Do not add to it- use the
3754 * TIME_FORMAT field in MC_CMD_PTP_OUT_GET_ATTRIBUTES instead.
3755 */
3756#define MC_CMD_PTP_OUT_GET_TIME_FORMAT_FORMAT_OFST 0
3757#define MC_CMD_PTP_OUT_GET_TIME_FORMAT_FORMAT_LEN 4
3758/* enum: Times are in seconds and nanoseconds */
3759#define MC_CMD_PTP_OUT_GET_TIME_FORMAT_SECONDS_NANOSECONDS 0x0
3760/* enum: Major register has units of 16 second per tick, minor 8 ns per tick */
3761#define MC_CMD_PTP_OUT_GET_TIME_FORMAT_16SECONDS_8NANOSECONDS 0x1
3762/* enum: Major register has units of seconds, minor 2^-27s per tick */
3763#define MC_CMD_PTP_OUT_GET_TIME_FORMAT_SECONDS_27FRACTION 0x2
3764
3765/* MC_CMD_PTP_OUT_GET_ATTRIBUTES msgresponse */
3766#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_LEN 24
3767/* Time format required/used by for this NIC. Applies to all PTP MCDI
3768 * operations that pass times between the host and firmware. If this operation
3769 * is not supported (older firmware) a format of seconds and nanoseconds should
3770 * be assumed.
3771 */
3772#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_TIME_FORMAT_OFST 0
3773#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_TIME_FORMAT_LEN 4
3774/* enum: Times are in seconds and nanoseconds */
3775#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_NANOSECONDS 0x0
3776/* enum: Major register has units of 16 second per tick, minor 8 ns per tick */
3777#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_16SECONDS_8NANOSECONDS 0x1
3778/* enum: Major register has units of seconds, minor 2^-27s per tick */
3779#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_27FRACTION 0x2
3780/* enum: Major register units are seconds, minor units are quarter nanoseconds
3781 */
3782#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_QTR_NANOSECONDS 0x3
3783/* Minimum acceptable value for a corrected synchronization timeset. When
3784 * comparing host and NIC clock times, the MC returns a set of samples that
3785 * contain the host start and end time, the MC time when the host start was
3786 * detected and the time the MC waited between reading the time and detecting
3787 * the host end. The corrected sync window is the difference between the host
3788 * end and start times minus the time that the MC waited for host end.
3789 */
3790#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SYNC_WINDOW_MIN_OFST 4
3791#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SYNC_WINDOW_MIN_LEN 4
3792/* Various PTP capabilities */
3793#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_CAPABILITIES_OFST 8
3794#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_CAPABILITIES_LEN 4
3795#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_OFST 8
3796#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_LBN 0
3797#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_WIDTH 1
3798#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RX_TSTAMP_OOB_OFST 8
3799#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RX_TSTAMP_OOB_LBN 1
3800#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RX_TSTAMP_OOB_WIDTH 1
3801#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_64BIT_SECONDS_OFST 8
3802#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_64BIT_SECONDS_LBN 2
3803#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_64BIT_SECONDS_WIDTH 1
3804#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_FP44_FREQ_ADJ_OFST 8
3805#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_FP44_FREQ_ADJ_LBN 3
3806#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_FP44_FREQ_ADJ_WIDTH 1
3807#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED0_OFST 12
3808#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED0_LEN 4
3809#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED1_OFST 16
3810#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED1_LEN 4
3811#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED2_OFST 20
3812#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED2_LEN 4
3813
3814/* MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2 msgresponse */
3815#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_LEN 40
3816/* Time format required/used by for this NIC. Applies to all PTP MCDI
3817 * operations that pass times between the host and firmware. If this operation
3818 * is not supported (older firmware) a format of seconds and nanoseconds should
3819 * be assumed.
3820 */
3821#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_TIME_FORMAT_OFST 0
3822#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_TIME_FORMAT_LEN 4
3823/* enum: Times are in seconds and nanoseconds */
3824#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_SECONDS_NANOSECONDS 0x0
3825/* enum: Major register has units of 16 second per tick, minor 8 ns per tick */
3826#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_16SECONDS_8NANOSECONDS 0x1
3827/* enum: Major register has units of seconds, minor 2^-27s per tick */
3828#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_SECONDS_27FRACTION 0x2
3829/* enum: Major register units are seconds, minor units are quarter nanoseconds
3830 */
3831#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_SECONDS_QTR_NANOSECONDS 0x3
3832/* Minimum acceptable value for a corrected synchronization timeset. When
3833 * comparing host and NIC clock times, the MC returns a set of samples that
3834 * contain the host start and end time, the MC time when the host start was
3835 * detected and the time the MC waited between reading the time and detecting
3836 * the host end. The corrected sync window is the difference between the host
3837 * end and start times minus the time that the MC waited for host end.
3838 */
3839#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_SYNC_WINDOW_MIN_OFST 4
3840#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_SYNC_WINDOW_MIN_LEN 4
3841/* Various PTP capabilities */
3842#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_CAPABILITIES_OFST 8
3843#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_CAPABILITIES_LEN 4
3844#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_REPORT_SYNC_STATUS_OFST 8
3845#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_REPORT_SYNC_STATUS_LBN 0
3846#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_REPORT_SYNC_STATUS_WIDTH 1
3847#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_RX_TSTAMP_OOB_OFST 8
3848#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_RX_TSTAMP_OOB_LBN 1
3849#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_RX_TSTAMP_OOB_WIDTH 1
3850#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_64BIT_SECONDS_OFST 8
3851#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_64BIT_SECONDS_LBN 2
3852#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_64BIT_SECONDS_WIDTH 1
3853#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FP44_FREQ_ADJ_OFST 8
3854#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FP44_FREQ_ADJ_LBN 3
3855#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FP44_FREQ_ADJ_WIDTH 1
3856#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_RESERVED0_OFST 12
3857#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_RESERVED0_LEN 4
3858#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_RESERVED1_OFST 16
3859#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_RESERVED1_LEN 4
3860#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_RESERVED2_OFST 20
3861#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_RESERVED2_LEN 4
3862/* Minimum supported value for the FREQ field in
3863 * MC_CMD_PTP/MC_CMD_PTP_IN_ADJUST and
3864 * MC_CMD_PTP/MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST message requests. If this message
3865 * response is not supported a value of -0.1 ns should be assumed, which is
3866 * equivalent to a -10% adjustment.
3867 */
3868#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MIN_OFST 24
3869#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MIN_LEN 8
3870#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MIN_LO_OFST 24
3871#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MIN_LO_LEN 4
3872#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MIN_LO_LBN 192
3873#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MIN_LO_WIDTH 32
3874#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MIN_HI_OFST 28
3875#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MIN_HI_LEN 4
3876#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MIN_HI_LBN 224
3877#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MIN_HI_WIDTH 32
3878/* Maximum supported value for the FREQ field in
3879 * MC_CMD_PTP/MC_CMD_PTP_IN_ADJUST and
3880 * MC_CMD_PTP/MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST message requests. If this message
3881 * response is not supported a value of 0.1 ns should be assumed, which is
3882 * equivalent to a +10% adjustment.
3883 */
3884#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MAX_OFST 32
3885#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MAX_LEN 8
3886#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MAX_LO_OFST 32
3887#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MAX_LO_LEN 4
3888#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MAX_LO_LBN 256
3889#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MAX_LO_WIDTH 32
3890#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MAX_HI_OFST 36
3891#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MAX_HI_LEN 4
3892#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MAX_HI_LBN 288
3893#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MAX_HI_WIDTH 32
3894
3895/* MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS msgresponse */
3896#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_LEN 16
3897/* Uncorrected error on PTP transmit timestamps in NIC clock format */
3898#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_TRANSMIT_OFST 0
3899#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_TRANSMIT_LEN 4
3900/* Uncorrected error on PTP receive timestamps in NIC clock format */
3901#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_RECEIVE_OFST 4
3902#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_RECEIVE_LEN 4
3903/* Uncorrected error on PPS output in NIC clock format */
3904#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_OUT_OFST 8
3905#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_OUT_LEN 4
3906/* Uncorrected error on PPS input in NIC clock format */
3907#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_IN_OFST 12
3908#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_IN_LEN 4
3909
3910/* MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2 msgresponse */
3911#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_LEN 24
3912/* Uncorrected error on PTP transmit timestamps in NIC clock format */
3913#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_TX_OFST 0
3914#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_TX_LEN 4
3915/* Uncorrected error on PTP receive timestamps in NIC clock format */
3916#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_RX_OFST 4
3917#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_RX_LEN 4
3918/* Uncorrected error on PPS output in NIC clock format */
3919#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_OUT_OFST 8
3920#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_OUT_LEN 4
3921/* Uncorrected error on PPS input in NIC clock format */
3922#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_IN_OFST 12
3923#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_IN_LEN 4
3924/* Uncorrected error on non-PTP transmit timestamps in NIC clock format */
3925#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_TX_OFST 16
3926#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_TX_LEN 4
3927/* Uncorrected error on non-PTP receive timestamps in NIC clock format */
3928#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_RX_OFST 20
3929#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_RX_LEN 4
3930
3931/* MC_CMD_PTP_OUT_MANFTEST_PPS msgresponse */
3932#define MC_CMD_PTP_OUT_MANFTEST_PPS_LEN 4
3933/* Results of testing */
3934#define MC_CMD_PTP_OUT_MANFTEST_PPS_TEST_RESULT_OFST 0
3935#define MC_CMD_PTP_OUT_MANFTEST_PPS_TEST_RESULT_LEN 4
3936/* Enum values, see field(s): */
3937/* MC_CMD_PTP_OUT_MANFTEST_BASIC/TEST_RESULT */
3938
3939/* MC_CMD_PTP_OUT_SET_SYNC_STATUS msgresponse */
3940#define MC_CMD_PTP_OUT_SET_SYNC_STATUS_LEN 0
3941
3942
3943/***********************************/
3944/* MC_CMD_CSR_READ32
3945 * Read 32bit words from the indirect memory map.
3946 */
3947#define MC_CMD_CSR_READ32 0xc
3948#undef MC_CMD_0xc_PRIVILEGE_CTG
3949
3950#define MC_CMD_0xc_PRIVILEGE_CTG SRIOV_CTG_INSECURE
3951
3952/* MC_CMD_CSR_READ32_IN msgrequest */
3953#define MC_CMD_CSR_READ32_IN_LEN 12
3954/* Address */
3955#define MC_CMD_CSR_READ32_IN_ADDR_OFST 0
3956#define MC_CMD_CSR_READ32_IN_ADDR_LEN 4
3957#define MC_CMD_CSR_READ32_IN_STEP_OFST 4
3958#define MC_CMD_CSR_READ32_IN_STEP_LEN 4
3959#define MC_CMD_CSR_READ32_IN_NUMWORDS_OFST 8
3960#define MC_CMD_CSR_READ32_IN_NUMWORDS_LEN 4
3961
3962/* MC_CMD_CSR_READ32_OUT msgresponse */
3963#define MC_CMD_CSR_READ32_OUT_LENMIN 4
3964#define MC_CMD_CSR_READ32_OUT_LENMAX 252
3965#define MC_CMD_CSR_READ32_OUT_LENMAX_MCDI2 1020
3966#define MC_CMD_CSR_READ32_OUT_LEN(num) (0+4*(num))
3967#define MC_CMD_CSR_READ32_OUT_BUFFER_NUM(len) (((len)-0)/4)
3968/* The last dword is the status, not a value read */
3969#define MC_CMD_CSR_READ32_OUT_BUFFER_OFST 0
3970#define MC_CMD_CSR_READ32_OUT_BUFFER_LEN 4
3971#define MC_CMD_CSR_READ32_OUT_BUFFER_MINNUM 1
3972#define MC_CMD_CSR_READ32_OUT_BUFFER_MAXNUM 63
3973#define MC_CMD_CSR_READ32_OUT_BUFFER_MAXNUM_MCDI2 255
3974
3975
3976/***********************************/
3977/* MC_CMD_CSR_WRITE32
3978 * Write 32bit dwords to the indirect memory map.
3979 */
3980#define MC_CMD_CSR_WRITE32 0xd
3981#undef MC_CMD_0xd_PRIVILEGE_CTG
3982
3983#define MC_CMD_0xd_PRIVILEGE_CTG SRIOV_CTG_INSECURE
3984
3985/* MC_CMD_CSR_WRITE32_IN msgrequest */
3986#define MC_CMD_CSR_WRITE32_IN_LENMIN 12
3987#define MC_CMD_CSR_WRITE32_IN_LENMAX 252
3988#define MC_CMD_CSR_WRITE32_IN_LENMAX_MCDI2 1020
3989#define MC_CMD_CSR_WRITE32_IN_LEN(num) (8+4*(num))
3990#define MC_CMD_CSR_WRITE32_IN_BUFFER_NUM(len) (((len)-8)/4)
3991/* Address */
3992#define MC_CMD_CSR_WRITE32_IN_ADDR_OFST 0
3993#define MC_CMD_CSR_WRITE32_IN_ADDR_LEN 4
3994#define MC_CMD_CSR_WRITE32_IN_STEP_OFST 4
3995#define MC_CMD_CSR_WRITE32_IN_STEP_LEN 4
3996#define MC_CMD_CSR_WRITE32_IN_BUFFER_OFST 8
3997#define MC_CMD_CSR_WRITE32_IN_BUFFER_LEN 4
3998#define MC_CMD_CSR_WRITE32_IN_BUFFER_MINNUM 1
3999#define MC_CMD_CSR_WRITE32_IN_BUFFER_MAXNUM 61
4000#define MC_CMD_CSR_WRITE32_IN_BUFFER_MAXNUM_MCDI2 253
4001
4002/* MC_CMD_CSR_WRITE32_OUT msgresponse */
4003#define MC_CMD_CSR_WRITE32_OUT_LEN 4
4004#define MC_CMD_CSR_WRITE32_OUT_STATUS_OFST 0
4005#define MC_CMD_CSR_WRITE32_OUT_STATUS_LEN 4
4006
4007
4008/***********************************/
4009/* MC_CMD_HP
4010 * These commands are used for HP related features. They are grouped under one
4011 * MCDI command to avoid creating too many MCDI commands.
4012 */
4013#define MC_CMD_HP 0x54
4014#undef MC_CMD_0x54_PRIVILEGE_CTG
4015
4016#define MC_CMD_0x54_PRIVILEGE_CTG SRIOV_CTG_ADMIN
4017
4018/* MC_CMD_HP_IN msgrequest */
4019#define MC_CMD_HP_IN_LEN 16
4020/* HP OCSD sub-command. When address is not NULL, request activation of OCSD at
4021 * the specified address with the specified interval.When address is NULL,
4022 * INTERVAL is interpreted as a command: 0: stop OCSD / 1: Report OCSD current
4023 * state / 2: (debug) Show temperature reported by one of the supported
4024 * sensors.
4025 */
4026#define MC_CMD_HP_IN_SUBCMD_OFST 0
4027#define MC_CMD_HP_IN_SUBCMD_LEN 4
4028/* enum: OCSD (Option Card Sensor Data) sub-command. */
4029#define MC_CMD_HP_IN_OCSD_SUBCMD 0x0
4030/* enum: Last known valid HP sub-command. */
4031#define MC_CMD_HP_IN_LAST_SUBCMD 0x0
4032/* The address to the array of sensor fields. (Or NULL to use a sub-command.)
4033 */
4034#define MC_CMD_HP_IN_OCSD_ADDR_OFST 4
4035#define MC_CMD_HP_IN_OCSD_ADDR_LEN 8
4036#define MC_CMD_HP_IN_OCSD_ADDR_LO_OFST 4
4037#define MC_CMD_HP_IN_OCSD_ADDR_LO_LEN 4
4038#define MC_CMD_HP_IN_OCSD_ADDR_LO_LBN 32
4039#define MC_CMD_HP_IN_OCSD_ADDR_LO_WIDTH 32
4040#define MC_CMD_HP_IN_OCSD_ADDR_HI_OFST 8
4041#define MC_CMD_HP_IN_OCSD_ADDR_HI_LEN 4
4042#define MC_CMD_HP_IN_OCSD_ADDR_HI_LBN 64
4043#define MC_CMD_HP_IN_OCSD_ADDR_HI_WIDTH 32
4044/* The requested update interval, in seconds. (Or the sub-command if ADDR is
4045 * NULL.)
4046 */
4047#define MC_CMD_HP_IN_OCSD_INTERVAL_OFST 12
4048#define MC_CMD_HP_IN_OCSD_INTERVAL_LEN 4
4049
4050/* MC_CMD_HP_OUT msgresponse */
4051#define MC_CMD_HP_OUT_LEN 4
4052#define MC_CMD_HP_OUT_OCSD_STATUS_OFST 0
4053#define MC_CMD_HP_OUT_OCSD_STATUS_LEN 4
4054/* enum: OCSD stopped for this card. */
4055#define MC_CMD_HP_OUT_OCSD_STOPPED 0x1
4056/* enum: OCSD was successfully started with the address provided. */
4057#define MC_CMD_HP_OUT_OCSD_STARTED 0x2
4058/* enum: OCSD was already started for this card. */
4059#define MC_CMD_HP_OUT_OCSD_ALREADY_STARTED 0x3
4060
4061
4062/***********************************/
4063/* MC_CMD_STACKINFO
4064 * Get stack information.
4065 */
4066#define MC_CMD_STACKINFO 0xf
4067#undef MC_CMD_0xf_PRIVILEGE_CTG
4068
4069#define MC_CMD_0xf_PRIVILEGE_CTG SRIOV_CTG_ADMIN
4070
4071/* MC_CMD_STACKINFO_IN msgrequest */
4072#define MC_CMD_STACKINFO_IN_LEN 0
4073
4074/* MC_CMD_STACKINFO_OUT msgresponse */
4075#define MC_CMD_STACKINFO_OUT_LENMIN 12
4076#define MC_CMD_STACKINFO_OUT_LENMAX 252
4077#define MC_CMD_STACKINFO_OUT_LENMAX_MCDI2 1020
4078#define MC_CMD_STACKINFO_OUT_LEN(num) (0+12*(num))
4079#define MC_CMD_STACKINFO_OUT_THREAD_INFO_NUM(len) (((len)-0)/12)
4080/* (thread ptr, stack size, free space) for each thread in system */
4081#define MC_CMD_STACKINFO_OUT_THREAD_INFO_OFST 0
4082#define MC_CMD_STACKINFO_OUT_THREAD_INFO_LEN 12
4083#define MC_CMD_STACKINFO_OUT_THREAD_INFO_MINNUM 1
4084#define MC_CMD_STACKINFO_OUT_THREAD_INFO_MAXNUM 21
4085#define MC_CMD_STACKINFO_OUT_THREAD_INFO_MAXNUM_MCDI2 85
4086
4087
4088/***********************************/
4089/* MC_CMD_MDIO_READ
4090 * MDIO register read.
4091 */
4092#define MC_CMD_MDIO_READ 0x10
4093#undef MC_CMD_0x10_PRIVILEGE_CTG
4094
4095#define MC_CMD_0x10_PRIVILEGE_CTG SRIOV_CTG_GENERAL
4096
4097/* MC_CMD_MDIO_READ_IN msgrequest */
4098#define MC_CMD_MDIO_READ_IN_LEN 16
4099/* Bus number; there are two MDIO buses: one for the internal PHY, and one for
4100 * external devices.
4101 */
4102#define MC_CMD_MDIO_READ_IN_BUS_OFST 0
4103#define MC_CMD_MDIO_READ_IN_BUS_LEN 4
4104/* enum: Internal. */
4105#define MC_CMD_MDIO_BUS_INTERNAL 0x0
4106/* enum: External. */
4107#define MC_CMD_MDIO_BUS_EXTERNAL 0x1
4108/* Port address */
4109#define MC_CMD_MDIO_READ_IN_PRTAD_OFST 4
4110#define MC_CMD_MDIO_READ_IN_PRTAD_LEN 4
4111/* Device Address or clause 22. */
4112#define MC_CMD_MDIO_READ_IN_DEVAD_OFST 8
4113#define MC_CMD_MDIO_READ_IN_DEVAD_LEN 4
4114/* enum: By default all the MCDI MDIO operations perform clause45 mode. If you
4115 * want to use clause22 then set DEVAD = MC_CMD_MDIO_CLAUSE22.
4116 */
4117#define MC_CMD_MDIO_CLAUSE22 0x20
4118/* Address */
4119#define MC_CMD_MDIO_READ_IN_ADDR_OFST 12
4120#define MC_CMD_MDIO_READ_IN_ADDR_LEN 4
4121
4122/* MC_CMD_MDIO_READ_OUT msgresponse */
4123#define MC_CMD_MDIO_READ_OUT_LEN 8
4124/* Value */
4125#define MC_CMD_MDIO_READ_OUT_VALUE_OFST 0
4126#define MC_CMD_MDIO_READ_OUT_VALUE_LEN 4
4127/* Status the MDIO commands return the raw status bits from the MDIO block. A
4128 * "good" transaction should have the DONE bit set and all other bits clear.
4129 */
4130#define MC_CMD_MDIO_READ_OUT_STATUS_OFST 4
4131#define MC_CMD_MDIO_READ_OUT_STATUS_LEN 4
4132/* enum: Good. */
4133#define MC_CMD_MDIO_STATUS_GOOD 0x8
4134
4135
4136/***********************************/
4137/* MC_CMD_MDIO_WRITE
4138 * MDIO register write.
4139 */
4140#define MC_CMD_MDIO_WRITE 0x11
4141#undef MC_CMD_0x11_PRIVILEGE_CTG
4142
4143#define MC_CMD_0x11_PRIVILEGE_CTG SRIOV_CTG_ADMIN
4144
4145/* MC_CMD_MDIO_WRITE_IN msgrequest */
4146#define MC_CMD_MDIO_WRITE_IN_LEN 20
4147/* Bus number; there are two MDIO buses: one for the internal PHY, and one for
4148 * external devices.
4149 */
4150#define MC_CMD_MDIO_WRITE_IN_BUS_OFST 0
4151#define MC_CMD_MDIO_WRITE_IN_BUS_LEN 4
4152/* enum: Internal. */
4153/* MC_CMD_MDIO_BUS_INTERNAL 0x0 */
4154/* enum: External. */
4155/* MC_CMD_MDIO_BUS_EXTERNAL 0x1 */
4156/* Port address */
4157#define MC_CMD_MDIO_WRITE_IN_PRTAD_OFST 4
4158#define MC_CMD_MDIO_WRITE_IN_PRTAD_LEN 4
4159/* Device Address or clause 22. */
4160#define MC_CMD_MDIO_WRITE_IN_DEVAD_OFST 8
4161#define MC_CMD_MDIO_WRITE_IN_DEVAD_LEN 4
4162/* enum: By default all the MCDI MDIO operations perform clause45 mode. If you
4163 * want to use clause22 then set DEVAD = MC_CMD_MDIO_CLAUSE22.
4164 */
4165/* MC_CMD_MDIO_CLAUSE22 0x20 */
4166/* Address */
4167#define MC_CMD_MDIO_WRITE_IN_ADDR_OFST 12
4168#define MC_CMD_MDIO_WRITE_IN_ADDR_LEN 4
4169/* Value */
4170#define MC_CMD_MDIO_WRITE_IN_VALUE_OFST 16
4171#define MC_CMD_MDIO_WRITE_IN_VALUE_LEN 4
4172
4173/* MC_CMD_MDIO_WRITE_OUT msgresponse */
4174#define MC_CMD_MDIO_WRITE_OUT_LEN 4
4175/* Status; the MDIO commands return the raw status bits from the MDIO block. A
4176 * "good" transaction should have the DONE bit set and all other bits clear.
4177 */
4178#define MC_CMD_MDIO_WRITE_OUT_STATUS_OFST 0
4179#define MC_CMD_MDIO_WRITE_OUT_STATUS_LEN 4
4180/* enum: Good. */
4181/* MC_CMD_MDIO_STATUS_GOOD 0x8 */
4182
4183
4184/***********************************/
4185/* MC_CMD_DBI_WRITE
4186 * Write DBI register(s).
4187 */
4188#define MC_CMD_DBI_WRITE 0x12
4189#undef MC_CMD_0x12_PRIVILEGE_CTG
4190
4191#define MC_CMD_0x12_PRIVILEGE_CTG SRIOV_CTG_INSECURE
4192
4193/* MC_CMD_DBI_WRITE_IN msgrequest */
4194#define MC_CMD_DBI_WRITE_IN_LENMIN 12
4195#define MC_CMD_DBI_WRITE_IN_LENMAX 252
4196#define MC_CMD_DBI_WRITE_IN_LENMAX_MCDI2 1020
4197#define MC_CMD_DBI_WRITE_IN_LEN(num) (0+12*(num))
4198#define MC_CMD_DBI_WRITE_IN_DBIWROP_NUM(len) (((len)-0)/12)
4199/* Each write op consists of an address (offset 0), byte enable/VF/CS2 (offset
4200 * 32) and value (offset 64). See MC_CMD_DBIWROP_TYPEDEF.
4201 */
4202#define MC_CMD_DBI_WRITE_IN_DBIWROP_OFST 0
4203#define MC_CMD_DBI_WRITE_IN_DBIWROP_LEN 12
4204#define MC_CMD_DBI_WRITE_IN_DBIWROP_MINNUM 1
4205#define MC_CMD_DBI_WRITE_IN_DBIWROP_MAXNUM 21
4206#define MC_CMD_DBI_WRITE_IN_DBIWROP_MAXNUM_MCDI2 85
4207
4208/* MC_CMD_DBI_WRITE_OUT msgresponse */
4209#define MC_CMD_DBI_WRITE_OUT_LEN 0
4210
4211/* MC_CMD_DBIWROP_TYPEDEF structuredef */
4212#define MC_CMD_DBIWROP_TYPEDEF_LEN 12
4213#define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST 0
4214#define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_LEN 4
4215#define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_LBN 0
4216#define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_WIDTH 32
4217#define MC_CMD_DBIWROP_TYPEDEF_PARMS_OFST 4
4218#define MC_CMD_DBIWROP_TYPEDEF_PARMS_LEN 4
4219#define MC_CMD_DBIWROP_TYPEDEF_VF_NUM_OFST 4
4220#define MC_CMD_DBIWROP_TYPEDEF_VF_NUM_LBN 16
4221#define MC_CMD_DBIWROP_TYPEDEF_VF_NUM_WIDTH 16
4222#define MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_OFST 4
4223#define MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_LBN 15
4224#define MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_WIDTH 1
4225#define MC_CMD_DBIWROP_TYPEDEF_CS2_OFST 4
4226#define MC_CMD_DBIWROP_TYPEDEF_CS2_LBN 14
4227#define MC_CMD_DBIWROP_TYPEDEF_CS2_WIDTH 1
4228#define MC_CMD_DBIWROP_TYPEDEF_PARMS_LBN 32
4229#define MC_CMD_DBIWROP_TYPEDEF_PARMS_WIDTH 32
4230#define MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST 8
4231#define MC_CMD_DBIWROP_TYPEDEF_VALUE_LEN 4
4232#define MC_CMD_DBIWROP_TYPEDEF_VALUE_LBN 64
4233#define MC_CMD_DBIWROP_TYPEDEF_VALUE_WIDTH 32
4234
4235
4236/***********************************/
4237/* MC_CMD_PORT_READ32
4238 * Read a 32-bit register from the indirect port register map. The port to
4239 * access is implied by the Shared memory channel used.
4240 */
4241#define MC_CMD_PORT_READ32 0x14
4242
4243/* MC_CMD_PORT_READ32_IN msgrequest */
4244#define MC_CMD_PORT_READ32_IN_LEN 4
4245/* Address */
4246#define MC_CMD_PORT_READ32_IN_ADDR_OFST 0
4247#define MC_CMD_PORT_READ32_IN_ADDR_LEN 4
4248
4249/* MC_CMD_PORT_READ32_OUT msgresponse */
4250#define MC_CMD_PORT_READ32_OUT_LEN 8
4251/* Value */
4252#define MC_CMD_PORT_READ32_OUT_VALUE_OFST 0
4253#define MC_CMD_PORT_READ32_OUT_VALUE_LEN 4
4254/* Status */
4255#define MC_CMD_PORT_READ32_OUT_STATUS_OFST 4
4256#define MC_CMD_PORT_READ32_OUT_STATUS_LEN 4
4257
4258
4259/***********************************/
4260/* MC_CMD_PORT_WRITE32
4261 * Write a 32-bit register to the indirect port register map. The port to
4262 * access is implied by the Shared memory channel used.
4263 */
4264#define MC_CMD_PORT_WRITE32 0x15
4265
4266/* MC_CMD_PORT_WRITE32_IN msgrequest */
4267#define MC_CMD_PORT_WRITE32_IN_LEN 8
4268/* Address */
4269#define MC_CMD_PORT_WRITE32_IN_ADDR_OFST 0
4270#define MC_CMD_PORT_WRITE32_IN_ADDR_LEN 4
4271/* Value */
4272#define MC_CMD_PORT_WRITE32_IN_VALUE_OFST 4
4273#define MC_CMD_PORT_WRITE32_IN_VALUE_LEN 4
4274
4275/* MC_CMD_PORT_WRITE32_OUT msgresponse */
4276#define MC_CMD_PORT_WRITE32_OUT_LEN 4
4277/* Status */
4278#define MC_CMD_PORT_WRITE32_OUT_STATUS_OFST 0
4279#define MC_CMD_PORT_WRITE32_OUT_STATUS_LEN 4
4280
4281
4282/***********************************/
4283/* MC_CMD_PORT_READ128
4284 * Read a 128-bit register from the indirect port register map. The port to
4285 * access is implied by the Shared memory channel used.
4286 */
4287#define MC_CMD_PORT_READ128 0x16
4288
4289/* MC_CMD_PORT_READ128_IN msgrequest */
4290#define MC_CMD_PORT_READ128_IN_LEN 4
4291/* Address */
4292#define MC_CMD_PORT_READ128_IN_ADDR_OFST 0
4293#define MC_CMD_PORT_READ128_IN_ADDR_LEN 4
4294
4295/* MC_CMD_PORT_READ128_OUT msgresponse */
4296#define MC_CMD_PORT_READ128_OUT_LEN 20
4297/* Value */
4298#define MC_CMD_PORT_READ128_OUT_VALUE_OFST 0
4299#define MC_CMD_PORT_READ128_OUT_VALUE_LEN 16
4300/* Status */
4301#define MC_CMD_PORT_READ128_OUT_STATUS_OFST 16
4302#define MC_CMD_PORT_READ128_OUT_STATUS_LEN 4
4303
4304
4305/***********************************/
4306/* MC_CMD_PORT_WRITE128
4307 * Write a 128-bit register to the indirect port register map. The port to
4308 * access is implied by the Shared memory channel used.
4309 */
4310#define MC_CMD_PORT_WRITE128 0x17
4311
4312/* MC_CMD_PORT_WRITE128_IN msgrequest */
4313#define MC_CMD_PORT_WRITE128_IN_LEN 20
4314/* Address */
4315#define MC_CMD_PORT_WRITE128_IN_ADDR_OFST 0
4316#define MC_CMD_PORT_WRITE128_IN_ADDR_LEN 4
4317/* Value */
4318#define MC_CMD_PORT_WRITE128_IN_VALUE_OFST 4
4319#define MC_CMD_PORT_WRITE128_IN_VALUE_LEN 16
4320
4321/* MC_CMD_PORT_WRITE128_OUT msgresponse */
4322#define MC_CMD_PORT_WRITE128_OUT_LEN 4
4323/* Status */
4324#define MC_CMD_PORT_WRITE128_OUT_STATUS_OFST 0
4325#define MC_CMD_PORT_WRITE128_OUT_STATUS_LEN 4
4326
4327/* MC_CMD_CAPABILITIES structuredef */
4328#define MC_CMD_CAPABILITIES_LEN 4
4329/* Small buf table. */
4330#define MC_CMD_CAPABILITIES_SMALL_BUF_TBL_LBN 0
4331#define MC_CMD_CAPABILITIES_SMALL_BUF_TBL_WIDTH 1
4332/* Turbo mode (for Maranello). */
4333#define MC_CMD_CAPABILITIES_TURBO_LBN 1
4334#define MC_CMD_CAPABILITIES_TURBO_WIDTH 1
4335/* Turbo mode active (for Maranello). */
4336#define MC_CMD_CAPABILITIES_TURBO_ACTIVE_LBN 2
4337#define MC_CMD_CAPABILITIES_TURBO_ACTIVE_WIDTH 1
4338/* PTP offload. */
4339#define MC_CMD_CAPABILITIES_PTP_LBN 3
4340#define MC_CMD_CAPABILITIES_PTP_WIDTH 1
4341/* AOE mode. */
4342#define MC_CMD_CAPABILITIES_AOE_LBN 4
4343#define MC_CMD_CAPABILITIES_AOE_WIDTH 1
4344/* AOE mode active. */
4345#define MC_CMD_CAPABILITIES_AOE_ACTIVE_LBN 5
4346#define MC_CMD_CAPABILITIES_AOE_ACTIVE_WIDTH 1
4347/* AOE mode active. */
4348#define MC_CMD_CAPABILITIES_FC_ACTIVE_LBN 6
4349#define MC_CMD_CAPABILITIES_FC_ACTIVE_WIDTH 1
4350#define MC_CMD_CAPABILITIES_RESERVED_LBN 7
4351#define MC_CMD_CAPABILITIES_RESERVED_WIDTH 25
4352
4353
4354/***********************************/
4355/* MC_CMD_GET_BOARD_CFG
4356 * Returns the MC firmware configuration structure.
4357 */
4358#define MC_CMD_GET_BOARD_CFG 0x18
4359#undef MC_CMD_0x18_PRIVILEGE_CTG
4360
4361#define MC_CMD_0x18_PRIVILEGE_CTG SRIOV_CTG_GENERAL
4362
4363/* MC_CMD_GET_BOARD_CFG_IN msgrequest */
4364#define MC_CMD_GET_BOARD_CFG_IN_LEN 0
4365
4366/* MC_CMD_GET_BOARD_CFG_OUT msgresponse */
4367#define MC_CMD_GET_BOARD_CFG_OUT_LENMIN 96
4368#define MC_CMD_GET_BOARD_CFG_OUT_LENMAX 136
4369#define MC_CMD_GET_BOARD_CFG_OUT_LENMAX_MCDI2 136
4370#define MC_CMD_GET_BOARD_CFG_OUT_LEN(num) (72+2*(num))
4371#define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_NUM(len) (((len)-72)/2)
4372#define MC_CMD_GET_BOARD_CFG_OUT_BOARD_TYPE_OFST 0
4373#define MC_CMD_GET_BOARD_CFG_OUT_BOARD_TYPE_LEN 4
4374#define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_OFST 4
4375#define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_LEN 32
4376/* Capabilities for Siena Port0 (see struct MC_CMD_CAPABILITIES). Unused on
4377 * EF10 and later (use MC_CMD_GET_CAPABILITIES).
4378 */
4379#define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT0_OFST 36
4380#define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT0_LEN 4
4381/* Capabilities for Siena Port1 (see struct MC_CMD_CAPABILITIES). Unused on
4382 * EF10 and later (use MC_CMD_GET_CAPABILITIES).
4383 */
4384#define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT1_OFST 40
4385#define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT1_LEN 4
4386/* Base MAC address for Siena Port0. Unused on EF10 and later (use
4387 * MC_CMD_GET_MAC_ADDRESSES).
4388 */
4389#define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_OFST 44
4390#define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_LEN 6
4391/* Base MAC address for Siena Port1. Unused on EF10 and later (use
4392 * MC_CMD_GET_MAC_ADDRESSES).
4393 */
4394#define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_OFST 50
4395#define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_LEN 6
4396/* Size of MAC address pool for Siena Port0. Unused on EF10 and later (use
4397 * MC_CMD_GET_MAC_ADDRESSES).
4398 */
4399#define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT0_OFST 56
4400#define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT0_LEN 4
4401/* Size of MAC address pool for Siena Port1. Unused on EF10 and later (use
4402 * MC_CMD_GET_MAC_ADDRESSES).
4403 */
4404#define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT1_OFST 60
4405#define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT1_LEN 4
4406/* Increment between addresses in MAC address pool for Siena Port0. Unused on
4407 * EF10 and later (use MC_CMD_GET_MAC_ADDRESSES).
4408 */
4409#define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT0_OFST 64
4410#define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT0_LEN 4
4411/* Increment between addresses in MAC address pool for Siena Port1. Unused on
4412 * EF10 and later (use MC_CMD_GET_MAC_ADDRESSES).
4413 */
4414#define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT1_OFST 68
4415#define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT1_LEN 4
4416/* Siena only. This field contains a 16-bit value for each of the types of
4417 * NVRAM area. The values are defined in the firmware/mc/platform/.c file for a
4418 * specific board type, but otherwise have no meaning to the MC; they are used
4419 * by the driver to manage selection of appropriate firmware updates. Unused on
4420 * EF10 and later (use MC_CMD_NVRAM_METADATA).
4421 */
4422#define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_OFST 72
4423#define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_LEN 2
4424#define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MINNUM 12
4425#define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM 32
4426#define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM_MCDI2 32
4427
4428
4429/***********************************/
4430/* MC_CMD_DBI_READX
4431 * Read DBI register(s) -- extended functionality
4432 */
4433#define MC_CMD_DBI_READX 0x19
4434#undef MC_CMD_0x19_PRIVILEGE_CTG
4435
4436#define MC_CMD_0x19_PRIVILEGE_CTG SRIOV_CTG_INSECURE
4437
4438/* MC_CMD_DBI_READX_IN msgrequest */
4439#define MC_CMD_DBI_READX_IN_LENMIN 8
4440#define MC_CMD_DBI_READX_IN_LENMAX 248
4441#define MC_CMD_DBI_READX_IN_LENMAX_MCDI2 1016
4442#define MC_CMD_DBI_READX_IN_LEN(num) (0+8*(num))
4443#define MC_CMD_DBI_READX_IN_DBIRDOP_NUM(len) (((len)-0)/8)
4444/* Each Read op consists of an address (offset 0), VF/CS2) */
4445#define MC_CMD_DBI_READX_IN_DBIRDOP_OFST 0
4446#define MC_CMD_DBI_READX_IN_DBIRDOP_LEN 8
4447#define MC_CMD_DBI_READX_IN_DBIRDOP_LO_OFST 0
4448#define MC_CMD_DBI_READX_IN_DBIRDOP_LO_LEN 4
4449#define MC_CMD_DBI_READX_IN_DBIRDOP_LO_LBN 0
4450#define MC_CMD_DBI_READX_IN_DBIRDOP_LO_WIDTH 32
4451#define MC_CMD_DBI_READX_IN_DBIRDOP_HI_OFST 4
4452#define MC_CMD_DBI_READX_IN_DBIRDOP_HI_LEN 4
4453#define MC_CMD_DBI_READX_IN_DBIRDOP_HI_LBN 32
4454#define MC_CMD_DBI_READX_IN_DBIRDOP_HI_WIDTH 32
4455#define MC_CMD_DBI_READX_IN_DBIRDOP_MINNUM 1
4456#define MC_CMD_DBI_READX_IN_DBIRDOP_MAXNUM 31
4457#define MC_CMD_DBI_READX_IN_DBIRDOP_MAXNUM_MCDI2 127
4458
4459/* MC_CMD_DBI_READX_OUT msgresponse */
4460#define MC_CMD_DBI_READX_OUT_LENMIN 4
4461#define MC_CMD_DBI_READX_OUT_LENMAX 252
4462#define MC_CMD_DBI_READX_OUT_LENMAX_MCDI2 1020
4463#define MC_CMD_DBI_READX_OUT_LEN(num) (0+4*(num))
4464#define MC_CMD_DBI_READX_OUT_VALUE_NUM(len) (((len)-0)/4)
4465/* Value */
4466#define MC_CMD_DBI_READX_OUT_VALUE_OFST 0
4467#define MC_CMD_DBI_READX_OUT_VALUE_LEN 4
4468#define MC_CMD_DBI_READX_OUT_VALUE_MINNUM 1
4469#define MC_CMD_DBI_READX_OUT_VALUE_MAXNUM 63
4470#define MC_CMD_DBI_READX_OUT_VALUE_MAXNUM_MCDI2 255
4471
4472/* MC_CMD_DBIRDOP_TYPEDEF structuredef */
4473#define MC_CMD_DBIRDOP_TYPEDEF_LEN 8
4474#define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_OFST 0
4475#define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_LEN 4
4476#define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_LBN 0
4477#define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_WIDTH 32
4478#define MC_CMD_DBIRDOP_TYPEDEF_PARMS_OFST 4
4479#define MC_CMD_DBIRDOP_TYPEDEF_PARMS_LEN 4
4480#define MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_OFST 4
4481#define MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_LBN 16
4482#define MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_WIDTH 16
4483#define MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_OFST 4
4484#define MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_LBN 15
4485#define MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_WIDTH 1
4486#define MC_CMD_DBIRDOP_TYPEDEF_CS2_OFST 4
4487#define MC_CMD_DBIRDOP_TYPEDEF_CS2_LBN 14
4488#define MC_CMD_DBIRDOP_TYPEDEF_CS2_WIDTH 1
4489#define MC_CMD_DBIRDOP_TYPEDEF_PARMS_LBN 32
4490#define MC_CMD_DBIRDOP_TYPEDEF_PARMS_WIDTH 32
4491
4492
4493/***********************************/
4494/* MC_CMD_SET_RAND_SEED
4495 * Set the 16byte seed for the MC pseudo-random generator.
4496 */
4497#define MC_CMD_SET_RAND_SEED 0x1a
4498#undef MC_CMD_0x1a_PRIVILEGE_CTG
4499
4500#define MC_CMD_0x1a_PRIVILEGE_CTG SRIOV_CTG_INSECURE
4501
4502/* MC_CMD_SET_RAND_SEED_IN msgrequest */
4503#define MC_CMD_SET_RAND_SEED_IN_LEN 16
4504/* Seed value. */
4505#define MC_CMD_SET_RAND_SEED_IN_SEED_OFST 0
4506#define MC_CMD_SET_RAND_SEED_IN_SEED_LEN 16
4507
4508/* MC_CMD_SET_RAND_SEED_OUT msgresponse */
4509#define MC_CMD_SET_RAND_SEED_OUT_LEN 0
4510
4511
4512/***********************************/
4513/* MC_CMD_LTSSM_HIST
4514 * Retrieve the history of the LTSSM, if the build supports it.
4515 */
4516#define MC_CMD_LTSSM_HIST 0x1b
4517
4518/* MC_CMD_LTSSM_HIST_IN msgrequest */
4519#define MC_CMD_LTSSM_HIST_IN_LEN 0
4520
4521/* MC_CMD_LTSSM_HIST_OUT msgresponse */
4522#define MC_CMD_LTSSM_HIST_OUT_LENMIN 0
4523#define MC_CMD_LTSSM_HIST_OUT_LENMAX 252
4524#define MC_CMD_LTSSM_HIST_OUT_LENMAX_MCDI2 1020
4525#define MC_CMD_LTSSM_HIST_OUT_LEN(num) (0+4*(num))
4526#define MC_CMD_LTSSM_HIST_OUT_DATA_NUM(len) (((len)-0)/4)
4527/* variable number of LTSSM values, as bytes. The history is read-to-clear. */
4528#define MC_CMD_LTSSM_HIST_OUT_DATA_OFST 0
4529#define MC_CMD_LTSSM_HIST_OUT_DATA_LEN 4
4530#define MC_CMD_LTSSM_HIST_OUT_DATA_MINNUM 0
4531#define MC_CMD_LTSSM_HIST_OUT_DATA_MAXNUM 63
4532#define MC_CMD_LTSSM_HIST_OUT_DATA_MAXNUM_MCDI2 255
4533
4534
4535/***********************************/
4536/* MC_CMD_DRV_ATTACH
4537 * Inform MCPU that this port is managed on the host (i.e. driver active). For
4538 * Huntington, also request the preferred datapath firmware to use if possible
4539 * (it may not be possible for this request to be fulfilled; the driver must
4540 * issue a subsequent MC_CMD_GET_CAPABILITIES command to determine which
4541 * features are actually available). The FIRMWARE_ID field is ignored by older
4542 * platforms.
4543 */
4544#define MC_CMD_DRV_ATTACH 0x1c
4545#undef MC_CMD_0x1c_PRIVILEGE_CTG
4546
4547#define MC_CMD_0x1c_PRIVILEGE_CTG SRIOV_CTG_GENERAL
4548
4549/* MC_CMD_DRV_ATTACH_IN msgrequest */
4550#define MC_CMD_DRV_ATTACH_IN_LEN 12
4551/* new state to set if UPDATE=1 */
4552#define MC_CMD_DRV_ATTACH_IN_NEW_STATE_OFST 0
4553#define MC_CMD_DRV_ATTACH_IN_NEW_STATE_LEN 4
4554#define MC_CMD_DRV_ATTACH_OFST 0
4555#define MC_CMD_DRV_ATTACH_LBN 0
4556#define MC_CMD_DRV_ATTACH_WIDTH 1
4557#define MC_CMD_DRV_ATTACH_IN_ATTACH_OFST 0
4558#define MC_CMD_DRV_ATTACH_IN_ATTACH_LBN 0
4559#define MC_CMD_DRV_ATTACH_IN_ATTACH_WIDTH 1
4560#define MC_CMD_DRV_PREBOOT_OFST 0
4561#define MC_CMD_DRV_PREBOOT_LBN 1
4562#define MC_CMD_DRV_PREBOOT_WIDTH 1
4563#define MC_CMD_DRV_ATTACH_IN_PREBOOT_OFST 0
4564#define MC_CMD_DRV_ATTACH_IN_PREBOOT_LBN 1
4565#define MC_CMD_DRV_ATTACH_IN_PREBOOT_WIDTH 1
4566#define MC_CMD_DRV_ATTACH_IN_SUBVARIANT_AWARE_OFST 0
4567#define MC_CMD_DRV_ATTACH_IN_SUBVARIANT_AWARE_LBN 2
4568#define MC_CMD_DRV_ATTACH_IN_SUBVARIANT_AWARE_WIDTH 1
4569#define MC_CMD_DRV_ATTACH_IN_WANT_VI_SPREADING_OFST 0
4570#define MC_CMD_DRV_ATTACH_IN_WANT_VI_SPREADING_LBN 3
4571#define MC_CMD_DRV_ATTACH_IN_WANT_VI_SPREADING_WIDTH 1
4572#define MC_CMD_DRV_ATTACH_IN_WANT_V2_LINKCHANGES_OFST 0
4573#define MC_CMD_DRV_ATTACH_IN_WANT_V2_LINKCHANGES_LBN 4
4574#define MC_CMD_DRV_ATTACH_IN_WANT_V2_LINKCHANGES_WIDTH 1
4575#define MC_CMD_DRV_ATTACH_IN_WANT_RX_VI_SPREADING_INHIBIT_OFST 0
4576#define MC_CMD_DRV_ATTACH_IN_WANT_RX_VI_SPREADING_INHIBIT_LBN 5
4577#define MC_CMD_DRV_ATTACH_IN_WANT_RX_VI_SPREADING_INHIBIT_WIDTH 1
4578#define MC_CMD_DRV_ATTACH_IN_WANT_TX_ONLY_SPREADING_OFST 0
4579#define MC_CMD_DRV_ATTACH_IN_WANT_TX_ONLY_SPREADING_LBN 5
4580#define MC_CMD_DRV_ATTACH_IN_WANT_TX_ONLY_SPREADING_WIDTH 1
4581/* 1 to set new state, or 0 to just report the existing state */
4582#define MC_CMD_DRV_ATTACH_IN_UPDATE_OFST 4
4583#define MC_CMD_DRV_ATTACH_IN_UPDATE_LEN 4
4584/* preferred datapath firmware (for Huntington; ignored for Siena) */
4585#define MC_CMD_DRV_ATTACH_IN_FIRMWARE_ID_OFST 8
4586#define MC_CMD_DRV_ATTACH_IN_FIRMWARE_ID_LEN 4
4587/* enum: Prefer to use full featured firmware */
4588#define MC_CMD_FW_FULL_FEATURED 0x0
4589/* enum: Prefer to use firmware with fewer features but lower latency */
4590#define MC_CMD_FW_LOW_LATENCY 0x1
4591/* enum: Prefer to use firmware for SolarCapture packed stream mode */
4592#define MC_CMD_FW_PACKED_STREAM 0x2
4593/* enum: Prefer to use firmware with fewer features and simpler TX event
4594 * batching but higher TX packet rate
4595 */
4596#define MC_CMD_FW_HIGH_TX_RATE 0x3
4597/* enum: Reserved value */
4598#define MC_CMD_FW_PACKED_STREAM_HASH_MODE_1 0x4
4599/* enum: Prefer to use firmware with additional "rules engine" filtering
4600 * support
4601 */
4602#define MC_CMD_FW_RULES_ENGINE 0x5
4603/* enum: Prefer to use firmware with additional DPDK support */
4604#define MC_CMD_FW_DPDK 0x6
4605/* enum: Prefer to use "l3xudp" custom datapath firmware (see SF-119495-PD and
4606 * bug69716)
4607 */
4608#define MC_CMD_FW_L3XUDP 0x7
4609/* enum: Requests that the MC keep whatever datapath firmware is currently
4610 * running. It's used for test purposes, where we want to be able to shmboot
4611 * special test firmware variants. This option is only recognised in eftest
4612 * (i.e. non-production) builds.
4613 */
4614#define MC_CMD_FW_KEEP_CURRENT_EFTEST_ONLY 0xfffffffe
4615/* enum: Only this option is allowed for non-admin functions */
4616#define MC_CMD_FW_DONT_CARE 0xffffffff
4617
4618/* MC_CMD_DRV_ATTACH_IN_V2 msgrequest: Updated DRV_ATTACH to include driver
4619 * version
4620 */
4621#define MC_CMD_DRV_ATTACH_IN_V2_LEN 32
4622/* new state to set if UPDATE=1 */
4623#define MC_CMD_DRV_ATTACH_IN_V2_NEW_STATE_OFST 0
4624#define MC_CMD_DRV_ATTACH_IN_V2_NEW_STATE_LEN 4
4625/* MC_CMD_DRV_ATTACH_OFST 0 */
4626/* MC_CMD_DRV_ATTACH_LBN 0 */
4627/* MC_CMD_DRV_ATTACH_WIDTH 1 */
4628#define MC_CMD_DRV_ATTACH_IN_V2_ATTACH_OFST 0
4629#define MC_CMD_DRV_ATTACH_IN_V2_ATTACH_LBN 0
4630#define MC_CMD_DRV_ATTACH_IN_V2_ATTACH_WIDTH 1
4631/* MC_CMD_DRV_PREBOOT_OFST 0 */
4632/* MC_CMD_DRV_PREBOOT_LBN 1 */
4633/* MC_CMD_DRV_PREBOOT_WIDTH 1 */
4634#define MC_CMD_DRV_ATTACH_IN_V2_PREBOOT_OFST 0
4635#define MC_CMD_DRV_ATTACH_IN_V2_PREBOOT_LBN 1
4636#define MC_CMD_DRV_ATTACH_IN_V2_PREBOOT_WIDTH 1
4637#define MC_CMD_DRV_ATTACH_IN_V2_SUBVARIANT_AWARE_OFST 0
4638#define MC_CMD_DRV_ATTACH_IN_V2_SUBVARIANT_AWARE_LBN 2
4639#define MC_CMD_DRV_ATTACH_IN_V2_SUBVARIANT_AWARE_WIDTH 1
4640#define MC_CMD_DRV_ATTACH_IN_V2_WANT_VI_SPREADING_OFST 0
4641#define MC_CMD_DRV_ATTACH_IN_V2_WANT_VI_SPREADING_LBN 3
4642#define MC_CMD_DRV_ATTACH_IN_V2_WANT_VI_SPREADING_WIDTH 1
4643#define MC_CMD_DRV_ATTACH_IN_V2_WANT_V2_LINKCHANGES_OFST 0
4644#define MC_CMD_DRV_ATTACH_IN_V2_WANT_V2_LINKCHANGES_LBN 4
4645#define MC_CMD_DRV_ATTACH_IN_V2_WANT_V2_LINKCHANGES_WIDTH 1
4646#define MC_CMD_DRV_ATTACH_IN_V2_WANT_RX_VI_SPREADING_INHIBIT_OFST 0
4647#define MC_CMD_DRV_ATTACH_IN_V2_WANT_RX_VI_SPREADING_INHIBIT_LBN 5
4648#define MC_CMD_DRV_ATTACH_IN_V2_WANT_RX_VI_SPREADING_INHIBIT_WIDTH 1
4649#define MC_CMD_DRV_ATTACH_IN_V2_WANT_TX_ONLY_SPREADING_OFST 0
4650#define MC_CMD_DRV_ATTACH_IN_V2_WANT_TX_ONLY_SPREADING_LBN 5
4651#define MC_CMD_DRV_ATTACH_IN_V2_WANT_TX_ONLY_SPREADING_WIDTH 1
4652/* 1 to set new state, or 0 to just report the existing state */
4653#define MC_CMD_DRV_ATTACH_IN_V2_UPDATE_OFST 4
4654#define MC_CMD_DRV_ATTACH_IN_V2_UPDATE_LEN 4
4655/* preferred datapath firmware (for Huntington; ignored for Siena) */
4656#define MC_CMD_DRV_ATTACH_IN_V2_FIRMWARE_ID_OFST 8
4657#define MC_CMD_DRV_ATTACH_IN_V2_FIRMWARE_ID_LEN 4
4658/* enum: Prefer to use full featured firmware */
4659/* MC_CMD_FW_FULL_FEATURED 0x0 */
4660/* enum: Prefer to use firmware with fewer features but lower latency */
4661/* MC_CMD_FW_LOW_LATENCY 0x1 */
4662/* enum: Prefer to use firmware for SolarCapture packed stream mode */
4663/* MC_CMD_FW_PACKED_STREAM 0x2 */
4664/* enum: Prefer to use firmware with fewer features and simpler TX event
4665 * batching but higher TX packet rate
4666 */
4667/* MC_CMD_FW_HIGH_TX_RATE 0x3 */
4668/* enum: Reserved value */
4669/* MC_CMD_FW_PACKED_STREAM_HASH_MODE_1 0x4 */
4670/* enum: Prefer to use firmware with additional "rules engine" filtering
4671 * support
4672 */
4673/* MC_CMD_FW_RULES_ENGINE 0x5 */
4674/* enum: Prefer to use firmware with additional DPDK support */
4675/* MC_CMD_FW_DPDK 0x6 */
4676/* enum: Prefer to use "l3xudp" custom datapath firmware (see SF-119495-PD and
4677 * bug69716)
4678 */
4679/* MC_CMD_FW_L3XUDP 0x7 */
4680/* enum: Requests that the MC keep whatever datapath firmware is currently
4681 * running. It's used for test purposes, where we want to be able to shmboot
4682 * special test firmware variants. This option is only recognised in eftest
4683 * (i.e. non-production) builds.
4684 */
4685/* MC_CMD_FW_KEEP_CURRENT_EFTEST_ONLY 0xfffffffe */
4686/* enum: Only this option is allowed for non-admin functions */
4687/* MC_CMD_FW_DONT_CARE 0xffffffff */
4688/* Version of the driver to be reported by management protocols (e.g. NC-SI)
4689 * handled by the NIC. This is a zero-terminated ASCII string.
4690 */
4691#define MC_CMD_DRV_ATTACH_IN_V2_DRIVER_VERSION_OFST 12
4692#define MC_CMD_DRV_ATTACH_IN_V2_DRIVER_VERSION_LEN 20
4693
4694/* MC_CMD_DRV_ATTACH_OUT msgresponse */
4695#define MC_CMD_DRV_ATTACH_OUT_LEN 4
4696/* previous or existing state, see the bitmask at NEW_STATE */
4697#define MC_CMD_DRV_ATTACH_OUT_OLD_STATE_OFST 0
4698#define MC_CMD_DRV_ATTACH_OUT_OLD_STATE_LEN 4
4699
4700/* MC_CMD_DRV_ATTACH_EXT_OUT msgresponse */
4701#define MC_CMD_DRV_ATTACH_EXT_OUT_LEN 8
4702/* previous or existing state, see the bitmask at NEW_STATE */
4703#define MC_CMD_DRV_ATTACH_EXT_OUT_OLD_STATE_OFST 0
4704#define MC_CMD_DRV_ATTACH_EXT_OUT_OLD_STATE_LEN 4
4705/* Flags associated with this function */
4706#define MC_CMD_DRV_ATTACH_EXT_OUT_FUNC_FLAGS_OFST 4
4707#define MC_CMD_DRV_ATTACH_EXT_OUT_FUNC_FLAGS_LEN 4
4708/* enum: Labels the lowest-numbered function visible to the OS */
4709#define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY 0x0
4710/* enum: The function can control the link state of the physical port it is
4711 * bound to.
4712 */
4713#define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL 0x1
4714/* enum: The function can perform privileged operations */
4715#define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TRUSTED 0x2
4716/* enum: The function does not have an active port associated with it. The port
4717 * refers to the Sorrento external FPGA port.
4718 */
4719#define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_NO_ACTIVE_PORT 0x3
4720/* enum: If set, indicates that VI spreading is currently enabled. Will always
4721 * indicate the current state, regardless of the value in the WANT_VI_SPREADING
4722 * input.
4723 */
4724#define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_VI_SPREADING_ENABLED 0x4
4725/* enum: Used during development only. Should no longer be used. */
4726#define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_RX_VI_SPREADING_INHIBITED 0x5
4727/* enum: If set, indicates that TX only spreading is enabled. Even-numbered
4728 * TXQs will use one engine, and odd-numbered TXQs will use the other. This
4729 * also has the effect that only even-numbered RXQs will receive traffic.
4730 */
4731#define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TX_ONLY_VI_SPREADING_ENABLED 0x5
4732
4733
4734/***********************************/
4735/* MC_CMD_SHMUART
4736 * Route UART output to circular buffer in shared memory instead.
4737 */
4738#define MC_CMD_SHMUART 0x1f
4739
4740/* MC_CMD_SHMUART_IN msgrequest */
4741#define MC_CMD_SHMUART_IN_LEN 4
4742/* ??? */
4743#define MC_CMD_SHMUART_IN_FLAG_OFST 0
4744#define MC_CMD_SHMUART_IN_FLAG_LEN 4
4745
4746/* MC_CMD_SHMUART_OUT msgresponse */
4747#define MC_CMD_SHMUART_OUT_LEN 0
4748
4749
4750/***********************************/
4751/* MC_CMD_PORT_RESET
4752 * Generic per-port reset. There is no equivalent for per-board reset. Locks
4753 * required: None; Return code: 0, ETIME. NOTE: This command is deprecated -
4754 * use MC_CMD_ENTITY_RESET instead.
4755 */
4756#define MC_CMD_PORT_RESET 0x20
4757#undef MC_CMD_0x20_PRIVILEGE_CTG
4758
4759#define MC_CMD_0x20_PRIVILEGE_CTG SRIOV_CTG_GENERAL
4760
4761/* MC_CMD_PORT_RESET_IN msgrequest */
4762#define MC_CMD_PORT_RESET_IN_LEN 0
4763
4764/* MC_CMD_PORT_RESET_OUT msgresponse */
4765#define MC_CMD_PORT_RESET_OUT_LEN 0
4766
4767
4768/***********************************/
4769/* MC_CMD_ENTITY_RESET
4770 * Generic per-resource reset. There is no equivalent for per-board reset.
4771 * Locks required: None; Return code: 0, ETIME. NOTE: This command is an
4772 * extended version of the deprecated MC_CMD_PORT_RESET with added fields.
4773 */
4774#define MC_CMD_ENTITY_RESET 0x20
4775/* MC_CMD_0x20_PRIVILEGE_CTG SRIOV_CTG_GENERAL */
4776
4777/* MC_CMD_ENTITY_RESET_IN msgrequest */
4778#define MC_CMD_ENTITY_RESET_IN_LEN 4
4779/* Optional flags field. Omitting this will perform a "legacy" reset action
4780 * (TBD).
4781 */
4782#define MC_CMD_ENTITY_RESET_IN_FLAG_OFST 0
4783#define MC_CMD_ENTITY_RESET_IN_FLAG_LEN 4
4784#define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_OFST 0
4785#define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_LBN 0
4786#define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_WIDTH 1
4787
4788/* MC_CMD_ENTITY_RESET_OUT msgresponse */
4789#define MC_CMD_ENTITY_RESET_OUT_LEN 0
4790
4791
4792/***********************************/
4793/* MC_CMD_PCIE_CREDITS
4794 * Read instantaneous and minimum flow control thresholds.
4795 */
4796#define MC_CMD_PCIE_CREDITS 0x21
4797
4798/* MC_CMD_PCIE_CREDITS_IN msgrequest */
4799#define MC_CMD_PCIE_CREDITS_IN_LEN 8
4800/* poll period. 0 is disabled */
4801#define MC_CMD_PCIE_CREDITS_IN_POLL_PERIOD_OFST 0
4802#define MC_CMD_PCIE_CREDITS_IN_POLL_PERIOD_LEN 4
4803/* wipe statistics */
4804#define MC_CMD_PCIE_CREDITS_IN_WIPE_OFST 4
4805#define MC_CMD_PCIE_CREDITS_IN_WIPE_LEN 4
4806
4807/* MC_CMD_PCIE_CREDITS_OUT msgresponse */
4808#define MC_CMD_PCIE_CREDITS_OUT_LEN 16
4809#define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_OFST 0
4810#define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_LEN 2
4811#define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_OFST 2
4812#define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_LEN 2
4813#define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_OFST 4
4814#define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_LEN 2
4815#define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_OFST 6
4816#define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_LEN 2
4817#define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_OFST 8
4818#define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_LEN 2
4819#define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_OFST 10
4820#define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_LEN 2
4821#define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_OFST 12
4822#define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_LEN 2
4823#define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_OFST 14
4824#define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_LEN 2
4825
4826
4827/***********************************/
4828/* MC_CMD_RXD_MONITOR
4829 * Get histogram of RX queue fill level.
4830 */
4831#define MC_CMD_RXD_MONITOR 0x22
4832
4833/* MC_CMD_RXD_MONITOR_IN msgrequest */
4834#define MC_CMD_RXD_MONITOR_IN_LEN 12
4835#define MC_CMD_RXD_MONITOR_IN_QID_OFST 0
4836#define MC_CMD_RXD_MONITOR_IN_QID_LEN 4
4837#define MC_CMD_RXD_MONITOR_IN_POLL_PERIOD_OFST 4
4838#define MC_CMD_RXD_MONITOR_IN_POLL_PERIOD_LEN 4
4839#define MC_CMD_RXD_MONITOR_IN_WIPE_OFST 8
4840#define MC_CMD_RXD_MONITOR_IN_WIPE_LEN 4
4841
4842/* MC_CMD_RXD_MONITOR_OUT msgresponse */
4843#define MC_CMD_RXD_MONITOR_OUT_LEN 80
4844#define MC_CMD_RXD_MONITOR_OUT_QID_OFST 0
4845#define MC_CMD_RXD_MONITOR_OUT_QID_LEN 4
4846#define MC_CMD_RXD_MONITOR_OUT_RING_FILL_OFST 4
4847#define MC_CMD_RXD_MONITOR_OUT_RING_FILL_LEN 4
4848#define MC_CMD_RXD_MONITOR_OUT_CACHE_FILL_OFST 8
4849#define MC_CMD_RXD_MONITOR_OUT_CACHE_FILL_LEN 4
4850#define MC_CMD_RXD_MONITOR_OUT_RING_LT_1_OFST 12
4851#define MC_CMD_RXD_MONITOR_OUT_RING_LT_1_LEN 4
4852#define MC_CMD_RXD_MONITOR_OUT_RING_LT_2_OFST 16
4853#define MC_CMD_RXD_MONITOR_OUT_RING_LT_2_LEN 4
4854#define MC_CMD_RXD_MONITOR_OUT_RING_LT_4_OFST 20
4855#define MC_CMD_RXD_MONITOR_OUT_RING_LT_4_LEN 4
4856#define MC_CMD_RXD_MONITOR_OUT_RING_LT_8_OFST 24
4857#define MC_CMD_RXD_MONITOR_OUT_RING_LT_8_LEN 4
4858#define MC_CMD_RXD_MONITOR_OUT_RING_LT_16_OFST 28
4859#define MC_CMD_RXD_MONITOR_OUT_RING_LT_16_LEN 4
4860#define MC_CMD_RXD_MONITOR_OUT_RING_LT_32_OFST 32
4861#define MC_CMD_RXD_MONITOR_OUT_RING_LT_32_LEN 4
4862#define MC_CMD_RXD_MONITOR_OUT_RING_LT_64_OFST 36
4863#define MC_CMD_RXD_MONITOR_OUT_RING_LT_64_LEN 4
4864#define MC_CMD_RXD_MONITOR_OUT_RING_LT_128_OFST 40
4865#define MC_CMD_RXD_MONITOR_OUT_RING_LT_128_LEN 4
4866#define MC_CMD_RXD_MONITOR_OUT_RING_LT_256_OFST 44
4867#define MC_CMD_RXD_MONITOR_OUT_RING_LT_256_LEN 4
4868#define MC_CMD_RXD_MONITOR_OUT_RING_GE_256_OFST 48
4869#define MC_CMD_RXD_MONITOR_OUT_RING_GE_256_LEN 4
4870#define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_1_OFST 52
4871#define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_1_LEN 4
4872#define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_2_OFST 56
4873#define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_2_LEN 4
4874#define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_4_OFST 60
4875#define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_4_LEN 4
4876#define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_8_OFST 64
4877#define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_8_LEN 4
4878#define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_16_OFST 68
4879#define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_16_LEN 4
4880#define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_32_OFST 72
4881#define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_32_LEN 4
4882#define MC_CMD_RXD_MONITOR_OUT_CACHE_GE_32_OFST 76
4883#define MC_CMD_RXD_MONITOR_OUT_CACHE_GE_32_LEN 4
4884
4885
4886/***********************************/
4887/* MC_CMD_PUTS
4888 * Copy the given ASCII string out onto UART and/or out of the network port.
4889 */
4890#define MC_CMD_PUTS 0x23
4891#undef MC_CMD_0x23_PRIVILEGE_CTG
4892
4893#define MC_CMD_0x23_PRIVILEGE_CTG SRIOV_CTG_INSECURE
4894
4895/* MC_CMD_PUTS_IN msgrequest */
4896#define MC_CMD_PUTS_IN_LENMIN 13
4897#define MC_CMD_PUTS_IN_LENMAX 252
4898#define MC_CMD_PUTS_IN_LENMAX_MCDI2 1020
4899#define MC_CMD_PUTS_IN_LEN(num) (12+1*(num))
4900#define MC_CMD_PUTS_IN_STRING_NUM(len) (((len)-12)/1)
4901#define MC_CMD_PUTS_IN_DEST_OFST 0
4902#define MC_CMD_PUTS_IN_DEST_LEN 4
4903#define MC_CMD_PUTS_IN_UART_OFST 0
4904#define MC_CMD_PUTS_IN_UART_LBN 0
4905#define MC_CMD_PUTS_IN_UART_WIDTH 1
4906#define MC_CMD_PUTS_IN_PORT_OFST 0
4907#define MC_CMD_PUTS_IN_PORT_LBN 1
4908#define MC_CMD_PUTS_IN_PORT_WIDTH 1
4909#define MC_CMD_PUTS_IN_DHOST_OFST 4
4910#define MC_CMD_PUTS_IN_DHOST_LEN 6
4911#define MC_CMD_PUTS_IN_STRING_OFST 12
4912#define MC_CMD_PUTS_IN_STRING_LEN 1
4913#define MC_CMD_PUTS_IN_STRING_MINNUM 1
4914#define MC_CMD_PUTS_IN_STRING_MAXNUM 240
4915#define MC_CMD_PUTS_IN_STRING_MAXNUM_MCDI2 1008
4916
4917/* MC_CMD_PUTS_OUT msgresponse */
4918#define MC_CMD_PUTS_OUT_LEN 0
4919
4920
4921/***********************************/
4922/* MC_CMD_GET_PHY_CFG
4923 * Report PHY configuration. This guarantees to succeed even if the PHY is in a
4924 * 'zombie' state. Locks required: None
4925 */
4926#define MC_CMD_GET_PHY_CFG 0x24
4927#undef MC_CMD_0x24_PRIVILEGE_CTG
4928
4929#define MC_CMD_0x24_PRIVILEGE_CTG SRIOV_CTG_GENERAL
4930
4931/* MC_CMD_GET_PHY_CFG_IN msgrequest */
4932#define MC_CMD_GET_PHY_CFG_IN_LEN 0
4933
4934/* MC_CMD_GET_PHY_CFG_OUT msgresponse */
4935#define MC_CMD_GET_PHY_CFG_OUT_LEN 72
4936/* flags */
4937#define MC_CMD_GET_PHY_CFG_OUT_FLAGS_OFST 0
4938#define MC_CMD_GET_PHY_CFG_OUT_FLAGS_LEN 4
4939#define MC_CMD_GET_PHY_CFG_OUT_PRESENT_OFST 0
4940#define MC_CMD_GET_PHY_CFG_OUT_PRESENT_LBN 0
4941#define MC_CMD_GET_PHY_CFG_OUT_PRESENT_WIDTH 1
4942#define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_OFST 0
4943#define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_LBN 1
4944#define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_WIDTH 1
4945#define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_OFST 0
4946#define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_LBN 2
4947#define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_WIDTH 1
4948#define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_OFST 0
4949#define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_LBN 3
4950#define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_WIDTH 1
4951#define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_OFST 0
4952#define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_LBN 4
4953#define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_WIDTH 1
4954#define MC_CMD_GET_PHY_CFG_OUT_TXDIS_OFST 0
4955#define MC_CMD_GET_PHY_CFG_OUT_TXDIS_LBN 5
4956#define MC_CMD_GET_PHY_CFG_OUT_TXDIS_WIDTH 1
4957#define MC_CMD_GET_PHY_CFG_OUT_BIST_OFST 0
4958#define MC_CMD_GET_PHY_CFG_OUT_BIST_LBN 6
4959#define MC_CMD_GET_PHY_CFG_OUT_BIST_WIDTH 1
4960/* ?? */
4961#define MC_CMD_GET_PHY_CFG_OUT_TYPE_OFST 4
4962#define MC_CMD_GET_PHY_CFG_OUT_TYPE_LEN 4
4963/* Bitmask of supported capabilities */
4964#define MC_CMD_GET_PHY_CFG_OUT_SUPPORTED_CAP_OFST 8
4965#define MC_CMD_GET_PHY_CFG_OUT_SUPPORTED_CAP_LEN 4
4966#define MC_CMD_PHY_CAP_10HDX_OFST 8
4967#define MC_CMD_PHY_CAP_10HDX_LBN 1
4968#define MC_CMD_PHY_CAP_10HDX_WIDTH 1
4969#define MC_CMD_PHY_CAP_10FDX_OFST 8
4970#define MC_CMD_PHY_CAP_10FDX_LBN 2
4971#define MC_CMD_PHY_CAP_10FDX_WIDTH 1
4972#define MC_CMD_PHY_CAP_100HDX_OFST 8
4973#define MC_CMD_PHY_CAP_100HDX_LBN 3
4974#define MC_CMD_PHY_CAP_100HDX_WIDTH 1
4975#define MC_CMD_PHY_CAP_100FDX_OFST 8
4976#define MC_CMD_PHY_CAP_100FDX_LBN 4
4977#define MC_CMD_PHY_CAP_100FDX_WIDTH 1
4978#define MC_CMD_PHY_CAP_1000HDX_OFST 8
4979#define MC_CMD_PHY_CAP_1000HDX_LBN 5
4980#define MC_CMD_PHY_CAP_1000HDX_WIDTH 1
4981#define MC_CMD_PHY_CAP_1000FDX_OFST 8
4982#define MC_CMD_PHY_CAP_1000FDX_LBN 6
4983#define MC_CMD_PHY_CAP_1000FDX_WIDTH 1
4984#define MC_CMD_PHY_CAP_10000FDX_OFST 8
4985#define MC_CMD_PHY_CAP_10000FDX_LBN 7
4986#define MC_CMD_PHY_CAP_10000FDX_WIDTH 1
4987#define MC_CMD_PHY_CAP_PAUSE_OFST 8
4988#define MC_CMD_PHY_CAP_PAUSE_LBN 8
4989#define MC_CMD_PHY_CAP_PAUSE_WIDTH 1
4990#define MC_CMD_PHY_CAP_ASYM_OFST 8
4991#define MC_CMD_PHY_CAP_ASYM_LBN 9
4992#define MC_CMD_PHY_CAP_ASYM_WIDTH 1
4993#define MC_CMD_PHY_CAP_AN_OFST 8
4994#define MC_CMD_PHY_CAP_AN_LBN 10
4995#define MC_CMD_PHY_CAP_AN_WIDTH 1
4996#define MC_CMD_PHY_CAP_40000FDX_OFST 8
4997#define MC_CMD_PHY_CAP_40000FDX_LBN 11
4998#define MC_CMD_PHY_CAP_40000FDX_WIDTH 1
4999#define MC_CMD_PHY_CAP_DDM_OFST 8
5000#define MC_CMD_PHY_CAP_DDM_LBN 12
5001#define MC_CMD_PHY_CAP_DDM_WIDTH 1
5002#define MC_CMD_PHY_CAP_100000FDX_OFST 8
5003#define MC_CMD_PHY_CAP_100000FDX_LBN 13
5004#define MC_CMD_PHY_CAP_100000FDX_WIDTH 1
5005#define MC_CMD_PHY_CAP_25000FDX_OFST 8
5006#define MC_CMD_PHY_CAP_25000FDX_LBN 14
5007#define MC_CMD_PHY_CAP_25000FDX_WIDTH 1
5008#define MC_CMD_PHY_CAP_50000FDX_OFST 8
5009#define MC_CMD_PHY_CAP_50000FDX_LBN 15
5010#define MC_CMD_PHY_CAP_50000FDX_WIDTH 1
5011#define MC_CMD_PHY_CAP_BASER_FEC_OFST 8
5012#define MC_CMD_PHY_CAP_BASER_FEC_LBN 16
5013#define MC_CMD_PHY_CAP_BASER_FEC_WIDTH 1
5014#define MC_CMD_PHY_CAP_BASER_FEC_REQUESTED_OFST 8
5015#define MC_CMD_PHY_CAP_BASER_FEC_REQUESTED_LBN 17
5016#define MC_CMD_PHY_CAP_BASER_FEC_REQUESTED_WIDTH 1
5017#define MC_CMD_PHY_CAP_RS_FEC_OFST 8
5018#define MC_CMD_PHY_CAP_RS_FEC_LBN 18
5019#define MC_CMD_PHY_CAP_RS_FEC_WIDTH 1
5020#define MC_CMD_PHY_CAP_RS_FEC_REQUESTED_OFST 8
5021#define MC_CMD_PHY_CAP_RS_FEC_REQUESTED_LBN 19
5022#define MC_CMD_PHY_CAP_RS_FEC_REQUESTED_WIDTH 1
5023#define MC_CMD_PHY_CAP_25G_BASER_FEC_OFST 8
5024#define MC_CMD_PHY_CAP_25G_BASER_FEC_LBN 20
5025#define MC_CMD_PHY_CAP_25G_BASER_FEC_WIDTH 1
5026#define MC_CMD_PHY_CAP_25G_BASER_FEC_REQUESTED_OFST 8
5027#define MC_CMD_PHY_CAP_25G_BASER_FEC_REQUESTED_LBN 21
5028#define MC_CMD_PHY_CAP_25G_BASER_FEC_REQUESTED_WIDTH 1
5029/* ?? */
5030#define MC_CMD_GET_PHY_CFG_OUT_CHANNEL_OFST 12
5031#define MC_CMD_GET_PHY_CFG_OUT_CHANNEL_LEN 4
5032/* ?? */
5033#define MC_CMD_GET_PHY_CFG_OUT_PRT_OFST 16
5034#define MC_CMD_GET_PHY_CFG_OUT_PRT_LEN 4
5035/* ?? */
5036#define MC_CMD_GET_PHY_CFG_OUT_STATS_MASK_OFST 20
5037#define MC_CMD_GET_PHY_CFG_OUT_STATS_MASK_LEN 4
5038/* ?? */
5039#define MC_CMD_GET_PHY_CFG_OUT_NAME_OFST 24
5040#define MC_CMD_GET_PHY_CFG_OUT_NAME_LEN 20
5041/* ?? */
5042#define MC_CMD_GET_PHY_CFG_OUT_MEDIA_TYPE_OFST 44
5043#define MC_CMD_GET_PHY_CFG_OUT_MEDIA_TYPE_LEN 4
5044/* enum: Xaui. */
5045#define MC_CMD_MEDIA_XAUI 0x1
5046/* enum: CX4. */
5047#define MC_CMD_MEDIA_CX4 0x2
5048/* enum: KX4. */
5049#define MC_CMD_MEDIA_KX4 0x3
5050/* enum: XFP Far. */
5051#define MC_CMD_MEDIA_XFP 0x4
5052/* enum: SFP+. */
5053#define MC_CMD_MEDIA_SFP_PLUS 0x5
5054/* enum: 10GBaseT. */
5055#define MC_CMD_MEDIA_BASE_T 0x6
5056/* enum: QSFP+. */
5057#define MC_CMD_MEDIA_QSFP_PLUS 0x7
5058/* enum: DSFP. */
5059#define MC_CMD_MEDIA_DSFP 0x8
5060#define MC_CMD_GET_PHY_CFG_OUT_MMD_MASK_OFST 48
5061#define MC_CMD_GET_PHY_CFG_OUT_MMD_MASK_LEN 4
5062/* enum: Native clause 22 */
5063#define MC_CMD_MMD_CLAUSE22 0x0
5064#define MC_CMD_MMD_CLAUSE45_PMAPMD 0x1 /* enum */
5065#define MC_CMD_MMD_CLAUSE45_WIS 0x2 /* enum */
5066#define MC_CMD_MMD_CLAUSE45_PCS 0x3 /* enum */
5067#define MC_CMD_MMD_CLAUSE45_PHYXS 0x4 /* enum */
5068#define MC_CMD_MMD_CLAUSE45_DTEXS 0x5 /* enum */
5069#define MC_CMD_MMD_CLAUSE45_TC 0x6 /* enum */
5070#define MC_CMD_MMD_CLAUSE45_AN 0x7 /* enum */
5071/* enum: Clause22 proxied over clause45 by PHY. */
5072#define MC_CMD_MMD_CLAUSE45_C22EXT 0x1d
5073#define MC_CMD_MMD_CLAUSE45_VEND1 0x1e /* enum */
5074#define MC_CMD_MMD_CLAUSE45_VEND2 0x1f /* enum */
5075#define MC_CMD_GET_PHY_CFG_OUT_REVISION_OFST 52
5076#define MC_CMD_GET_PHY_CFG_OUT_REVISION_LEN 20
5077
5078
5079/***********************************/
5080/* MC_CMD_START_BIST
5081 * Start a BIST test on the PHY. Locks required: PHY_LOCK if doing a PHY BIST
5082 * Return code: 0, EINVAL, EACCES (if PHY_LOCK is not held)
5083 */
5084#define MC_CMD_START_BIST 0x25
5085#undef MC_CMD_0x25_PRIVILEGE_CTG
5086
5087#define MC_CMD_0x25_PRIVILEGE_CTG SRIOV_CTG_ADMIN
5088
5089/* MC_CMD_START_BIST_IN msgrequest */
5090#define MC_CMD_START_BIST_IN_LEN 4
5091/* Type of test. */
5092#define MC_CMD_START_BIST_IN_TYPE_OFST 0
5093#define MC_CMD_START_BIST_IN_TYPE_LEN 4
5094/* enum: Run the PHY's short cable BIST. */
5095#define MC_CMD_PHY_BIST_CABLE_SHORT 0x1
5096/* enum: Run the PHY's long cable BIST. */
5097#define MC_CMD_PHY_BIST_CABLE_LONG 0x2
5098/* enum: Run BIST on the currently selected BPX Serdes (XAUI or XFI) . */
5099#define MC_CMD_BPX_SERDES_BIST 0x3
5100/* enum: Run the MC loopback tests. */
5101#define MC_CMD_MC_LOOPBACK_BIST 0x4
5102/* enum: Run the PHY's standard BIST. */
5103#define MC_CMD_PHY_BIST 0x5
5104/* enum: Run MC RAM test. */
5105#define MC_CMD_MC_MEM_BIST 0x6
5106/* enum: Run Port RAM test. */
5107#define MC_CMD_PORT_MEM_BIST 0x7
5108/* enum: Run register test. */
5109#define MC_CMD_REG_BIST 0x8
5110
5111/* MC_CMD_START_BIST_OUT msgresponse */
5112#define MC_CMD_START_BIST_OUT_LEN 0
5113
5114
5115/***********************************/
5116/* MC_CMD_POLL_BIST
5117 * Poll for BIST completion. Returns a single status code, and optionally some
5118 * PHY specific bist output. The driver should only consume the BIST output
5119 * after validating OUTLEN and MC_CMD_GET_PHY_CFG.TYPE. If a driver can't
5120 * successfully parse the BIST output, it should still respect the pass/Fail in
5121 * OUT.RESULT. Locks required: PHY_LOCK if doing a PHY BIST. Return code: 0,
5122 * EACCES (if PHY_LOCK is not held).
5123 */
5124#define MC_CMD_POLL_BIST 0x26
5125#undef MC_CMD_0x26_PRIVILEGE_CTG
5126
5127#define MC_CMD_0x26_PRIVILEGE_CTG SRIOV_CTG_ADMIN
5128
5129/* MC_CMD_POLL_BIST_IN msgrequest */
5130#define MC_CMD_POLL_BIST_IN_LEN 0
5131
5132/* MC_CMD_POLL_BIST_OUT msgresponse */
5133#define MC_CMD_POLL_BIST_OUT_LEN 8
5134/* result */
5135#define MC_CMD_POLL_BIST_OUT_RESULT_OFST 0
5136#define MC_CMD_POLL_BIST_OUT_RESULT_LEN 4
5137/* enum: Running. */
5138#define MC_CMD_POLL_BIST_RUNNING 0x1
5139/* enum: Passed. */
5140#define MC_CMD_POLL_BIST_PASSED 0x2
5141/* enum: Failed. */
5142#define MC_CMD_POLL_BIST_FAILED 0x3
5143/* enum: Timed-out. */
5144#define MC_CMD_POLL_BIST_TIMEOUT 0x4
5145#define MC_CMD_POLL_BIST_OUT_PRIVATE_OFST 4
5146#define MC_CMD_POLL_BIST_OUT_PRIVATE_LEN 4
5147
5148/* MC_CMD_POLL_BIST_OUT_SFT9001 msgresponse */
5149#define MC_CMD_POLL_BIST_OUT_SFT9001_LEN 36
5150/* result */
5151/* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */
5152/* MC_CMD_POLL_BIST_OUT_RESULT_LEN 4 */
5153/* Enum values, see field(s): */
5154/* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */
5155#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A_OFST 4
5156#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A_LEN 4
5157#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_B_OFST 8
5158#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_B_LEN 4
5159#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_C_OFST 12
5160#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_C_LEN 4
5161#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_D_OFST 16
5162#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_D_LEN 4
5163/* Status of each channel A */
5164#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_A_OFST 20
5165#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_A_LEN 4
5166/* enum: Ok. */
5167#define MC_CMD_POLL_BIST_SFT9001_PAIR_OK 0x1
5168/* enum: Open. */
5169#define MC_CMD_POLL_BIST_SFT9001_PAIR_OPEN 0x2
5170/* enum: Intra-pair short. */
5171#define MC_CMD_POLL_BIST_SFT9001_INTRA_PAIR_SHORT 0x3
5172/* enum: Inter-pair short. */
5173#define MC_CMD_POLL_BIST_SFT9001_INTER_PAIR_SHORT 0x4
5174/* enum: Busy. */
5175#define MC_CMD_POLL_BIST_SFT9001_PAIR_BUSY 0x9
5176/* Status of each channel B */
5177#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_B_OFST 24
5178#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_B_LEN 4
5179/* Enum values, see field(s): */
5180/* CABLE_STATUS_A */
5181/* Status of each channel C */
5182#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_C_OFST 28
5183#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_C_LEN 4
5184/* Enum values, see field(s): */
5185/* CABLE_STATUS_A */
5186/* Status of each channel D */
5187#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_D_OFST 32
5188#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_D_LEN 4
5189/* Enum values, see field(s): */
5190/* CABLE_STATUS_A */
5191
5192/* MC_CMD_POLL_BIST_OUT_MRSFP msgresponse */
5193#define MC_CMD_POLL_BIST_OUT_MRSFP_LEN 8
5194/* result */
5195/* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */
5196/* MC_CMD_POLL_BIST_OUT_RESULT_LEN 4 */
5197/* Enum values, see field(s): */
5198/* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */
5199#define MC_CMD_POLL_BIST_OUT_MRSFP_TEST_OFST 4
5200#define MC_CMD_POLL_BIST_OUT_MRSFP_TEST_LEN 4
5201/* enum: Complete. */
5202#define MC_CMD_POLL_BIST_MRSFP_TEST_COMPLETE 0x0
5203/* enum: Bus switch off I2C write. */
5204#define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_WRITE 0x1
5205/* enum: Bus switch off I2C no access IO exp. */
5206#define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_IO_EXP 0x2
5207/* enum: Bus switch off I2C no access module. */
5208#define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_MODULE 0x3
5209/* enum: IO exp I2C configure. */
5210#define MC_CMD_POLL_BIST_MRSFP_TEST_IO_EXP_I2C_CONFIGURE 0x4
5211/* enum: Bus switch I2C no cross talk. */
5212#define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_I2C_NO_CROSSTALK 0x5
5213/* enum: Module presence. */
5214#define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_PRESENCE 0x6
5215/* enum: Module ID I2C access. */
5216#define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_I2C_ACCESS 0x7
5217/* enum: Module ID sane value. */
5218#define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_SANE_VALUE 0x8
5219
5220/* MC_CMD_POLL_BIST_OUT_MEM msgresponse */
5221#define MC_CMD_POLL_BIST_OUT_MEM_LEN 36
5222/* result */
5223/* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */
5224/* MC_CMD_POLL_BIST_OUT_RESULT_LEN 4 */
5225/* Enum values, see field(s): */
5226/* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */
5227#define MC_CMD_POLL_BIST_OUT_MEM_TEST_OFST 4
5228#define MC_CMD_POLL_BIST_OUT_MEM_TEST_LEN 4
5229/* enum: Test has completed. */
5230#define MC_CMD_POLL_BIST_MEM_COMPLETE 0x0
5231/* enum: RAM test - walk ones. */
5232#define MC_CMD_POLL_BIST_MEM_MEM_WALK_ONES 0x1
5233/* enum: RAM test - walk zeros. */
5234#define MC_CMD_POLL_BIST_MEM_MEM_WALK_ZEROS 0x2
5235/* enum: RAM test - walking inversions zeros/ones. */
5236#define MC_CMD_POLL_BIST_MEM_MEM_INV_ZERO_ONE 0x3
5237/* enum: RAM test - walking inversions checkerboard. */
5238#define MC_CMD_POLL_BIST_MEM_MEM_INV_CHKBOARD 0x4
5239/* enum: Register test - set / clear individual bits. */
5240#define MC_CMD_POLL_BIST_MEM_REG 0x5
5241/* enum: ECC error detected. */
5242#define MC_CMD_POLL_BIST_MEM_ECC 0x6
5243/* Failure address, only valid if result is POLL_BIST_FAILED */
5244#define MC_CMD_POLL_BIST_OUT_MEM_ADDR_OFST 8
5245#define MC_CMD_POLL_BIST_OUT_MEM_ADDR_LEN 4
5246/* Bus or address space to which the failure address corresponds */
5247#define MC_CMD_POLL_BIST_OUT_MEM_BUS_OFST 12
5248#define MC_CMD_POLL_BIST_OUT_MEM_BUS_LEN 4
5249/* enum: MC MIPS bus. */
5250#define MC_CMD_POLL_BIST_MEM_BUS_MC 0x0
5251/* enum: CSR IREG bus. */
5252#define MC_CMD_POLL_BIST_MEM_BUS_CSR 0x1
5253/* enum: RX0 DPCPU bus. */
5254#define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_RX 0x2
5255/* enum: TX0 DPCPU bus. */
5256#define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_TX0 0x3
5257/* enum: TX1 DPCPU bus. */
5258#define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_TX1 0x4
5259/* enum: RX0 DICPU bus. */
5260#define MC_CMD_POLL_BIST_MEM_BUS_DICPU_RX 0x5
5261/* enum: TX DICPU bus. */
5262#define MC_CMD_POLL_BIST_MEM_BUS_DICPU_TX 0x6
5263/* enum: RX1 DPCPU bus. */
5264#define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_RX1 0x7
5265/* enum: RX1 DICPU bus. */
5266#define MC_CMD_POLL_BIST_MEM_BUS_DICPU_RX1 0x8
5267/* Pattern written to RAM / register */
5268#define MC_CMD_POLL_BIST_OUT_MEM_EXPECT_OFST 16
5269#define MC_CMD_POLL_BIST_OUT_MEM_EXPECT_LEN 4
5270/* Actual value read from RAM / register */
5271#define MC_CMD_POLL_BIST_OUT_MEM_ACTUAL_OFST 20
5272#define MC_CMD_POLL_BIST_OUT_MEM_ACTUAL_LEN 4
5273/* ECC error mask */
5274#define MC_CMD_POLL_BIST_OUT_MEM_ECC_OFST 24
5275#define MC_CMD_POLL_BIST_OUT_MEM_ECC_LEN 4
5276/* ECC parity error mask */
5277#define MC_CMD_POLL_BIST_OUT_MEM_ECC_PARITY_OFST 28
5278#define MC_CMD_POLL_BIST_OUT_MEM_ECC_PARITY_LEN 4
5279/* ECC fatal error mask */
5280#define MC_CMD_POLL_BIST_OUT_MEM_ECC_FATAL_OFST 32
5281#define MC_CMD_POLL_BIST_OUT_MEM_ECC_FATAL_LEN 4
5282
5283
5284/***********************************/
5285/* MC_CMD_FLUSH_RX_QUEUES
5286 * Flush receive queue(s). If SRIOV is enabled (via MC_CMD_SRIOV), then RXQ
5287 * flushes should be initiated via this MCDI operation, rather than via
5288 * directly writing FLUSH_CMD.
5289 *
5290 * The flush is completed (either done/fail) asynchronously (after this command
5291 * returns). The driver must still wait for flush done/failure events as usual.
5292 */
5293#define MC_CMD_FLUSH_RX_QUEUES 0x27
5294
5295/* MC_CMD_FLUSH_RX_QUEUES_IN msgrequest */
5296#define MC_CMD_FLUSH_RX_QUEUES_IN_LENMIN 4
5297#define MC_CMD_FLUSH_RX_QUEUES_IN_LENMAX 252
5298#define MC_CMD_FLUSH_RX_QUEUES_IN_LENMAX_MCDI2 1020
5299#define MC_CMD_FLUSH_RX_QUEUES_IN_LEN(num) (0+4*(num))
5300#define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_NUM(len) (((len)-0)/4)
5301#define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_OFST 0
5302#define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_LEN 4
5303#define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MINNUM 1
5304#define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MAXNUM 63
5305#define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MAXNUM_MCDI2 255
5306
5307/* MC_CMD_FLUSH_RX_QUEUES_OUT msgresponse */
5308#define MC_CMD_FLUSH_RX_QUEUES_OUT_LEN 0
5309
5310
5311/***********************************/
5312/* MC_CMD_GET_LOOPBACK_MODES
5313 * Returns a bitmask of loopback modes available at each speed.
5314 */
5315#define MC_CMD_GET_LOOPBACK_MODES 0x28
5316#undef MC_CMD_0x28_PRIVILEGE_CTG
5317
5318#define MC_CMD_0x28_PRIVILEGE_CTG SRIOV_CTG_GENERAL
5319
5320/* MC_CMD_GET_LOOPBACK_MODES_IN msgrequest */
5321#define MC_CMD_GET_LOOPBACK_MODES_IN_LEN 0
5322
5323/* MC_CMD_GET_LOOPBACK_MODES_OUT msgresponse */
5324#define MC_CMD_GET_LOOPBACK_MODES_OUT_LEN 40
5325/* Supported loopbacks. */
5326#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_OFST 0
5327#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LEN 8
5328#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_OFST 0
5329#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_LEN 4
5330#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_LBN 0
5331#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_WIDTH 32
5332#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_OFST 4
5333#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_LEN 4
5334#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_LBN 32
5335#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_WIDTH 32
5336/* enum: None. */
5337#define MC_CMD_LOOPBACK_NONE 0x0
5338/* enum: Data. */
5339#define MC_CMD_LOOPBACK_DATA 0x1
5340/* enum: GMAC. */
5341#define MC_CMD_LOOPBACK_GMAC 0x2
5342/* enum: XGMII. */
5343#define MC_CMD_LOOPBACK_XGMII 0x3
5344/* enum: XGXS. */
5345#define MC_CMD_LOOPBACK_XGXS 0x4
5346/* enum: XAUI. */
5347#define MC_CMD_LOOPBACK_XAUI 0x5
5348/* enum: GMII. */
5349#define MC_CMD_LOOPBACK_GMII 0x6
5350/* enum: SGMII. */
5351#define MC_CMD_LOOPBACK_SGMII 0x7
5352/* enum: XGBR. */
5353#define MC_CMD_LOOPBACK_XGBR 0x8
5354/* enum: XFI. */
5355#define MC_CMD_LOOPBACK_XFI 0x9
5356/* enum: XAUI Far. */
5357#define MC_CMD_LOOPBACK_XAUI_FAR 0xa
5358/* enum: GMII Far. */
5359#define MC_CMD_LOOPBACK_GMII_FAR 0xb
5360/* enum: SGMII Far. */
5361#define MC_CMD_LOOPBACK_SGMII_FAR 0xc
5362/* enum: XFI Far. */
5363#define MC_CMD_LOOPBACK_XFI_FAR 0xd
5364/* enum: GPhy. */
5365#define MC_CMD_LOOPBACK_GPHY 0xe
5366/* enum: PhyXS. */
5367#define MC_CMD_LOOPBACK_PHYXS 0xf
5368/* enum: PCS. */
5369#define MC_CMD_LOOPBACK_PCS 0x10
5370/* enum: PMA-PMD. */
5371#define MC_CMD_LOOPBACK_PMAPMD 0x11
5372/* enum: Cross-Port. */
5373#define MC_CMD_LOOPBACK_XPORT 0x12
5374/* enum: XGMII-Wireside. */
5375#define MC_CMD_LOOPBACK_XGMII_WS 0x13
5376/* enum: XAUI Wireside. */
5377#define MC_CMD_LOOPBACK_XAUI_WS 0x14
5378/* enum: XAUI Wireside Far. */
5379#define MC_CMD_LOOPBACK_XAUI_WS_FAR 0x15
5380/* enum: XAUI Wireside near. */
5381#define MC_CMD_LOOPBACK_XAUI_WS_NEAR 0x16
5382/* enum: GMII Wireside. */
5383#define MC_CMD_LOOPBACK_GMII_WS 0x17
5384/* enum: XFI Wireside. */
5385#define MC_CMD_LOOPBACK_XFI_WS 0x18
5386/* enum: XFI Wireside Far. */
5387#define MC_CMD_LOOPBACK_XFI_WS_FAR 0x19
5388/* enum: PhyXS Wireside. */
5389#define MC_CMD_LOOPBACK_PHYXS_WS 0x1a
5390/* enum: PMA lanes MAC-Serdes. */
5391#define MC_CMD_LOOPBACK_PMA_INT 0x1b
5392/* enum: KR Serdes Parallel (Encoder). */
5393#define MC_CMD_LOOPBACK_SD_NEAR 0x1c
5394/* enum: KR Serdes Serial. */
5395#define MC_CMD_LOOPBACK_SD_FAR 0x1d
5396/* enum: PMA lanes MAC-Serdes Wireside. */
5397#define MC_CMD_LOOPBACK_PMA_INT_WS 0x1e
5398/* enum: KR Serdes Parallel Wireside (Full PCS). */
5399#define MC_CMD_LOOPBACK_SD_FEP2_WS 0x1f
5400/* enum: KR Serdes Parallel Wireside (Sym Aligner to TX). */
5401#define MC_CMD_LOOPBACK_SD_FEP1_5_WS 0x20
5402/* enum: KR Serdes Parallel Wireside (Deserializer to Serializer). */
5403#define MC_CMD_LOOPBACK_SD_FEP_WS 0x21
5404/* enum: KR Serdes Serial Wireside. */
5405#define MC_CMD_LOOPBACK_SD_FES_WS 0x22
5406/* enum: Near side of AOE Siena side port */
5407#define MC_CMD_LOOPBACK_AOE_INT_NEAR 0x23
5408/* enum: Medford Wireside datapath loopback */
5409#define MC_CMD_LOOPBACK_DATA_WS 0x24
5410/* enum: Force link up without setting up any physical loopback (snapper use
5411 * only)
5412 */
5413#define MC_CMD_LOOPBACK_FORCE_EXT_LINK 0x25
5414/* Supported loopbacks. */
5415#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_OFST 8
5416#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LEN 8
5417#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LO_OFST 8
5418#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LO_LEN 4
5419#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LO_LBN 64
5420#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LO_WIDTH 32
5421#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_HI_OFST 12
5422#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_HI_LEN 4
5423#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_HI_LBN 96
5424#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_HI_WIDTH 32
5425/* Enum values, see field(s): */
5426/* 100M */
5427/* Supported loopbacks. */
5428#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_OFST 16
5429#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LEN 8
5430#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LO_OFST 16
5431#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LO_LEN 4
5432#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LO_LBN 128
5433#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LO_WIDTH 32
5434#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_HI_OFST 20
5435#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_HI_LEN 4
5436#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_HI_LBN 160
5437#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_HI_WIDTH 32
5438/* Enum values, see field(s): */
5439/* 100M */
5440/* Supported loopbacks. */
5441#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_OFST 24
5442#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LEN 8
5443#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LO_OFST 24
5444#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LO_LEN 4
5445#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LO_LBN 192
5446#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LO_WIDTH 32
5447#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_HI_OFST 28
5448#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_HI_LEN 4
5449#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_HI_LBN 224
5450#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_HI_WIDTH 32
5451/* Enum values, see field(s): */
5452/* 100M */
5453/* Supported loopbacks. */
5454#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_OFST 32
5455#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LEN 8
5456#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LO_OFST 32
5457#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LO_LEN 4
5458#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LO_LBN 256
5459#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LO_WIDTH 32
5460#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_HI_OFST 36
5461#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_HI_LEN 4
5462#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_HI_LBN 288
5463#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_HI_WIDTH 32
5464/* Enum values, see field(s): */
5465/* 100M */
5466
5467/* MC_CMD_GET_LOOPBACK_MODES_OUT_V2 msgresponse: Supported loopback modes for
5468 * newer NICs with 25G/50G/100G support
5469 */
5470#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_LEN 64
5471/* Supported loopbacks. */
5472#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_OFST 0
5473#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_LEN 8
5474#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_LO_OFST 0
5475#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_LO_LEN 4
5476#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_LO_LBN 0
5477#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_LO_WIDTH 32
5478#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_HI_OFST 4
5479#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_HI_LEN 4
5480#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_HI_LBN 32
5481#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_HI_WIDTH 32
5482/* enum: None. */
5483/* MC_CMD_LOOPBACK_NONE 0x0 */
5484/* enum: Data. */
5485/* MC_CMD_LOOPBACK_DATA 0x1 */
5486/* enum: GMAC. */
5487/* MC_CMD_LOOPBACK_GMAC 0x2 */
5488/* enum: XGMII. */
5489/* MC_CMD_LOOPBACK_XGMII 0x3 */
5490/* enum: XGXS. */
5491/* MC_CMD_LOOPBACK_XGXS 0x4 */
5492/* enum: XAUI. */
5493/* MC_CMD_LOOPBACK_XAUI 0x5 */
5494/* enum: GMII. */
5495/* MC_CMD_LOOPBACK_GMII 0x6 */
5496/* enum: SGMII. */
5497/* MC_CMD_LOOPBACK_SGMII 0x7 */
5498/* enum: XGBR. */
5499/* MC_CMD_LOOPBACK_XGBR 0x8 */
5500/* enum: XFI. */
5501/* MC_CMD_LOOPBACK_XFI 0x9 */
5502/* enum: XAUI Far. */
5503/* MC_CMD_LOOPBACK_XAUI_FAR 0xa */
5504/* enum: GMII Far. */
5505/* MC_CMD_LOOPBACK_GMII_FAR 0xb */
5506/* enum: SGMII Far. */
5507/* MC_CMD_LOOPBACK_SGMII_FAR 0xc */
5508/* enum: XFI Far. */
5509/* MC_CMD_LOOPBACK_XFI_FAR 0xd */
5510/* enum: GPhy. */
5511/* MC_CMD_LOOPBACK_GPHY 0xe */
5512/* enum: PhyXS. */
5513/* MC_CMD_LOOPBACK_PHYXS 0xf */
5514/* enum: PCS. */
5515/* MC_CMD_LOOPBACK_PCS 0x10 */
5516/* enum: PMA-PMD. */
5517/* MC_CMD_LOOPBACK_PMAPMD 0x11 */
5518/* enum: Cross-Port. */
5519/* MC_CMD_LOOPBACK_XPORT 0x12 */
5520/* enum: XGMII-Wireside. */
5521/* MC_CMD_LOOPBACK_XGMII_WS 0x13 */
5522/* enum: XAUI Wireside. */
5523/* MC_CMD_LOOPBACK_XAUI_WS 0x14 */
5524/* enum: XAUI Wireside Far. */
5525/* MC_CMD_LOOPBACK_XAUI_WS_FAR 0x15 */
5526/* enum: XAUI Wireside near. */
5527/* MC_CMD_LOOPBACK_XAUI_WS_NEAR 0x16 */
5528/* enum: GMII Wireside. */
5529/* MC_CMD_LOOPBACK_GMII_WS 0x17 */
5530/* enum: XFI Wireside. */
5531/* MC_CMD_LOOPBACK_XFI_WS 0x18 */
5532/* enum: XFI Wireside Far. */
5533/* MC_CMD_LOOPBACK_XFI_WS_FAR 0x19 */
5534/* enum: PhyXS Wireside. */
5535/* MC_CMD_LOOPBACK_PHYXS_WS 0x1a */
5536/* enum: PMA lanes MAC-Serdes. */
5537/* MC_CMD_LOOPBACK_PMA_INT 0x1b */
5538/* enum: KR Serdes Parallel (Encoder). */
5539/* MC_CMD_LOOPBACK_SD_NEAR 0x1c */
5540/* enum: KR Serdes Serial. */
5541/* MC_CMD_LOOPBACK_SD_FAR 0x1d */
5542/* enum: PMA lanes MAC-Serdes Wireside. */
5543/* MC_CMD_LOOPBACK_PMA_INT_WS 0x1e */
5544/* enum: KR Serdes Parallel Wireside (Full PCS). */
5545/* MC_CMD_LOOPBACK_SD_FEP2_WS 0x1f */
5546/* enum: KR Serdes Parallel Wireside (Sym Aligner to TX). */
5547/* MC_CMD_LOOPBACK_SD_FEP1_5_WS 0x20 */
5548/* enum: KR Serdes Parallel Wireside (Deserializer to Serializer). */
5549/* MC_CMD_LOOPBACK_SD_FEP_WS 0x21 */
5550/* enum: KR Serdes Serial Wireside. */
5551/* MC_CMD_LOOPBACK_SD_FES_WS 0x22 */
5552/* enum: Near side of AOE Siena side port */
5553/* MC_CMD_LOOPBACK_AOE_INT_NEAR 0x23 */
5554/* enum: Medford Wireside datapath loopback */
5555/* MC_CMD_LOOPBACK_DATA_WS 0x24 */
5556/* enum: Force link up without setting up any physical loopback (snapper use
5557 * only)
5558 */
5559/* MC_CMD_LOOPBACK_FORCE_EXT_LINK 0x25 */
5560/* Supported loopbacks. */
5561#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_OFST 8
5562#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_LEN 8
5563#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_LO_OFST 8
5564#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_LO_LEN 4
5565#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_LO_LBN 64
5566#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_LO_WIDTH 32
5567#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_HI_OFST 12
5568#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_HI_LEN 4
5569#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_HI_LBN 96
5570#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_HI_WIDTH 32
5571/* Enum values, see field(s): */
5572/* 100M */
5573/* Supported loopbacks. */
5574#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_OFST 16
5575#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_LEN 8
5576#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_LO_OFST 16
5577#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_LO_LEN 4
5578#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_LO_LBN 128
5579#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_LO_WIDTH 32
5580#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_HI_OFST 20
5581#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_HI_LEN 4
5582#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_HI_LBN 160
5583#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_HI_WIDTH 32
5584/* Enum values, see field(s): */
5585/* 100M */
5586/* Supported loopbacks. */
5587#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_OFST 24
5588#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_LEN 8
5589#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_LO_OFST 24
5590#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_LO_LEN 4
5591#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_LO_LBN 192
5592#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_LO_WIDTH 32
5593#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_HI_OFST 28
5594#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_HI_LEN 4
5595#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_HI_LBN 224
5596#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_HI_WIDTH 32
5597/* Enum values, see field(s): */
5598/* 100M */
5599/* Supported loopbacks. */
5600#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_OFST 32
5601#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_LEN 8
5602#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_LO_OFST 32
5603#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_LO_LEN 4
5604#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_LO_LBN 256
5605#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_LO_WIDTH 32
5606#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_HI_OFST 36
5607#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_HI_LEN 4
5608#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_HI_LBN 288
5609#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_HI_WIDTH 32
5610/* Enum values, see field(s): */
5611/* 100M */
5612/* Supported 25G loopbacks. */
5613#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_OFST 40
5614#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LEN 8
5615#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LO_OFST 40
5616#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LO_LEN 4
5617#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LO_LBN 320
5618#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LO_WIDTH 32
5619#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_HI_OFST 44
5620#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_HI_LEN 4
5621#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_HI_LBN 352
5622#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_HI_WIDTH 32
5623/* Enum values, see field(s): */
5624/* 100M */
5625/* Supported 50 loopbacks. */
5626#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_OFST 48
5627#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LEN 8
5628#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LO_OFST 48
5629#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LO_LEN 4
5630#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LO_LBN 384
5631#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LO_WIDTH 32
5632#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_HI_OFST 52
5633#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_HI_LEN 4
5634#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_HI_LBN 416
5635#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_HI_WIDTH 32
5636/* Enum values, see field(s): */
5637/* 100M */
5638/* Supported 100G loopbacks. */
5639#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_OFST 56
5640#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LEN 8
5641#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LO_OFST 56
5642#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LO_LEN 4
5643#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LO_LBN 448
5644#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LO_WIDTH 32
5645#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_HI_OFST 60
5646#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_HI_LEN 4
5647#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_HI_LBN 480
5648#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_HI_WIDTH 32
5649/* Enum values, see field(s): */
5650/* 100M */
5651
5652/* AN_TYPE structuredef: Auto-negotiation types defined in IEEE802.3 */
5653#define AN_TYPE_LEN 4
5654#define AN_TYPE_TYPE_OFST 0
5655#define AN_TYPE_TYPE_LEN 4
5656/* enum: None, AN disabled or not supported */
5657#define MC_CMD_AN_NONE 0x0
5658/* enum: Clause 28 - BASE-T */
5659#define MC_CMD_AN_CLAUSE28 0x1
5660/* enum: Clause 37 - BASE-X */
5661#define MC_CMD_AN_CLAUSE37 0x2
5662/* enum: Clause 73 - BASE-R startup protocol for backplane and copper cable
5663 * assemblies. Includes Clause 72/Clause 92 link-training.
5664 */
5665#define MC_CMD_AN_CLAUSE73 0x3
5666#define AN_TYPE_TYPE_LBN 0
5667#define AN_TYPE_TYPE_WIDTH 32
5668
5669/* FEC_TYPE structuredef: Forward error correction types defined in IEEE802.3
5670 */
5671#define FEC_TYPE_LEN 4
5672#define FEC_TYPE_TYPE_OFST 0
5673#define FEC_TYPE_TYPE_LEN 4
5674/* enum: No FEC */
5675#define MC_CMD_FEC_NONE 0x0
5676/* enum: Clause 74 BASE-R FEC (a.k.a Firecode) */
5677#define MC_CMD_FEC_BASER 0x1
5678/* enum: Clause 91/Clause 108 Reed-Solomon FEC */
5679#define MC_CMD_FEC_RS 0x2
5680#define FEC_TYPE_TYPE_LBN 0
5681#define FEC_TYPE_TYPE_WIDTH 32
5682
5683
5684/***********************************/
5685/* MC_CMD_GET_LINK
5686 * Read the unified MAC/PHY link state. Locks required: None Return code: 0,
5687 * ETIME.
5688 */
5689#define MC_CMD_GET_LINK 0x29
5690#undef MC_CMD_0x29_PRIVILEGE_CTG
5691
5692#define MC_CMD_0x29_PRIVILEGE_CTG SRIOV_CTG_GENERAL
5693
5694/* MC_CMD_GET_LINK_IN msgrequest */
5695#define MC_CMD_GET_LINK_IN_LEN 0
5696
5697/* MC_CMD_GET_LINK_OUT msgresponse */
5698#define MC_CMD_GET_LINK_OUT_LEN 28
5699/* Near-side advertised capabilities. Refer to
5700 * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions.
5701 */
5702#define MC_CMD_GET_LINK_OUT_CAP_OFST 0
5703#define MC_CMD_GET_LINK_OUT_CAP_LEN 4
5704/* Link-partner advertised capabilities. Refer to
5705 * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions.
5706 */
5707#define MC_CMD_GET_LINK_OUT_LP_CAP_OFST 4
5708#define MC_CMD_GET_LINK_OUT_LP_CAP_LEN 4
5709/* Autonegotiated speed in mbit/s. The link may still be down even if this
5710 * reads non-zero.
5711 */
5712#define MC_CMD_GET_LINK_OUT_LINK_SPEED_OFST 8
5713#define MC_CMD_GET_LINK_OUT_LINK_SPEED_LEN 4
5714/* Current loopback setting. */
5715#define MC_CMD_GET_LINK_OUT_LOOPBACK_MODE_OFST 12
5716#define MC_CMD_GET_LINK_OUT_LOOPBACK_MODE_LEN 4
5717/* Enum values, see field(s): */
5718/* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */
5719#define MC_CMD_GET_LINK_OUT_FLAGS_OFST 16
5720#define MC_CMD_GET_LINK_OUT_FLAGS_LEN 4
5721#define MC_CMD_GET_LINK_OUT_LINK_UP_OFST 16
5722#define MC_CMD_GET_LINK_OUT_LINK_UP_LBN 0
5723#define MC_CMD_GET_LINK_OUT_LINK_UP_WIDTH 1
5724#define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_OFST 16
5725#define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_LBN 1
5726#define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_WIDTH 1
5727#define MC_CMD_GET_LINK_OUT_BPX_LINK_OFST 16
5728#define MC_CMD_GET_LINK_OUT_BPX_LINK_LBN 2
5729#define MC_CMD_GET_LINK_OUT_BPX_LINK_WIDTH 1
5730#define MC_CMD_GET_LINK_OUT_PHY_LINK_OFST 16
5731#define MC_CMD_GET_LINK_OUT_PHY_LINK_LBN 3
5732#define MC_CMD_GET_LINK_OUT_PHY_LINK_WIDTH 1
5733#define MC_CMD_GET_LINK_OUT_LINK_FAULT_RX_OFST 16
5734#define MC_CMD_GET_LINK_OUT_LINK_FAULT_RX_LBN 6
5735#define MC_CMD_GET_LINK_OUT_LINK_FAULT_RX_WIDTH 1
5736#define MC_CMD_GET_LINK_OUT_LINK_FAULT_TX_OFST 16
5737#define MC_CMD_GET_LINK_OUT_LINK_FAULT_TX_LBN 7
5738#define MC_CMD_GET_LINK_OUT_LINK_FAULT_TX_WIDTH 1
5739#define MC_CMD_GET_LINK_OUT_MODULE_UP_VALID_OFST 16
5740#define MC_CMD_GET_LINK_OUT_MODULE_UP_VALID_LBN 8
5741#define MC_CMD_GET_LINK_OUT_MODULE_UP_VALID_WIDTH 1
5742#define MC_CMD_GET_LINK_OUT_MODULE_UP_OFST 16
5743#define MC_CMD_GET_LINK_OUT_MODULE_UP_LBN 9
5744#define MC_CMD_GET_LINK_OUT_MODULE_UP_WIDTH 1
5745/* This returns the negotiated flow control value. */
5746#define MC_CMD_GET_LINK_OUT_FCNTL_OFST 20
5747#define MC_CMD_GET_LINK_OUT_FCNTL_LEN 4
5748/* Enum values, see field(s): */
5749/* MC_CMD_SET_MAC/MC_CMD_SET_MAC_IN/FCNTL */
5750#define MC_CMD_GET_LINK_OUT_MAC_FAULT_OFST 24
5751#define MC_CMD_GET_LINK_OUT_MAC_FAULT_LEN 4
5752#define MC_CMD_MAC_FAULT_XGMII_LOCAL_OFST 24
5753#define MC_CMD_MAC_FAULT_XGMII_LOCAL_LBN 0
5754#define MC_CMD_MAC_FAULT_XGMII_LOCAL_WIDTH 1
5755#define MC_CMD_MAC_FAULT_XGMII_REMOTE_OFST 24
5756#define MC_CMD_MAC_FAULT_XGMII_REMOTE_LBN 1
5757#define MC_CMD_MAC_FAULT_XGMII_REMOTE_WIDTH 1
5758#define MC_CMD_MAC_FAULT_SGMII_REMOTE_OFST 24
5759#define MC_CMD_MAC_FAULT_SGMII_REMOTE_LBN 2
5760#define MC_CMD_MAC_FAULT_SGMII_REMOTE_WIDTH 1
5761#define MC_CMD_MAC_FAULT_PENDING_RECONFIG_OFST 24
5762#define MC_CMD_MAC_FAULT_PENDING_RECONFIG_LBN 3
5763#define MC_CMD_MAC_FAULT_PENDING_RECONFIG_WIDTH 1
5764
5765/* MC_CMD_GET_LINK_OUT_V2 msgresponse: Extended link state information */
5766#define MC_CMD_GET_LINK_OUT_V2_LEN 44
5767/* Near-side advertised capabilities. Refer to
5768 * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions.
5769 */
5770#define MC_CMD_GET_LINK_OUT_V2_CAP_OFST 0
5771#define MC_CMD_GET_LINK_OUT_V2_CAP_LEN 4
5772/* Link-partner advertised capabilities. Refer to
5773 * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions.
5774 */
5775#define MC_CMD_GET_LINK_OUT_V2_LP_CAP_OFST 4
5776#define MC_CMD_GET_LINK_OUT_V2_LP_CAP_LEN 4
5777/* Autonegotiated speed in mbit/s. The link may still be down even if this
5778 * reads non-zero.
5779 */
5780#define MC_CMD_GET_LINK_OUT_V2_LINK_SPEED_OFST 8
5781#define MC_CMD_GET_LINK_OUT_V2_LINK_SPEED_LEN 4
5782/* Current loopback setting. */
5783#define MC_CMD_GET_LINK_OUT_V2_LOOPBACK_MODE_OFST 12
5784#define MC_CMD_GET_LINK_OUT_V2_LOOPBACK_MODE_LEN 4
5785/* Enum values, see field(s): */
5786/* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */
5787#define MC_CMD_GET_LINK_OUT_V2_FLAGS_OFST 16
5788#define MC_CMD_GET_LINK_OUT_V2_FLAGS_LEN 4
5789#define MC_CMD_GET_LINK_OUT_V2_LINK_UP_OFST 16
5790#define MC_CMD_GET_LINK_OUT_V2_LINK_UP_LBN 0
5791#define MC_CMD_GET_LINK_OUT_V2_LINK_UP_WIDTH 1
5792#define MC_CMD_GET_LINK_OUT_V2_FULL_DUPLEX_OFST 16
5793#define MC_CMD_GET_LINK_OUT_V2_FULL_DUPLEX_LBN 1
5794#define MC_CMD_GET_LINK_OUT_V2_FULL_DUPLEX_WIDTH 1
5795#define MC_CMD_GET_LINK_OUT_V2_BPX_LINK_OFST 16
5796#define MC_CMD_GET_LINK_OUT_V2_BPX_LINK_LBN 2
5797#define MC_CMD_GET_LINK_OUT_V2_BPX_LINK_WIDTH 1
5798#define MC_CMD_GET_LINK_OUT_V2_PHY_LINK_OFST 16
5799#define MC_CMD_GET_LINK_OUT_V2_PHY_LINK_LBN 3
5800#define MC_CMD_GET_LINK_OUT_V2_PHY_LINK_WIDTH 1
5801#define MC_CMD_GET_LINK_OUT_V2_LINK_FAULT_RX_OFST 16
5802#define MC_CMD_GET_LINK_OUT_V2_LINK_FAULT_RX_LBN 6
5803#define MC_CMD_GET_LINK_OUT_V2_LINK_FAULT_RX_WIDTH 1
5804#define MC_CMD_GET_LINK_OUT_V2_LINK_FAULT_TX_OFST 16
5805#define MC_CMD_GET_LINK_OUT_V2_LINK_FAULT_TX_LBN 7
5806#define MC_CMD_GET_LINK_OUT_V2_LINK_FAULT_TX_WIDTH 1
5807#define MC_CMD_GET_LINK_OUT_V2_MODULE_UP_VALID_OFST 16
5808#define MC_CMD_GET_LINK_OUT_V2_MODULE_UP_VALID_LBN 8
5809#define MC_CMD_GET_LINK_OUT_V2_MODULE_UP_VALID_WIDTH 1
5810#define MC_CMD_GET_LINK_OUT_V2_MODULE_UP_OFST 16
5811#define MC_CMD_GET_LINK_OUT_V2_MODULE_UP_LBN 9
5812#define MC_CMD_GET_LINK_OUT_V2_MODULE_UP_WIDTH 1
5813/* This returns the negotiated flow control value. */
5814#define MC_CMD_GET_LINK_OUT_V2_FCNTL_OFST 20
5815#define MC_CMD_GET_LINK_OUT_V2_FCNTL_LEN 4
5816/* Enum values, see field(s): */
5817/* MC_CMD_SET_MAC/MC_CMD_SET_MAC_IN/FCNTL */
5818#define MC_CMD_GET_LINK_OUT_V2_MAC_FAULT_OFST 24
5819#define MC_CMD_GET_LINK_OUT_V2_MAC_FAULT_LEN 4
5820/* MC_CMD_MAC_FAULT_XGMII_LOCAL_OFST 24 */
5821/* MC_CMD_MAC_FAULT_XGMII_LOCAL_LBN 0 */
5822/* MC_CMD_MAC_FAULT_XGMII_LOCAL_WIDTH 1 */
5823/* MC_CMD_MAC_FAULT_XGMII_REMOTE_OFST 24 */
5824/* MC_CMD_MAC_FAULT_XGMII_REMOTE_LBN 1 */
5825/* MC_CMD_MAC_FAULT_XGMII_REMOTE_WIDTH 1 */
5826/* MC_CMD_MAC_FAULT_SGMII_REMOTE_OFST 24 */
5827/* MC_CMD_MAC_FAULT_SGMII_REMOTE_LBN 2 */
5828/* MC_CMD_MAC_FAULT_SGMII_REMOTE_WIDTH 1 */
5829/* MC_CMD_MAC_FAULT_PENDING_RECONFIG_OFST 24 */
5830/* MC_CMD_MAC_FAULT_PENDING_RECONFIG_LBN 3 */
5831/* MC_CMD_MAC_FAULT_PENDING_RECONFIG_WIDTH 1 */
5832/* True local device capabilities (taking into account currently used PMD/MDI,
5833 * e.g. plugged-in module). In general, subset of
5834 * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP, but may include extra _FEC_REQUEST
5835 * bits, if the PMD requires FEC. 0 if unknown (e.g. module unplugged). Equal
5836 * to SUPPORTED_CAP for non-pluggable PMDs. Refer to
5837 * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions.
5838 */
5839#define MC_CMD_GET_LINK_OUT_V2_LD_CAP_OFST 28
5840#define MC_CMD_GET_LINK_OUT_V2_LD_CAP_LEN 4
5841/* Auto-negotiation type used on the link */
5842#define MC_CMD_GET_LINK_OUT_V2_AN_TYPE_OFST 32
5843#define MC_CMD_GET_LINK_OUT_V2_AN_TYPE_LEN 4
5844/* Enum values, see field(s): */
5845/* AN_TYPE/TYPE */
5846/* Forward error correction used on the link */
5847#define MC_CMD_GET_LINK_OUT_V2_FEC_TYPE_OFST 36
5848#define MC_CMD_GET_LINK_OUT_V2_FEC_TYPE_LEN 4
5849/* Enum values, see field(s): */
5850/* FEC_TYPE/TYPE */
5851#define MC_CMD_GET_LINK_OUT_V2_EXT_FLAGS_OFST 40
5852#define MC_CMD_GET_LINK_OUT_V2_EXT_FLAGS_LEN 4
5853#define MC_CMD_GET_LINK_OUT_V2_PMD_MDI_CONNECTED_OFST 40
5854#define MC_CMD_GET_LINK_OUT_V2_PMD_MDI_CONNECTED_LBN 0
5855#define MC_CMD_GET_LINK_OUT_V2_PMD_MDI_CONNECTED_WIDTH 1
5856#define MC_CMD_GET_LINK_OUT_V2_PMD_READY_OFST 40
5857#define MC_CMD_GET_LINK_OUT_V2_PMD_READY_LBN 1
5858#define MC_CMD_GET_LINK_OUT_V2_PMD_READY_WIDTH 1
5859#define MC_CMD_GET_LINK_OUT_V2_PMD_LINK_UP_OFST 40
5860#define MC_CMD_GET_LINK_OUT_V2_PMD_LINK_UP_LBN 2
5861#define MC_CMD_GET_LINK_OUT_V2_PMD_LINK_UP_WIDTH 1
5862#define MC_CMD_GET_LINK_OUT_V2_PMA_LINK_UP_OFST 40
5863#define MC_CMD_GET_LINK_OUT_V2_PMA_LINK_UP_LBN 3
5864#define MC_CMD_GET_LINK_OUT_V2_PMA_LINK_UP_WIDTH 1
5865#define MC_CMD_GET_LINK_OUT_V2_PCS_LOCK_OFST 40
5866#define MC_CMD_GET_LINK_OUT_V2_PCS_LOCK_LBN 4
5867#define MC_CMD_GET_LINK_OUT_V2_PCS_LOCK_WIDTH 1
5868#define MC_CMD_GET_LINK_OUT_V2_ALIGN_LOCK_OFST 40
5869#define MC_CMD_GET_LINK_OUT_V2_ALIGN_LOCK_LBN 5
5870#define MC_CMD_GET_LINK_OUT_V2_ALIGN_LOCK_WIDTH 1
5871#define MC_CMD_GET_LINK_OUT_V2_HI_BER_OFST 40
5872#define MC_CMD_GET_LINK_OUT_V2_HI_BER_LBN 6
5873#define MC_CMD_GET_LINK_OUT_V2_HI_BER_WIDTH 1
5874#define MC_CMD_GET_LINK_OUT_V2_FEC_LOCK_OFST 40
5875#define MC_CMD_GET_LINK_OUT_V2_FEC_LOCK_LBN 7
5876#define MC_CMD_GET_LINK_OUT_V2_FEC_LOCK_WIDTH 1
5877#define MC_CMD_GET_LINK_OUT_V2_AN_DONE_OFST 40
5878#define MC_CMD_GET_LINK_OUT_V2_AN_DONE_LBN 8
5879#define MC_CMD_GET_LINK_OUT_V2_AN_DONE_WIDTH 1
5880#define MC_CMD_GET_LINK_OUT_V2_PORT_SHUTDOWN_OFST 40
5881#define MC_CMD_GET_LINK_OUT_V2_PORT_SHUTDOWN_LBN 9
5882#define MC_CMD_GET_LINK_OUT_V2_PORT_SHUTDOWN_WIDTH 1
5883
5884
5885/***********************************/
5886/* MC_CMD_SET_LINK
5887 * Write the unified MAC/PHY link configuration. Locks required: None. Return
5888 * code: 0, EINVAL, ETIME, EAGAIN
5889 */
5890#define MC_CMD_SET_LINK 0x2a
5891#undef MC_CMD_0x2a_PRIVILEGE_CTG
5892
5893#define MC_CMD_0x2a_PRIVILEGE_CTG SRIOV_CTG_LINK
5894
5895/* MC_CMD_SET_LINK_IN msgrequest */
5896#define MC_CMD_SET_LINK_IN_LEN 16
5897/* Near-side advertised capabilities. Refer to
5898 * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions.
5899 */
5900#define MC_CMD_SET_LINK_IN_CAP_OFST 0
5901#define MC_CMD_SET_LINK_IN_CAP_LEN 4
5902/* Flags */
5903#define MC_CMD_SET_LINK_IN_FLAGS_OFST 4
5904#define MC_CMD_SET_LINK_IN_FLAGS_LEN 4
5905#define MC_CMD_SET_LINK_IN_LOWPOWER_OFST 4
5906#define MC_CMD_SET_LINK_IN_LOWPOWER_LBN 0
5907#define MC_CMD_SET_LINK_IN_LOWPOWER_WIDTH 1
5908#define MC_CMD_SET_LINK_IN_POWEROFF_OFST 4
5909#define MC_CMD_SET_LINK_IN_POWEROFF_LBN 1
5910#define MC_CMD_SET_LINK_IN_POWEROFF_WIDTH 1
5911#define MC_CMD_SET_LINK_IN_TXDIS_OFST 4
5912#define MC_CMD_SET_LINK_IN_TXDIS_LBN 2
5913#define MC_CMD_SET_LINK_IN_TXDIS_WIDTH 1
5914#define MC_CMD_SET_LINK_IN_LINKDOWN_OFST 4
5915#define MC_CMD_SET_LINK_IN_LINKDOWN_LBN 3
5916#define MC_CMD_SET_LINK_IN_LINKDOWN_WIDTH 1
5917/* Loopback mode. */
5918#define MC_CMD_SET_LINK_IN_LOOPBACK_MODE_OFST 8
5919#define MC_CMD_SET_LINK_IN_LOOPBACK_MODE_LEN 4
5920/* Enum values, see field(s): */
5921/* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */
5922/* A loopback speed of "0" is supported, and means (choose any available
5923 * speed).
5924 */
5925#define MC_CMD_SET_LINK_IN_LOOPBACK_SPEED_OFST 12
5926#define MC_CMD_SET_LINK_IN_LOOPBACK_SPEED_LEN 4
5927
5928/* MC_CMD_SET_LINK_IN_V2 msgrequest: Updated SET_LINK to include sequence
5929 * number to ensure this SET_LINK command corresponds to the latest
5930 * MODULECHANGE event.
5931 */
5932#define MC_CMD_SET_LINK_IN_V2_LEN 17
5933/* Near-side advertised capabilities. Refer to
5934 * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions.
5935 */
5936#define MC_CMD_SET_LINK_IN_V2_CAP_OFST 0
5937#define MC_CMD_SET_LINK_IN_V2_CAP_LEN 4
5938/* Flags */
5939#define MC_CMD_SET_LINK_IN_V2_FLAGS_OFST 4
5940#define MC_CMD_SET_LINK_IN_V2_FLAGS_LEN 4
5941#define MC_CMD_SET_LINK_IN_V2_LOWPOWER_OFST 4
5942#define MC_CMD_SET_LINK_IN_V2_LOWPOWER_LBN 0
5943#define MC_CMD_SET_LINK_IN_V2_LOWPOWER_WIDTH 1
5944#define MC_CMD_SET_LINK_IN_V2_POWEROFF_OFST 4
5945#define MC_CMD_SET_LINK_IN_V2_POWEROFF_LBN 1
5946#define MC_CMD_SET_LINK_IN_V2_POWEROFF_WIDTH 1
5947#define MC_CMD_SET_LINK_IN_V2_TXDIS_OFST 4
5948#define MC_CMD_SET_LINK_IN_V2_TXDIS_LBN 2
5949#define MC_CMD_SET_LINK_IN_V2_TXDIS_WIDTH 1
5950#define MC_CMD_SET_LINK_IN_V2_LINKDOWN_OFST 4
5951#define MC_CMD_SET_LINK_IN_V2_LINKDOWN_LBN 3
5952#define MC_CMD_SET_LINK_IN_V2_LINKDOWN_WIDTH 1
5953/* Loopback mode. */
5954#define MC_CMD_SET_LINK_IN_V2_LOOPBACK_MODE_OFST 8
5955#define MC_CMD_SET_LINK_IN_V2_LOOPBACK_MODE_LEN 4
5956/* Enum values, see field(s): */
5957/* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */
5958/* A loopback speed of "0" is supported, and means (choose any available
5959 * speed).
5960 */
5961#define MC_CMD_SET_LINK_IN_V2_LOOPBACK_SPEED_OFST 12
5962#define MC_CMD_SET_LINK_IN_V2_LOOPBACK_SPEED_LEN 4
5963#define MC_CMD_SET_LINK_IN_V2_MODULE_SEQ_OFST 16
5964#define MC_CMD_SET_LINK_IN_V2_MODULE_SEQ_LEN 1
5965#define MC_CMD_SET_LINK_IN_V2_MODULE_SEQ_NUMBER_OFST 16
5966#define MC_CMD_SET_LINK_IN_V2_MODULE_SEQ_NUMBER_LBN 0
5967#define MC_CMD_SET_LINK_IN_V2_MODULE_SEQ_NUMBER_WIDTH 7
5968#define MC_CMD_SET_LINK_IN_V2_MODULE_SEQ_IGNORE_OFST 16
5969#define MC_CMD_SET_LINK_IN_V2_MODULE_SEQ_IGNORE_LBN 7
5970#define MC_CMD_SET_LINK_IN_V2_MODULE_SEQ_IGNORE_WIDTH 1
5971
5972/* MC_CMD_SET_LINK_OUT msgresponse */
5973#define MC_CMD_SET_LINK_OUT_LEN 0
5974
5975
5976/***********************************/
5977/* MC_CMD_SET_ID_LED
5978 * Set identification LED state. Locks required: None. Return code: 0, EINVAL
5979 */
5980#define MC_CMD_SET_ID_LED 0x2b
5981#undef MC_CMD_0x2b_PRIVILEGE_CTG
5982
5983#define MC_CMD_0x2b_PRIVILEGE_CTG SRIOV_CTG_LINK
5984
5985/* MC_CMD_SET_ID_LED_IN msgrequest */
5986#define MC_CMD_SET_ID_LED_IN_LEN 4
5987/* Set LED state. */
5988#define MC_CMD_SET_ID_LED_IN_STATE_OFST 0
5989#define MC_CMD_SET_ID_LED_IN_STATE_LEN 4
5990#define MC_CMD_LED_OFF 0x0 /* enum */
5991#define MC_CMD_LED_ON 0x1 /* enum */
5992#define MC_CMD_LED_DEFAULT 0x2 /* enum */
5993
5994/* MC_CMD_SET_ID_LED_OUT msgresponse */
5995#define MC_CMD_SET_ID_LED_OUT_LEN 0
5996
5997
5998/***********************************/
5999/* MC_CMD_SET_MAC
6000 * Set MAC configuration. Locks required: None. Return code: 0, EINVAL
6001 */
6002#define MC_CMD_SET_MAC 0x2c
6003#undef MC_CMD_0x2c_PRIVILEGE_CTG
6004
6005#define MC_CMD_0x2c_PRIVILEGE_CTG SRIOV_CTG_GENERAL
6006
6007/* MC_CMD_SET_MAC_IN msgrequest */
6008#define MC_CMD_SET_MAC_IN_LEN 28
6009/* The MTU is the MTU programmed directly into the XMAC/GMAC (inclusive of
6010 * EtherII, VLAN, bug16011 padding).
6011 */
6012#define MC_CMD_SET_MAC_IN_MTU_OFST 0
6013#define MC_CMD_SET_MAC_IN_MTU_LEN 4
6014#define MC_CMD_SET_MAC_IN_DRAIN_OFST 4
6015#define MC_CMD_SET_MAC_IN_DRAIN_LEN 4
6016#define MC_CMD_SET_MAC_IN_ADDR_OFST 8
6017#define MC_CMD_SET_MAC_IN_ADDR_LEN 8
6018#define MC_CMD_SET_MAC_IN_ADDR_LO_OFST 8
6019#define MC_CMD_SET_MAC_IN_ADDR_LO_LEN 4
6020#define MC_CMD_SET_MAC_IN_ADDR_LO_LBN 64
6021#define MC_CMD_SET_MAC_IN_ADDR_LO_WIDTH 32
6022#define MC_CMD_SET_MAC_IN_ADDR_HI_OFST 12
6023#define MC_CMD_SET_MAC_IN_ADDR_HI_LEN 4
6024#define MC_CMD_SET_MAC_IN_ADDR_HI_LBN 96
6025#define MC_CMD_SET_MAC_IN_ADDR_HI_WIDTH 32
6026#define MC_CMD_SET_MAC_IN_REJECT_OFST 16
6027#define MC_CMD_SET_MAC_IN_REJECT_LEN 4
6028#define MC_CMD_SET_MAC_IN_REJECT_UNCST_OFST 16
6029#define MC_CMD_SET_MAC_IN_REJECT_UNCST_LBN 0
6030#define MC_CMD_SET_MAC_IN_REJECT_UNCST_WIDTH 1
6031#define MC_CMD_SET_MAC_IN_REJECT_BRDCST_OFST 16
6032#define MC_CMD_SET_MAC_IN_REJECT_BRDCST_LBN 1
6033#define MC_CMD_SET_MAC_IN_REJECT_BRDCST_WIDTH 1
6034#define MC_CMD_SET_MAC_IN_FCNTL_OFST 20
6035#define MC_CMD_SET_MAC_IN_FCNTL_LEN 4
6036/* enum: Flow control is off. */
6037#define MC_CMD_FCNTL_OFF 0x0
6038/* enum: Respond to flow control. */
6039#define MC_CMD_FCNTL_RESPOND 0x1
6040/* enum: Respond to and Issue flow control. */
6041#define MC_CMD_FCNTL_BIDIR 0x2
6042/* enum: Auto neg flow control. */
6043#define MC_CMD_FCNTL_AUTO 0x3
6044/* enum: Priority flow control (eftest builds only). */
6045#define MC_CMD_FCNTL_QBB 0x4
6046/* enum: Issue flow control. */
6047#define MC_CMD_FCNTL_GENERATE 0x5
6048#define MC_CMD_SET_MAC_IN_FLAGS_OFST 24
6049#define MC_CMD_SET_MAC_IN_FLAGS_LEN 4
6050#define MC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_OFST 24
6051#define MC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_LBN 0
6052#define MC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_WIDTH 1
6053
6054/* MC_CMD_SET_MAC_EXT_IN msgrequest */
6055#define MC_CMD_SET_MAC_EXT_IN_LEN 32
6056/* The MTU is the MTU programmed directly into the XMAC/GMAC (inclusive of
6057 * EtherII, VLAN, bug16011 padding).
6058 */
6059#define MC_CMD_SET_MAC_EXT_IN_MTU_OFST 0
6060#define MC_CMD_SET_MAC_EXT_IN_MTU_LEN 4
6061#define MC_CMD_SET_MAC_EXT_IN_DRAIN_OFST 4
6062#define MC_CMD_SET_MAC_EXT_IN_DRAIN_LEN 4
6063#define MC_CMD_SET_MAC_EXT_IN_ADDR_OFST 8
6064#define MC_CMD_SET_MAC_EXT_IN_ADDR_LEN 8
6065#define MC_CMD_SET_MAC_EXT_IN_ADDR_LO_OFST 8
6066#define MC_CMD_SET_MAC_EXT_IN_ADDR_LO_LEN 4
6067#define MC_CMD_SET_MAC_EXT_IN_ADDR_LO_LBN 64
6068#define MC_CMD_SET_MAC_EXT_IN_ADDR_LO_WIDTH 32
6069#define MC_CMD_SET_MAC_EXT_IN_ADDR_HI_OFST 12
6070#define MC_CMD_SET_MAC_EXT_IN_ADDR_HI_LEN 4
6071#define MC_CMD_SET_MAC_EXT_IN_ADDR_HI_LBN 96
6072#define MC_CMD_SET_MAC_EXT_IN_ADDR_HI_WIDTH 32
6073#define MC_CMD_SET_MAC_EXT_IN_REJECT_OFST 16
6074#define MC_CMD_SET_MAC_EXT_IN_REJECT_LEN 4
6075#define MC_CMD_SET_MAC_EXT_IN_REJECT_UNCST_OFST 16
6076#define MC_CMD_SET_MAC_EXT_IN_REJECT_UNCST_LBN 0
6077#define MC_CMD_SET_MAC_EXT_IN_REJECT_UNCST_WIDTH 1
6078#define MC_CMD_SET_MAC_EXT_IN_REJECT_BRDCST_OFST 16
6079#define MC_CMD_SET_MAC_EXT_IN_REJECT_BRDCST_LBN 1
6080#define MC_CMD_SET_MAC_EXT_IN_REJECT_BRDCST_WIDTH 1
6081#define MC_CMD_SET_MAC_EXT_IN_FCNTL_OFST 20
6082#define MC_CMD_SET_MAC_EXT_IN_FCNTL_LEN 4
6083/* enum: Flow control is off. */
6084/* MC_CMD_FCNTL_OFF 0x0 */
6085/* enum: Respond to flow control. */
6086/* MC_CMD_FCNTL_RESPOND 0x1 */
6087/* enum: Respond to and Issue flow control. */
6088/* MC_CMD_FCNTL_BIDIR 0x2 */
6089/* enum: Auto neg flow control. */
6090/* MC_CMD_FCNTL_AUTO 0x3 */
6091/* enum: Priority flow control (eftest builds only). */
6092/* MC_CMD_FCNTL_QBB 0x4 */
6093/* enum: Issue flow control. */
6094/* MC_CMD_FCNTL_GENERATE 0x5 */
6095#define MC_CMD_SET_MAC_EXT_IN_FLAGS_OFST 24
6096#define MC_CMD_SET_MAC_EXT_IN_FLAGS_LEN 4
6097#define MC_CMD_SET_MAC_EXT_IN_FLAG_INCLUDE_FCS_OFST 24
6098#define MC_CMD_SET_MAC_EXT_IN_FLAG_INCLUDE_FCS_LBN 0
6099#define MC_CMD_SET_MAC_EXT_IN_FLAG_INCLUDE_FCS_WIDTH 1
6100/* Select which parameters to configure. A parameter will only be modified if
6101 * the corresponding control flag is set. If SET_MAC_ENHANCED is not set in
6102 * capabilities then this field is ignored (and all flags are assumed to be
6103 * set).
6104 */
6105#define MC_CMD_SET_MAC_EXT_IN_CONTROL_OFST 28
6106#define MC_CMD_SET_MAC_EXT_IN_CONTROL_LEN 4
6107#define MC_CMD_SET_MAC_EXT_IN_CFG_MTU_OFST 28
6108#define MC_CMD_SET_MAC_EXT_IN_CFG_MTU_LBN 0
6109#define MC_CMD_SET_MAC_EXT_IN_CFG_MTU_WIDTH 1
6110#define MC_CMD_SET_MAC_EXT_IN_CFG_DRAIN_OFST 28
6111#define MC_CMD_SET_MAC_EXT_IN_CFG_DRAIN_LBN 1
6112#define MC_CMD_SET_MAC_EXT_IN_CFG_DRAIN_WIDTH 1
6113#define MC_CMD_SET_MAC_EXT_IN_CFG_REJECT_OFST 28
6114#define MC_CMD_SET_MAC_EXT_IN_CFG_REJECT_LBN 2
6115#define MC_CMD_SET_MAC_EXT_IN_CFG_REJECT_WIDTH 1
6116#define MC_CMD_SET_MAC_EXT_IN_CFG_FCNTL_OFST 28
6117#define MC_CMD_SET_MAC_EXT_IN_CFG_FCNTL_LBN 3
6118#define MC_CMD_SET_MAC_EXT_IN_CFG_FCNTL_WIDTH 1
6119#define MC_CMD_SET_MAC_EXT_IN_CFG_FCS_OFST 28
6120#define MC_CMD_SET_MAC_EXT_IN_CFG_FCS_LBN 4
6121#define MC_CMD_SET_MAC_EXT_IN_CFG_FCS_WIDTH 1
6122
6123/* MC_CMD_SET_MAC_V3_IN msgrequest */
6124#define MC_CMD_SET_MAC_V3_IN_LEN 40
6125/* The MTU is the MTU programmed directly into the XMAC/GMAC (inclusive of
6126 * EtherII, VLAN, bug16011 padding).
6127 */
6128#define MC_CMD_SET_MAC_V3_IN_MTU_OFST 0
6129#define MC_CMD_SET_MAC_V3_IN_MTU_LEN 4
6130#define MC_CMD_SET_MAC_V3_IN_DRAIN_OFST 4
6131#define MC_CMD_SET_MAC_V3_IN_DRAIN_LEN 4
6132#define MC_CMD_SET_MAC_V3_IN_ADDR_OFST 8
6133#define MC_CMD_SET_MAC_V3_IN_ADDR_LEN 8
6134#define MC_CMD_SET_MAC_V3_IN_ADDR_LO_OFST 8
6135#define MC_CMD_SET_MAC_V3_IN_ADDR_LO_LEN 4
6136#define MC_CMD_SET_MAC_V3_IN_ADDR_LO_LBN 64
6137#define MC_CMD_SET_MAC_V3_IN_ADDR_LO_WIDTH 32
6138#define MC_CMD_SET_MAC_V3_IN_ADDR_HI_OFST 12
6139#define MC_CMD_SET_MAC_V3_IN_ADDR_HI_LEN 4
6140#define MC_CMD_SET_MAC_V3_IN_ADDR_HI_LBN 96
6141#define MC_CMD_SET_MAC_V3_IN_ADDR_HI_WIDTH 32
6142#define MC_CMD_SET_MAC_V3_IN_REJECT_OFST 16
6143#define MC_CMD_SET_MAC_V3_IN_REJECT_LEN 4
6144#define MC_CMD_SET_MAC_V3_IN_REJECT_UNCST_OFST 16
6145#define MC_CMD_SET_MAC_V3_IN_REJECT_UNCST_LBN 0
6146#define MC_CMD_SET_MAC_V3_IN_REJECT_UNCST_WIDTH 1
6147#define MC_CMD_SET_MAC_V3_IN_REJECT_BRDCST_OFST 16
6148#define MC_CMD_SET_MAC_V3_IN_REJECT_BRDCST_LBN 1
6149#define MC_CMD_SET_MAC_V3_IN_REJECT_BRDCST_WIDTH 1
6150#define MC_CMD_SET_MAC_V3_IN_FCNTL_OFST 20
6151#define MC_CMD_SET_MAC_V3_IN_FCNTL_LEN 4
6152/* enum: Flow control is off. */
6153/* MC_CMD_FCNTL_OFF 0x0 */
6154/* enum: Respond to flow control. */
6155/* MC_CMD_FCNTL_RESPOND 0x1 */
6156/* enum: Respond to and Issue flow control. */
6157/* MC_CMD_FCNTL_BIDIR 0x2 */
6158/* enum: Auto neg flow control. */
6159/* MC_CMD_FCNTL_AUTO 0x3 */
6160/* enum: Priority flow control (eftest builds only). */
6161/* MC_CMD_FCNTL_QBB 0x4 */
6162/* enum: Issue flow control. */
6163/* MC_CMD_FCNTL_GENERATE 0x5 */
6164#define MC_CMD_SET_MAC_V3_IN_FLAGS_OFST 24
6165#define MC_CMD_SET_MAC_V3_IN_FLAGS_LEN 4
6166#define MC_CMD_SET_MAC_V3_IN_FLAG_INCLUDE_FCS_OFST 24
6167#define MC_CMD_SET_MAC_V3_IN_FLAG_INCLUDE_FCS_LBN 0
6168#define MC_CMD_SET_MAC_V3_IN_FLAG_INCLUDE_FCS_WIDTH 1
6169/* Select which parameters to configure. A parameter will only be modified if
6170 * the corresponding control flag is set. If SET_MAC_ENHANCED is not set in
6171 * capabilities then this field is ignored (and all flags are assumed to be
6172 * set).
6173 */
6174#define MC_CMD_SET_MAC_V3_IN_CONTROL_OFST 28
6175#define MC_CMD_SET_MAC_V3_IN_CONTROL_LEN 4
6176#define MC_CMD_SET_MAC_V3_IN_CFG_MTU_OFST 28
6177#define MC_CMD_SET_MAC_V3_IN_CFG_MTU_LBN 0
6178#define MC_CMD_SET_MAC_V3_IN_CFG_MTU_WIDTH 1
6179#define MC_CMD_SET_MAC_V3_IN_CFG_DRAIN_OFST 28
6180#define MC_CMD_SET_MAC_V3_IN_CFG_DRAIN_LBN 1
6181#define MC_CMD_SET_MAC_V3_IN_CFG_DRAIN_WIDTH 1
6182#define MC_CMD_SET_MAC_V3_IN_CFG_REJECT_OFST 28
6183#define MC_CMD_SET_MAC_V3_IN_CFG_REJECT_LBN 2
6184#define MC_CMD_SET_MAC_V3_IN_CFG_REJECT_WIDTH 1
6185#define MC_CMD_SET_MAC_V3_IN_CFG_FCNTL_OFST 28
6186#define MC_CMD_SET_MAC_V3_IN_CFG_FCNTL_LBN 3
6187#define MC_CMD_SET_MAC_V3_IN_CFG_FCNTL_WIDTH 1
6188#define MC_CMD_SET_MAC_V3_IN_CFG_FCS_OFST 28
6189#define MC_CMD_SET_MAC_V3_IN_CFG_FCS_LBN 4
6190#define MC_CMD_SET_MAC_V3_IN_CFG_FCS_WIDTH 1
6191/* Identifies the MAC to update by the specifying the end of a logical MAE
6192 * link. Setting TARGET to MAE_LINK_ENDPOINT_COMPAT is equivalent to using the
6193 * previous version of the command (MC_CMD_SET_MAC_EXT). Not all possible
6194 * combinations of MPORT_END and MPORT_SELECTOR in TARGET will work in all
6195 * circumstances. 1. Some will always work (e.g. a VF can always address its
6196 * logical MAC using MPORT_SELECTOR=ASSIGNED,LINK_END=VNIC), 2. Some are not
6197 * meaningful and will always fail with EINVAL (e.g. attempting to address the
6198 * VNIC end of a link to a physical port), 3. Some are meaningful but require
6199 * the MCDI client to have the required permission and fail with EPERM
6200 * otherwise (e.g. trying to set the MAC on a VF the caller cannot administer),
6201 * and 4. Some could be implementation-specific and fail with ENOTSUP if not
6202 * available (no examples exist right now). See SF-123581-TC section 4.3 for
6203 * more details.
6204 */
6205#define MC_CMD_SET_MAC_V3_IN_TARGET_OFST 32
6206#define MC_CMD_SET_MAC_V3_IN_TARGET_LEN 8
6207#define MC_CMD_SET_MAC_V3_IN_TARGET_LO_OFST 32
6208#define MC_CMD_SET_MAC_V3_IN_TARGET_LO_LEN 4
6209#define MC_CMD_SET_MAC_V3_IN_TARGET_LO_LBN 256
6210#define MC_CMD_SET_MAC_V3_IN_TARGET_LO_WIDTH 32
6211#define MC_CMD_SET_MAC_V3_IN_TARGET_HI_OFST 36
6212#define MC_CMD_SET_MAC_V3_IN_TARGET_HI_LEN 4
6213#define MC_CMD_SET_MAC_V3_IN_TARGET_HI_LBN 288
6214#define MC_CMD_SET_MAC_V3_IN_TARGET_HI_WIDTH 32
6215#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_OFST 32
6216#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_LEN 4
6217#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FLAT_OFST 32
6218#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FLAT_LEN 4
6219#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_TYPE_OFST 35
6220#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_TYPE_LEN 1
6221#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_MPORT_ID_OFST 32
6222#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_MPORT_ID_LEN 3
6223#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_PPORT_ID_LBN 256
6224#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_PPORT_ID_WIDTH 4
6225#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_LBN 276
6226#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_WIDTH 4
6227#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_LBN 272
6228#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_WIDTH 4
6229#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FUNC_PF_ID_OFST 34
6230#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FUNC_PF_ID_LEN 1
6231#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FUNC_VF_ID_OFST 32
6232#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FUNC_VF_ID_LEN 2
6233#define MC_CMD_SET_MAC_V3_IN_TARGET_LINK_END_OFST 36
6234#define MC_CMD_SET_MAC_V3_IN_TARGET_LINK_END_LEN 4
6235#define MC_CMD_SET_MAC_V3_IN_TARGET_FLAT_OFST 32
6236#define MC_CMD_SET_MAC_V3_IN_TARGET_FLAT_LEN 8
6237#define MC_CMD_SET_MAC_V3_IN_TARGET_FLAT_LO_OFST 32
6238#define MC_CMD_SET_MAC_V3_IN_TARGET_FLAT_LO_LEN 4
6239#define MC_CMD_SET_MAC_V3_IN_TARGET_FLAT_LO_LBN 256
6240#define MC_CMD_SET_MAC_V3_IN_TARGET_FLAT_LO_WIDTH 32
6241#define MC_CMD_SET_MAC_V3_IN_TARGET_FLAT_HI_OFST 36
6242#define MC_CMD_SET_MAC_V3_IN_TARGET_FLAT_HI_LEN 4
6243#define MC_CMD_SET_MAC_V3_IN_TARGET_FLAT_HI_LBN 288
6244#define MC_CMD_SET_MAC_V3_IN_TARGET_FLAT_HI_WIDTH 32
6245
6246/* MC_CMD_SET_MAC_OUT msgresponse */
6247#define MC_CMD_SET_MAC_OUT_LEN 0
6248
6249/* MC_CMD_SET_MAC_V2_OUT msgresponse */
6250#define MC_CMD_SET_MAC_V2_OUT_LEN 4
6251/* MTU as configured after processing the request. See comment at
6252 * MC_CMD_SET_MAC_IN/MTU. To query MTU without doing any changes, set CONTROL
6253 * to 0.
6254 */
6255#define MC_CMD_SET_MAC_V2_OUT_MTU_OFST 0
6256#define MC_CMD_SET_MAC_V2_OUT_MTU_LEN 4
6257
6258
6259/***********************************/
6260/* MC_CMD_PHY_STATS
6261 * Get generic PHY statistics. This call returns the statistics for a generic
6262 * PHY in a sparse array (indexed by the enumerate). Each value is represented
6263 * by a 32bit number. If the DMA_ADDR is 0, then no DMA is performed, and the
6264 * statistics may be read from the message response. If DMA_ADDR != 0, then the
6265 * statistics are dmad to that (page-aligned location). Locks required: None.
6266 * Returns: 0, ETIME
6267 */
6268#define MC_CMD_PHY_STATS 0x2d
6269#undef MC_CMD_0x2d_PRIVILEGE_CTG
6270
6271#define MC_CMD_0x2d_PRIVILEGE_CTG SRIOV_CTG_LINK
6272
6273/* MC_CMD_PHY_STATS_IN msgrequest */
6274#define MC_CMD_PHY_STATS_IN_LEN 8
6275/* ??? */
6276#define MC_CMD_PHY_STATS_IN_DMA_ADDR_OFST 0
6277#define MC_CMD_PHY_STATS_IN_DMA_ADDR_LEN 8
6278#define MC_CMD_PHY_STATS_IN_DMA_ADDR_LO_OFST 0
6279#define MC_CMD_PHY_STATS_IN_DMA_ADDR_LO_LEN 4
6280#define MC_CMD_PHY_STATS_IN_DMA_ADDR_LO_LBN 0
6281#define MC_CMD_PHY_STATS_IN_DMA_ADDR_LO_WIDTH 32
6282#define MC_CMD_PHY_STATS_IN_DMA_ADDR_HI_OFST 4
6283#define MC_CMD_PHY_STATS_IN_DMA_ADDR_HI_LEN 4
6284#define MC_CMD_PHY_STATS_IN_DMA_ADDR_HI_LBN 32
6285#define MC_CMD_PHY_STATS_IN_DMA_ADDR_HI_WIDTH 32
6286
6287/* MC_CMD_PHY_STATS_OUT_DMA msgresponse */
6288#define MC_CMD_PHY_STATS_OUT_DMA_LEN 0
6289
6290/* MC_CMD_PHY_STATS_OUT_NO_DMA msgresponse */
6291#define MC_CMD_PHY_STATS_OUT_NO_DMA_LEN (((MC_CMD_PHY_NSTATS*32))>>3)
6292#define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_OFST 0
6293#define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_LEN 4
6294#define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_PHY_NSTATS
6295/* enum: OUI. */
6296#define MC_CMD_OUI 0x0
6297/* enum: PMA-PMD Link Up. */
6298#define MC_CMD_PMA_PMD_LINK_UP 0x1
6299/* enum: PMA-PMD RX Fault. */
6300#define MC_CMD_PMA_PMD_RX_FAULT 0x2
6301/* enum: PMA-PMD TX Fault. */
6302#define MC_CMD_PMA_PMD_TX_FAULT 0x3
6303/* enum: PMA-PMD Signal */
6304#define MC_CMD_PMA_PMD_SIGNAL 0x4
6305/* enum: PMA-PMD SNR A. */
6306#define MC_CMD_PMA_PMD_SNR_A 0x5
6307/* enum: PMA-PMD SNR B. */
6308#define MC_CMD_PMA_PMD_SNR_B 0x6
6309/* enum: PMA-PMD SNR C. */
6310#define MC_CMD_PMA_PMD_SNR_C 0x7
6311/* enum: PMA-PMD SNR D. */
6312#define MC_CMD_PMA_PMD_SNR_D 0x8
6313/* enum: PCS Link Up. */
6314#define MC_CMD_PCS_LINK_UP 0x9
6315/* enum: PCS RX Fault. */
6316#define MC_CMD_PCS_RX_FAULT 0xa
6317/* enum: PCS TX Fault. */
6318#define MC_CMD_PCS_TX_FAULT 0xb
6319/* enum: PCS BER. */
6320#define MC_CMD_PCS_BER 0xc
6321/* enum: PCS Block Errors. */
6322#define MC_CMD_PCS_BLOCK_ERRORS 0xd
6323/* enum: PhyXS Link Up. */
6324#define MC_CMD_PHYXS_LINK_UP 0xe
6325/* enum: PhyXS RX Fault. */
6326#define MC_CMD_PHYXS_RX_FAULT 0xf
6327/* enum: PhyXS TX Fault. */
6328#define MC_CMD_PHYXS_TX_FAULT 0x10
6329/* enum: PhyXS Align. */
6330#define MC_CMD_PHYXS_ALIGN 0x11
6331/* enum: PhyXS Sync. */
6332#define MC_CMD_PHYXS_SYNC 0x12
6333/* enum: AN link-up. */
6334#define MC_CMD_AN_LINK_UP 0x13
6335/* enum: AN Complete. */
6336#define MC_CMD_AN_COMPLETE 0x14
6337/* enum: AN 10GBaseT Status. */
6338#define MC_CMD_AN_10GBT_STATUS 0x15
6339/* enum: Clause 22 Link-Up. */
6340#define MC_CMD_CL22_LINK_UP 0x16
6341/* enum: (Last entry) */
6342#define MC_CMD_PHY_NSTATS 0x17
6343
6344
6345/***********************************/
6346/* MC_CMD_MAC_STATS
6347 * Get generic MAC statistics. This call returns unified statistics maintained
6348 * by the MC as it switches between the GMAC and XMAC. The MC will write out
6349 * all supported stats. The driver should zero initialise the buffer to
6350 * guarantee consistent results. If the DMA_ADDR is 0, then no DMA is
6351 * performed, and the statistics may be read from the message response. If
6352 * DMA_ADDR != 0, then the statistics are dmad to that (page-aligned location).
6353 * Locks required: None. The PERIODIC_CLEAR option is not used and now has no
6354 * effect. Returns: 0, ETIME
6355 */
6356#define MC_CMD_MAC_STATS 0x2e
6357#undef MC_CMD_0x2e_PRIVILEGE_CTG
6358
6359#define MC_CMD_0x2e_PRIVILEGE_CTG SRIOV_CTG_GENERAL
6360
6361/* MC_CMD_MAC_STATS_IN msgrequest */
6362#define MC_CMD_MAC_STATS_IN_LEN 20
6363/* ??? */
6364#define MC_CMD_MAC_STATS_IN_DMA_ADDR_OFST 0
6365#define MC_CMD_MAC_STATS_IN_DMA_ADDR_LEN 8
6366#define MC_CMD_MAC_STATS_IN_DMA_ADDR_LO_OFST 0
6367#define MC_CMD_MAC_STATS_IN_DMA_ADDR_LO_LEN 4
6368#define MC_CMD_MAC_STATS_IN_DMA_ADDR_LO_LBN 0
6369#define MC_CMD_MAC_STATS_IN_DMA_ADDR_LO_WIDTH 32
6370#define MC_CMD_MAC_STATS_IN_DMA_ADDR_HI_OFST 4
6371#define MC_CMD_MAC_STATS_IN_DMA_ADDR_HI_LEN 4
6372#define MC_CMD_MAC_STATS_IN_DMA_ADDR_HI_LBN 32
6373#define MC_CMD_MAC_STATS_IN_DMA_ADDR_HI_WIDTH 32
6374#define MC_CMD_MAC_STATS_IN_CMD_OFST 8
6375#define MC_CMD_MAC_STATS_IN_CMD_LEN 4
6376#define MC_CMD_MAC_STATS_IN_DMA_OFST 8
6377#define MC_CMD_MAC_STATS_IN_DMA_LBN 0
6378#define MC_CMD_MAC_STATS_IN_DMA_WIDTH 1
6379#define MC_CMD_MAC_STATS_IN_CLEAR_OFST 8
6380#define MC_CMD_MAC_STATS_IN_CLEAR_LBN 1
6381#define MC_CMD_MAC_STATS_IN_CLEAR_WIDTH 1
6382#define MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_OFST 8
6383#define MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_LBN 2
6384#define MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_WIDTH 1
6385#define MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_OFST 8
6386#define MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_LBN 3
6387#define MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_WIDTH 1
6388#define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_OFST 8
6389#define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_LBN 4
6390#define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_WIDTH 1
6391#define MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_OFST 8
6392#define MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_LBN 5
6393#define MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_WIDTH 1
6394#define MC_CMD_MAC_STATS_IN_PERIOD_MS_OFST 8
6395#define MC_CMD_MAC_STATS_IN_PERIOD_MS_LBN 16
6396#define MC_CMD_MAC_STATS_IN_PERIOD_MS_WIDTH 16
6397/* DMA length. Should be set to MAC_STATS_NUM_STATS * sizeof(uint64_t), as
6398 * returned by MC_CMD_GET_CAPABILITIES_V4_OUT. For legacy firmware not
6399 * supporting MC_CMD_GET_CAPABILITIES_V4_OUT, DMA_LEN should be set to
6400 * MC_CMD_MAC_NSTATS * sizeof(uint64_t)
6401 */
6402#define MC_CMD_MAC_STATS_IN_DMA_LEN_OFST 12
6403#define MC_CMD_MAC_STATS_IN_DMA_LEN_LEN 4
6404/* port id so vadapter stats can be provided */
6405#define MC_CMD_MAC_STATS_IN_PORT_ID_OFST 16
6406#define MC_CMD_MAC_STATS_IN_PORT_ID_LEN 4
6407
6408/* MC_CMD_MAC_STATS_OUT_DMA msgresponse */
6409#define MC_CMD_MAC_STATS_OUT_DMA_LEN 0
6410
6411/* MC_CMD_MAC_STATS_OUT_NO_DMA msgresponse */
6412#define MC_CMD_MAC_STATS_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS*64))>>3)
6413#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_OFST 0
6414#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LEN 8
6415#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_OFST 0
6416#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_LEN 4
6417#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_LBN 0
6418#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_WIDTH 32
6419#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_OFST 4
6420#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_LEN 4
6421#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_LBN 32
6422#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_WIDTH 32
6423#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS
6424#define MC_CMD_MAC_GENERATION_START 0x0 /* enum */
6425#define MC_CMD_MAC_DMABUF_START 0x1 /* enum */
6426#define MC_CMD_MAC_TX_PKTS 0x1 /* enum */
6427#define MC_CMD_MAC_TX_PAUSE_PKTS 0x2 /* enum */
6428#define MC_CMD_MAC_TX_CONTROL_PKTS 0x3 /* enum */
6429#define MC_CMD_MAC_TX_UNICAST_PKTS 0x4 /* enum */
6430#define MC_CMD_MAC_TX_MULTICAST_PKTS 0x5 /* enum */
6431#define MC_CMD_MAC_TX_BROADCAST_PKTS 0x6 /* enum */
6432#define MC_CMD_MAC_TX_BYTES 0x7 /* enum */
6433#define MC_CMD_MAC_TX_BAD_BYTES 0x8 /* enum */
6434#define MC_CMD_MAC_TX_LT64_PKTS 0x9 /* enum */
6435#define MC_CMD_MAC_TX_64_PKTS 0xa /* enum */
6436#define MC_CMD_MAC_TX_65_TO_127_PKTS 0xb /* enum */
6437#define MC_CMD_MAC_TX_128_TO_255_PKTS 0xc /* enum */
6438#define MC_CMD_MAC_TX_256_TO_511_PKTS 0xd /* enum */
6439#define MC_CMD_MAC_TX_512_TO_1023_PKTS 0xe /* enum */
6440#define MC_CMD_MAC_TX_1024_TO_15XX_PKTS 0xf /* enum */
6441#define MC_CMD_MAC_TX_15XX_TO_JUMBO_PKTS 0x10 /* enum */
6442#define MC_CMD_MAC_TX_GTJUMBO_PKTS 0x11 /* enum */
6443#define MC_CMD_MAC_TX_BAD_FCS_PKTS 0x12 /* enum */
6444#define MC_CMD_MAC_TX_SINGLE_COLLISION_PKTS 0x13 /* enum */
6445#define MC_CMD_MAC_TX_MULTIPLE_COLLISION_PKTS 0x14 /* enum */
6446#define MC_CMD_MAC_TX_EXCESSIVE_COLLISION_PKTS 0x15 /* enum */
6447#define MC_CMD_MAC_TX_LATE_COLLISION_PKTS 0x16 /* enum */
6448#define MC_CMD_MAC_TX_DEFERRED_PKTS 0x17 /* enum */
6449#define MC_CMD_MAC_TX_EXCESSIVE_DEFERRED_PKTS 0x18 /* enum */
6450#define MC_CMD_MAC_TX_NON_TCPUDP_PKTS 0x19 /* enum */
6451#define MC_CMD_MAC_TX_MAC_SRC_ERR_PKTS 0x1a /* enum */
6452#define MC_CMD_MAC_TX_IP_SRC_ERR_PKTS 0x1b /* enum */
6453#define MC_CMD_MAC_RX_PKTS 0x1c /* enum */
6454#define MC_CMD_MAC_RX_PAUSE_PKTS 0x1d /* enum */
6455#define MC_CMD_MAC_RX_GOOD_PKTS 0x1e /* enum */
6456#define MC_CMD_MAC_RX_CONTROL_PKTS 0x1f /* enum */
6457#define MC_CMD_MAC_RX_UNICAST_PKTS 0x20 /* enum */
6458#define MC_CMD_MAC_RX_MULTICAST_PKTS 0x21 /* enum */
6459#define MC_CMD_MAC_RX_BROADCAST_PKTS 0x22 /* enum */
6460#define MC_CMD_MAC_RX_BYTES 0x23 /* enum */
6461#define MC_CMD_MAC_RX_BAD_BYTES 0x24 /* enum */
6462#define MC_CMD_MAC_RX_64_PKTS 0x25 /* enum */
6463#define MC_CMD_MAC_RX_65_TO_127_PKTS 0x26 /* enum */
6464#define MC_CMD_MAC_RX_128_TO_255_PKTS 0x27 /* enum */
6465#define MC_CMD_MAC_RX_256_TO_511_PKTS 0x28 /* enum */
6466#define MC_CMD_MAC_RX_512_TO_1023_PKTS 0x29 /* enum */
6467#define MC_CMD_MAC_RX_1024_TO_15XX_PKTS 0x2a /* enum */
6468#define MC_CMD_MAC_RX_15XX_TO_JUMBO_PKTS 0x2b /* enum */
6469#define MC_CMD_MAC_RX_GTJUMBO_PKTS 0x2c /* enum */
6470#define MC_CMD_MAC_RX_UNDERSIZE_PKTS 0x2d /* enum */
6471#define MC_CMD_MAC_RX_BAD_FCS_PKTS 0x2e /* enum */
6472#define MC_CMD_MAC_RX_OVERFLOW_PKTS 0x2f /* enum */
6473#define MC_CMD_MAC_RX_FALSE_CARRIER_PKTS 0x30 /* enum */
6474#define MC_CMD_MAC_RX_SYMBOL_ERROR_PKTS 0x31 /* enum */
6475#define MC_CMD_MAC_RX_ALIGN_ERROR_PKTS 0x32 /* enum */
6476#define MC_CMD_MAC_RX_LENGTH_ERROR_PKTS 0x33 /* enum */
6477#define MC_CMD_MAC_RX_INTERNAL_ERROR_PKTS 0x34 /* enum */
6478#define MC_CMD_MAC_RX_JABBER_PKTS 0x35 /* enum */
6479#define MC_CMD_MAC_RX_NODESC_DROPS 0x36 /* enum */
6480#define MC_CMD_MAC_RX_LANES01_CHAR_ERR 0x37 /* enum */
6481#define MC_CMD_MAC_RX_LANES23_CHAR_ERR 0x38 /* enum */
6482#define MC_CMD_MAC_RX_LANES01_DISP_ERR 0x39 /* enum */
6483#define MC_CMD_MAC_RX_LANES23_DISP_ERR 0x3a /* enum */
6484#define MC_CMD_MAC_RX_MATCH_FAULT 0x3b /* enum */
6485/* enum: PM trunc_bb_overflow counter. Valid for EF10 with PM_AND_RXDP_COUNTERS
6486 * capability only.
6487 */
6488#define MC_CMD_MAC_PM_TRUNC_BB_OVERFLOW 0x3c
6489/* enum: PM discard_bb_overflow counter. Valid for EF10 with
6490 * PM_AND_RXDP_COUNTERS capability only.
6491 */
6492#define MC_CMD_MAC_PM_DISCARD_BB_OVERFLOW 0x3d
6493/* enum: PM trunc_vfifo_full counter. Valid for EF10 with PM_AND_RXDP_COUNTERS
6494 * capability only.
6495 */
6496#define MC_CMD_MAC_PM_TRUNC_VFIFO_FULL 0x3e
6497/* enum: PM discard_vfifo_full counter. Valid for EF10 with
6498 * PM_AND_RXDP_COUNTERS capability only.
6499 */
6500#define MC_CMD_MAC_PM_DISCARD_VFIFO_FULL 0x3f
6501/* enum: PM trunc_qbb counter. Valid for EF10 with PM_AND_RXDP_COUNTERS
6502 * capability only.
6503 */
6504#define MC_CMD_MAC_PM_TRUNC_QBB 0x40
6505/* enum: PM discard_qbb counter. Valid for EF10 with PM_AND_RXDP_COUNTERS
6506 * capability only.
6507 */
6508#define MC_CMD_MAC_PM_DISCARD_QBB 0x41
6509/* enum: PM discard_mapping counter. Valid for EF10 with PM_AND_RXDP_COUNTERS
6510 * capability only.
6511 */
6512#define MC_CMD_MAC_PM_DISCARD_MAPPING 0x42
6513/* enum: RXDP counter: Number of packets dropped due to the queue being
6514 * disabled. Valid for EF10 with PM_AND_RXDP_COUNTERS capability only.
6515 */
6516#define MC_CMD_MAC_RXDP_Q_DISABLED_PKTS 0x43
6517/* enum: RXDP counter: Number of packets dropped by the DICPU. Valid for EF10
6518 * with PM_AND_RXDP_COUNTERS capability only.
6519 */
6520#define MC_CMD_MAC_RXDP_DI_DROPPED_PKTS 0x45
6521/* enum: RXDP counter: Number of non-host packets. Valid for EF10 with
6522 * PM_AND_RXDP_COUNTERS capability only.
6523 */
6524#define MC_CMD_MAC_RXDP_STREAMING_PKTS 0x46
6525/* enum: RXDP counter: Number of times an hlb descriptor fetch was performed.
6526 * Valid for EF10 with PM_AND_RXDP_COUNTERS capability only.
6527 */
6528#define MC_CMD_MAC_RXDP_HLB_FETCH_CONDITIONS 0x47
6529/* enum: RXDP counter: Number of times the DPCPU waited for an existing
6530 * descriptor fetch. Valid for EF10 with PM_AND_RXDP_COUNTERS capability only.
6531 */
6532#define MC_CMD_MAC_RXDP_HLB_WAIT_CONDITIONS 0x48
6533#define MC_CMD_MAC_VADAPTER_RX_DMABUF_START 0x4c /* enum */
6534#define MC_CMD_MAC_VADAPTER_RX_UNICAST_PACKETS 0x4c /* enum */
6535#define MC_CMD_MAC_VADAPTER_RX_UNICAST_BYTES 0x4d /* enum */
6536#define MC_CMD_MAC_VADAPTER_RX_MULTICAST_PACKETS 0x4e /* enum */
6537#define MC_CMD_MAC_VADAPTER_RX_MULTICAST_BYTES 0x4f /* enum */
6538#define MC_CMD_MAC_VADAPTER_RX_BROADCAST_PACKETS 0x50 /* enum */
6539#define MC_CMD_MAC_VADAPTER_RX_BROADCAST_BYTES 0x51 /* enum */
6540#define MC_CMD_MAC_VADAPTER_RX_BAD_PACKETS 0x52 /* enum */
6541#define MC_CMD_MAC_VADAPTER_RX_BAD_BYTES 0x53 /* enum */
6542#define MC_CMD_MAC_VADAPTER_RX_OVERFLOW 0x54 /* enum */
6543#define MC_CMD_MAC_VADAPTER_TX_DMABUF_START 0x57 /* enum */
6544#define MC_CMD_MAC_VADAPTER_TX_UNICAST_PACKETS 0x57 /* enum */
6545#define MC_CMD_MAC_VADAPTER_TX_UNICAST_BYTES 0x58 /* enum */
6546#define MC_CMD_MAC_VADAPTER_TX_MULTICAST_PACKETS 0x59 /* enum */
6547#define MC_CMD_MAC_VADAPTER_TX_MULTICAST_BYTES 0x5a /* enum */
6548#define MC_CMD_MAC_VADAPTER_TX_BROADCAST_PACKETS 0x5b /* enum */
6549#define MC_CMD_MAC_VADAPTER_TX_BROADCAST_BYTES 0x5c /* enum */
6550#define MC_CMD_MAC_VADAPTER_TX_BAD_PACKETS 0x5d /* enum */
6551#define MC_CMD_MAC_VADAPTER_TX_BAD_BYTES 0x5e /* enum */
6552#define MC_CMD_MAC_VADAPTER_TX_OVERFLOW 0x5f /* enum */
6553/* enum: Start of GMAC stats buffer space, for Siena only. */
6554#define MC_CMD_GMAC_DMABUF_START 0x40
6555/* enum: End of GMAC stats buffer space, for Siena only. */
6556#define MC_CMD_GMAC_DMABUF_END 0x5f
6557/* enum: GENERATION_END value, used together with GENERATION_START to verify
6558 * consistency of DMAd data. For legacy firmware / drivers without extended
6559 * stats (more precisely, when DMA_LEN == MC_CMD_MAC_NSTATS *
6560 * sizeof(uint64_t)), this entry holds the GENERATION_END value. Otherwise,
6561 * this value is invalid/ reserved and GENERATION_END is written as the last
6562 * 64-bit word of the DMA buffer (at DMA_LEN - sizeof(uint64_t)). Note that
6563 * this is consistent with the legacy behaviour, in the sense that entry 96 is
6564 * the last 64-bit word in the buffer when DMA_LEN == MC_CMD_MAC_NSTATS *
6565 * sizeof(uint64_t). See SF-109306-TC, Section 9.2 for details.
6566 */
6567#define MC_CMD_MAC_GENERATION_END 0x60
6568#define MC_CMD_MAC_NSTATS 0x61 /* enum */
6569
6570/* MC_CMD_MAC_STATS_V2_OUT_DMA msgresponse */
6571#define MC_CMD_MAC_STATS_V2_OUT_DMA_LEN 0
6572
6573/* MC_CMD_MAC_STATS_V2_OUT_NO_DMA msgresponse */
6574#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS_V2*64))>>3)
6575#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_OFST 0
6576#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_LEN 8
6577#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_LO_OFST 0
6578#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_LO_LEN 4
6579#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_LO_LBN 0
6580#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_LO_WIDTH 32
6581#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_HI_OFST 4
6582#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_HI_LEN 4
6583#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_HI_LBN 32
6584#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_HI_WIDTH 32
6585#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS_V2
6586/* enum: Start of FEC stats buffer space, Medford2 and up */
6587#define MC_CMD_MAC_FEC_DMABUF_START 0x61
6588/* enum: Number of uncorrected FEC codewords on link (RS-FEC only for Medford2)
6589 */
6590#define MC_CMD_MAC_FEC_UNCORRECTED_ERRORS 0x61
6591/* enum: Number of corrected FEC codewords on link (RS-FEC only for Medford2)
6592 */
6593#define MC_CMD_MAC_FEC_CORRECTED_ERRORS 0x62
6594/* enum: Number of corrected 10-bit symbol errors, lane 0 (RS-FEC only) */
6595#define MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE0 0x63
6596/* enum: Number of corrected 10-bit symbol errors, lane 1 (RS-FEC only) */
6597#define MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE1 0x64
6598/* enum: Number of corrected 10-bit symbol errors, lane 2 (RS-FEC only) */
6599#define MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE2 0x65
6600/* enum: Number of corrected 10-bit symbol errors, lane 3 (RS-FEC only) */
6601#define MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE3 0x66
6602/* enum: This includes the space at offset 103 which is the final
6603 * GENERATION_END in a MAC_STATS_V2 response and otherwise unused.
6604 */
6605#define MC_CMD_MAC_NSTATS_V2 0x68
6606/* Other enum values, see field(s): */
6607/* MC_CMD_MAC_STATS_OUT_NO_DMA/STATISTICS */
6608
6609/* MC_CMD_MAC_STATS_V3_OUT_DMA msgresponse */
6610#define MC_CMD_MAC_STATS_V3_OUT_DMA_LEN 0
6611
6612/* MC_CMD_MAC_STATS_V3_OUT_NO_DMA msgresponse */
6613#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS_V3*64))>>3)
6614#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_OFST 0
6615#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_LEN 8
6616#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_LO_OFST 0
6617#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_LO_LEN 4
6618#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_LO_LBN 0
6619#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_LO_WIDTH 32
6620#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_HI_OFST 4
6621#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_HI_LEN 4
6622#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_HI_LBN 32
6623#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_HI_WIDTH 32
6624#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS_V3
6625/* enum: Start of CTPIO stats buffer space, Medford2 and up */
6626#define MC_CMD_MAC_CTPIO_DMABUF_START 0x68
6627/* enum: Number of CTPIO fallbacks because a DMA packet was in progress on the
6628 * target VI
6629 */
6630#define MC_CMD_MAC_CTPIO_VI_BUSY_FALLBACK 0x68
6631/* enum: Number of times a CTPIO send wrote beyond frame end (informational
6632 * only)
6633 */
6634#define MC_CMD_MAC_CTPIO_LONG_WRITE_SUCCESS 0x69
6635/* enum: Number of CTPIO failures because the TX doorbell was written before
6636 * the end of the frame data
6637 */
6638#define MC_CMD_MAC_CTPIO_MISSING_DBELL_FAIL 0x6a
6639/* enum: Number of CTPIO failures because the internal FIFO overflowed */
6640#define MC_CMD_MAC_CTPIO_OVERFLOW_FAIL 0x6b
6641/* enum: Number of CTPIO failures because the host did not deliver data fast
6642 * enough to avoid MAC underflow
6643 */
6644#define MC_CMD_MAC_CTPIO_UNDERFLOW_FAIL 0x6c
6645/* enum: Number of CTPIO failures because the host did not deliver all the
6646 * frame data within the timeout
6647 */
6648#define MC_CMD_MAC_CTPIO_TIMEOUT_FAIL 0x6d
6649/* enum: Number of CTPIO failures because the frame data arrived out of order
6650 * or with gaps
6651 */
6652#define MC_CMD_MAC_CTPIO_NONCONTIG_WR_FAIL 0x6e
6653/* enum: Number of CTPIO failures because the host started a new frame before
6654 * completing the previous one
6655 */
6656#define MC_CMD_MAC_CTPIO_FRM_CLOBBER_FAIL 0x6f
6657/* enum: Number of CTPIO failures because a write was not a multiple of 32 bits
6658 * or not 32-bit aligned
6659 */
6660#define MC_CMD_MAC_CTPIO_INVALID_WR_FAIL 0x70
6661/* enum: Number of CTPIO fallbacks because another VI on the same port was
6662 * sending a CTPIO frame
6663 */
6664#define MC_CMD_MAC_CTPIO_VI_CLOBBER_FALLBACK 0x71
6665/* enum: Number of CTPIO fallbacks because target VI did not have CTPIO enabled
6666 */
6667#define MC_CMD_MAC_CTPIO_UNQUALIFIED_FALLBACK 0x72
6668/* enum: Number of CTPIO fallbacks because length in header was less than 29
6669 * bytes
6670 */
6671#define MC_CMD_MAC_CTPIO_RUNT_FALLBACK 0x73
6672/* enum: Total number of successful CTPIO sends on this port */
6673#define MC_CMD_MAC_CTPIO_SUCCESS 0x74
6674/* enum: Total number of CTPIO fallbacks on this port */
6675#define MC_CMD_MAC_CTPIO_FALLBACK 0x75
6676/* enum: Total number of CTPIO poisoned frames on this port, whether erased or
6677 * not
6678 */
6679#define MC_CMD_MAC_CTPIO_POISON 0x76
6680/* enum: Total number of CTPIO erased frames on this port */
6681#define MC_CMD_MAC_CTPIO_ERASE 0x77
6682/* enum: This includes the space at offset 120 which is the final
6683 * GENERATION_END in a MAC_STATS_V3 response and otherwise unused.
6684 */
6685#define MC_CMD_MAC_NSTATS_V3 0x79
6686/* Other enum values, see field(s): */
6687/* MC_CMD_MAC_STATS_V2_OUT_NO_DMA/STATISTICS */
6688
6689/* MC_CMD_MAC_STATS_V4_OUT_DMA msgresponse */
6690#define MC_CMD_MAC_STATS_V4_OUT_DMA_LEN 0
6691
6692/* MC_CMD_MAC_STATS_V4_OUT_NO_DMA msgresponse */
6693#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS_V4*64))>>3)
6694#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_OFST 0
6695#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_LEN 8
6696#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_LO_OFST 0
6697#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_LO_LEN 4
6698#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_LO_LBN 0
6699#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_LO_WIDTH 32
6700#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_HI_OFST 4
6701#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_HI_LEN 4
6702#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_HI_LBN 32
6703#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_HI_WIDTH 32
6704#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS_V4
6705/* enum: Start of V4 stats buffer space */
6706#define MC_CMD_MAC_V4_DMABUF_START 0x79
6707/* enum: RXDP counter: Number of packets truncated because scattering was
6708 * disabled.
6709 */
6710#define MC_CMD_MAC_RXDP_SCATTER_DISABLED_TRUNC 0x79
6711/* enum: RXDP counter: Number of times the RXDP head of line blocked waiting
6712 * for descriptors. Will be zero unless RXDP_HLB_IDLE capability is set.
6713 */
6714#define MC_CMD_MAC_RXDP_HLB_IDLE 0x7a
6715/* enum: RXDP counter: Number of times the RXDP timed out while head of line
6716 * blocking. Will be zero unless RXDP_HLB_IDLE capability is set.
6717 */
6718#define MC_CMD_MAC_RXDP_HLB_TIMEOUT 0x7b
6719/* enum: This includes the space at offset 124 which is the final
6720 * GENERATION_END in a MAC_STATS_V4 response and otherwise unused.
6721 */
6722#define MC_CMD_MAC_NSTATS_V4 0x7d
6723/* Other enum values, see field(s): */
6724/* MC_CMD_MAC_STATS_V3_OUT_NO_DMA/STATISTICS */
6725
6726
6727/***********************************/
6728/* MC_CMD_SRIOV
6729 * to be documented
6730 */
6731#define MC_CMD_SRIOV 0x30
6732
6733/* MC_CMD_SRIOV_IN msgrequest */
6734#define MC_CMD_SRIOV_IN_LEN 12
6735#define MC_CMD_SRIOV_IN_ENABLE_OFST 0
6736#define MC_CMD_SRIOV_IN_ENABLE_LEN 4
6737#define MC_CMD_SRIOV_IN_VI_BASE_OFST 4
6738#define MC_CMD_SRIOV_IN_VI_BASE_LEN 4
6739#define MC_CMD_SRIOV_IN_VF_COUNT_OFST 8
6740#define MC_CMD_SRIOV_IN_VF_COUNT_LEN 4
6741
6742/* MC_CMD_SRIOV_OUT msgresponse */
6743#define MC_CMD_SRIOV_OUT_LEN 8
6744#define MC_CMD_SRIOV_OUT_VI_SCALE_OFST 0
6745#define MC_CMD_SRIOV_OUT_VI_SCALE_LEN 4
6746#define MC_CMD_SRIOV_OUT_VF_TOTAL_OFST 4
6747#define MC_CMD_SRIOV_OUT_VF_TOTAL_LEN 4
6748
6749/* MC_CMD_MEMCPY_RECORD_TYPEDEF structuredef */
6750#define MC_CMD_MEMCPY_RECORD_TYPEDEF_LEN 32
6751/* this is only used for the first record */
6752#define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_OFST 0
6753#define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_LEN 4
6754#define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_LBN 0
6755#define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_WIDTH 32
6756#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_OFST 4
6757#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_LEN 4
6758#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_LBN 32
6759#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_WIDTH 32
6760#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_OFST 8
6761#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LEN 8
6762#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LO_OFST 8
6763#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LO_LEN 4
6764#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LO_LBN 64
6765#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LO_WIDTH 32
6766#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_HI_OFST 12
6767#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_HI_LEN 4
6768#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_HI_LBN 96
6769#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_HI_WIDTH 32
6770#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LBN 64
6771#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_WIDTH 64
6772#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_OFST 16
6773#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_LEN 4
6774#define MC_CMD_MEMCPY_RECORD_TYPEDEF_RID_INLINE 0x100 /* enum */
6775#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_LBN 128
6776#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_WIDTH 32
6777#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_OFST 20
6778#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LEN 8
6779#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LO_OFST 20
6780#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LO_LEN 4
6781#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LO_LBN 160
6782#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LO_WIDTH 32
6783#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_HI_OFST 24
6784#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_HI_LEN 4
6785#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_HI_LBN 192
6786#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_HI_WIDTH 32
6787#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LBN 160
6788#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_WIDTH 64
6789#define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_OFST 28
6790#define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_LEN 4
6791#define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_LBN 224
6792#define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_WIDTH 32
6793
6794
6795/***********************************/
6796/* MC_CMD_MEMCPY
6797 * DMA write data into (Rid,Addr), either by dma reading (Rid,Addr), or by data
6798 * embedded directly in the command.
6799 *
6800 * A common pattern is for a client to use generation counts to signal a dma
6801 * update of a datastructure. To facilitate this, this MCDI operation can
6802 * contain multiple requests which are executed in strict order. Requests take
6803 * the form of duplicating the entire MCDI request continuously (including the
6804 * requests record, which is ignored in all but the first structure)
6805 *
6806 * The source data can either come from a DMA from the host, or it can be
6807 * embedded within the request directly, thereby eliminating a DMA read. To
6808 * indicate this, the client sets FROM_RID=%RID_INLINE, ADDR_HI=0, and
6809 * ADDR_LO=offset, and inserts the data at %offset from the start of the
6810 * payload. It's the callers responsibility to ensure that the embedded data
6811 * doesn't overlap the records.
6812 *
6813 * Returns: 0, EINVAL (invalid RID)
6814 */
6815#define MC_CMD_MEMCPY 0x31
6816
6817/* MC_CMD_MEMCPY_IN msgrequest */
6818#define MC_CMD_MEMCPY_IN_LENMIN 32
6819#define MC_CMD_MEMCPY_IN_LENMAX 224
6820#define MC_CMD_MEMCPY_IN_LENMAX_MCDI2 992
6821#define MC_CMD_MEMCPY_IN_LEN(num) (0+32*(num))
6822#define MC_CMD_MEMCPY_IN_RECORD_NUM(len) (((len)-0)/32)
6823/* see MC_CMD_MEMCPY_RECORD_TYPEDEF */
6824#define MC_CMD_MEMCPY_IN_RECORD_OFST 0
6825#define MC_CMD_MEMCPY_IN_RECORD_LEN 32
6826#define MC_CMD_MEMCPY_IN_RECORD_MINNUM 1
6827#define MC_CMD_MEMCPY_IN_RECORD_MAXNUM 7
6828#define MC_CMD_MEMCPY_IN_RECORD_MAXNUM_MCDI2 31
6829
6830/* MC_CMD_MEMCPY_OUT msgresponse */
6831#define MC_CMD_MEMCPY_OUT_LEN 0
6832
6833
6834/***********************************/
6835/* MC_CMD_WOL_FILTER_SET
6836 * Set a WoL filter.
6837 */
6838#define MC_CMD_WOL_FILTER_SET 0x32
6839#undef MC_CMD_0x32_PRIVILEGE_CTG
6840
6841#define MC_CMD_0x32_PRIVILEGE_CTG SRIOV_CTG_LINK
6842
6843/* MC_CMD_WOL_FILTER_SET_IN msgrequest */
6844#define MC_CMD_WOL_FILTER_SET_IN_LEN 192
6845#define MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0
6846#define MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4
6847#define MC_CMD_FILTER_MODE_SIMPLE 0x0 /* enum */
6848#define MC_CMD_FILTER_MODE_STRUCTURED 0xffffffff /* enum */
6849/* A type value of 1 is unused. */
6850#define MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4
6851#define MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4
6852/* enum: Magic */
6853#define MC_CMD_WOL_TYPE_MAGIC 0x0
6854/* enum: MS Windows Magic */
6855#define MC_CMD_WOL_TYPE_WIN_MAGIC 0x2
6856/* enum: IPv4 Syn */
6857#define MC_CMD_WOL_TYPE_IPV4_SYN 0x3
6858/* enum: IPv6 Syn */
6859#define MC_CMD_WOL_TYPE_IPV6_SYN 0x4
6860/* enum: Bitmap */
6861#define MC_CMD_WOL_TYPE_BITMAP 0x5
6862/* enum: Link */
6863#define MC_CMD_WOL_TYPE_LINK 0x6
6864/* enum: (Above this for future use) */
6865#define MC_CMD_WOL_TYPE_MAX 0x7
6866#define MC_CMD_WOL_FILTER_SET_IN_DATA_OFST 8
6867#define MC_CMD_WOL_FILTER_SET_IN_DATA_LEN 4
6868#define MC_CMD_WOL_FILTER_SET_IN_DATA_NUM 46
6869
6870/* MC_CMD_WOL_FILTER_SET_IN_MAGIC msgrequest */
6871#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_LEN 16
6872/* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
6873/* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */
6874/* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
6875/* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */
6876#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_OFST 8
6877#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LEN 8
6878#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LO_OFST 8
6879#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LO_LEN 4
6880#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LO_LBN 64
6881#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LO_WIDTH 32
6882#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_HI_OFST 12
6883#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_HI_LEN 4
6884#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_HI_LBN 96
6885#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_HI_WIDTH 32
6886
6887/* MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN msgrequest */
6888#define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_LEN 20
6889/* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
6890/* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */
6891/* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
6892/* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */
6893#define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_IP_OFST 8
6894#define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_IP_LEN 4
6895#define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_IP_OFST 12
6896#define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_IP_LEN 4
6897#define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_OFST 16
6898#define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_LEN 2
6899#define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_OFST 18
6900#define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_LEN 2
6901
6902/* MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN msgrequest */
6903#define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_LEN 44
6904/* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
6905/* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */
6906/* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
6907/* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */
6908#define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_OFST 8
6909#define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_LEN 16
6910#define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_OFST 24
6911#define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_LEN 16
6912#define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_OFST 40
6913#define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_LEN 2
6914#define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_OFST 42
6915#define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_LEN 2
6916
6917/* MC_CMD_WOL_FILTER_SET_IN_BITMAP msgrequest */
6918#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN 187
6919/* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
6920/* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */
6921/* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
6922/* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */
6923#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_OFST 8
6924#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_LEN 48
6925#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_OFST 56
6926#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_LEN 128
6927#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_OFST 184
6928#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_LEN 1
6929#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_OFST 185
6930#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_LEN 1
6931#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_OFST 186
6932#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_LEN 1
6933
6934/* MC_CMD_WOL_FILTER_SET_IN_LINK msgrequest */
6935#define MC_CMD_WOL_FILTER_SET_IN_LINK_LEN 12
6936/* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
6937/* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */
6938/* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
6939/* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */
6940#define MC_CMD_WOL_FILTER_SET_IN_LINK_MASK_OFST 8
6941#define MC_CMD_WOL_FILTER_SET_IN_LINK_MASK_LEN 4
6942#define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_OFST 8
6943#define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_LBN 0
6944#define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_WIDTH 1
6945#define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_OFST 8
6946#define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_LBN 1
6947#define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_WIDTH 1
6948
6949/* MC_CMD_WOL_FILTER_SET_OUT msgresponse */
6950#define MC_CMD_WOL_FILTER_SET_OUT_LEN 4
6951#define MC_CMD_WOL_FILTER_SET_OUT_FILTER_ID_OFST 0
6952#define MC_CMD_WOL_FILTER_SET_OUT_FILTER_ID_LEN 4
6953
6954
6955/***********************************/
6956/* MC_CMD_WOL_FILTER_REMOVE
6957 * Remove a WoL filter. Locks required: None. Returns: 0, EINVAL, ENOSYS
6958 */
6959#define MC_CMD_WOL_FILTER_REMOVE 0x33
6960#undef MC_CMD_0x33_PRIVILEGE_CTG
6961
6962#define MC_CMD_0x33_PRIVILEGE_CTG SRIOV_CTG_LINK
6963
6964/* MC_CMD_WOL_FILTER_REMOVE_IN msgrequest */
6965#define MC_CMD_WOL_FILTER_REMOVE_IN_LEN 4
6966#define MC_CMD_WOL_FILTER_REMOVE_IN_FILTER_ID_OFST 0
6967#define MC_CMD_WOL_FILTER_REMOVE_IN_FILTER_ID_LEN 4
6968
6969/* MC_CMD_WOL_FILTER_REMOVE_OUT msgresponse */
6970#define MC_CMD_WOL_FILTER_REMOVE_OUT_LEN 0
6971
6972
6973/***********************************/
6974/* MC_CMD_WOL_FILTER_RESET
6975 * Reset (i.e. remove all) WoL filters. Locks required: None. Returns: 0,
6976 * ENOSYS
6977 */
6978#define MC_CMD_WOL_FILTER_RESET 0x34
6979#undef MC_CMD_0x34_PRIVILEGE_CTG
6980
6981#define MC_CMD_0x34_PRIVILEGE_CTG SRIOV_CTG_LINK
6982
6983/* MC_CMD_WOL_FILTER_RESET_IN msgrequest */
6984#define MC_CMD_WOL_FILTER_RESET_IN_LEN 4
6985#define MC_CMD_WOL_FILTER_RESET_IN_MASK_OFST 0
6986#define MC_CMD_WOL_FILTER_RESET_IN_MASK_LEN 4
6987#define MC_CMD_WOL_FILTER_RESET_IN_WAKE_FILTERS 0x1 /* enum */
6988#define MC_CMD_WOL_FILTER_RESET_IN_LIGHTSOUT_OFFLOADS 0x2 /* enum */
6989
6990/* MC_CMD_WOL_FILTER_RESET_OUT msgresponse */
6991#define MC_CMD_WOL_FILTER_RESET_OUT_LEN 0
6992
6993
6994/***********************************/
6995/* MC_CMD_SET_MCAST_HASH
6996 * Set the MCAST hash value without otherwise reconfiguring the MAC
6997 */
6998#define MC_CMD_SET_MCAST_HASH 0x35
6999
7000/* MC_CMD_SET_MCAST_HASH_IN msgrequest */
7001#define MC_CMD_SET_MCAST_HASH_IN_LEN 32
7002#define MC_CMD_SET_MCAST_HASH_IN_HASH0_OFST 0
7003#define MC_CMD_SET_MCAST_HASH_IN_HASH0_LEN 16
7004#define MC_CMD_SET_MCAST_HASH_IN_HASH1_OFST 16
7005#define MC_CMD_SET_MCAST_HASH_IN_HASH1_LEN 16
7006
7007/* MC_CMD_SET_MCAST_HASH_OUT msgresponse */
7008#define MC_CMD_SET_MCAST_HASH_OUT_LEN 0
7009
7010
7011/***********************************/
7012/* MC_CMD_NVRAM_TYPES
7013 * Return bitfield indicating available types of virtual NVRAM partitions.
7014 * Locks required: none. Returns: 0
7015 */
7016#define MC_CMD_NVRAM_TYPES 0x36
7017#undef MC_CMD_0x36_PRIVILEGE_CTG
7018
7019#define MC_CMD_0x36_PRIVILEGE_CTG SRIOV_CTG_ADMIN
7020
7021/* MC_CMD_NVRAM_TYPES_IN msgrequest */
7022#define MC_CMD_NVRAM_TYPES_IN_LEN 0
7023
7024/* MC_CMD_NVRAM_TYPES_OUT msgresponse */
7025#define MC_CMD_NVRAM_TYPES_OUT_LEN 4
7026/* Bit mask of supported types. */
7027#define MC_CMD_NVRAM_TYPES_OUT_TYPES_OFST 0
7028#define MC_CMD_NVRAM_TYPES_OUT_TYPES_LEN 4
7029/* enum: Disabled callisto. */
7030#define MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO 0x0
7031/* enum: MC firmware. */
7032#define MC_CMD_NVRAM_TYPE_MC_FW 0x1
7033/* enum: MC backup firmware. */
7034#define MC_CMD_NVRAM_TYPE_MC_FW_BACKUP 0x2
7035/* enum: Static configuration Port0. */
7036#define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT0 0x3
7037/* enum: Static configuration Port1. */
7038#define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT1 0x4
7039/* enum: Dynamic configuration Port0. */
7040#define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0 0x5
7041/* enum: Dynamic configuration Port1. */
7042#define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1 0x6
7043/* enum: Expansion Rom. */
7044#define MC_CMD_NVRAM_TYPE_EXP_ROM 0x7
7045/* enum: Expansion Rom Configuration Port0. */
7046#define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT0 0x8
7047/* enum: Expansion Rom Configuration Port1. */
7048#define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT1 0x9
7049/* enum: Phy Configuration Port0. */
7050#define MC_CMD_NVRAM_TYPE_PHY_PORT0 0xa
7051/* enum: Phy Configuration Port1. */
7052#define MC_CMD_NVRAM_TYPE_PHY_PORT1 0xb
7053/* enum: Log. */
7054#define MC_CMD_NVRAM_TYPE_LOG 0xc
7055/* enum: FPGA image. */
7056#define MC_CMD_NVRAM_TYPE_FPGA 0xd
7057/* enum: FPGA backup image */
7058#define MC_CMD_NVRAM_TYPE_FPGA_BACKUP 0xe
7059/* enum: FC firmware. */
7060#define MC_CMD_NVRAM_TYPE_FC_FW 0xf
7061/* enum: FC backup firmware. */
7062#define MC_CMD_NVRAM_TYPE_FC_FW_BACKUP 0x10
7063/* enum: CPLD image. */
7064#define MC_CMD_NVRAM_TYPE_CPLD 0x11
7065/* enum: Licensing information. */
7066#define MC_CMD_NVRAM_TYPE_LICENSE 0x12
7067/* enum: FC Log. */
7068#define MC_CMD_NVRAM_TYPE_FC_LOG 0x13
7069/* enum: Additional flash on FPGA. */
7070#define MC_CMD_NVRAM_TYPE_FC_EXTRA 0x14
7071
7072
7073/***********************************/
7074/* MC_CMD_NVRAM_INFO
7075 * Read info about a virtual NVRAM partition. Locks required: none. Returns: 0,
7076 * EINVAL (bad type).
7077 */
7078#define MC_CMD_NVRAM_INFO 0x37
7079#undef MC_CMD_0x37_PRIVILEGE_CTG
7080
7081#define MC_CMD_0x37_PRIVILEGE_CTG SRIOV_CTG_ADMIN
7082
7083/* MC_CMD_NVRAM_INFO_IN msgrequest */
7084#define MC_CMD_NVRAM_INFO_IN_LEN 4
7085#define MC_CMD_NVRAM_INFO_IN_TYPE_OFST 0
7086#define MC_CMD_NVRAM_INFO_IN_TYPE_LEN 4
7087/* Enum values, see field(s): */
7088/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
7089
7090/* MC_CMD_NVRAM_INFO_OUT msgresponse */
7091#define MC_CMD_NVRAM_INFO_OUT_LEN 24
7092#define MC_CMD_NVRAM_INFO_OUT_TYPE_OFST 0
7093#define MC_CMD_NVRAM_INFO_OUT_TYPE_LEN 4
7094/* Enum values, see field(s): */
7095/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
7096#define MC_CMD_NVRAM_INFO_OUT_SIZE_OFST 4
7097#define MC_CMD_NVRAM_INFO_OUT_SIZE_LEN 4
7098#define MC_CMD_NVRAM_INFO_OUT_ERASESIZE_OFST 8
7099#define MC_CMD_NVRAM_INFO_OUT_ERASESIZE_LEN 4
7100#define MC_CMD_NVRAM_INFO_OUT_FLAGS_OFST 12
7101#define MC_CMD_NVRAM_INFO_OUT_FLAGS_LEN 4
7102#define MC_CMD_NVRAM_INFO_OUT_PROTECTED_OFST 12
7103#define MC_CMD_NVRAM_INFO_OUT_PROTECTED_LBN 0
7104#define MC_CMD_NVRAM_INFO_OUT_PROTECTED_WIDTH 1
7105#define MC_CMD_NVRAM_INFO_OUT_TLV_OFST 12
7106#define MC_CMD_NVRAM_INFO_OUT_TLV_LBN 1
7107#define MC_CMD_NVRAM_INFO_OUT_TLV_WIDTH 1
7108#define MC_CMD_NVRAM_INFO_OUT_READ_ONLY_IF_TSA_BOUND_OFST 12
7109#define MC_CMD_NVRAM_INFO_OUT_READ_ONLY_IF_TSA_BOUND_LBN 2
7110#define MC_CMD_NVRAM_INFO_OUT_READ_ONLY_IF_TSA_BOUND_WIDTH 1
7111#define MC_CMD_NVRAM_INFO_OUT_CRC_OFST 12
7112#define MC_CMD_NVRAM_INFO_OUT_CRC_LBN 3
7113#define MC_CMD_NVRAM_INFO_OUT_CRC_WIDTH 1
7114#define MC_CMD_NVRAM_INFO_OUT_READ_ONLY_OFST 12
7115#define MC_CMD_NVRAM_INFO_OUT_READ_ONLY_LBN 5
7116#define MC_CMD_NVRAM_INFO_OUT_READ_ONLY_WIDTH 1
7117#define MC_CMD_NVRAM_INFO_OUT_CMAC_OFST 12
7118#define MC_CMD_NVRAM_INFO_OUT_CMAC_LBN 6
7119#define MC_CMD_NVRAM_INFO_OUT_CMAC_WIDTH 1
7120#define MC_CMD_NVRAM_INFO_OUT_A_B_OFST 12
7121#define MC_CMD_NVRAM_INFO_OUT_A_B_LBN 7
7122#define MC_CMD_NVRAM_INFO_OUT_A_B_WIDTH 1
7123#define MC_CMD_NVRAM_INFO_OUT_PHYSDEV_OFST 16
7124#define MC_CMD_NVRAM_INFO_OUT_PHYSDEV_LEN 4
7125#define MC_CMD_NVRAM_INFO_OUT_PHYSADDR_OFST 20
7126#define MC_CMD_NVRAM_INFO_OUT_PHYSADDR_LEN 4
7127
7128/* MC_CMD_NVRAM_INFO_V2_OUT msgresponse */
7129#define MC_CMD_NVRAM_INFO_V2_OUT_LEN 28
7130#define MC_CMD_NVRAM_INFO_V2_OUT_TYPE_OFST 0
7131#define MC_CMD_NVRAM_INFO_V2_OUT_TYPE_LEN 4
7132/* Enum values, see field(s): */
7133/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
7134#define MC_CMD_NVRAM_INFO_V2_OUT_SIZE_OFST 4
7135#define MC_CMD_NVRAM_INFO_V2_OUT_SIZE_LEN 4
7136#define MC_CMD_NVRAM_INFO_V2_OUT_ERASESIZE_OFST 8
7137#define MC_CMD_NVRAM_INFO_V2_OUT_ERASESIZE_LEN 4
7138#define MC_CMD_NVRAM_INFO_V2_OUT_FLAGS_OFST 12
7139#define MC_CMD_NVRAM_INFO_V2_OUT_FLAGS_LEN 4
7140#define MC_CMD_NVRAM_INFO_V2_OUT_PROTECTED_OFST 12
7141#define MC_CMD_NVRAM_INFO_V2_OUT_PROTECTED_LBN 0
7142#define MC_CMD_NVRAM_INFO_V2_OUT_PROTECTED_WIDTH 1
7143#define MC_CMD_NVRAM_INFO_V2_OUT_TLV_OFST 12
7144#define MC_CMD_NVRAM_INFO_V2_OUT_TLV_LBN 1
7145#define MC_CMD_NVRAM_INFO_V2_OUT_TLV_WIDTH 1
7146#define MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_IF_TSA_BOUND_OFST 12
7147#define MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_IF_TSA_BOUND_LBN 2
7148#define MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_IF_TSA_BOUND_WIDTH 1
7149#define MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_OFST 12
7150#define MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_LBN 5
7151#define MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_WIDTH 1
7152#define MC_CMD_NVRAM_INFO_V2_OUT_A_B_OFST 12
7153#define MC_CMD_NVRAM_INFO_V2_OUT_A_B_LBN 7
7154#define MC_CMD_NVRAM_INFO_V2_OUT_A_B_WIDTH 1
7155#define MC_CMD_NVRAM_INFO_V2_OUT_PHYSDEV_OFST 16
7156#define MC_CMD_NVRAM_INFO_V2_OUT_PHYSDEV_LEN 4
7157#define MC_CMD_NVRAM_INFO_V2_OUT_PHYSADDR_OFST 20
7158#define MC_CMD_NVRAM_INFO_V2_OUT_PHYSADDR_LEN 4
7159/* Writes must be multiples of this size. Added to support the MUM on Sorrento.
7160 */
7161#define MC_CMD_NVRAM_INFO_V2_OUT_WRITESIZE_OFST 24
7162#define MC_CMD_NVRAM_INFO_V2_OUT_WRITESIZE_LEN 4
7163
7164
7165/***********************************/
7166/* MC_CMD_NVRAM_UPDATE_START
7167 * Start a group of update operations on a virtual NVRAM partition. Locks
7168 * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad type), EACCES (if
7169 * PHY_LOCK required and not held). In an adapter bound to a TSA controller,
7170 * MC_CMD_NVRAM_UPDATE_START can only be used on a subset of partition types
7171 * i.e. static config, dynamic config and expansion ROM config. Attempting to
7172 * perform this operation on a restricted partition will return the error
7173 * EPERM.
7174 */
7175#define MC_CMD_NVRAM_UPDATE_START 0x38
7176#undef MC_CMD_0x38_PRIVILEGE_CTG
7177
7178#define MC_CMD_0x38_PRIVILEGE_CTG SRIOV_CTG_ADMIN
7179
7180/* MC_CMD_NVRAM_UPDATE_START_IN msgrequest: Legacy NVRAM_UPDATE_START request.
7181 * Use NVRAM_UPDATE_START_V2_IN in new code
7182 */
7183#define MC_CMD_NVRAM_UPDATE_START_IN_LEN 4
7184#define MC_CMD_NVRAM_UPDATE_START_IN_TYPE_OFST 0
7185#define MC_CMD_NVRAM_UPDATE_START_IN_TYPE_LEN 4
7186/* Enum values, see field(s): */
7187/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
7188
7189/* MC_CMD_NVRAM_UPDATE_START_V2_IN msgrequest: Extended NVRAM_UPDATE_START
7190 * request with additional flags indicating version of command in use. See
7191 * MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT for details of extended functionality. Use
7192 * paired up with NVRAM_UPDATE_FINISH_V2_IN.
7193 */
7194#define MC_CMD_NVRAM_UPDATE_START_V2_IN_LEN 8
7195#define MC_CMD_NVRAM_UPDATE_START_V2_IN_TYPE_OFST 0
7196#define MC_CMD_NVRAM_UPDATE_START_V2_IN_TYPE_LEN 4
7197/* Enum values, see field(s): */
7198/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
7199#define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAGS_OFST 4
7200#define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAGS_LEN 4
7201#define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAG_REPORT_VERIFY_RESULT_OFST 4
7202#define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAG_REPORT_VERIFY_RESULT_LBN 0
7203#define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAG_REPORT_VERIFY_RESULT_WIDTH 1
7204
7205/* MC_CMD_NVRAM_UPDATE_START_OUT msgresponse */
7206#define MC_CMD_NVRAM_UPDATE_START_OUT_LEN 0
7207
7208
7209/***********************************/
7210/* MC_CMD_NVRAM_READ
7211 * Read data from a virtual NVRAM partition. Locks required: PHY_LOCK if
7212 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if
7213 * PHY_LOCK required and not held)
7214 */
7215#define MC_CMD_NVRAM_READ 0x39
7216#undef MC_CMD_0x39_PRIVILEGE_CTG
7217
7218#define MC_CMD_0x39_PRIVILEGE_CTG SRIOV_CTG_ADMIN
7219
7220/* MC_CMD_NVRAM_READ_IN msgrequest */
7221#define MC_CMD_NVRAM_READ_IN_LEN 12
7222#define MC_CMD_NVRAM_READ_IN_TYPE_OFST 0
7223#define MC_CMD_NVRAM_READ_IN_TYPE_LEN 4
7224/* Enum values, see field(s): */
7225/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
7226#define MC_CMD_NVRAM_READ_IN_OFFSET_OFST 4
7227#define MC_CMD_NVRAM_READ_IN_OFFSET_LEN 4
7228/* amount to read in bytes */
7229#define MC_CMD_NVRAM_READ_IN_LENGTH_OFST 8
7230#define MC_CMD_NVRAM_READ_IN_LENGTH_LEN 4
7231
7232/* MC_CMD_NVRAM_READ_IN_V2 msgrequest */
7233#define MC_CMD_NVRAM_READ_IN_V2_LEN 16
7234#define MC_CMD_NVRAM_READ_IN_V2_TYPE_OFST 0
7235#define MC_CMD_NVRAM_READ_IN_V2_TYPE_LEN 4
7236/* Enum values, see field(s): */
7237/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
7238#define MC_CMD_NVRAM_READ_IN_V2_OFFSET_OFST 4
7239#define MC_CMD_NVRAM_READ_IN_V2_OFFSET_LEN 4
7240/* amount to read in bytes */
7241#define MC_CMD_NVRAM_READ_IN_V2_LENGTH_OFST 8
7242#define MC_CMD_NVRAM_READ_IN_V2_LENGTH_LEN 4
7243/* Optional control info. If a partition is stored with an A/B versioning
7244 * scheme (i.e. in more than one physical partition in NVRAM) the host can set
7245 * this to control which underlying physical partition is used to read data
7246 * from. This allows it to perform a read-modify-write-verify with the write
7247 * lock continuously held by calling NVRAM_UPDATE_START, reading the old
7248 * contents using MODE=TARGET_CURRENT, overwriting the old partition and then
7249 * verifying by reading with MODE=TARGET_BACKUP.
7250 */
7251#define MC_CMD_NVRAM_READ_IN_V2_MODE_OFST 12
7252#define MC_CMD_NVRAM_READ_IN_V2_MODE_LEN 4
7253/* enum: Same as omitting MODE: caller sees data in current partition unless it
7254 * holds the write lock in which case it sees data in the partition it is
7255 * updating.
7256 */
7257#define MC_CMD_NVRAM_READ_IN_V2_DEFAULT 0x0
7258/* enum: Read from the current partition of an A/B pair, even if holding the
7259 * write lock.
7260 */
7261#define MC_CMD_NVRAM_READ_IN_V2_TARGET_CURRENT 0x1
7262/* enum: Read from the non-current (i.e. to be updated) partition of an A/B
7263 * pair
7264 */
7265#define MC_CMD_NVRAM_READ_IN_V2_TARGET_BACKUP 0x2
7266
7267/* MC_CMD_NVRAM_READ_OUT msgresponse */
7268#define MC_CMD_NVRAM_READ_OUT_LENMIN 1
7269#define MC_CMD_NVRAM_READ_OUT_LENMAX 252
7270#define MC_CMD_NVRAM_READ_OUT_LENMAX_MCDI2 1020
7271#define MC_CMD_NVRAM_READ_OUT_LEN(num) (0+1*(num))
7272#define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_NUM(len) (((len)-0)/1)
7273#define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_OFST 0
7274#define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_LEN 1
7275#define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MINNUM 1
7276#define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MAXNUM 252
7277#define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MAXNUM_MCDI2 1020
7278
7279
7280/***********************************/
7281/* MC_CMD_NVRAM_WRITE
7282 * Write data to a virtual NVRAM partition. Locks required: PHY_LOCK if
7283 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if
7284 * PHY_LOCK required and not held)
7285 */
7286#define MC_CMD_NVRAM_WRITE 0x3a
7287#undef MC_CMD_0x3a_PRIVILEGE_CTG
7288
7289#define MC_CMD_0x3a_PRIVILEGE_CTG SRIOV_CTG_ADMIN
7290
7291/* MC_CMD_NVRAM_WRITE_IN msgrequest */
7292#define MC_CMD_NVRAM_WRITE_IN_LENMIN 13
7293#define MC_CMD_NVRAM_WRITE_IN_LENMAX 252
7294#define MC_CMD_NVRAM_WRITE_IN_LENMAX_MCDI2 1020
7295#define MC_CMD_NVRAM_WRITE_IN_LEN(num) (12+1*(num))
7296#define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_NUM(len) (((len)-12)/1)
7297#define MC_CMD_NVRAM_WRITE_IN_TYPE_OFST 0
7298#define MC_CMD_NVRAM_WRITE_IN_TYPE_LEN 4
7299/* Enum values, see field(s): */
7300/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
7301#define MC_CMD_NVRAM_WRITE_IN_OFFSET_OFST 4
7302#define MC_CMD_NVRAM_WRITE_IN_OFFSET_LEN 4
7303#define MC_CMD_NVRAM_WRITE_IN_LENGTH_OFST 8
7304#define MC_CMD_NVRAM_WRITE_IN_LENGTH_LEN 4
7305#define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_OFST 12
7306#define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_LEN 1
7307#define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MINNUM 1
7308#define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MAXNUM 240
7309#define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MAXNUM_MCDI2 1008
7310
7311/* MC_CMD_NVRAM_WRITE_OUT msgresponse */
7312#define MC_CMD_NVRAM_WRITE_OUT_LEN 0
7313
7314
7315/***********************************/
7316/* MC_CMD_NVRAM_ERASE
7317 * Erase sector(s) from a virtual NVRAM partition. Locks required: PHY_LOCK if
7318 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if
7319 * PHY_LOCK required and not held)
7320 */
7321#define MC_CMD_NVRAM_ERASE 0x3b
7322#undef MC_CMD_0x3b_PRIVILEGE_CTG
7323
7324#define MC_CMD_0x3b_PRIVILEGE_CTG SRIOV_CTG_ADMIN
7325
7326/* MC_CMD_NVRAM_ERASE_IN msgrequest */
7327#define MC_CMD_NVRAM_ERASE_IN_LEN 12
7328#define MC_CMD_NVRAM_ERASE_IN_TYPE_OFST 0
7329#define MC_CMD_NVRAM_ERASE_IN_TYPE_LEN 4
7330/* Enum values, see field(s): */
7331/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
7332#define MC_CMD_NVRAM_ERASE_IN_OFFSET_OFST 4
7333#define MC_CMD_NVRAM_ERASE_IN_OFFSET_LEN 4
7334#define MC_CMD_NVRAM_ERASE_IN_LENGTH_OFST 8
7335#define MC_CMD_NVRAM_ERASE_IN_LENGTH_LEN 4
7336
7337/* MC_CMD_NVRAM_ERASE_OUT msgresponse */
7338#define MC_CMD_NVRAM_ERASE_OUT_LEN 0
7339
7340
7341/***********************************/
7342/* MC_CMD_NVRAM_UPDATE_FINISH
7343 * Finish a group of update operations on a virtual NVRAM partition. Locks
7344 * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad type/offset/
7345 * length), EACCES (if PHY_LOCK required and not held). In an adapter bound to
7346 * a TSA controller, MC_CMD_NVRAM_UPDATE_FINISH can only be used on a subset of
7347 * partition types i.e. static config, dynamic config and expansion ROM config.
7348 * Attempting to perform this operation on a restricted partition will return
7349 * the error EPERM.
7350 */
7351#define MC_CMD_NVRAM_UPDATE_FINISH 0x3c
7352#undef MC_CMD_0x3c_PRIVILEGE_CTG
7353
7354#define MC_CMD_0x3c_PRIVILEGE_CTG SRIOV_CTG_ADMIN
7355
7356/* MC_CMD_NVRAM_UPDATE_FINISH_IN msgrequest: Legacy NVRAM_UPDATE_FINISH
7357 * request. Use NVRAM_UPDATE_FINISH_V2_IN in new code
7358 */
7359#define MC_CMD_NVRAM_UPDATE_FINISH_IN_LEN 8
7360#define MC_CMD_NVRAM_UPDATE_FINISH_IN_TYPE_OFST 0
7361#define MC_CMD_NVRAM_UPDATE_FINISH_IN_TYPE_LEN 4
7362/* Enum values, see field(s): */
7363/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
7364#define MC_CMD_NVRAM_UPDATE_FINISH_IN_REBOOT_OFST 4
7365#define MC_CMD_NVRAM_UPDATE_FINISH_IN_REBOOT_LEN 4
7366
7367/* MC_CMD_NVRAM_UPDATE_FINISH_V2_IN msgrequest: Extended NVRAM_UPDATE_FINISH
7368 * request with additional flags indicating version of NVRAM_UPDATE commands in
7369 * use. See MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT for details of extended
7370 * functionality. Use paired up with NVRAM_UPDATE_START_V2_IN.
7371 */
7372#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_LEN 12
7373#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_TYPE_OFST 0
7374#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_TYPE_LEN 4
7375/* Enum values, see field(s): */
7376/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
7377#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_REBOOT_OFST 4
7378#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_REBOOT_LEN 4
7379#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAGS_OFST 8
7380#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAGS_LEN 4
7381#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_REPORT_VERIFY_RESULT_OFST 8
7382#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_REPORT_VERIFY_RESULT_LBN 0
7383#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_REPORT_VERIFY_RESULT_WIDTH 1
7384#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_RUN_IN_BACKGROUND_OFST 8
7385#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_RUN_IN_BACKGROUND_LBN 1
7386#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_RUN_IN_BACKGROUND_WIDTH 1
7387#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_POLL_VERIFY_RESULT_OFST 8
7388#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_POLL_VERIFY_RESULT_LBN 2
7389#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_POLL_VERIFY_RESULT_WIDTH 1
7390#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_ABORT_OFST 8
7391#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_ABORT_LBN 3
7392#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_ABORT_WIDTH 1
7393
7394/* MC_CMD_NVRAM_UPDATE_FINISH_OUT msgresponse: Legacy NVRAM_UPDATE_FINISH
7395 * response. Use NVRAM_UPDATE_FINISH_V2_OUT in new code
7396 */
7397#define MC_CMD_NVRAM_UPDATE_FINISH_OUT_LEN 0
7398
7399/* MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT msgresponse:
7400 *
7401 * Extended NVRAM_UPDATE_FINISH response that communicates the result of secure
7402 * firmware validation where applicable back to the host.
7403 *
7404 * Medford only: For signed firmware images, such as those for medford, the MC
7405 * firmware verifies the signature before marking the firmware image as valid.
7406 * This process takes a few seconds to complete. So is likely to take more than
7407 * the MCDI timeout. Hence signature verification is initiated when
7408 * MC_CMD_NVRAM_UPDATE_FINISH_V2_IN is received by the firmware, however, the
7409 * MCDI command is run in a background MCDI processing thread. This response
7410 * payload includes the results of the signature verification. Note that the
7411 * per-partition nvram lock in firmware is only released after the verification
7412 * has completed.
7413 */
7414#define MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_LEN 4
7415/* Result of nvram update completion processing. Result codes that indicate an
7416 * internal build failure and therefore not expected to be seen by customers in
7417 * the field are marked with a prefix 'Internal-error'.
7418 */
7419#define MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_RESULT_CODE_OFST 0
7420#define MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_RESULT_CODE_LEN 4
7421/* enum: Invalid return code; only non-zero values are defined. Defined as
7422 * unknown for backwards compatibility with NVRAM_UPDATE_FINISH_OUT.
7423 */
7424#define MC_CMD_NVRAM_VERIFY_RC_UNKNOWN 0x0
7425/* enum: Verify succeeded without any errors. */
7426#define MC_CMD_NVRAM_VERIFY_RC_SUCCESS 0x1
7427/* enum: CMS format verification failed due to an internal error. */
7428#define MC_CMD_NVRAM_VERIFY_RC_CMS_CHECK_FAILED 0x2
7429/* enum: Invalid CMS format in image metadata. */
7430#define MC_CMD_NVRAM_VERIFY_RC_INVALID_CMS_FORMAT 0x3
7431/* enum: Message digest verification failed due to an internal error. */
7432#define MC_CMD_NVRAM_VERIFY_RC_MESSAGE_DIGEST_CHECK_FAILED 0x4
7433/* enum: Error in message digest calculated over the reflash-header, payload
7434 * and reflash-trailer.
7435 */
7436#define MC_CMD_NVRAM_VERIFY_RC_BAD_MESSAGE_DIGEST 0x5
7437/* enum: Signature verification failed due to an internal error. */
7438#define MC_CMD_NVRAM_VERIFY_RC_SIGNATURE_CHECK_FAILED 0x6
7439/* enum: There are no valid signatures in the image. */
7440#define MC_CMD_NVRAM_VERIFY_RC_NO_VALID_SIGNATURES 0x7
7441/* enum: Trusted approvers verification failed due to an internal error. */
7442#define MC_CMD_NVRAM_VERIFY_RC_TRUSTED_APPROVERS_CHECK_FAILED 0x8
7443/* enum: The Trusted approver's list is empty. */
7444#define MC_CMD_NVRAM_VERIFY_RC_NO_TRUSTED_APPROVERS 0x9
7445/* enum: Signature chain verification failed due to an internal error. */
7446#define MC_CMD_NVRAM_VERIFY_RC_SIGNATURE_CHAIN_CHECK_FAILED 0xa
7447/* enum: The signers of the signatures in the image are not listed in the
7448 * Trusted approver's list.
7449 */
7450#define MC_CMD_NVRAM_VERIFY_RC_NO_SIGNATURE_MATCH 0xb
7451/* enum: The image contains a test-signed certificate, but the adapter accepts
7452 * only production signed images.
7453 */
7454#define MC_CMD_NVRAM_VERIFY_RC_REJECT_TEST_SIGNED 0xc
7455/* enum: The image has a lower security level than the current firmware. */
7456#define MC_CMD_NVRAM_VERIFY_RC_SECURITY_LEVEL_DOWNGRADE 0xd
7457/* enum: Internal-error. The signed image is missing the 'contents' section,
7458 * where the 'contents' section holds the actual image payload to be applied.
7459 */
7460#define MC_CMD_NVRAM_VERIFY_RC_CONTENT_NOT_FOUND 0xe
7461/* enum: Internal-error. The bundle header is invalid. */
7462#define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_CONTENT_HEADER_INVALID 0xf
7463/* enum: Internal-error. The bundle does not have a valid reflash image layout.
7464 */
7465#define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_REFLASH_IMAGE_INVALID 0x10
7466/* enum: Internal-error. The bundle has an inconsistent layout of components or
7467 * incorrect checksum.
7468 */
7469#define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_IMAGE_LAYOUT_INVALID 0x11
7470/* enum: Internal-error. The bundle manifest is inconsistent with components in
7471 * the bundle.
7472 */
7473#define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_INVALID 0x12
7474/* enum: Internal-error. The number of components in a bundle do not match the
7475 * number of components advertised by the bundle manifest.
7476 */
7477#define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_NUM_COMPONENTS_MISMATCH 0x13
7478/* enum: Internal-error. The bundle contains too many components for the MC
7479 * firmware to process
7480 */
7481#define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_TOO_MANY_COMPONENTS 0x14
7482/* enum: Internal-error. The bundle manifest has an invalid/inconsistent
7483 * component.
7484 */
7485#define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_COMPONENT_INVALID 0x15
7486/* enum: Internal-error. The hash of a component does not match the hash stored
7487 * in the bundle manifest.
7488 */
7489#define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_COMPONENT_HASH_MISMATCH 0x16
7490/* enum: Internal-error. Component hash calculation failed. */
7491#define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_COMPONENT_HASH_FAILED 0x17
7492/* enum: Internal-error. The component does not have a valid reflash image
7493 * layout.
7494 */
7495#define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_COMPONENT_REFLASH_IMAGE_INVALID 0x18
7496/* enum: The bundle processing code failed to copy a component to its target
7497 * partition.
7498 */
7499#define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_COMPONENT_COPY_FAILED 0x19
7500/* enum: The update operation is in-progress. */
7501#define MC_CMD_NVRAM_VERIFY_RC_PENDING 0x1a
7502
7503
7504/***********************************/
7505/* MC_CMD_REBOOT
7506 * Reboot the MC.
7507 *
7508 * The AFTER_ASSERTION flag is intended to be used when the driver notices an
7509 * assertion failure (at which point it is expected to perform a complete tear
7510 * down and reinitialise), to allow both ports to reset the MC once in an
7511 * atomic fashion.
7512 *
7513 * Production mc firmwares are generally compiled with REBOOT_ON_ASSERT=1,
7514 * which means that they will automatically reboot out of the assertion
7515 * handler, so this is in practise an optional operation. It is still
7516 * recommended that drivers execute this to support custom firmwares with
7517 * REBOOT_ON_ASSERT=0.
7518 *
7519 * Locks required: NONE Returns: Nothing. You get back a response with ERR=1,
7520 * DATALEN=0
7521 */
7522#define MC_CMD_REBOOT 0x3d
7523#undef MC_CMD_0x3d_PRIVILEGE_CTG
7524
7525#define MC_CMD_0x3d_PRIVILEGE_CTG SRIOV_CTG_ADMIN
7526
7527/* MC_CMD_REBOOT_IN msgrequest */
7528#define MC_CMD_REBOOT_IN_LEN 4
7529#define MC_CMD_REBOOT_IN_FLAGS_OFST 0
7530#define MC_CMD_REBOOT_IN_FLAGS_LEN 4
7531#define MC_CMD_REBOOT_FLAGS_AFTER_ASSERTION 0x1 /* enum */
7532
7533/* MC_CMD_REBOOT_OUT msgresponse */
7534#define MC_CMD_REBOOT_OUT_LEN 0
7535
7536
7537/***********************************/
7538/* MC_CMD_SCHEDINFO
7539 * Request scheduler info. Locks required: NONE. Returns: An array of
7540 * (timeslice,maximum overrun), one for each thread, in ascending order of
7541 * thread address.
7542 */
7543#define MC_CMD_SCHEDINFO 0x3e
7544#undef MC_CMD_0x3e_PRIVILEGE_CTG
7545
7546#define MC_CMD_0x3e_PRIVILEGE_CTG SRIOV_CTG_ADMIN
7547
7548/* MC_CMD_SCHEDINFO_IN msgrequest */
7549#define MC_CMD_SCHEDINFO_IN_LEN 0
7550
7551/* MC_CMD_SCHEDINFO_OUT msgresponse */
7552#define MC_CMD_SCHEDINFO_OUT_LENMIN 4
7553#define MC_CMD_SCHEDINFO_OUT_LENMAX 252
7554#define MC_CMD_SCHEDINFO_OUT_LENMAX_MCDI2 1020
7555#define MC_CMD_SCHEDINFO_OUT_LEN(num) (0+4*(num))
7556#define MC_CMD_SCHEDINFO_OUT_DATA_NUM(len) (((len)-0)/4)
7557#define MC_CMD_SCHEDINFO_OUT_DATA_OFST 0
7558#define MC_CMD_SCHEDINFO_OUT_DATA_LEN 4
7559#define MC_CMD_SCHEDINFO_OUT_DATA_MINNUM 1
7560#define MC_CMD_SCHEDINFO_OUT_DATA_MAXNUM 63
7561#define MC_CMD_SCHEDINFO_OUT_DATA_MAXNUM_MCDI2 255
7562
7563
7564/***********************************/
7565/* MC_CMD_REBOOT_MODE
7566 * Set the mode for the next MC reboot. Locks required: NONE. Sets the reboot
7567 * mode to the specified value. Returns the old mode.
7568 */
7569#define MC_CMD_REBOOT_MODE 0x3f
7570#undef MC_CMD_0x3f_PRIVILEGE_CTG
7571
7572#define MC_CMD_0x3f_PRIVILEGE_CTG SRIOV_CTG_INSECURE
7573
7574/* MC_CMD_REBOOT_MODE_IN msgrequest */
7575#define MC_CMD_REBOOT_MODE_IN_LEN 4
7576#define MC_CMD_REBOOT_MODE_IN_VALUE_OFST 0
7577#define MC_CMD_REBOOT_MODE_IN_VALUE_LEN 4
7578/* enum: Normal. */
7579#define MC_CMD_REBOOT_MODE_NORMAL 0x0
7580/* enum: Power-on Reset. */
7581#define MC_CMD_REBOOT_MODE_POR 0x2
7582/* enum: Snapper. */
7583#define MC_CMD_REBOOT_MODE_SNAPPER 0x3
7584/* enum: snapper fake POR */
7585#define MC_CMD_REBOOT_MODE_SNAPPER_POR 0x4
7586#define MC_CMD_REBOOT_MODE_IN_FAKE_OFST 0
7587#define MC_CMD_REBOOT_MODE_IN_FAKE_LBN 7
7588#define MC_CMD_REBOOT_MODE_IN_FAKE_WIDTH 1
7589
7590/* MC_CMD_REBOOT_MODE_OUT msgresponse */
7591#define MC_CMD_REBOOT_MODE_OUT_LEN 4
7592#define MC_CMD_REBOOT_MODE_OUT_VALUE_OFST 0
7593#define MC_CMD_REBOOT_MODE_OUT_VALUE_LEN 4
7594
7595
7596/***********************************/
7597/* MC_CMD_SENSOR_INFO
7598 * Returns information about every available sensor.
7599 *
7600 * Each sensor has a single (16bit) value, and a corresponding state. The
7601 * mapping between value and state is nominally determined by the MC, but may
7602 * be implemented using up to 2 ranges per sensor.
7603 *
7604 * This call returns a mask (32bit) of the sensors that are supported by this
7605 * platform, then an array of sensor information structures, in order of sensor
7606 * type (but without gaps for unimplemented sensors). Each structure defines
7607 * the ranges for the corresponding sensor. An unused range is indicated by
7608 * equal limit values. If one range is used, a value outside that range results
7609 * in STATE_FATAL. If two ranges are used, a value outside the second range
7610 * results in STATE_FATAL while a value outside the first and inside the second
7611 * range results in STATE_WARNING.
7612 *
7613 * Sensor masks and sensor information arrays are organised into pages. For
7614 * backward compatibility, older host software can only use sensors in page 0.
7615 * Bit 32 in the sensor mask was previously unused, and is no reserved for use
7616 * as the next page flag.
7617 *
7618 * If the request does not contain a PAGE value then firmware will only return
7619 * page 0 of sensor information, with bit 31 in the sensor mask cleared.
7620 *
7621 * If the request contains a PAGE value then firmware responds with the sensor
7622 * mask and sensor information array for that page of sensors. In this case bit
7623 * 31 in the mask is set if another page exists.
7624 *
7625 * Locks required: None Returns: 0
7626 */
7627#define MC_CMD_SENSOR_INFO 0x41
7628#undef MC_CMD_0x41_PRIVILEGE_CTG
7629
7630#define MC_CMD_0x41_PRIVILEGE_CTG SRIOV_CTG_GENERAL
7631
7632/* MC_CMD_SENSOR_INFO_IN msgrequest */
7633#define MC_CMD_SENSOR_INFO_IN_LEN 0
7634
7635/* MC_CMD_SENSOR_INFO_EXT_IN msgrequest */
7636#define MC_CMD_SENSOR_INFO_EXT_IN_LEN 4
7637/* Which page of sensors to report.
7638 *
7639 * Page 0 contains sensors 0 to 30 (sensor 31 is the next page bit).
7640 *
7641 * Page 1 contains sensors 32 to 62 (sensor 63 is the next page bit). etc.
7642 */
7643#define MC_CMD_SENSOR_INFO_EXT_IN_PAGE_OFST 0
7644#define MC_CMD_SENSOR_INFO_EXT_IN_PAGE_LEN 4
7645
7646/* MC_CMD_SENSOR_INFO_EXT_IN_V2 msgrequest */
7647#define MC_CMD_SENSOR_INFO_EXT_IN_V2_LEN 8
7648/* Which page of sensors to report.
7649 *
7650 * Page 0 contains sensors 0 to 30 (sensor 31 is the next page bit).
7651 *
7652 * Page 1 contains sensors 32 to 62 (sensor 63 is the next page bit). etc.
7653 */
7654#define MC_CMD_SENSOR_INFO_EXT_IN_V2_PAGE_OFST 0
7655#define MC_CMD_SENSOR_INFO_EXT_IN_V2_PAGE_LEN 4
7656/* Flags controlling information retrieved */
7657#define MC_CMD_SENSOR_INFO_EXT_IN_V2_FLAGS_OFST 4
7658#define MC_CMD_SENSOR_INFO_EXT_IN_V2_FLAGS_LEN 4
7659#define MC_CMD_SENSOR_INFO_EXT_IN_V2_ENGINEERING_OFST 4
7660#define MC_CMD_SENSOR_INFO_EXT_IN_V2_ENGINEERING_LBN 0
7661#define MC_CMD_SENSOR_INFO_EXT_IN_V2_ENGINEERING_WIDTH 1
7662
7663/* MC_CMD_SENSOR_INFO_OUT msgresponse */
7664#define MC_CMD_SENSOR_INFO_OUT_LENMIN 4
7665#define MC_CMD_SENSOR_INFO_OUT_LENMAX 252
7666#define MC_CMD_SENSOR_INFO_OUT_LENMAX_MCDI2 1020
7667#define MC_CMD_SENSOR_INFO_OUT_LEN(num) (4+8*(num))
7668#define MC_CMD_SENSOR_INFO_OUT_MC_CMD_SENSOR_ENTRY_NUM(len) (((len)-4)/8)
7669#define MC_CMD_SENSOR_INFO_OUT_MASK_OFST 0
7670#define MC_CMD_SENSOR_INFO_OUT_MASK_LEN 4
7671/* enum: Controller temperature: degC */
7672#define MC_CMD_SENSOR_CONTROLLER_TEMP 0x0
7673/* enum: Phy common temperature: degC */
7674#define MC_CMD_SENSOR_PHY_COMMON_TEMP 0x1
7675/* enum: Controller cooling: bool */
7676#define MC_CMD_SENSOR_CONTROLLER_COOLING 0x2
7677/* enum: Phy 0 temperature: degC */
7678#define MC_CMD_SENSOR_PHY0_TEMP 0x3
7679/* enum: Phy 0 cooling: bool */
7680#define MC_CMD_SENSOR_PHY0_COOLING 0x4
7681/* enum: Phy 1 temperature: degC */
7682#define MC_CMD_SENSOR_PHY1_TEMP 0x5
7683/* enum: Phy 1 cooling: bool */
7684#define MC_CMD_SENSOR_PHY1_COOLING 0x6
7685/* enum: 1.0v power: mV */
7686#define MC_CMD_SENSOR_IN_1V0 0x7
7687/* enum: 1.2v power: mV */
7688#define MC_CMD_SENSOR_IN_1V2 0x8
7689/* enum: 1.8v power: mV */
7690#define MC_CMD_SENSOR_IN_1V8 0x9
7691/* enum: 2.5v power: mV */
7692#define MC_CMD_SENSOR_IN_2V5 0xa
7693/* enum: 3.3v power: mV */
7694#define MC_CMD_SENSOR_IN_3V3 0xb
7695/* enum: 12v power: mV */
7696#define MC_CMD_SENSOR_IN_12V0 0xc
7697/* enum: 1.2v analogue power: mV */
7698#define MC_CMD_SENSOR_IN_1V2A 0xd
7699/* enum: reference voltage: mV */
7700#define MC_CMD_SENSOR_IN_VREF 0xe
7701/* enum: AOE FPGA power: mV */
7702#define MC_CMD_SENSOR_OUT_VAOE 0xf
7703/* enum: AOE FPGA temperature: degC */
7704#define MC_CMD_SENSOR_AOE_TEMP 0x10
7705/* enum: AOE FPGA PSU temperature: degC */
7706#define MC_CMD_SENSOR_PSU_AOE_TEMP 0x11
7707/* enum: AOE PSU temperature: degC */
7708#define MC_CMD_SENSOR_PSU_TEMP 0x12
7709/* enum: Fan 0 speed: RPM */
7710#define MC_CMD_SENSOR_FAN_0 0x13
7711/* enum: Fan 1 speed: RPM */
7712#define MC_CMD_SENSOR_FAN_1 0x14
7713/* enum: Fan 2 speed: RPM */
7714#define MC_CMD_SENSOR_FAN_2 0x15
7715/* enum: Fan 3 speed: RPM */
7716#define MC_CMD_SENSOR_FAN_3 0x16
7717/* enum: Fan 4 speed: RPM */
7718#define MC_CMD_SENSOR_FAN_4 0x17
7719/* enum: AOE FPGA input power: mV */
7720#define MC_CMD_SENSOR_IN_VAOE 0x18
7721/* enum: AOE FPGA current: mA */
7722#define MC_CMD_SENSOR_OUT_IAOE 0x19
7723/* enum: AOE FPGA input current: mA */
7724#define MC_CMD_SENSOR_IN_IAOE 0x1a
7725/* enum: NIC power consumption: W */
7726#define MC_CMD_SENSOR_NIC_POWER 0x1b
7727/* enum: 0.9v power voltage: mV */
7728#define MC_CMD_SENSOR_IN_0V9 0x1c
7729/* enum: 0.9v power current: mA */
7730#define MC_CMD_SENSOR_IN_I0V9 0x1d
7731/* enum: 1.2v power current: mA */
7732#define MC_CMD_SENSOR_IN_I1V2 0x1e
7733/* enum: Not a sensor: reserved for the next page flag */
7734#define MC_CMD_SENSOR_PAGE0_NEXT 0x1f
7735/* enum: 0.9v power voltage (at ADC): mV */
7736#define MC_CMD_SENSOR_IN_0V9_ADC 0x20
7737/* enum: Controller temperature 2: degC */
7738#define MC_CMD_SENSOR_CONTROLLER_2_TEMP 0x21
7739/* enum: Voltage regulator internal temperature: degC */
7740#define MC_CMD_SENSOR_VREG_INTERNAL_TEMP 0x22
7741/* enum: 0.9V voltage regulator temperature: degC */
7742#define MC_CMD_SENSOR_VREG_0V9_TEMP 0x23
7743/* enum: 1.2V voltage regulator temperature: degC */
7744#define MC_CMD_SENSOR_VREG_1V2_TEMP 0x24
7745/* enum: controller internal temperature sensor voltage (internal ADC): mV */
7746#define MC_CMD_SENSOR_CONTROLLER_VPTAT 0x25
7747/* enum: controller internal temperature (internal ADC): degC */
7748#define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP 0x26
7749/* enum: controller internal temperature sensor voltage (external ADC): mV */
7750#define MC_CMD_SENSOR_CONTROLLER_VPTAT_EXTADC 0x27
7751/* enum: controller internal temperature (external ADC): degC */
7752#define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP_EXTADC 0x28
7753/* enum: ambient temperature: degC */
7754#define MC_CMD_SENSOR_AMBIENT_TEMP 0x29
7755/* enum: air flow: bool */
7756#define MC_CMD_SENSOR_AIRFLOW 0x2a
7757/* enum: voltage between VSS08D and VSS08D at CSR: mV */
7758#define MC_CMD_SENSOR_VDD08D_VSS08D_CSR 0x2b
7759/* enum: voltage between VSS08D and VSS08D at CSR (external ADC): mV */
7760#define MC_CMD_SENSOR_VDD08D_VSS08D_CSR_EXTADC 0x2c
7761/* enum: Hotpoint temperature: degC */
7762#define MC_CMD_SENSOR_HOTPOINT_TEMP 0x2d
7763/* enum: Port 0 PHY power switch over-current: bool */
7764#define MC_CMD_SENSOR_PHY_POWER_PORT0 0x2e
7765/* enum: Port 1 PHY power switch over-current: bool */
7766#define MC_CMD_SENSOR_PHY_POWER_PORT1 0x2f
7767/* enum: Mop-up microcontroller reference voltage: mV */
7768#define MC_CMD_SENSOR_MUM_VCC 0x30
7769/* enum: 0.9v power phase A voltage: mV */
7770#define MC_CMD_SENSOR_IN_0V9_A 0x31
7771/* enum: 0.9v power phase A current: mA */
7772#define MC_CMD_SENSOR_IN_I0V9_A 0x32
7773/* enum: 0.9V voltage regulator phase A temperature: degC */
7774#define MC_CMD_SENSOR_VREG_0V9_A_TEMP 0x33
7775/* enum: 0.9v power phase B voltage: mV */
7776#define MC_CMD_SENSOR_IN_0V9_B 0x34
7777/* enum: 0.9v power phase B current: mA */
7778#define MC_CMD_SENSOR_IN_I0V9_B 0x35
7779/* enum: 0.9V voltage regulator phase B temperature: degC */
7780#define MC_CMD_SENSOR_VREG_0V9_B_TEMP 0x36
7781/* enum: CCOM AVREG 1v2 supply (interval ADC): mV */
7782#define MC_CMD_SENSOR_CCOM_AVREG_1V2_SUPPLY 0x37
7783/* enum: CCOM AVREG 1v2 supply (external ADC): mV */
7784#define MC_CMD_SENSOR_CCOM_AVREG_1V2_SUPPLY_EXTADC 0x38
7785/* enum: CCOM AVREG 1v8 supply (interval ADC): mV */
7786#define MC_CMD_SENSOR_CCOM_AVREG_1V8_SUPPLY 0x39
7787/* enum: CCOM AVREG 1v8 supply (external ADC): mV */
7788#define MC_CMD_SENSOR_CCOM_AVREG_1V8_SUPPLY_EXTADC 0x3a
7789/* enum: CCOM RTS temperature: degC */
7790#define MC_CMD_SENSOR_CONTROLLER_RTS 0x3b
7791/* enum: Not a sensor: reserved for the next page flag */
7792#define MC_CMD_SENSOR_PAGE1_NEXT 0x3f
7793/* enum: controller internal temperature sensor voltage on master core
7794 * (internal ADC): mV
7795 */
7796#define MC_CMD_SENSOR_CONTROLLER_MASTER_VPTAT 0x40
7797/* enum: controller internal temperature on master core (internal ADC): degC */
7798#define MC_CMD_SENSOR_CONTROLLER_MASTER_INTERNAL_TEMP 0x41
7799/* enum: controller internal temperature sensor voltage on master core
7800 * (external ADC): mV
7801 */
7802#define MC_CMD_SENSOR_CONTROLLER_MASTER_VPTAT_EXTADC 0x42
7803/* enum: controller internal temperature on master core (external ADC): degC */
7804#define MC_CMD_SENSOR_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC 0x43
7805/* enum: controller internal temperature on slave core sensor voltage (internal
7806 * ADC): mV
7807 */
7808#define MC_CMD_SENSOR_CONTROLLER_SLAVE_VPTAT 0x44
7809/* enum: controller internal temperature on slave core (internal ADC): degC */
7810#define MC_CMD_SENSOR_CONTROLLER_SLAVE_INTERNAL_TEMP 0x45
7811/* enum: controller internal temperature on slave core sensor voltage (external
7812 * ADC): mV
7813 */
7814#define MC_CMD_SENSOR_CONTROLLER_SLAVE_VPTAT_EXTADC 0x46
7815/* enum: controller internal temperature on slave core (external ADC): degC */
7816#define MC_CMD_SENSOR_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC 0x47
7817/* enum: Voltage supplied to the SODIMMs from their power supply: mV */
7818#define MC_CMD_SENSOR_SODIMM_VOUT 0x49
7819/* enum: Temperature of SODIMM 0 (if installed): degC */
7820#define MC_CMD_SENSOR_SODIMM_0_TEMP 0x4a
7821/* enum: Temperature of SODIMM 1 (if installed): degC */
7822#define MC_CMD_SENSOR_SODIMM_1_TEMP 0x4b
7823/* enum: Voltage supplied to the QSFP #0 from their power supply: mV */
7824#define MC_CMD_SENSOR_PHY0_VCC 0x4c
7825/* enum: Voltage supplied to the QSFP #1 from their power supply: mV */
7826#define MC_CMD_SENSOR_PHY1_VCC 0x4d
7827/* enum: Controller die temperature (TDIODE): degC */
7828#define MC_CMD_SENSOR_CONTROLLER_TDIODE_TEMP 0x4e
7829/* enum: Board temperature (front): degC */
7830#define MC_CMD_SENSOR_BOARD_FRONT_TEMP 0x4f
7831/* enum: Board temperature (back): degC */
7832#define MC_CMD_SENSOR_BOARD_BACK_TEMP 0x50
7833/* enum: 1.8v power current: mA */
7834#define MC_CMD_SENSOR_IN_I1V8 0x51
7835/* enum: 2.5v power current: mA */
7836#define MC_CMD_SENSOR_IN_I2V5 0x52
7837/* enum: 3.3v power current: mA */
7838#define MC_CMD_SENSOR_IN_I3V3 0x53
7839/* enum: 12v power current: mA */
7840#define MC_CMD_SENSOR_IN_I12V0 0x54
7841/* enum: 1.3v power: mV */
7842#define MC_CMD_SENSOR_IN_1V3 0x55
7843/* enum: 1.3v power current: mA */
7844#define MC_CMD_SENSOR_IN_I1V3 0x56
7845/* enum: Engineering sensor 1 */
7846#define MC_CMD_SENSOR_ENGINEERING_1 0x57
7847/* enum: Engineering sensor 2 */
7848#define MC_CMD_SENSOR_ENGINEERING_2 0x58
7849/* enum: Engineering sensor 3 */
7850#define MC_CMD_SENSOR_ENGINEERING_3 0x59
7851/* enum: Engineering sensor 4 */
7852#define MC_CMD_SENSOR_ENGINEERING_4 0x5a
7853/* enum: Engineering sensor 5 */
7854#define MC_CMD_SENSOR_ENGINEERING_5 0x5b
7855/* enum: Engineering sensor 6 */
7856#define MC_CMD_SENSOR_ENGINEERING_6 0x5c
7857/* enum: Engineering sensor 7 */
7858#define MC_CMD_SENSOR_ENGINEERING_7 0x5d
7859/* enum: Engineering sensor 8 */
7860#define MC_CMD_SENSOR_ENGINEERING_8 0x5e
7861/* enum: Not a sensor: reserved for the next page flag */
7862#define MC_CMD_SENSOR_PAGE2_NEXT 0x5f
7863/* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF */
7864#define MC_CMD_SENSOR_ENTRY_OFST 4
7865#define MC_CMD_SENSOR_ENTRY_LEN 8
7866#define MC_CMD_SENSOR_ENTRY_LO_OFST 4
7867#define MC_CMD_SENSOR_ENTRY_LO_LEN 4
7868#define MC_CMD_SENSOR_ENTRY_LO_LBN 32
7869#define MC_CMD_SENSOR_ENTRY_LO_WIDTH 32
7870#define MC_CMD_SENSOR_ENTRY_HI_OFST 8
7871#define MC_CMD_SENSOR_ENTRY_HI_LEN 4
7872#define MC_CMD_SENSOR_ENTRY_HI_LBN 64
7873#define MC_CMD_SENSOR_ENTRY_HI_WIDTH 32
7874#define MC_CMD_SENSOR_ENTRY_MINNUM 0
7875#define MC_CMD_SENSOR_ENTRY_MAXNUM 31
7876#define MC_CMD_SENSOR_ENTRY_MAXNUM_MCDI2 127
7877
7878/* MC_CMD_SENSOR_INFO_EXT_OUT msgresponse */
7879#define MC_CMD_SENSOR_INFO_EXT_OUT_LENMIN 4
7880#define MC_CMD_SENSOR_INFO_EXT_OUT_LENMAX 252
7881#define MC_CMD_SENSOR_INFO_EXT_OUT_LENMAX_MCDI2 1020
7882#define MC_CMD_SENSOR_INFO_EXT_OUT_LEN(num) (4+8*(num))
7883#define MC_CMD_SENSOR_INFO_EXT_OUT_MC_CMD_SENSOR_ENTRY_NUM(len) (((len)-4)/8)
7884#define MC_CMD_SENSOR_INFO_EXT_OUT_MASK_OFST 0
7885#define MC_CMD_SENSOR_INFO_EXT_OUT_MASK_LEN 4
7886/* Enum values, see field(s): */
7887/* MC_CMD_SENSOR_INFO_OUT */
7888#define MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_OFST 0
7889#define MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_LBN 31
7890#define MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_WIDTH 1
7891/* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF */
7892/* MC_CMD_SENSOR_ENTRY_OFST 4 */
7893/* MC_CMD_SENSOR_ENTRY_LEN 8 */
7894/* MC_CMD_SENSOR_ENTRY_LO_OFST 4 */
7895/* MC_CMD_SENSOR_ENTRY_LO_LEN 4 */
7896/* MC_CMD_SENSOR_ENTRY_LO_LBN 32 */
7897/* MC_CMD_SENSOR_ENTRY_LO_WIDTH 32 */
7898/* MC_CMD_SENSOR_ENTRY_HI_OFST 8 */
7899/* MC_CMD_SENSOR_ENTRY_HI_LEN 4 */
7900/* MC_CMD_SENSOR_ENTRY_HI_LBN 64 */
7901/* MC_CMD_SENSOR_ENTRY_HI_WIDTH 32 */
7902/* MC_CMD_SENSOR_ENTRY_MINNUM 0 */
7903/* MC_CMD_SENSOR_ENTRY_MAXNUM 31 */
7904/* MC_CMD_SENSOR_ENTRY_MAXNUM_MCDI2 127 */
7905
7906/* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF structuredef */
7907#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_LEN 8
7908#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_OFST 0
7909#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LEN 2
7910#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LBN 0
7911#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_WIDTH 16
7912#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_OFST 2
7913#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LEN 2
7914#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LBN 16
7915#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_WIDTH 16
7916#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_OFST 4
7917#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LEN 2
7918#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LBN 32
7919#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_WIDTH 16
7920#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_OFST 6
7921#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LEN 2
7922#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LBN 48
7923#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_WIDTH 16
7924
7925
7926/***********************************/
7927/* MC_CMD_READ_SENSORS
7928 * Returns the current reading from each sensor. DMAs an array of sensor
7929 * readings, in order of sensor type (but without gaps for unimplemented
7930 * sensors), into host memory. Each array element is a
7931 * MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF dword.
7932 *
7933 * If the request does not contain the LENGTH field then only sensors 0 to 30
7934 * are reported, to avoid DMA buffer overflow in older host software. If the
7935 * sensor reading require more space than the LENGTH allows, then return
7936 * EINVAL.
7937 *
7938 * The MC will send a SENSOREVT event every time any sensor changes state. The
7939 * driver is responsible for ensuring that it doesn't miss any events. The
7940 * board will function normally if all sensors are in STATE_OK or
7941 * STATE_WARNING. Otherwise the board should not be expected to function.
7942 */
7943#define MC_CMD_READ_SENSORS 0x42
7944#undef MC_CMD_0x42_PRIVILEGE_CTG
7945
7946#define MC_CMD_0x42_PRIVILEGE_CTG SRIOV_CTG_GENERAL
7947
7948/* MC_CMD_READ_SENSORS_IN msgrequest */
7949#define MC_CMD_READ_SENSORS_IN_LEN 8
7950/* DMA address of host buffer for sensor readings (must be 4Kbyte aligned).
7951 *
7952 * If the address is 0xffffffffffffffff send the readings in the response (used
7953 * by cmdclient).
7954 */
7955#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_OFST 0
7956#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LEN 8
7957#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_OFST 0
7958#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_LEN 4
7959#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_LBN 0
7960#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_WIDTH 32
7961#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_OFST 4
7962#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_LEN 4
7963#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_LBN 32
7964#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_WIDTH 32
7965
7966/* MC_CMD_READ_SENSORS_EXT_IN msgrequest */
7967#define MC_CMD_READ_SENSORS_EXT_IN_LEN 12
7968/* DMA address of host buffer for sensor readings (must be 4Kbyte aligned).
7969 *
7970 * If the address is 0xffffffffffffffff send the readings in the response (used
7971 * by cmdclient).
7972 */
7973#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_OFST 0
7974#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LEN 8
7975#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_OFST 0
7976#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_LEN 4
7977#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_LBN 0
7978#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_WIDTH 32
7979#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_HI_OFST 4
7980#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_HI_LEN 4
7981#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_HI_LBN 32
7982#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_HI_WIDTH 32
7983/* Size in bytes of host buffer. */
7984#define MC_CMD_READ_SENSORS_EXT_IN_LENGTH_OFST 8
7985#define MC_CMD_READ_SENSORS_EXT_IN_LENGTH_LEN 4
7986
7987/* MC_CMD_READ_SENSORS_EXT_IN_V2 msgrequest */
7988#define MC_CMD_READ_SENSORS_EXT_IN_V2_LEN 16
7989/* DMA address of host buffer for sensor readings (must be 4Kbyte aligned).
7990 *
7991 * If the address is 0xffffffffffffffff send the readings in the response (used
7992 * by cmdclient).
7993 */
7994#define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_OFST 0
7995#define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_LEN 8
7996#define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_LO_OFST 0
7997#define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_LO_LEN 4
7998#define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_LO_LBN 0
7999#define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_LO_WIDTH 32
8000#define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_HI_OFST 4
8001#define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_HI_LEN 4
8002#define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_HI_LBN 32
8003#define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_HI_WIDTH 32
8004/* Size in bytes of host buffer. */
8005#define MC_CMD_READ_SENSORS_EXT_IN_V2_LENGTH_OFST 8
8006#define MC_CMD_READ_SENSORS_EXT_IN_V2_LENGTH_LEN 4
8007/* Flags controlling information retrieved */
8008#define MC_CMD_READ_SENSORS_EXT_IN_V2_FLAGS_OFST 12
8009#define MC_CMD_READ_SENSORS_EXT_IN_V2_FLAGS_LEN 4
8010#define MC_CMD_READ_SENSORS_EXT_IN_V2_ENGINEERING_OFST 12
8011#define MC_CMD_READ_SENSORS_EXT_IN_V2_ENGINEERING_LBN 0
8012#define MC_CMD_READ_SENSORS_EXT_IN_V2_ENGINEERING_WIDTH 1
8013
8014/* MC_CMD_READ_SENSORS_OUT msgresponse */
8015#define MC_CMD_READ_SENSORS_OUT_LEN 0
8016
8017/* MC_CMD_READ_SENSORS_EXT_OUT msgresponse */
8018#define MC_CMD_READ_SENSORS_EXT_OUT_LEN 0
8019
8020/* MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF structuredef */
8021#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_LEN 4
8022#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_OFST 0
8023#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LEN 2
8024#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LBN 0
8025#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_WIDTH 16
8026#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_OFST 2
8027#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LEN 1
8028/* enum: Ok. */
8029#define MC_CMD_SENSOR_STATE_OK 0x0
8030/* enum: Breached warning threshold. */
8031#define MC_CMD_SENSOR_STATE_WARNING 0x1
8032/* enum: Breached fatal threshold. */
8033#define MC_CMD_SENSOR_STATE_FATAL 0x2
8034/* enum: Fault with sensor. */
8035#define MC_CMD_SENSOR_STATE_BROKEN 0x3
8036/* enum: Sensor is working but does not currently have a reading. */
8037#define MC_CMD_SENSOR_STATE_NO_READING 0x4
8038/* enum: Sensor initialisation failed. */
8039#define MC_CMD_SENSOR_STATE_INIT_FAILED 0x5
8040#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LBN 16
8041#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_WIDTH 8
8042#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_OFST 3
8043#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_LEN 1
8044/* Enum values, see field(s): */
8045/* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */
8046#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_LBN 24
8047#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_WIDTH 8
8048
8049
8050/***********************************/
8051/* MC_CMD_GET_PHY_STATE
8052 * Report current state of PHY. A 'zombie' PHY is a PHY that has failed to boot
8053 * (e.g. due to missing or corrupted firmware). Locks required: None. Return
8054 * code: 0
8055 */
8056#define MC_CMD_GET_PHY_STATE 0x43
8057#undef MC_CMD_0x43_PRIVILEGE_CTG
8058
8059#define MC_CMD_0x43_PRIVILEGE_CTG SRIOV_CTG_GENERAL
8060
8061/* MC_CMD_GET_PHY_STATE_IN msgrequest */
8062#define MC_CMD_GET_PHY_STATE_IN_LEN 0
8063
8064/* MC_CMD_GET_PHY_STATE_OUT msgresponse */
8065#define MC_CMD_GET_PHY_STATE_OUT_LEN 4
8066#define MC_CMD_GET_PHY_STATE_OUT_STATE_OFST 0
8067#define MC_CMD_GET_PHY_STATE_OUT_STATE_LEN 4
8068/* enum: Ok. */
8069#define MC_CMD_PHY_STATE_OK 0x1
8070/* enum: Faulty. */
8071#define MC_CMD_PHY_STATE_ZOMBIE 0x2
8072
8073
8074/***********************************/
8075/* MC_CMD_SETUP_8021QBB
8076 * 802.1Qbb control. 8 Tx queues that map to priorities 0 - 7. Use all 1s to
8077 * disable 802.Qbb for a given priority.
8078 */
8079#define MC_CMD_SETUP_8021QBB 0x44
8080
8081/* MC_CMD_SETUP_8021QBB_IN msgrequest */
8082#define MC_CMD_SETUP_8021QBB_IN_LEN 32
8083#define MC_CMD_SETUP_8021QBB_IN_TXQS_OFST 0
8084#define MC_CMD_SETUP_8021QBB_IN_TXQS_LEN 32
8085
8086/* MC_CMD_SETUP_8021QBB_OUT msgresponse */
8087#define MC_CMD_SETUP_8021QBB_OUT_LEN 0
8088
8089
8090/***********************************/
8091/* MC_CMD_WOL_FILTER_GET
8092 * Retrieve ID of any WoL filters. Locks required: None. Returns: 0, ENOSYS
8093 */
8094#define MC_CMD_WOL_FILTER_GET 0x45
8095#undef MC_CMD_0x45_PRIVILEGE_CTG
8096
8097#define MC_CMD_0x45_PRIVILEGE_CTG SRIOV_CTG_LINK
8098
8099/* MC_CMD_WOL_FILTER_GET_IN msgrequest */
8100#define MC_CMD_WOL_FILTER_GET_IN_LEN 0
8101
8102/* MC_CMD_WOL_FILTER_GET_OUT msgresponse */
8103#define MC_CMD_WOL_FILTER_GET_OUT_LEN 4
8104#define MC_CMD_WOL_FILTER_GET_OUT_FILTER_ID_OFST 0
8105#define MC_CMD_WOL_FILTER_GET_OUT_FILTER_ID_LEN 4
8106
8107
8108/***********************************/
8109/* MC_CMD_ADD_LIGHTSOUT_OFFLOAD
8110 * Add a protocol offload to NIC for lights-out state. Locks required: None.
8111 * Returns: 0, ENOSYS
8112 */
8113#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD 0x46
8114#undef MC_CMD_0x46_PRIVILEGE_CTG
8115
8116#define MC_CMD_0x46_PRIVILEGE_CTG SRIOV_CTG_LINK
8117
8118/* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN msgrequest */
8119#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMIN 8
8120#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMAX 252
8121#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMAX_MCDI2 1020
8122#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LEN(num) (4+4*(num))
8123#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_NUM(len) (((len)-4)/4)
8124#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0
8125#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 4
8126#define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_ARP 0x1 /* enum */
8127#define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_NS 0x2 /* enum */
8128#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_OFST 4
8129#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_LEN 4
8130#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MINNUM 1
8131#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MAXNUM 62
8132#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MAXNUM_MCDI2 254
8133
8134/* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP msgrequest */
8135#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_LEN 14
8136/* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */
8137/* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 4 */
8138#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_OFST 4
8139#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_LEN 6
8140#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_IP_OFST 10
8141#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_IP_LEN 4
8142
8143/* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS msgrequest */
8144#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_LEN 42
8145/* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */
8146/* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 4 */
8147#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_OFST 4
8148#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_LEN 6
8149#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_OFST 10
8150#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_LEN 16
8151#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_OFST 26
8152#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_LEN 16
8153
8154/* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT msgresponse */
8155#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_LEN 4
8156#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_FILTER_ID_OFST 0
8157#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_FILTER_ID_LEN 4
8158
8159
8160/***********************************/
8161/* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD
8162 * Remove a protocol offload from NIC for lights-out state. Locks required:
8163 * None. Returns: 0, ENOSYS
8164 */
8165#define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD 0x47
8166#undef MC_CMD_0x47_PRIVILEGE_CTG
8167
8168#define MC_CMD_0x47_PRIVILEGE_CTG SRIOV_CTG_LINK
8169
8170/* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN msgrequest */
8171#define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_LEN 8
8172#define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0
8173#define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 4
8174#define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_FILTER_ID_OFST 4
8175#define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_FILTER_ID_LEN 4
8176
8177/* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT msgresponse */
8178#define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT_LEN 0
8179
8180
8181/***********************************/
8182/* MC_CMD_MAC_RESET_RESTORE
8183 * Restore MAC after block reset. Locks required: None. Returns: 0.
8184 */
8185#define MC_CMD_MAC_RESET_RESTORE 0x48
8186
8187/* MC_CMD_MAC_RESET_RESTORE_IN msgrequest */
8188#define MC_CMD_MAC_RESET_RESTORE_IN_LEN 0
8189
8190/* MC_CMD_MAC_RESET_RESTORE_OUT msgresponse */
8191#define MC_CMD_MAC_RESET_RESTORE_OUT_LEN 0
8192
8193
8194/***********************************/
8195/* MC_CMD_TESTASSERT
8196 * Deliberately trigger an assert-detonation in the firmware for testing
8197 * purposes (i.e. to allow tests that the driver copes gracefully). Locks
8198 * required: None Returns: 0
8199 */
8200#define MC_CMD_TESTASSERT 0x49
8201#undef MC_CMD_0x49_PRIVILEGE_CTG
8202
8203#define MC_CMD_0x49_PRIVILEGE_CTG SRIOV_CTG_ADMIN
8204
8205/* MC_CMD_TESTASSERT_IN msgrequest */
8206#define MC_CMD_TESTASSERT_IN_LEN 0
8207
8208/* MC_CMD_TESTASSERT_OUT msgresponse */
8209#define MC_CMD_TESTASSERT_OUT_LEN 0
8210
8211/* MC_CMD_TESTASSERT_V2_IN msgrequest */
8212#define MC_CMD_TESTASSERT_V2_IN_LEN 4
8213/* How to provoke the assertion */
8214#define MC_CMD_TESTASSERT_V2_IN_TYPE_OFST 0
8215#define MC_CMD_TESTASSERT_V2_IN_TYPE_LEN 4
8216/* enum: Assert using the FAIL_ASSERTION_WITH_USEFUL_VALUES macro. Unless
8217 * you're testing firmware, this is what you want.
8218 */
8219#define MC_CMD_TESTASSERT_V2_IN_FAIL_ASSERTION_WITH_USEFUL_VALUES 0x0
8220/* enum: Assert using assert(0); */
8221#define MC_CMD_TESTASSERT_V2_IN_ASSERT_FALSE 0x1
8222/* enum: Deliberately trigger a watchdog */
8223#define MC_CMD_TESTASSERT_V2_IN_WATCHDOG 0x2
8224/* enum: Deliberately trigger a trap by loading from an invalid address */
8225#define MC_CMD_TESTASSERT_V2_IN_LOAD_TRAP 0x3
8226/* enum: Deliberately trigger a trap by storing to an invalid address */
8227#define MC_CMD_TESTASSERT_V2_IN_STORE_TRAP 0x4
8228/* enum: Jump to an invalid address */
8229#define MC_CMD_TESTASSERT_V2_IN_JUMP_TRAP 0x5
8230
8231/* MC_CMD_TESTASSERT_V2_OUT msgresponse */
8232#define MC_CMD_TESTASSERT_V2_OUT_LEN 0
8233
8234
8235/***********************************/
8236/* MC_CMD_WORKAROUND
8237 * Enable/Disable a given workaround. The mcfw will return EINVAL if it doesn't
8238 * understand the given workaround number - which should not be treated as a
8239 * hard error by client code. This op does not imply any semantics about each
8240 * workaround, that's between the driver and the mcfw on a per-workaround
8241 * basis. Locks required: None. Returns: 0, EINVAL .
8242 */
8243#define MC_CMD_WORKAROUND 0x4a
8244#undef MC_CMD_0x4a_PRIVILEGE_CTG
8245
8246#define MC_CMD_0x4a_PRIVILEGE_CTG SRIOV_CTG_ADMIN
8247
8248/* MC_CMD_WORKAROUND_IN msgrequest */
8249#define MC_CMD_WORKAROUND_IN_LEN 8
8250/* The enums here must correspond with those in MC_CMD_GET_WORKAROUND. */
8251#define MC_CMD_WORKAROUND_IN_TYPE_OFST 0
8252#define MC_CMD_WORKAROUND_IN_TYPE_LEN 4
8253/* enum: Bug 17230 work around. */
8254#define MC_CMD_WORKAROUND_BUG17230 0x1
8255/* enum: Bug 35388 work around (unsafe EVQ writes). */
8256#define MC_CMD_WORKAROUND_BUG35388 0x2
8257/* enum: Bug35017 workaround (A64 tables must be identity map) */
8258#define MC_CMD_WORKAROUND_BUG35017 0x3
8259/* enum: Bug 41750 present (MC_CMD_TRIGGER_INTERRUPT won't work) */
8260#define MC_CMD_WORKAROUND_BUG41750 0x4
8261/* enum: Bug 42008 present (Interrupts can overtake associated events). Caution
8262 * - before adding code that queries this workaround, remember that there's
8263 * released Monza firmware that doesn't understand MC_CMD_WORKAROUND_BUG42008,
8264 * and will hence (incorrectly) report that the bug doesn't exist.
8265 */
8266#define MC_CMD_WORKAROUND_BUG42008 0x5
8267/* enum: Bug 26807 features present in firmware (multicast filter chaining)
8268 * This feature cannot be turned on/off while there are any filters already
8269 * present. The behaviour in such case depends on the acting client's privilege
8270 * level. If the client has the admin privilege, then all functions that have
8271 * filters installed will be FLRed and the FLR_DONE flag will be set. Otherwise
8272 * the command will fail with MC_CMD_ERR_FILTERS_PRESENT.
8273 */
8274#define MC_CMD_WORKAROUND_BUG26807 0x6
8275/* enum: Bug 61265 work around (broken EVQ TMR writes). */
8276#define MC_CMD_WORKAROUND_BUG61265 0x7
8277/* 0 = disable the workaround indicated by TYPE; any non-zero value = enable
8278 * the workaround
8279 */
8280#define MC_CMD_WORKAROUND_IN_ENABLED_OFST 4
8281#define MC_CMD_WORKAROUND_IN_ENABLED_LEN 4
8282
8283/* MC_CMD_WORKAROUND_OUT msgresponse */
8284#define MC_CMD_WORKAROUND_OUT_LEN 0
8285
8286/* MC_CMD_WORKAROUND_EXT_OUT msgresponse: This response format will be used
8287 * when (TYPE == MC_CMD_WORKAROUND_BUG26807)
8288 */
8289#define MC_CMD_WORKAROUND_EXT_OUT_LEN 4
8290#define MC_CMD_WORKAROUND_EXT_OUT_FLAGS_OFST 0
8291#define MC_CMD_WORKAROUND_EXT_OUT_FLAGS_LEN 4
8292#define MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_OFST 0
8293#define MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN 0
8294#define MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_WIDTH 1
8295
8296
8297/***********************************/
8298/* MC_CMD_GET_PHY_MEDIA_INFO
8299 * Read media-specific data from PHY (e.g. SFP/SFP+ module ID information for
8300 * SFP+ PHYs). The "media type" can be found via GET_PHY_CFG
8301 * (GET_PHY_CFG_OUT_MEDIA_TYPE); the valid "page number" input values, and the
8302 * output data, are interpreted on a per-type basis. For SFP+, PAGE=0 or 1
8303 * returns a 128-byte block read from module I2C address 0xA0 offset 0 or 0x80.
8304 * For QSFP, PAGE=-1 is the lower (unbanked) page. PAGE=2 is the EEPROM and
8305 * PAGE=3 is the module limits. For DSFP, module addressing requires a
8306 * "BANK:PAGE". Not every bank has the same number of pages. See the Common
8307 * Management Interface Specification (CMIS) for further details. A BANK:PAGE
8308 * of "0xffff:0xffff" retrieves the lower (unbanked) page. Locks required -
8309 * None. Return code - 0.
8310 */
8311#define MC_CMD_GET_PHY_MEDIA_INFO 0x4b
8312#undef MC_CMD_0x4b_PRIVILEGE_CTG
8313
8314#define MC_CMD_0x4b_PRIVILEGE_CTG SRIOV_CTG_ADMIN
8315
8316/* MC_CMD_GET_PHY_MEDIA_INFO_IN msgrequest */
8317#define MC_CMD_GET_PHY_MEDIA_INFO_IN_LEN 4
8318#define MC_CMD_GET_PHY_MEDIA_INFO_IN_PAGE_OFST 0
8319#define MC_CMD_GET_PHY_MEDIA_INFO_IN_PAGE_LEN 4
8320#define MC_CMD_GET_PHY_MEDIA_INFO_IN_DSFP_PAGE_OFST 0
8321#define MC_CMD_GET_PHY_MEDIA_INFO_IN_DSFP_PAGE_LBN 0
8322#define MC_CMD_GET_PHY_MEDIA_INFO_IN_DSFP_PAGE_WIDTH 16
8323#define MC_CMD_GET_PHY_MEDIA_INFO_IN_DSFP_BANK_OFST 0
8324#define MC_CMD_GET_PHY_MEDIA_INFO_IN_DSFP_BANK_LBN 16
8325#define MC_CMD_GET_PHY_MEDIA_INFO_IN_DSFP_BANK_WIDTH 16
8326
8327/* MC_CMD_GET_PHY_MEDIA_INFO_OUT msgresponse */
8328#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMIN 5
8329#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMAX 252
8330#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMAX_MCDI2 1020
8331#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LEN(num) (4+1*(num))
8332#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_NUM(len) (((len)-4)/1)
8333/* in bytes */
8334#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATALEN_OFST 0
8335#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATALEN_LEN 4
8336#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_OFST 4
8337#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_LEN 1
8338#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MINNUM 1
8339#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MAXNUM 248
8340#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MAXNUM_MCDI2 1016
8341
8342
8343/***********************************/
8344/* MC_CMD_NVRAM_TEST
8345 * Test a particular NVRAM partition for valid contents (where "valid" depends
8346 * on the type of partition).
8347 */
8348#define MC_CMD_NVRAM_TEST 0x4c
8349#undef MC_CMD_0x4c_PRIVILEGE_CTG
8350
8351#define MC_CMD_0x4c_PRIVILEGE_CTG SRIOV_CTG_ADMIN
8352
8353/* MC_CMD_NVRAM_TEST_IN msgrequest */
8354#define MC_CMD_NVRAM_TEST_IN_LEN 4
8355#define MC_CMD_NVRAM_TEST_IN_TYPE_OFST 0
8356#define MC_CMD_NVRAM_TEST_IN_TYPE_LEN 4
8357/* Enum values, see field(s): */
8358/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
8359
8360/* MC_CMD_NVRAM_TEST_OUT msgresponse */
8361#define MC_CMD_NVRAM_TEST_OUT_LEN 4
8362#define MC_CMD_NVRAM_TEST_OUT_RESULT_OFST 0
8363#define MC_CMD_NVRAM_TEST_OUT_RESULT_LEN 4
8364/* enum: Passed. */
8365#define MC_CMD_NVRAM_TEST_PASS 0x0
8366/* enum: Failed. */
8367#define MC_CMD_NVRAM_TEST_FAIL 0x1
8368/* enum: Not supported. */
8369#define MC_CMD_NVRAM_TEST_NOTSUPP 0x2
8370
8371
8372/***********************************/
8373/* MC_CMD_MRSFP_TWEAK
8374 * Read status and/or set parameters for the 'mrsfp' driver in mr_rusty builds.
8375 * I2C I/O expander bits are always read; if equaliser parameters are supplied,
8376 * they are configured first. Locks required: None. Return code: 0, EINVAL.
8377 */
8378#define MC_CMD_MRSFP_TWEAK 0x4d
8379
8380/* MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG msgrequest */
8381#define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_LEN 16
8382/* 0-6 low->high de-emph. */
8383#define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_LEVEL_OFST 0
8384#define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_LEVEL_LEN 4
8385/* 0-8 low->high ref.V */
8386#define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_DT_CFG_OFST 4
8387#define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_DT_CFG_LEN 4
8388/* 0-8 0-8 low->high boost */
8389#define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_BOOST_OFST 8
8390#define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_BOOST_LEN 4
8391/* 0-8 low->high ref.V */
8392#define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_DT_CFG_OFST 12
8393#define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_DT_CFG_LEN 4
8394
8395/* MC_CMD_MRSFP_TWEAK_IN_READ_ONLY msgrequest */
8396#define MC_CMD_MRSFP_TWEAK_IN_READ_ONLY_LEN 0
8397
8398/* MC_CMD_MRSFP_TWEAK_OUT msgresponse */
8399#define MC_CMD_MRSFP_TWEAK_OUT_LEN 12
8400/* input bits */
8401#define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_INPUTS_OFST 0
8402#define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_INPUTS_LEN 4
8403/* output bits */
8404#define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_OUTPUTS_OFST 4
8405#define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_OUTPUTS_LEN 4
8406/* direction */
8407#define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OFST 8
8408#define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_LEN 4
8409/* enum: Out. */
8410#define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OUT 0x0
8411/* enum: In. */
8412#define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_IN 0x1
8413
8414
8415/***********************************/
8416/* MC_CMD_SENSOR_SET_LIMS
8417 * Adjusts the sensor limits. This is a warranty-voiding operation. Returns:
8418 * ENOENT if the sensor specified does not exist, EINVAL if the limits are out
8419 * of range.
8420 */
8421#define MC_CMD_SENSOR_SET_LIMS 0x4e
8422#undef MC_CMD_0x4e_PRIVILEGE_CTG
8423
8424#define MC_CMD_0x4e_PRIVILEGE_CTG SRIOV_CTG_INSECURE
8425
8426/* MC_CMD_SENSOR_SET_LIMS_IN msgrequest */
8427#define MC_CMD_SENSOR_SET_LIMS_IN_LEN 20
8428#define MC_CMD_SENSOR_SET_LIMS_IN_SENSOR_OFST 0
8429#define MC_CMD_SENSOR_SET_LIMS_IN_SENSOR_LEN 4
8430/* Enum values, see field(s): */
8431/* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */
8432/* interpretation is is sensor-specific. */
8433#define MC_CMD_SENSOR_SET_LIMS_IN_LOW0_OFST 4
8434#define MC_CMD_SENSOR_SET_LIMS_IN_LOW0_LEN 4
8435/* interpretation is is sensor-specific. */
8436#define MC_CMD_SENSOR_SET_LIMS_IN_HI0_OFST 8
8437#define MC_CMD_SENSOR_SET_LIMS_IN_HI0_LEN 4
8438/* interpretation is is sensor-specific. */
8439#define MC_CMD_SENSOR_SET_LIMS_IN_LOW1_OFST 12
8440#define MC_CMD_SENSOR_SET_LIMS_IN_LOW1_LEN 4
8441/* interpretation is is sensor-specific. */
8442#define MC_CMD_SENSOR_SET_LIMS_IN_HI1_OFST 16
8443#define MC_CMD_SENSOR_SET_LIMS_IN_HI1_LEN 4
8444
8445/* MC_CMD_SENSOR_SET_LIMS_OUT msgresponse */
8446#define MC_CMD_SENSOR_SET_LIMS_OUT_LEN 0
8447
8448
8449/***********************************/
8450/* MC_CMD_GET_RESOURCE_LIMITS
8451 */
8452#define MC_CMD_GET_RESOURCE_LIMITS 0x4f
8453
8454/* MC_CMD_GET_RESOURCE_LIMITS_IN msgrequest */
8455#define MC_CMD_GET_RESOURCE_LIMITS_IN_LEN 0
8456
8457/* MC_CMD_GET_RESOURCE_LIMITS_OUT msgresponse */
8458#define MC_CMD_GET_RESOURCE_LIMITS_OUT_LEN 16
8459#define MC_CMD_GET_RESOURCE_LIMITS_OUT_BUFTBL_OFST 0
8460#define MC_CMD_GET_RESOURCE_LIMITS_OUT_BUFTBL_LEN 4
8461#define MC_CMD_GET_RESOURCE_LIMITS_OUT_EVQ_OFST 4
8462#define MC_CMD_GET_RESOURCE_LIMITS_OUT_EVQ_LEN 4
8463#define MC_CMD_GET_RESOURCE_LIMITS_OUT_RXQ_OFST 8
8464#define MC_CMD_GET_RESOURCE_LIMITS_OUT_RXQ_LEN 4
8465#define MC_CMD_GET_RESOURCE_LIMITS_OUT_TXQ_OFST 12
8466#define MC_CMD_GET_RESOURCE_LIMITS_OUT_TXQ_LEN 4
8467
8468
8469/***********************************/
8470/* MC_CMD_NVRAM_PARTITIONS
8471 * Reads the list of available virtual NVRAM partition types. Locks required:
8472 * none. Returns: 0, EINVAL (bad type).
8473 */
8474#define MC_CMD_NVRAM_PARTITIONS 0x51
8475#undef MC_CMD_0x51_PRIVILEGE_CTG
8476
8477#define MC_CMD_0x51_PRIVILEGE_CTG SRIOV_CTG_ADMIN
8478
8479/* MC_CMD_NVRAM_PARTITIONS_IN msgrequest */
8480#define MC_CMD_NVRAM_PARTITIONS_IN_LEN 0
8481
8482/* MC_CMD_NVRAM_PARTITIONS_OUT msgresponse */
8483#define MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN 4
8484#define MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX 252
8485#define MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX_MCDI2 1020
8486#define MC_CMD_NVRAM_PARTITIONS_OUT_LEN(num) (4+4*(num))
8487#define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_NUM(len) (((len)-4)/4)
8488/* total number of partitions */
8489#define MC_CMD_NVRAM_PARTITIONS_OUT_NUM_PARTITIONS_OFST 0
8490#define MC_CMD_NVRAM_PARTITIONS_OUT_NUM_PARTITIONS_LEN 4
8491/* type ID code for each of NUM_PARTITIONS partitions */
8492#define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_OFST 4
8493#define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_LEN 4
8494#define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MINNUM 0
8495#define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MAXNUM 62
8496#define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MAXNUM_MCDI2 254
8497
8498
8499/***********************************/
8500/* MC_CMD_NVRAM_METADATA
8501 * Reads soft metadata for a virtual NVRAM partition type. Locks required:
8502 * none. Returns: 0, EINVAL (bad type).
8503 */
8504#define MC_CMD_NVRAM_METADATA 0x52
8505#undef MC_CMD_0x52_PRIVILEGE_CTG
8506
8507#define MC_CMD_0x52_PRIVILEGE_CTG SRIOV_CTG_ADMIN
8508
8509/* MC_CMD_NVRAM_METADATA_IN msgrequest */
8510#define MC_CMD_NVRAM_METADATA_IN_LEN 4
8511/* Partition type ID code */
8512#define MC_CMD_NVRAM_METADATA_IN_TYPE_OFST 0
8513#define MC_CMD_NVRAM_METADATA_IN_TYPE_LEN 4
8514
8515/* MC_CMD_NVRAM_METADATA_OUT msgresponse */
8516#define MC_CMD_NVRAM_METADATA_OUT_LENMIN 20
8517#define MC_CMD_NVRAM_METADATA_OUT_LENMAX 252
8518#define MC_CMD_NVRAM_METADATA_OUT_LENMAX_MCDI2 1020
8519#define MC_CMD_NVRAM_METADATA_OUT_LEN(num) (20+1*(num))
8520#define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_NUM(len) (((len)-20)/1)
8521/* Partition type ID code */
8522#define MC_CMD_NVRAM_METADATA_OUT_TYPE_OFST 0
8523#define MC_CMD_NVRAM_METADATA_OUT_TYPE_LEN 4
8524#define MC_CMD_NVRAM_METADATA_OUT_FLAGS_OFST 4
8525#define MC_CMD_NVRAM_METADATA_OUT_FLAGS_LEN 4
8526#define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_OFST 4
8527#define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN 0
8528#define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_WIDTH 1
8529#define MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_OFST 4
8530#define MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_LBN 1
8531#define MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_WIDTH 1
8532#define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_OFST 4
8533#define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_LBN 2
8534#define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_WIDTH 1
8535/* Subtype ID code for content of this partition */
8536#define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_OFST 8
8537#define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_LEN 4
8538/* 1st component of W.X.Y.Z version number for content of this partition */
8539#define MC_CMD_NVRAM_METADATA_OUT_VERSION_W_OFST 12
8540#define MC_CMD_NVRAM_METADATA_OUT_VERSION_W_LEN 2
8541/* 2nd component of W.X.Y.Z version number for content of this partition */
8542#define MC_CMD_NVRAM_METADATA_OUT_VERSION_X_OFST 14
8543#define MC_CMD_NVRAM_METADATA_OUT_VERSION_X_LEN 2
8544/* 3rd component of W.X.Y.Z version number for content of this partition */
8545#define MC_CMD_NVRAM_METADATA_OUT_VERSION_Y_OFST 16
8546#define MC_CMD_NVRAM_METADATA_OUT_VERSION_Y_LEN 2
8547/* 4th component of W.X.Y.Z version number for content of this partition */
8548#define MC_CMD_NVRAM_METADATA_OUT_VERSION_Z_OFST 18
8549#define MC_CMD_NVRAM_METADATA_OUT_VERSION_Z_LEN 2
8550/* Zero-terminated string describing the content of this partition */
8551#define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_OFST 20
8552#define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_LEN 1
8553#define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MINNUM 0
8554#define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MAXNUM 232
8555#define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MAXNUM_MCDI2 1000
8556
8557
8558/***********************************/
8559/* MC_CMD_GET_MAC_ADDRESSES
8560 * Returns the base MAC, count and stride for the requesting function
8561 */
8562#define MC_CMD_GET_MAC_ADDRESSES 0x55
8563#undef MC_CMD_0x55_PRIVILEGE_CTG
8564
8565#define MC_CMD_0x55_PRIVILEGE_CTG SRIOV_CTG_GENERAL
8566
8567/* MC_CMD_GET_MAC_ADDRESSES_IN msgrequest */
8568#define MC_CMD_GET_MAC_ADDRESSES_IN_LEN 0
8569
8570/* MC_CMD_GET_MAC_ADDRESSES_OUT msgresponse */
8571#define MC_CMD_GET_MAC_ADDRESSES_OUT_LEN 16
8572/* Base MAC address */
8573#define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE_OFST 0
8574#define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE_LEN 6
8575/* Padding */
8576#define MC_CMD_GET_MAC_ADDRESSES_OUT_RESERVED_OFST 6
8577#define MC_CMD_GET_MAC_ADDRESSES_OUT_RESERVED_LEN 2
8578/* Number of allocated MAC addresses */
8579#define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_COUNT_OFST 8
8580#define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_COUNT_LEN 4
8581/* Spacing of allocated MAC addresses */
8582#define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_STRIDE_OFST 12
8583#define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_STRIDE_LEN 4
8584
8585
8586/***********************************/
8587/* MC_CMD_CLP
8588 * Perform a CLP related operation, see SF-110495-PS for details of CLP
8589 * processing. This command has been extended to accomodate the requirements of
8590 * different manufacturers which are to be found in SF-119187-TC, SF-119186-TC,
8591 * SF-120509-TC and SF-117282-PS.
8592 */
8593#define MC_CMD_CLP 0x56
8594#undef MC_CMD_0x56_PRIVILEGE_CTG
8595
8596#define MC_CMD_0x56_PRIVILEGE_CTG SRIOV_CTG_ADMIN
8597
8598/* MC_CMD_CLP_IN msgrequest */
8599#define MC_CMD_CLP_IN_LEN 4
8600/* Sub operation */
8601#define MC_CMD_CLP_IN_OP_OFST 0
8602#define MC_CMD_CLP_IN_OP_LEN 4
8603/* enum: Return to factory default settings */
8604#define MC_CMD_CLP_OP_DEFAULT 0x1
8605/* enum: Set MAC address */
8606#define MC_CMD_CLP_OP_SET_MAC 0x2
8607/* enum: Get MAC address */
8608#define MC_CMD_CLP_OP_GET_MAC 0x3
8609/* enum: Set UEFI/GPXE boot mode */
8610#define MC_CMD_CLP_OP_SET_BOOT 0x4
8611/* enum: Get UEFI/GPXE boot mode */
8612#define MC_CMD_CLP_OP_GET_BOOT 0x5
8613
8614/* MC_CMD_CLP_OUT msgresponse */
8615#define MC_CMD_CLP_OUT_LEN 0
8616
8617/* MC_CMD_CLP_IN_DEFAULT msgrequest */
8618#define MC_CMD_CLP_IN_DEFAULT_LEN 4
8619/* MC_CMD_CLP_IN_OP_OFST 0 */
8620/* MC_CMD_CLP_IN_OP_LEN 4 */
8621
8622/* MC_CMD_CLP_OUT_DEFAULT msgresponse */
8623#define MC_CMD_CLP_OUT_DEFAULT_LEN 0
8624
8625/* MC_CMD_CLP_IN_SET_MAC msgrequest */
8626#define MC_CMD_CLP_IN_SET_MAC_LEN 12
8627/* MC_CMD_CLP_IN_OP_OFST 0 */
8628/* MC_CMD_CLP_IN_OP_LEN 4 */
8629/* The MAC address assigned to port. A zero MAC address of 00:00:00:00:00:00
8630 * restores the permanent (factory-programmed) MAC address associated with the
8631 * port. A non-zero MAC address persists until a PCIe reset or a power cycle.
8632 */
8633#define MC_CMD_CLP_IN_SET_MAC_ADDR_OFST 4
8634#define MC_CMD_CLP_IN_SET_MAC_ADDR_LEN 6
8635/* Padding */
8636#define MC_CMD_CLP_IN_SET_MAC_RESERVED_OFST 10
8637#define MC_CMD_CLP_IN_SET_MAC_RESERVED_LEN 2
8638
8639/* MC_CMD_CLP_OUT_SET_MAC msgresponse */
8640#define MC_CMD_CLP_OUT_SET_MAC_LEN 0
8641
8642/* MC_CMD_CLP_IN_SET_MAC_V2 msgrequest */
8643#define MC_CMD_CLP_IN_SET_MAC_V2_LEN 16
8644/* MC_CMD_CLP_IN_OP_OFST 0 */
8645/* MC_CMD_CLP_IN_OP_LEN 4 */
8646/* The MAC address assigned to port. A zero MAC address of 00:00:00:00:00:00
8647 * restores the permanent (factory-programmed) MAC address associated with the
8648 * port. A non-zero MAC address persists until a PCIe reset or a power cycle.
8649 */
8650#define MC_CMD_CLP_IN_SET_MAC_V2_ADDR_OFST 4
8651#define MC_CMD_CLP_IN_SET_MAC_V2_ADDR_LEN 6
8652/* Padding */
8653#define MC_CMD_CLP_IN_SET_MAC_V2_RESERVED_OFST 10
8654#define MC_CMD_CLP_IN_SET_MAC_V2_RESERVED_LEN 2
8655#define MC_CMD_CLP_IN_SET_MAC_V2_FLAGS_OFST 12
8656#define MC_CMD_CLP_IN_SET_MAC_V2_FLAGS_LEN 4
8657#define MC_CMD_CLP_IN_SET_MAC_V2_VIRTUAL_OFST 12
8658#define MC_CMD_CLP_IN_SET_MAC_V2_VIRTUAL_LBN 0
8659#define MC_CMD_CLP_IN_SET_MAC_V2_VIRTUAL_WIDTH 1
8660
8661/* MC_CMD_CLP_IN_GET_MAC msgrequest */
8662#define MC_CMD_CLP_IN_GET_MAC_LEN 4
8663/* MC_CMD_CLP_IN_OP_OFST 0 */
8664/* MC_CMD_CLP_IN_OP_LEN 4 */
8665
8666/* MC_CMD_CLP_IN_GET_MAC_V2 msgrequest */
8667#define MC_CMD_CLP_IN_GET_MAC_V2_LEN 8
8668/* MC_CMD_CLP_IN_OP_OFST 0 */
8669/* MC_CMD_CLP_IN_OP_LEN 4 */
8670#define MC_CMD_CLP_IN_GET_MAC_V2_FLAGS_OFST 4
8671#define MC_CMD_CLP_IN_GET_MAC_V2_FLAGS_LEN 4
8672#define MC_CMD_CLP_IN_GET_MAC_V2_PERMANENT_OFST 4
8673#define MC_CMD_CLP_IN_GET_MAC_V2_PERMANENT_LBN 0
8674#define MC_CMD_CLP_IN_GET_MAC_V2_PERMANENT_WIDTH 1
8675
8676/* MC_CMD_CLP_OUT_GET_MAC msgresponse */
8677#define MC_CMD_CLP_OUT_GET_MAC_LEN 8
8678/* MAC address assigned to port */
8679#define MC_CMD_CLP_OUT_GET_MAC_ADDR_OFST 0
8680#define MC_CMD_CLP_OUT_GET_MAC_ADDR_LEN 6
8681/* Padding */
8682#define MC_CMD_CLP_OUT_GET_MAC_RESERVED_OFST 6
8683#define MC_CMD_CLP_OUT_GET_MAC_RESERVED_LEN 2
8684
8685/* MC_CMD_CLP_IN_SET_BOOT msgrequest */
8686#define MC_CMD_CLP_IN_SET_BOOT_LEN 5
8687/* MC_CMD_CLP_IN_OP_OFST 0 */
8688/* MC_CMD_CLP_IN_OP_LEN 4 */
8689/* Boot flag */
8690#define MC_CMD_CLP_IN_SET_BOOT_FLAG_OFST 4
8691#define MC_CMD_CLP_IN_SET_BOOT_FLAG_LEN 1
8692
8693/* MC_CMD_CLP_OUT_SET_BOOT msgresponse */
8694#define MC_CMD_CLP_OUT_SET_BOOT_LEN 0
8695
8696/* MC_CMD_CLP_IN_GET_BOOT msgrequest */
8697#define MC_CMD_CLP_IN_GET_BOOT_LEN 4
8698/* MC_CMD_CLP_IN_OP_OFST 0 */
8699/* MC_CMD_CLP_IN_OP_LEN 4 */
8700
8701/* MC_CMD_CLP_OUT_GET_BOOT msgresponse */
8702#define MC_CMD_CLP_OUT_GET_BOOT_LEN 4
8703/* Boot flag */
8704#define MC_CMD_CLP_OUT_GET_BOOT_FLAG_OFST 0
8705#define MC_CMD_CLP_OUT_GET_BOOT_FLAG_LEN 1
8706/* Padding */
8707#define MC_CMD_CLP_OUT_GET_BOOT_RESERVED_OFST 1
8708#define MC_CMD_CLP_OUT_GET_BOOT_RESERVED_LEN 3
8709
8710
8711/***********************************/
8712/* MC_CMD_MUM
8713 * Perform a MUM operation
8714 */
8715#define MC_CMD_MUM 0x57
8716#undef MC_CMD_0x57_PRIVILEGE_CTG
8717
8718#define MC_CMD_0x57_PRIVILEGE_CTG SRIOV_CTG_INSECURE
8719
8720/* MC_CMD_MUM_IN msgrequest */
8721#define MC_CMD_MUM_IN_LEN 4
8722#define MC_CMD_MUM_IN_OP_HDR_OFST 0
8723#define MC_CMD_MUM_IN_OP_HDR_LEN 4
8724#define MC_CMD_MUM_IN_OP_OFST 0
8725#define MC_CMD_MUM_IN_OP_LBN 0
8726#define MC_CMD_MUM_IN_OP_WIDTH 8
8727/* enum: NULL MCDI command to MUM */
8728#define MC_CMD_MUM_OP_NULL 0x1
8729/* enum: Get MUM version */
8730#define MC_CMD_MUM_OP_GET_VERSION 0x2
8731/* enum: Issue raw I2C command to MUM */
8732#define MC_CMD_MUM_OP_RAW_CMD 0x3
8733/* enum: Read from registers on devices connected to MUM. */
8734#define MC_CMD_MUM_OP_READ 0x4
8735/* enum: Write to registers on devices connected to MUM. */
8736#define MC_CMD_MUM_OP_WRITE 0x5
8737/* enum: Control UART logging. */
8738#define MC_CMD_MUM_OP_LOG 0x6
8739/* enum: Operations on MUM GPIO lines */
8740#define MC_CMD_MUM_OP_GPIO 0x7
8741/* enum: Get sensor readings from MUM */
8742#define MC_CMD_MUM_OP_READ_SENSORS 0x8
8743/* enum: Initiate clock programming on the MUM */
8744#define MC_CMD_MUM_OP_PROGRAM_CLOCKS 0x9
8745/* enum: Initiate FPGA load from flash on the MUM */
8746#define MC_CMD_MUM_OP_FPGA_LOAD 0xa
8747/* enum: Request sensor reading from MUM ADC resulting from earlier request via
8748 * MUM ATB
8749 */
8750#define MC_CMD_MUM_OP_READ_ATB_SENSOR 0xb
8751/* enum: Send commands relating to the QSFP ports via the MUM for PHY
8752 * operations
8753 */
8754#define MC_CMD_MUM_OP_QSFP 0xc
8755/* enum: Request discrete and SODIMM DDR info (type, size, speed grade, voltage
8756 * level) from MUM
8757 */
8758#define MC_CMD_MUM_OP_READ_DDR_INFO 0xd
8759
8760/* MC_CMD_MUM_IN_NULL msgrequest */
8761#define MC_CMD_MUM_IN_NULL_LEN 4
8762/* MUM cmd header */
8763#define MC_CMD_MUM_IN_CMD_OFST 0
8764#define MC_CMD_MUM_IN_CMD_LEN 4
8765
8766/* MC_CMD_MUM_IN_GET_VERSION msgrequest */
8767#define MC_CMD_MUM_IN_GET_VERSION_LEN 4
8768/* MUM cmd header */
8769/* MC_CMD_MUM_IN_CMD_OFST 0 */
8770/* MC_CMD_MUM_IN_CMD_LEN 4 */
8771
8772/* MC_CMD_MUM_IN_READ msgrequest */
8773#define MC_CMD_MUM_IN_READ_LEN 16
8774/* MUM cmd header */
8775/* MC_CMD_MUM_IN_CMD_OFST 0 */
8776/* MC_CMD_MUM_IN_CMD_LEN 4 */
8777/* ID of (device connected to MUM) to read from registers of */
8778#define MC_CMD_MUM_IN_READ_DEVICE_OFST 4
8779#define MC_CMD_MUM_IN_READ_DEVICE_LEN 4
8780/* enum: Hittite HMC1035 clock generator on Sorrento board */
8781#define MC_CMD_MUM_DEV_HITTITE 0x1
8782/* enum: Hittite HMC1035 clock generator for NIC-side on Sorrento board */
8783#define MC_CMD_MUM_DEV_HITTITE_NIC 0x2
8784/* 32-bit address to read from */
8785#define MC_CMD_MUM_IN_READ_ADDR_OFST 8
8786#define MC_CMD_MUM_IN_READ_ADDR_LEN 4
8787/* Number of words to read. */
8788#define MC_CMD_MUM_IN_READ_NUMWORDS_OFST 12
8789#define MC_CMD_MUM_IN_READ_NUMWORDS_LEN 4
8790
8791/* MC_CMD_MUM_IN_WRITE msgrequest */
8792#define MC_CMD_MUM_IN_WRITE_LENMIN 16
8793#define MC_CMD_MUM_IN_WRITE_LENMAX 252
8794#define MC_CMD_MUM_IN_WRITE_LENMAX_MCDI2 1020
8795#define MC_CMD_MUM_IN_WRITE_LEN(num) (12+4*(num))
8796#define MC_CMD_MUM_IN_WRITE_BUFFER_NUM(len) (((len)-12)/4)
8797/* MUM cmd header */
8798/* MC_CMD_MUM_IN_CMD_OFST 0 */
8799/* MC_CMD_MUM_IN_CMD_LEN 4 */
8800/* ID of (device connected to MUM) to write to registers of */
8801#define MC_CMD_MUM_IN_WRITE_DEVICE_OFST 4
8802#define MC_CMD_MUM_IN_WRITE_DEVICE_LEN 4
8803/* enum: Hittite HMC1035 clock generator on Sorrento board */
8804/* MC_CMD_MUM_DEV_HITTITE 0x1 */
8805/* 32-bit address to write to */
8806#define MC_CMD_MUM_IN_WRITE_ADDR_OFST 8
8807#define MC_CMD_MUM_IN_WRITE_ADDR_LEN 4
8808/* Words to write */
8809#define MC_CMD_MUM_IN_WRITE_BUFFER_OFST 12
8810#define MC_CMD_MUM_IN_WRITE_BUFFER_LEN 4
8811#define MC_CMD_MUM_IN_WRITE_BUFFER_MINNUM 1
8812#define MC_CMD_MUM_IN_WRITE_BUFFER_MAXNUM 60
8813#define MC_CMD_MUM_IN_WRITE_BUFFER_MAXNUM_MCDI2 252
8814
8815/* MC_CMD_MUM_IN_RAW_CMD msgrequest */
8816#define MC_CMD_MUM_IN_RAW_CMD_LENMIN 17
8817#define MC_CMD_MUM_IN_RAW_CMD_LENMAX 252
8818#define MC_CMD_MUM_IN_RAW_CMD_LENMAX_MCDI2 1020
8819#define MC_CMD_MUM_IN_RAW_CMD_LEN(num) (16+1*(num))
8820#define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_NUM(len) (((len)-16)/1)
8821/* MUM cmd header */
8822/* MC_CMD_MUM_IN_CMD_OFST 0 */
8823/* MC_CMD_MUM_IN_CMD_LEN 4 */
8824/* MUM I2C cmd code */
8825#define MC_CMD_MUM_IN_RAW_CMD_CMD_CODE_OFST 4
8826#define MC_CMD_MUM_IN_RAW_CMD_CMD_CODE_LEN 4
8827/* Number of bytes to write */
8828#define MC_CMD_MUM_IN_RAW_CMD_NUM_WRITE_OFST 8
8829#define MC_CMD_MUM_IN_RAW_CMD_NUM_WRITE_LEN 4
8830/* Number of bytes to read */
8831#define MC_CMD_MUM_IN_RAW_CMD_NUM_READ_OFST 12
8832#define MC_CMD_MUM_IN_RAW_CMD_NUM_READ_LEN 4
8833/* Bytes to write */
8834#define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_OFST 16
8835#define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_LEN 1
8836#define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_MINNUM 1
8837#define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_MAXNUM 236
8838#define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_MAXNUM_MCDI2 1004
8839
8840/* MC_CMD_MUM_IN_LOG msgrequest */
8841#define MC_CMD_MUM_IN_LOG_LEN 8
8842/* MUM cmd header */
8843/* MC_CMD_MUM_IN_CMD_OFST 0 */
8844/* MC_CMD_MUM_IN_CMD_LEN 4 */
8845#define MC_CMD_MUM_IN_LOG_OP_OFST 4
8846#define MC_CMD_MUM_IN_LOG_OP_LEN 4
8847#define MC_CMD_MUM_IN_LOG_OP_UART 0x1 /* enum */
8848
8849/* MC_CMD_MUM_IN_LOG_OP_UART msgrequest */
8850#define MC_CMD_MUM_IN_LOG_OP_UART_LEN 12
8851/* MC_CMD_MUM_IN_CMD_OFST 0 */
8852/* MC_CMD_MUM_IN_CMD_LEN 4 */
8853/* MC_CMD_MUM_IN_LOG_OP_OFST 4 */
8854/* MC_CMD_MUM_IN_LOG_OP_LEN 4 */
8855/* Enable/disable debug output to UART */
8856#define MC_CMD_MUM_IN_LOG_OP_UART_ENABLE_OFST 8
8857#define MC_CMD_MUM_IN_LOG_OP_UART_ENABLE_LEN 4
8858
8859/* MC_CMD_MUM_IN_GPIO msgrequest */
8860#define MC_CMD_MUM_IN_GPIO_LEN 8
8861/* MUM cmd header */
8862/* MC_CMD_MUM_IN_CMD_OFST 0 */
8863/* MC_CMD_MUM_IN_CMD_LEN 4 */
8864#define MC_CMD_MUM_IN_GPIO_HDR_OFST 4
8865#define MC_CMD_MUM_IN_GPIO_HDR_LEN 4
8866#define MC_CMD_MUM_IN_GPIO_OPCODE_OFST 4
8867#define MC_CMD_MUM_IN_GPIO_OPCODE_LBN 0
8868#define MC_CMD_MUM_IN_GPIO_OPCODE_WIDTH 8
8869#define MC_CMD_MUM_IN_GPIO_IN_READ 0x0 /* enum */
8870#define MC_CMD_MUM_IN_GPIO_OUT_WRITE 0x1 /* enum */
8871#define MC_CMD_MUM_IN_GPIO_OUT_READ 0x2 /* enum */
8872#define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE 0x3 /* enum */
8873#define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ 0x4 /* enum */
8874#define MC_CMD_MUM_IN_GPIO_OP 0x5 /* enum */
8875
8876/* MC_CMD_MUM_IN_GPIO_IN_READ msgrequest */
8877#define MC_CMD_MUM_IN_GPIO_IN_READ_LEN 8
8878/* MC_CMD_MUM_IN_CMD_OFST 0 */
8879/* MC_CMD_MUM_IN_CMD_LEN 4 */
8880#define MC_CMD_MUM_IN_GPIO_IN_READ_HDR_OFST 4
8881#define MC_CMD_MUM_IN_GPIO_IN_READ_HDR_LEN 4
8882
8883/* MC_CMD_MUM_IN_GPIO_OUT_WRITE msgrequest */
8884#define MC_CMD_MUM_IN_GPIO_OUT_WRITE_LEN 16
8885/* MC_CMD_MUM_IN_CMD_OFST 0 */
8886/* MC_CMD_MUM_IN_CMD_LEN 4 */
8887#define MC_CMD_MUM_IN_GPIO_OUT_WRITE_HDR_OFST 4
8888#define MC_CMD_MUM_IN_GPIO_OUT_WRITE_HDR_LEN 4
8889/* The first 32-bit word to be written to the GPIO OUT register. */
8890#define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK1_OFST 8
8891#define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK1_LEN 4
8892/* The second 32-bit word to be written to the GPIO OUT register. */
8893#define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK2_OFST 12
8894#define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK2_LEN 4
8895
8896/* MC_CMD_MUM_IN_GPIO_OUT_READ msgrequest */
8897#define MC_CMD_MUM_IN_GPIO_OUT_READ_LEN 8
8898/* MC_CMD_MUM_IN_CMD_OFST 0 */
8899/* MC_CMD_MUM_IN_CMD_LEN 4 */
8900#define MC_CMD_MUM_IN_GPIO_OUT_READ_HDR_OFST 4
8901#define MC_CMD_MUM_IN_GPIO_OUT_READ_HDR_LEN 4
8902
8903/* MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE msgrequest */
8904#define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_LEN 16
8905/* MC_CMD_MUM_IN_CMD_OFST 0 */
8906/* MC_CMD_MUM_IN_CMD_LEN 4 */
8907#define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_HDR_OFST 4
8908#define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_HDR_LEN 4
8909/* The first 32-bit word to be written to the GPIO OUT ENABLE register. */
8910#define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK1_OFST 8
8911#define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK1_LEN 4
8912/* The second 32-bit word to be written to the GPIO OUT ENABLE register. */
8913#define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK2_OFST 12
8914#define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK2_LEN 4
8915
8916/* MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ msgrequest */
8917#define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_LEN 8
8918/* MC_CMD_MUM_IN_CMD_OFST 0 */
8919/* MC_CMD_MUM_IN_CMD_LEN 4 */
8920#define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_HDR_OFST 4
8921#define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_HDR_LEN 4
8922
8923/* MC_CMD_MUM_IN_GPIO_OP msgrequest */
8924#define MC_CMD_MUM_IN_GPIO_OP_LEN 8
8925/* MC_CMD_MUM_IN_CMD_OFST 0 */
8926/* MC_CMD_MUM_IN_CMD_LEN 4 */
8927#define MC_CMD_MUM_IN_GPIO_OP_HDR_OFST 4
8928#define MC_CMD_MUM_IN_GPIO_OP_HDR_LEN 4
8929#define MC_CMD_MUM_IN_GPIO_OP_BITWISE_OP_OFST 4
8930#define MC_CMD_MUM_IN_GPIO_OP_BITWISE_OP_LBN 8
8931#define MC_CMD_MUM_IN_GPIO_OP_BITWISE_OP_WIDTH 8
8932#define MC_CMD_MUM_IN_GPIO_OP_OUT_READ 0x0 /* enum */
8933#define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE 0x1 /* enum */
8934#define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG 0x2 /* enum */
8935#define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE 0x3 /* enum */
8936#define MC_CMD_MUM_IN_GPIO_OP_GPIO_NUMBER_OFST 4
8937#define MC_CMD_MUM_IN_GPIO_OP_GPIO_NUMBER_LBN 16
8938#define MC_CMD_MUM_IN_GPIO_OP_GPIO_NUMBER_WIDTH 8
8939
8940/* MC_CMD_MUM_IN_GPIO_OP_OUT_READ msgrequest */
8941#define MC_CMD_MUM_IN_GPIO_OP_OUT_READ_LEN 8
8942/* MC_CMD_MUM_IN_CMD_OFST 0 */
8943/* MC_CMD_MUM_IN_CMD_LEN 4 */
8944#define MC_CMD_MUM_IN_GPIO_OP_OUT_READ_HDR_OFST 4
8945#define MC_CMD_MUM_IN_GPIO_OP_OUT_READ_HDR_LEN 4
8946
8947/* MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE msgrequest */
8948#define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_LEN 8
8949/* MC_CMD_MUM_IN_CMD_OFST 0 */
8950/* MC_CMD_MUM_IN_CMD_LEN 4 */
8951#define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_HDR_OFST 4
8952#define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_HDR_LEN 4
8953#define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_WRITEBIT_OFST 4
8954#define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_WRITEBIT_LBN 24
8955#define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_WRITEBIT_WIDTH 8
8956
8957/* MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG msgrequest */
8958#define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_LEN 8
8959/* MC_CMD_MUM_IN_CMD_OFST 0 */
8960/* MC_CMD_MUM_IN_CMD_LEN 4 */
8961#define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_HDR_OFST 4
8962#define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_HDR_LEN 4
8963#define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_CFG_OFST 4
8964#define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_CFG_LBN 24
8965#define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_CFG_WIDTH 8
8966
8967/* MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE msgrequest */
8968#define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_LEN 8
8969/* MC_CMD_MUM_IN_CMD_OFST 0 */
8970/* MC_CMD_MUM_IN_CMD_LEN 4 */
8971#define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_HDR_OFST 4
8972#define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_HDR_LEN 4
8973#define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_ENABLEBIT_OFST 4
8974#define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_ENABLEBIT_LBN 24
8975#define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_ENABLEBIT_WIDTH 8
8976
8977/* MC_CMD_MUM_IN_READ_SENSORS msgrequest */
8978#define MC_CMD_MUM_IN_READ_SENSORS_LEN 8
8979/* MUM cmd header */
8980/* MC_CMD_MUM_IN_CMD_OFST 0 */
8981/* MC_CMD_MUM_IN_CMD_LEN 4 */
8982#define MC_CMD_MUM_IN_READ_SENSORS_PARAMS_OFST 4
8983#define MC_CMD_MUM_IN_READ_SENSORS_PARAMS_LEN 4
8984#define MC_CMD_MUM_IN_READ_SENSORS_SENSOR_ID_OFST 4
8985#define MC_CMD_MUM_IN_READ_SENSORS_SENSOR_ID_LBN 0
8986#define MC_CMD_MUM_IN_READ_SENSORS_SENSOR_ID_WIDTH 8
8987#define MC_CMD_MUM_IN_READ_SENSORS_NUM_SENSORS_OFST 4
8988#define MC_CMD_MUM_IN_READ_SENSORS_NUM_SENSORS_LBN 8
8989#define MC_CMD_MUM_IN_READ_SENSORS_NUM_SENSORS_WIDTH 8
8990
8991/* MC_CMD_MUM_IN_PROGRAM_CLOCKS msgrequest */
8992#define MC_CMD_MUM_IN_PROGRAM_CLOCKS_LEN 12
8993/* MUM cmd header */
8994/* MC_CMD_MUM_IN_CMD_OFST 0 */
8995/* MC_CMD_MUM_IN_CMD_LEN 4 */
8996/* Bit-mask of clocks to be programmed */
8997#define MC_CMD_MUM_IN_PROGRAM_CLOCKS_MASK_OFST 4
8998#define MC_CMD_MUM_IN_PROGRAM_CLOCKS_MASK_LEN 4
8999#define MC_CMD_MUM_CLOCK_ID_FPGA 0x0 /* enum */
9000#define MC_CMD_MUM_CLOCK_ID_DDR 0x1 /* enum */
9001#define MC_CMD_MUM_CLOCK_ID_NIC 0x2 /* enum */
9002/* Control flags for clock programming */
9003#define MC_CMD_MUM_IN_PROGRAM_CLOCKS_FLAGS_OFST 8
9004#define MC_CMD_MUM_IN_PROGRAM_CLOCKS_FLAGS_LEN 4
9005#define MC_CMD_MUM_IN_PROGRAM_CLOCKS_OVERCLOCK_110_OFST 8
9006#define MC_CMD_MUM_IN_PROGRAM_CLOCKS_OVERCLOCK_110_LBN 0
9007#define MC_CMD_MUM_IN_PROGRAM_CLOCKS_OVERCLOCK_110_WIDTH 1
9008#define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_NIC_FROM_FPGA_OFST 8
9009#define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_NIC_FROM_FPGA_LBN 1
9010#define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_NIC_FROM_FPGA_WIDTH 1
9011#define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_REF_FROM_XO_OFST 8
9012#define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_REF_FROM_XO_LBN 2
9013#define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_REF_FROM_XO_WIDTH 1
9014
9015/* MC_CMD_MUM_IN_FPGA_LOAD msgrequest */
9016#define MC_CMD_MUM_IN_FPGA_LOAD_LEN 8
9017/* MUM cmd header */
9018/* MC_CMD_MUM_IN_CMD_OFST 0 */
9019/* MC_CMD_MUM_IN_CMD_LEN 4 */
9020/* Enable/Disable FPGA config from flash */
9021#define MC_CMD_MUM_IN_FPGA_LOAD_ENABLE_OFST 4
9022#define MC_CMD_MUM_IN_FPGA_LOAD_ENABLE_LEN 4
9023
9024/* MC_CMD_MUM_IN_READ_ATB_SENSOR msgrequest */
9025#define MC_CMD_MUM_IN_READ_ATB_SENSOR_LEN 4
9026/* MUM cmd header */
9027/* MC_CMD_MUM_IN_CMD_OFST 0 */
9028/* MC_CMD_MUM_IN_CMD_LEN 4 */
9029
9030/* MC_CMD_MUM_IN_QSFP msgrequest */
9031#define MC_CMD_MUM_IN_QSFP_LEN 12
9032/* MUM cmd header */
9033/* MC_CMD_MUM_IN_CMD_OFST 0 */
9034/* MC_CMD_MUM_IN_CMD_LEN 4 */
9035#define MC_CMD_MUM_IN_QSFP_HDR_OFST 4
9036#define MC_CMD_MUM_IN_QSFP_HDR_LEN 4
9037#define MC_CMD_MUM_IN_QSFP_OPCODE_OFST 4
9038#define MC_CMD_MUM_IN_QSFP_OPCODE_LBN 0
9039#define MC_CMD_MUM_IN_QSFP_OPCODE_WIDTH 4
9040#define MC_CMD_MUM_IN_QSFP_INIT 0x0 /* enum */
9041#define MC_CMD_MUM_IN_QSFP_RECONFIGURE 0x1 /* enum */
9042#define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP 0x2 /* enum */
9043#define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO 0x3 /* enum */
9044#define MC_CMD_MUM_IN_QSFP_FILL_STATS 0x4 /* enum */
9045#define MC_CMD_MUM_IN_QSFP_POLL_BIST 0x5 /* enum */
9046#define MC_CMD_MUM_IN_QSFP_IDX_OFST 8
9047#define MC_CMD_MUM_IN_QSFP_IDX_LEN 4
9048
9049/* MC_CMD_MUM_IN_QSFP_INIT msgrequest */
9050#define MC_CMD_MUM_IN_QSFP_INIT_LEN 16
9051/* MC_CMD_MUM_IN_CMD_OFST 0 */
9052/* MC_CMD_MUM_IN_CMD_LEN 4 */
9053#define MC_CMD_MUM_IN_QSFP_INIT_HDR_OFST 4
9054#define MC_CMD_MUM_IN_QSFP_INIT_HDR_LEN 4
9055#define MC_CMD_MUM_IN_QSFP_INIT_IDX_OFST 8
9056#define MC_CMD_MUM_IN_QSFP_INIT_IDX_LEN 4
9057#define MC_CMD_MUM_IN_QSFP_INIT_CAGE_OFST 12
9058#define MC_CMD_MUM_IN_QSFP_INIT_CAGE_LEN 4
9059
9060/* MC_CMD_MUM_IN_QSFP_RECONFIGURE msgrequest */
9061#define MC_CMD_MUM_IN_QSFP_RECONFIGURE_LEN 24
9062/* MC_CMD_MUM_IN_CMD_OFST 0 */
9063/* MC_CMD_MUM_IN_CMD_LEN 4 */
9064#define MC_CMD_MUM_IN_QSFP_RECONFIGURE_HDR_OFST 4
9065#define MC_CMD_MUM_IN_QSFP_RECONFIGURE_HDR_LEN 4
9066#define MC_CMD_MUM_IN_QSFP_RECONFIGURE_IDX_OFST 8
9067#define MC_CMD_MUM_IN_QSFP_RECONFIGURE_IDX_LEN 4
9068#define MC_CMD_MUM_IN_QSFP_RECONFIGURE_TX_DISABLE_OFST 12
9069#define MC_CMD_MUM_IN_QSFP_RECONFIGURE_TX_DISABLE_LEN 4
9070#define MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LANES_OFST 16
9071#define MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LANES_LEN 4
9072#define MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LINK_SPEED_OFST 20
9073#define MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LINK_SPEED_LEN 4
9074
9075/* MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP msgrequest */
9076#define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_LEN 12
9077/* MC_CMD_MUM_IN_CMD_OFST 0 */
9078/* MC_CMD_MUM_IN_CMD_LEN 4 */
9079#define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_HDR_OFST 4
9080#define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_HDR_LEN 4
9081#define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_IDX_OFST 8
9082#define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_IDX_LEN 4
9083
9084/* MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO msgrequest */
9085#define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_LEN 16
9086/* MC_CMD_MUM_IN_CMD_OFST 0 */
9087/* MC_CMD_MUM_IN_CMD_LEN 4 */
9088#define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_HDR_OFST 4
9089#define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_HDR_LEN 4
9090#define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_IDX_OFST 8
9091#define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_IDX_LEN 4
9092#define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_PAGE_OFST 12
9093#define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_PAGE_LEN 4
9094
9095/* MC_CMD_MUM_IN_QSFP_FILL_STATS msgrequest */
9096#define MC_CMD_MUM_IN_QSFP_FILL_STATS_LEN 12
9097/* MC_CMD_MUM_IN_CMD_OFST 0 */
9098/* MC_CMD_MUM_IN_CMD_LEN 4 */
9099#define MC_CMD_MUM_IN_QSFP_FILL_STATS_HDR_OFST 4
9100#define MC_CMD_MUM_IN_QSFP_FILL_STATS_HDR_LEN 4
9101#define MC_CMD_MUM_IN_QSFP_FILL_STATS_IDX_OFST 8
9102#define MC_CMD_MUM_IN_QSFP_FILL_STATS_IDX_LEN 4
9103
9104/* MC_CMD_MUM_IN_QSFP_POLL_BIST msgrequest */
9105#define MC_CMD_MUM_IN_QSFP_POLL_BIST_LEN 12
9106/* MC_CMD_MUM_IN_CMD_OFST 0 */
9107/* MC_CMD_MUM_IN_CMD_LEN 4 */
9108#define MC_CMD_MUM_IN_QSFP_POLL_BIST_HDR_OFST 4
9109#define MC_CMD_MUM_IN_QSFP_POLL_BIST_HDR_LEN 4
9110#define MC_CMD_MUM_IN_QSFP_POLL_BIST_IDX_OFST 8
9111#define MC_CMD_MUM_IN_QSFP_POLL_BIST_IDX_LEN 4
9112
9113/* MC_CMD_MUM_IN_READ_DDR_INFO msgrequest */
9114#define MC_CMD_MUM_IN_READ_DDR_INFO_LEN 4
9115/* MUM cmd header */
9116/* MC_CMD_MUM_IN_CMD_OFST 0 */
9117/* MC_CMD_MUM_IN_CMD_LEN 4 */
9118
9119/* MC_CMD_MUM_OUT msgresponse */
9120#define MC_CMD_MUM_OUT_LEN 0
9121
9122/* MC_CMD_MUM_OUT_NULL msgresponse */
9123#define MC_CMD_MUM_OUT_NULL_LEN 0
9124
9125/* MC_CMD_MUM_OUT_GET_VERSION msgresponse */
9126#define MC_CMD_MUM_OUT_GET_VERSION_LEN 12
9127#define MC_CMD_MUM_OUT_GET_VERSION_FIRMWARE_OFST 0
9128#define MC_CMD_MUM_OUT_GET_VERSION_FIRMWARE_LEN 4
9129#define MC_CMD_MUM_OUT_GET_VERSION_VERSION_OFST 4
9130#define MC_CMD_MUM_OUT_GET_VERSION_VERSION_LEN 8
9131#define MC_CMD_MUM_OUT_GET_VERSION_VERSION_LO_OFST 4
9132#define MC_CMD_MUM_OUT_GET_VERSION_VERSION_LO_LEN 4
9133#define MC_CMD_MUM_OUT_GET_VERSION_VERSION_LO_LBN 32
9134#define MC_CMD_MUM_OUT_GET_VERSION_VERSION_LO_WIDTH 32
9135#define MC_CMD_MUM_OUT_GET_VERSION_VERSION_HI_OFST 8
9136#define MC_CMD_MUM_OUT_GET_VERSION_VERSION_HI_LEN 4
9137#define MC_CMD_MUM_OUT_GET_VERSION_VERSION_HI_LBN 64
9138#define MC_CMD_MUM_OUT_GET_VERSION_VERSION_HI_WIDTH 32
9139
9140/* MC_CMD_MUM_OUT_RAW_CMD msgresponse */
9141#define MC_CMD_MUM_OUT_RAW_CMD_LENMIN 1
9142#define MC_CMD_MUM_OUT_RAW_CMD_LENMAX 252
9143#define MC_CMD_MUM_OUT_RAW_CMD_LENMAX_MCDI2 1020
9144#define MC_CMD_MUM_OUT_RAW_CMD_LEN(num) (0+1*(num))
9145#define MC_CMD_MUM_OUT_RAW_CMD_DATA_NUM(len) (((len)-0)/1)
9146/* returned data */
9147#define MC_CMD_MUM_OUT_RAW_CMD_DATA_OFST 0
9148#define MC_CMD_MUM_OUT_RAW_CMD_DATA_LEN 1
9149#define MC_CMD_MUM_OUT_RAW_CMD_DATA_MINNUM 1
9150#define MC_CMD_MUM_OUT_RAW_CMD_DATA_MAXNUM 252
9151#define MC_CMD_MUM_OUT_RAW_CMD_DATA_MAXNUM_MCDI2 1020
9152
9153/* MC_CMD_MUM_OUT_READ msgresponse */
9154#define MC_CMD_MUM_OUT_READ_LENMIN 4
9155#define MC_CMD_MUM_OUT_READ_LENMAX 252
9156#define MC_CMD_MUM_OUT_READ_LENMAX_MCDI2 1020
9157#define MC_CMD_MUM_OUT_READ_LEN(num) (0+4*(num))
9158#define MC_CMD_MUM_OUT_READ_BUFFER_NUM(len) (((len)-0)/4)
9159#define MC_CMD_MUM_OUT_READ_BUFFER_OFST 0
9160#define MC_CMD_MUM_OUT_READ_BUFFER_LEN 4
9161#define MC_CMD_MUM_OUT_READ_BUFFER_MINNUM 1
9162#define MC_CMD_MUM_OUT_READ_BUFFER_MAXNUM 63
9163#define MC_CMD_MUM_OUT_READ_BUFFER_MAXNUM_MCDI2 255
9164
9165/* MC_CMD_MUM_OUT_WRITE msgresponse */
9166#define MC_CMD_MUM_OUT_WRITE_LEN 0
9167
9168/* MC_CMD_MUM_OUT_LOG msgresponse */
9169#define MC_CMD_MUM_OUT_LOG_LEN 0
9170
9171/* MC_CMD_MUM_OUT_LOG_OP_UART msgresponse */
9172#define MC_CMD_MUM_OUT_LOG_OP_UART_LEN 0
9173
9174/* MC_CMD_MUM_OUT_GPIO_IN_READ msgresponse */
9175#define MC_CMD_MUM_OUT_GPIO_IN_READ_LEN 8
9176/* The first 32-bit word read from the GPIO IN register. */
9177#define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK1_OFST 0
9178#define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK1_LEN 4
9179/* The second 32-bit word read from the GPIO IN register. */
9180#define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK2_OFST 4
9181#define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK2_LEN 4
9182
9183/* MC_CMD_MUM_OUT_GPIO_OUT_WRITE msgresponse */
9184#define MC_CMD_MUM_OUT_GPIO_OUT_WRITE_LEN 0
9185
9186/* MC_CMD_MUM_OUT_GPIO_OUT_READ msgresponse */
9187#define MC_CMD_MUM_OUT_GPIO_OUT_READ_LEN 8
9188/* The first 32-bit word read from the GPIO OUT register. */
9189#define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK1_OFST 0
9190#define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK1_LEN 4
9191/* The second 32-bit word read from the GPIO OUT register. */
9192#define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK2_OFST 4
9193#define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK2_LEN 4
9194
9195/* MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_WRITE msgresponse */
9196#define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_WRITE_LEN 0
9197
9198/* MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ msgresponse */
9199#define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_LEN 8
9200#define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK1_OFST 0
9201#define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK1_LEN 4
9202#define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK2_OFST 4
9203#define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK2_LEN 4
9204
9205/* MC_CMD_MUM_OUT_GPIO_OP_OUT_READ msgresponse */
9206#define MC_CMD_MUM_OUT_GPIO_OP_OUT_READ_LEN 4
9207#define MC_CMD_MUM_OUT_GPIO_OP_OUT_READ_BIT_READ_OFST 0
9208#define MC_CMD_MUM_OUT_GPIO_OP_OUT_READ_BIT_READ_LEN 4
9209
9210/* MC_CMD_MUM_OUT_GPIO_OP_OUT_WRITE msgresponse */
9211#define MC_CMD_MUM_OUT_GPIO_OP_OUT_WRITE_LEN 0
9212
9213/* MC_CMD_MUM_OUT_GPIO_OP_OUT_CONFIG msgresponse */
9214#define MC_CMD_MUM_OUT_GPIO_OP_OUT_CONFIG_LEN 0
9215
9216/* MC_CMD_MUM_OUT_GPIO_OP_OUT_ENABLE msgresponse */
9217#define MC_CMD_MUM_OUT_GPIO_OP_OUT_ENABLE_LEN 0
9218
9219/* MC_CMD_MUM_OUT_READ_SENSORS msgresponse */
9220#define MC_CMD_MUM_OUT_READ_SENSORS_LENMIN 4
9221#define MC_CMD_MUM_OUT_READ_SENSORS_LENMAX 252
9222#define MC_CMD_MUM_OUT_READ_SENSORS_LENMAX_MCDI2 1020
9223#define MC_CMD_MUM_OUT_READ_SENSORS_LEN(num) (0+4*(num))
9224#define MC_CMD_MUM_OUT_READ_SENSORS_DATA_NUM(len) (((len)-0)/4)
9225#define MC_CMD_MUM_OUT_READ_SENSORS_DATA_OFST 0
9226#define MC_CMD_MUM_OUT_READ_SENSORS_DATA_LEN 4
9227#define MC_CMD_MUM_OUT_READ_SENSORS_DATA_MINNUM 1
9228#define MC_CMD_MUM_OUT_READ_SENSORS_DATA_MAXNUM 63
9229#define MC_CMD_MUM_OUT_READ_SENSORS_DATA_MAXNUM_MCDI2 255
9230#define MC_CMD_MUM_OUT_READ_SENSORS_READING_OFST 0
9231#define MC_CMD_MUM_OUT_READ_SENSORS_READING_LBN 0
9232#define MC_CMD_MUM_OUT_READ_SENSORS_READING_WIDTH 16
9233#define MC_CMD_MUM_OUT_READ_SENSORS_STATE_OFST 0
9234#define MC_CMD_MUM_OUT_READ_SENSORS_STATE_LBN 16
9235#define MC_CMD_MUM_OUT_READ_SENSORS_STATE_WIDTH 8
9236#define MC_CMD_MUM_OUT_READ_SENSORS_TYPE_OFST 0
9237#define MC_CMD_MUM_OUT_READ_SENSORS_TYPE_LBN 24
9238#define MC_CMD_MUM_OUT_READ_SENSORS_TYPE_WIDTH 8
9239
9240/* MC_CMD_MUM_OUT_PROGRAM_CLOCKS msgresponse */
9241#define MC_CMD_MUM_OUT_PROGRAM_CLOCKS_LEN 4
9242#define MC_CMD_MUM_OUT_PROGRAM_CLOCKS_OK_MASK_OFST 0
9243#define MC_CMD_MUM_OUT_PROGRAM_CLOCKS_OK_MASK_LEN 4
9244
9245/* MC_CMD_MUM_OUT_FPGA_LOAD msgresponse */
9246#define MC_CMD_MUM_OUT_FPGA_LOAD_LEN 0
9247
9248/* MC_CMD_MUM_OUT_READ_ATB_SENSOR msgresponse */
9249#define MC_CMD_MUM_OUT_READ_ATB_SENSOR_LEN 4
9250#define MC_CMD_MUM_OUT_READ_ATB_SENSOR_RESULT_OFST 0
9251#define MC_CMD_MUM_OUT_READ_ATB_SENSOR_RESULT_LEN 4
9252
9253/* MC_CMD_MUM_OUT_QSFP_INIT msgresponse */
9254#define MC_CMD_MUM_OUT_QSFP_INIT_LEN 0
9255
9256/* MC_CMD_MUM_OUT_QSFP_RECONFIGURE msgresponse */
9257#define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_LEN 8
9258#define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LP_CAP_OFST 0
9259#define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LP_CAP_LEN 4
9260#define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_FLAGS_OFST 4
9261#define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_FLAGS_LEN 4
9262#define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_OFST 4
9263#define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_LBN 0
9264#define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_WIDTH 1
9265#define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LINK_UP_OFST 4
9266#define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LINK_UP_LBN 1
9267#define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LINK_UP_WIDTH 1
9268
9269/* MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP msgresponse */
9270#define MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_LEN 4
9271#define MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_PORT_PHY_LP_CAP_OFST 0
9272#define MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_PORT_PHY_LP_CAP_LEN 4
9273
9274/* MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO msgresponse */
9275#define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LENMIN 5
9276#define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LENMAX 252
9277#define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LENMAX_MCDI2 1020
9278#define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LEN(num) (4+1*(num))
9279#define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_NUM(len) (((len)-4)/1)
9280/* in bytes */
9281#define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATALEN_OFST 0
9282#define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATALEN_LEN 4
9283#define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_OFST 4
9284#define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_LEN 1
9285#define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_MINNUM 1
9286#define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_MAXNUM 248
9287#define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_MAXNUM_MCDI2 1016
9288
9289/* MC_CMD_MUM_OUT_QSFP_FILL_STATS msgresponse */
9290#define MC_CMD_MUM_OUT_QSFP_FILL_STATS_LEN 8
9291#define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PMA_PMD_LINK_UP_OFST 0
9292#define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PMA_PMD_LINK_UP_LEN 4
9293#define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PCS_LINK_UP_OFST 4
9294#define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PCS_LINK_UP_LEN 4
9295
9296/* MC_CMD_MUM_OUT_QSFP_POLL_BIST msgresponse */
9297#define MC_CMD_MUM_OUT_QSFP_POLL_BIST_LEN 4
9298#define MC_CMD_MUM_OUT_QSFP_POLL_BIST_TEST_OFST 0
9299#define MC_CMD_MUM_OUT_QSFP_POLL_BIST_TEST_LEN 4
9300
9301/* MC_CMD_MUM_OUT_READ_DDR_INFO msgresponse */
9302#define MC_CMD_MUM_OUT_READ_DDR_INFO_LENMIN 24
9303#define MC_CMD_MUM_OUT_READ_DDR_INFO_LENMAX 248
9304#define MC_CMD_MUM_OUT_READ_DDR_INFO_LENMAX_MCDI2 1016
9305#define MC_CMD_MUM_OUT_READ_DDR_INFO_LEN(num) (8+8*(num))
9306#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_NUM(len) (((len)-8)/8)
9307/* Discrete (soldered) DDR resistor strap info */
9308#define MC_CMD_MUM_OUT_READ_DDR_INFO_DISCRETE_DDR_INFO_OFST 0
9309#define MC_CMD_MUM_OUT_READ_DDR_INFO_DISCRETE_DDR_INFO_LEN 4
9310#define MC_CMD_MUM_OUT_READ_DDR_INFO_VRATIO_OFST 0
9311#define MC_CMD_MUM_OUT_READ_DDR_INFO_VRATIO_LBN 0
9312#define MC_CMD_MUM_OUT_READ_DDR_INFO_VRATIO_WIDTH 16
9313#define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED1_OFST 0
9314#define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED1_LBN 16
9315#define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED1_WIDTH 16
9316/* Number of SODIMM info records */
9317#define MC_CMD_MUM_OUT_READ_DDR_INFO_NUM_RECORDS_OFST 4
9318#define MC_CMD_MUM_OUT_READ_DDR_INFO_NUM_RECORDS_LEN 4
9319/* Array of SODIMM info records */
9320#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_OFST 8
9321#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LEN 8
9322#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LO_OFST 8
9323#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LO_LEN 4
9324#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LO_LBN 64
9325#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LO_WIDTH 32
9326#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_HI_OFST 12
9327#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_HI_LEN 4
9328#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_HI_LBN 96
9329#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_HI_WIDTH 32
9330#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_MINNUM 2
9331#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_MAXNUM 30
9332#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_MAXNUM_MCDI2 126
9333#define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK_ID_OFST 8
9334#define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK_ID_LBN 0
9335#define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK_ID_WIDTH 8
9336/* enum: SODIMM bank 1 (Top SODIMM for Sorrento) */
9337#define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK1 0x0
9338/* enum: SODIMM bank 2 (Bottom SODDIMM for Sorrento) */
9339#define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK2 0x1
9340/* enum: Total number of SODIMM banks */
9341#define MC_CMD_MUM_OUT_READ_DDR_INFO_NUM_BANKS 0x2
9342#define MC_CMD_MUM_OUT_READ_DDR_INFO_TYPE_OFST 8
9343#define MC_CMD_MUM_OUT_READ_DDR_INFO_TYPE_LBN 8
9344#define MC_CMD_MUM_OUT_READ_DDR_INFO_TYPE_WIDTH 8
9345#define MC_CMD_MUM_OUT_READ_DDR_INFO_RANK_OFST 8
9346#define MC_CMD_MUM_OUT_READ_DDR_INFO_RANK_LBN 16
9347#define MC_CMD_MUM_OUT_READ_DDR_INFO_RANK_WIDTH 4
9348#define MC_CMD_MUM_OUT_READ_DDR_INFO_VOLTAGE_OFST 8
9349#define MC_CMD_MUM_OUT_READ_DDR_INFO_VOLTAGE_LBN 20
9350#define MC_CMD_MUM_OUT_READ_DDR_INFO_VOLTAGE_WIDTH 4
9351#define MC_CMD_MUM_OUT_READ_DDR_INFO_NOT_POWERED 0x0 /* enum */
9352#define MC_CMD_MUM_OUT_READ_DDR_INFO_1V25 0x1 /* enum */
9353#define MC_CMD_MUM_OUT_READ_DDR_INFO_1V35 0x2 /* enum */
9354#define MC_CMD_MUM_OUT_READ_DDR_INFO_1V5 0x3 /* enum */
9355/* enum: Values 5-15 are reserved for future usage */
9356#define MC_CMD_MUM_OUT_READ_DDR_INFO_1V8 0x4
9357#define MC_CMD_MUM_OUT_READ_DDR_INFO_SIZE_OFST 8
9358#define MC_CMD_MUM_OUT_READ_DDR_INFO_SIZE_LBN 24
9359#define MC_CMD_MUM_OUT_READ_DDR_INFO_SIZE_WIDTH 8
9360#define MC_CMD_MUM_OUT_READ_DDR_INFO_SPEED_OFST 8
9361#define MC_CMD_MUM_OUT_READ_DDR_INFO_SPEED_LBN 32
9362#define MC_CMD_MUM_OUT_READ_DDR_INFO_SPEED_WIDTH 16
9363#define MC_CMD_MUM_OUT_READ_DDR_INFO_STATE_OFST 8
9364#define MC_CMD_MUM_OUT_READ_DDR_INFO_STATE_LBN 48
9365#define MC_CMD_MUM_OUT_READ_DDR_INFO_STATE_WIDTH 4
9366/* enum: No module present */
9367#define MC_CMD_MUM_OUT_READ_DDR_INFO_ABSENT 0x0
9368/* enum: Module present supported and powered on */
9369#define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_POWERED 0x1
9370/* enum: Module present but bad type */
9371#define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_TYPE 0x2
9372/* enum: Module present but incompatible voltage */
9373#define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_VOLTAGE 0x3
9374/* enum: Module present but unknown SPD */
9375#define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_SPD 0x4
9376/* enum: Module present but slot cannot support it */
9377#define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_SLOT 0x5
9378/* enum: Modules may or may not be present, but cannot establish contact by I2C
9379 */
9380#define MC_CMD_MUM_OUT_READ_DDR_INFO_NOT_REACHABLE 0x6
9381#define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED2_OFST 8
9382#define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED2_LBN 52
9383#define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED2_WIDTH 12
9384
9385/* MC_CMD_DYNAMIC_SENSORS_LIMITS structuredef: Set of sensor limits. This
9386 * should match the equivalent structure in the sensor_query SPHINX service.
9387 */
9388#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LEN 24
9389/* A value below this will trigger a warning event. */
9390#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_WARNING_OFST 0
9391#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_WARNING_LEN 4
9392#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_WARNING_LBN 0
9393#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_WARNING_WIDTH 32
9394/* A value below this will trigger a critical event. */
9395#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_CRITICAL_OFST 4
9396#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_CRITICAL_LEN 4
9397#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_CRITICAL_LBN 32
9398#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_CRITICAL_WIDTH 32
9399/* A value below this will shut down the card. */
9400#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_FATAL_OFST 8
9401#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_FATAL_LEN 4
9402#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_FATAL_LBN 64
9403#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_FATAL_WIDTH 32
9404/* A value above this will trigger a warning event. */
9405#define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_WARNING_OFST 12
9406#define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_WARNING_LEN 4
9407#define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_WARNING_LBN 96
9408#define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_WARNING_WIDTH 32
9409/* A value above this will trigger a critical event. */
9410#define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_CRITICAL_OFST 16
9411#define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_CRITICAL_LEN 4
9412#define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_CRITICAL_LBN 128
9413#define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_CRITICAL_WIDTH 32
9414/* A value above this will shut down the card. */
9415#define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_FATAL_OFST 20
9416#define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_FATAL_LEN 4
9417#define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_FATAL_LBN 160
9418#define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_FATAL_WIDTH 32
9419
9420/* MC_CMD_DYNAMIC_SENSORS_DESCRIPTION structuredef: Description of a sensor.
9421 * This should match the equivalent structure in the sensor_query SPHINX
9422 * service.
9423 */
9424#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_LEN 64
9425/* The handle used to identify the sensor in calls to
9426 * MC_CMD_DYNAMIC_SENSORS_GET_VALUES
9427 */
9428#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_HANDLE_OFST 0
9429#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_HANDLE_LEN 4
9430#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_HANDLE_LBN 0
9431#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_HANDLE_WIDTH 32
9432/* A human-readable name for the sensor (zero terminated string, max 32 bytes)
9433 */
9434#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_NAME_OFST 4
9435#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_NAME_LEN 32
9436#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_NAME_LBN 32
9437#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_NAME_WIDTH 256
9438/* The type of the sensor device, and by implication the unit of that the
9439 * values will be reported in
9440 */
9441#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_TYPE_OFST 36
9442#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_TYPE_LEN 4
9443/* enum: A voltage sensor. Unit is mV */
9444#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_VOLTAGE 0x0
9445/* enum: A current sensor. Unit is mA */
9446#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_CURRENT 0x1
9447/* enum: A power sensor. Unit is mW */
9448#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_POWER 0x2
9449/* enum: A temperature sensor. Unit is Celsius */
9450#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_TEMPERATURE 0x3
9451/* enum: A cooling fan sensor. Unit is RPM */
9452#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_FAN 0x4
9453#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_TYPE_LBN 288
9454#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_TYPE_WIDTH 32
9455/* A single MC_CMD_DYNAMIC_SENSORS_LIMITS structure */
9456#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_LIMITS_OFST 40
9457#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_LIMITS_LEN 24
9458#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_LIMITS_LBN 320
9459#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_LIMITS_WIDTH 192
9460
9461/* MC_CMD_DYNAMIC_SENSORS_READING structuredef: State and value of a sensor.
9462 * This should match the equivalent structure in the sensor_query SPHINX
9463 * service.
9464 */
9465#define MC_CMD_DYNAMIC_SENSORS_READING_LEN 12
9466/* The handle used to identify the sensor */
9467#define MC_CMD_DYNAMIC_SENSORS_READING_HANDLE_OFST 0
9468#define MC_CMD_DYNAMIC_SENSORS_READING_HANDLE_LEN 4
9469#define MC_CMD_DYNAMIC_SENSORS_READING_HANDLE_LBN 0
9470#define MC_CMD_DYNAMIC_SENSORS_READING_HANDLE_WIDTH 32
9471/* The current value of the sensor */
9472#define MC_CMD_DYNAMIC_SENSORS_READING_VALUE_OFST 4
9473#define MC_CMD_DYNAMIC_SENSORS_READING_VALUE_LEN 4
9474#define MC_CMD_DYNAMIC_SENSORS_READING_VALUE_LBN 32
9475#define MC_CMD_DYNAMIC_SENSORS_READING_VALUE_WIDTH 32
9476/* The sensor's condition, e.g. good, broken or removed */
9477#define MC_CMD_DYNAMIC_SENSORS_READING_STATE_OFST 8
9478#define MC_CMD_DYNAMIC_SENSORS_READING_STATE_LEN 4
9479/* enum: Sensor working normally within limits */
9480#define MC_CMD_DYNAMIC_SENSORS_READING_OK 0x0
9481/* enum: Warning threshold breached */
9482#define MC_CMD_DYNAMIC_SENSORS_READING_WARNING 0x1
9483/* enum: Critical threshold breached */
9484#define MC_CMD_DYNAMIC_SENSORS_READING_CRITICAL 0x2
9485/* enum: Fatal threshold breached */
9486#define MC_CMD_DYNAMIC_SENSORS_READING_FATAL 0x3
9487/* enum: Sensor not working */
9488#define MC_CMD_DYNAMIC_SENSORS_READING_BROKEN 0x4
9489/* enum: Sensor working but no reading available */
9490#define MC_CMD_DYNAMIC_SENSORS_READING_NO_READING 0x5
9491/* enum: Sensor initialization failed */
9492#define MC_CMD_DYNAMIC_SENSORS_READING_INIT_FAILED 0x6
9493#define MC_CMD_DYNAMIC_SENSORS_READING_STATE_LBN 64
9494#define MC_CMD_DYNAMIC_SENSORS_READING_STATE_WIDTH 32
9495
9496
9497/***********************************/
9498/* MC_CMD_DYNAMIC_SENSORS_LIST
9499 * Return a complete list of handles for sensors currently managed by the MC,
9500 * and a generation count for this version of the sensor table. On systems
9501 * advertising the DYNAMIC_SENSORS capability bit, this replaces the
9502 * MC_CMD_READ_SENSORS command. On multi-MC systems this may include sensors
9503 * added by the NMC.
9504 *
9505 * Sensor handles are persistent for the lifetime of the sensor and are used to
9506 * identify sensors in MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS and
9507 * MC_CMD_DYNAMIC_SENSORS_GET_VALUES.
9508 *
9509 * The generation count is maintained by the MC, is persistent across reboots
9510 * and will be incremented each time the sensor table is modified. When the
9511 * table is modified, a CODE_DYNAMIC_SENSORS_CHANGE event will be generated
9512 * containing the new generation count. The driver should compare this against
9513 * the current generation count, and if it is different, call
9514 * MC_CMD_DYNAMIC_SENSORS_LIST again to update it's copy of the sensor table.
9515 *
9516 * The sensor count is provided to allow a future path to supporting more than
9517 * MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_MAXNUM_MCDI2 sensors, i.e.
9518 * the maximum number that will fit in a single response. As this is a fairly
9519 * large number (253) it is not anticipated that this will be needed in the
9520 * near future, so can currently be ignored.
9521 *
9522 * On Riverhead this command is implemented as a wrapper for `list` in the
9523 * sensor_query SPHINX service.
9524 */
9525#define MC_CMD_DYNAMIC_SENSORS_LIST 0x66
9526#undef MC_CMD_0x66_PRIVILEGE_CTG
9527
9528#define MC_CMD_0x66_PRIVILEGE_CTG SRIOV_CTG_GENERAL
9529
9530/* MC_CMD_DYNAMIC_SENSORS_LIST_IN msgrequest */
9531#define MC_CMD_DYNAMIC_SENSORS_LIST_IN_LEN 0
9532
9533/* MC_CMD_DYNAMIC_SENSORS_LIST_OUT msgresponse */
9534#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_LENMIN 8
9535#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_LENMAX 252
9536#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_LENMAX_MCDI2 1020
9537#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_LEN(num) (8+4*(num))
9538#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_HANDLES_NUM(len) (((len)-8)/4)
9539/* Generation count, which will be updated each time a sensor is added to or
9540 * removed from the MC sensor table.
9541 */
9542#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_GENERATION_OFST 0
9543#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_GENERATION_LEN 4
9544/* Number of sensors managed by the MC. Note that in principle, this can be
9545 * larger than the size of the HANDLES array.
9546 */
9547#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_COUNT_OFST 4
9548#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_COUNT_LEN 4
9549/* Array of sensor handles */
9550#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_HANDLES_OFST 8
9551#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_HANDLES_LEN 4
9552#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_HANDLES_MINNUM 0
9553#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_HANDLES_MAXNUM 61
9554#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_HANDLES_MAXNUM_MCDI2 253
9555
9556
9557/***********************************/
9558/* MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS
9559 * Get descriptions for a set of sensors, specified as an array of sensor
9560 * handles as returned by MC_CMD_DYNAMIC_SENSORS_LIST
9561 *
9562 * Any handles which do not correspond to a sensor currently managed by the MC
9563 * will be dropped from from the response. This may happen when a sensor table
9564 * update is in progress, and effectively means the set of usable sensors is
9565 * the intersection between the sets of sensors known to the driver and the MC.
9566 *
9567 * On Riverhead this command is implemented as a wrapper for
9568 * `get_descriptions` in the sensor_query SPHINX service.
9569 */
9570#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS 0x67
9571#undef MC_CMD_0x67_PRIVILEGE_CTG
9572
9573#define MC_CMD_0x67_PRIVILEGE_CTG SRIOV_CTG_GENERAL
9574
9575/* MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN msgrequest */
9576#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_LENMIN 0
9577#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_LENMAX 252
9578#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_LENMAX_MCDI2 1020
9579#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_LEN(num) (0+4*(num))
9580#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_HANDLES_NUM(len) (((len)-0)/4)
9581/* Array of sensor handles */
9582#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_HANDLES_OFST 0
9583#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_HANDLES_LEN 4
9584#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_HANDLES_MINNUM 0
9585#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_HANDLES_MAXNUM 63
9586#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_HANDLES_MAXNUM_MCDI2 255
9587
9588/* MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT msgresponse */
9589#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_LENMIN 0
9590#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_LENMAX 192
9591#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_LENMAX_MCDI2 960
9592#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_LEN(num) (0+64*(num))
9593#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_SENSORS_NUM(len) (((len)-0)/64)
9594/* Array of MC_CMD_DYNAMIC_SENSORS_DESCRIPTION structures */
9595#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_SENSORS_OFST 0
9596#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_SENSORS_LEN 64
9597#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_SENSORS_MINNUM 0
9598#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_SENSORS_MAXNUM 3
9599#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_SENSORS_MAXNUM_MCDI2 15
9600
9601
9602/***********************************/
9603/* MC_CMD_DYNAMIC_SENSORS_GET_READINGS
9604 * Read the state and value for a set of sensors, specified as an array of
9605 * sensor handles as returned by MC_CMD_DYNAMIC_SENSORS_LIST.
9606 *
9607 * In the case of a broken sensor, then the state of the response's
9608 * MC_CMD_DYNAMIC_SENSORS_VALUE entry will be set to BROKEN, and any value
9609 * provided should be treated as erroneous.
9610 *
9611 * Any handles which do not correspond to a sensor currently managed by the MC
9612 * will be dropped from from the response. This may happen when a sensor table
9613 * update is in progress, and effectively means the set of usable sensors is
9614 * the intersection between the sets of sensors known to the driver and the MC.
9615 *
9616 * On Riverhead this command is implemented as a wrapper for `get_readings`
9617 * in the sensor_query SPHINX service.
9618 */
9619#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS 0x68
9620#undef MC_CMD_0x68_PRIVILEGE_CTG
9621
9622#define MC_CMD_0x68_PRIVILEGE_CTG SRIOV_CTG_GENERAL
9623
9624/* MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN msgrequest */
9625#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_LENMIN 0
9626#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_LENMAX 252
9627#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_LENMAX_MCDI2 1020
9628#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_LEN(num) (0+4*(num))
9629#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_NUM(len) (((len)-0)/4)
9630/* Array of sensor handles */
9631#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_OFST 0
9632#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_LEN 4
9633#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_MINNUM 0
9634#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_MAXNUM 63
9635#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_MAXNUM_MCDI2 255
9636
9637/* MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT msgresponse */
9638#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_LENMIN 0
9639#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_LENMAX 252
9640#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_LENMAX_MCDI2 1020
9641#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_LEN(num) (0+12*(num))
9642#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_VALUES_NUM(len) (((len)-0)/12)
9643/* Array of MC_CMD_DYNAMIC_SENSORS_READING structures */
9644#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_VALUES_OFST 0
9645#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_VALUES_LEN 12
9646#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_VALUES_MINNUM 0
9647#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_VALUES_MAXNUM 21
9648#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_VALUES_MAXNUM_MCDI2 85
9649
9650
9651/***********************************/
9652/* MC_CMD_EVENT_CTRL
9653 * Configure which categories of unsolicited events the driver expects to
9654 * receive (Riverhead).
9655 */
9656#define MC_CMD_EVENT_CTRL 0x69
9657#undef MC_CMD_0x69_PRIVILEGE_CTG
9658
9659#define MC_CMD_0x69_PRIVILEGE_CTG SRIOV_CTG_GENERAL
9660
9661/* MC_CMD_EVENT_CTRL_IN msgrequest */
9662#define MC_CMD_EVENT_CTRL_IN_LENMIN 0
9663#define MC_CMD_EVENT_CTRL_IN_LENMAX 252
9664#define MC_CMD_EVENT_CTRL_IN_LENMAX_MCDI2 1020
9665#define MC_CMD_EVENT_CTRL_IN_LEN(num) (0+4*(num))
9666#define MC_CMD_EVENT_CTRL_IN_EVENT_TYPE_NUM(len) (((len)-0)/4)
9667/* Array of event categories for which the driver wishes to receive events. */
9668#define MC_CMD_EVENT_CTRL_IN_EVENT_TYPE_OFST 0
9669#define MC_CMD_EVENT_CTRL_IN_EVENT_TYPE_LEN 4
9670#define MC_CMD_EVENT_CTRL_IN_EVENT_TYPE_MINNUM 0
9671#define MC_CMD_EVENT_CTRL_IN_EVENT_TYPE_MAXNUM 63
9672#define MC_CMD_EVENT_CTRL_IN_EVENT_TYPE_MAXNUM_MCDI2 255
9673/* enum: Driver wishes to receive LINKCHANGE events. */
9674#define MC_CMD_EVENT_CTRL_IN_MCDI_EVENT_CODE_LINKCHANGE 0x0
9675/* enum: Driver wishes to receive SENSOR_CHANGE and SENSOR_STATE_CHANGE events.
9676 */
9677#define MC_CMD_EVENT_CTRL_IN_MCDI_EVENT_CODE_SENSOREVT 0x1
9678/* enum: Driver wishes to receive receive errors. */
9679#define MC_CMD_EVENT_CTRL_IN_MCDI_EVENT_CODE_RX_ERR 0x2
9680/* enum: Driver wishes to receive transmit errors. */
9681#define MC_CMD_EVENT_CTRL_IN_MCDI_EVENT_CODE_TX_ERR 0x3
9682/* enum: Driver wishes to receive firmware alerts. */
9683#define MC_CMD_EVENT_CTRL_IN_MCDI_EVENT_CODE_FWALERT 0x4
9684/* enum: Driver wishes to receive reboot events. */
9685#define MC_CMD_EVENT_CTRL_IN_MCDI_EVENT_CODE_MC_REBOOT 0x5
9686
9687/* MC_CMD_EVENT_CTRL_OUT msgrequest */
9688#define MC_CMD_EVENT_CTRL_OUT_LEN 0
9689
9690/* EVB_PORT_ID structuredef */
9691#define EVB_PORT_ID_LEN 4
9692#define EVB_PORT_ID_PORT_ID_OFST 0
9693#define EVB_PORT_ID_PORT_ID_LEN 4
9694/* enum: An invalid port handle. */
9695#define EVB_PORT_ID_NULL 0x0
9696/* enum: The port assigned to this function.. */
9697#define EVB_PORT_ID_ASSIGNED 0x1000000
9698/* enum: External network port 0 */
9699#define EVB_PORT_ID_MAC0 0x2000000
9700/* enum: External network port 1 */
9701#define EVB_PORT_ID_MAC1 0x2000001
9702/* enum: External network port 2 */
9703#define EVB_PORT_ID_MAC2 0x2000002
9704/* enum: External network port 3 */
9705#define EVB_PORT_ID_MAC3 0x2000003
9706#define EVB_PORT_ID_PORT_ID_LBN 0
9707#define EVB_PORT_ID_PORT_ID_WIDTH 32
9708
9709/* EVB_VLAN_TAG structuredef */
9710#define EVB_VLAN_TAG_LEN 2
9711/* The VLAN tag value */
9712#define EVB_VLAN_TAG_VLAN_ID_LBN 0
9713#define EVB_VLAN_TAG_VLAN_ID_WIDTH 12
9714#define EVB_VLAN_TAG_MODE_LBN 12
9715#define EVB_VLAN_TAG_MODE_WIDTH 4
9716/* enum: Insert the VLAN. */
9717#define EVB_VLAN_TAG_INSERT 0x0
9718/* enum: Replace the VLAN if already present. */
9719#define EVB_VLAN_TAG_REPLACE 0x1
9720
9721/* BUFTBL_ENTRY structuredef */
9722#define BUFTBL_ENTRY_LEN 12
9723/* the owner ID */
9724#define BUFTBL_ENTRY_OID_OFST 0
9725#define BUFTBL_ENTRY_OID_LEN 2
9726#define BUFTBL_ENTRY_OID_LBN 0
9727#define BUFTBL_ENTRY_OID_WIDTH 16
9728/* the page parameter as one of ESE_DZ_SMC_PAGE_SIZE_ */
9729#define BUFTBL_ENTRY_PGSZ_OFST 2
9730#define BUFTBL_ENTRY_PGSZ_LEN 2
9731#define BUFTBL_ENTRY_PGSZ_LBN 16
9732#define BUFTBL_ENTRY_PGSZ_WIDTH 16
9733/* the raw 64-bit address field from the SMC, not adjusted for page size */
9734#define BUFTBL_ENTRY_RAWADDR_OFST 4
9735#define BUFTBL_ENTRY_RAWADDR_LEN 8
9736#define BUFTBL_ENTRY_RAWADDR_LO_OFST 4
9737#define BUFTBL_ENTRY_RAWADDR_LO_LEN 4
9738#define BUFTBL_ENTRY_RAWADDR_LO_LBN 32
9739#define BUFTBL_ENTRY_RAWADDR_LO_WIDTH 32
9740#define BUFTBL_ENTRY_RAWADDR_HI_OFST 8
9741#define BUFTBL_ENTRY_RAWADDR_HI_LEN 4
9742#define BUFTBL_ENTRY_RAWADDR_HI_LBN 64
9743#define BUFTBL_ENTRY_RAWADDR_HI_WIDTH 32
9744#define BUFTBL_ENTRY_RAWADDR_LBN 32
9745#define BUFTBL_ENTRY_RAWADDR_WIDTH 64
9746
9747/* NVRAM_PARTITION_TYPE structuredef */
9748#define NVRAM_PARTITION_TYPE_LEN 2
9749#define NVRAM_PARTITION_TYPE_ID_OFST 0
9750#define NVRAM_PARTITION_TYPE_ID_LEN 2
9751/* enum: Primary MC firmware partition */
9752#define NVRAM_PARTITION_TYPE_MC_FIRMWARE 0x100
9753/* enum: NMC firmware partition (this is intentionally an alias of MC_FIRMWARE)
9754 */
9755#define NVRAM_PARTITION_TYPE_NMC_FIRMWARE 0x100
9756/* enum: Secondary MC firmware partition */
9757#define NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP 0x200
9758/* enum: Expansion ROM partition */
9759#define NVRAM_PARTITION_TYPE_EXPANSION_ROM 0x300
9760/* enum: Static configuration TLV partition */
9761#define NVRAM_PARTITION_TYPE_STATIC_CONFIG 0x400
9762/* enum: Factory configuration TLV partition (this is intentionally an alias of
9763 * STATIC_CONFIG)
9764 */
9765#define NVRAM_PARTITION_TYPE_FACTORY_CONFIG 0x400
9766/* enum: Dynamic configuration TLV partition */
9767#define NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG 0x500
9768/* enum: User configuration TLV partition (this is intentionally an alias of
9769 * DYNAMIC_CONFIG)
9770 */
9771#define NVRAM_PARTITION_TYPE_USER_CONFIG 0x500
9772/* enum: Expansion ROM configuration data for port 0 */
9773#define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0 0x600
9774/* enum: Synonym for EXPROM_CONFIG_PORT0 as used in pmap files */
9775#define NVRAM_PARTITION_TYPE_EXPROM_CONFIG 0x600
9776/* enum: Expansion ROM configuration data for port 1 */
9777#define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1 0x601
9778/* enum: Expansion ROM configuration data for port 2 */
9779#define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2 0x602
9780/* enum: Expansion ROM configuration data for port 3 */
9781#define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3 0x603
9782/* enum: Non-volatile log output partition */
9783#define NVRAM_PARTITION_TYPE_LOG 0x700
9784/* enum: Non-volatile log output partition for NMC firmware (this is
9785 * intentionally an alias of LOG)
9786 */
9787#define NVRAM_PARTITION_TYPE_NMC_LOG 0x700
9788/* enum: Non-volatile log output of second core on dual-core device */
9789#define NVRAM_PARTITION_TYPE_LOG_SLAVE 0x701
9790/* enum: Device state dump output partition */
9791#define NVRAM_PARTITION_TYPE_DUMP 0x800
9792/* enum: Crash log partition for NMC firmware */
9793#define NVRAM_PARTITION_TYPE_NMC_CRASH_LOG 0x801
9794/* enum: Application license key storage partition */
9795#define NVRAM_PARTITION_TYPE_LICENSE 0x900
9796/* enum: Start of range used for PHY partitions (low 8 bits are the PHY ID) */
9797#define NVRAM_PARTITION_TYPE_PHY_MIN 0xa00
9798/* enum: End of range used for PHY partitions (low 8 bits are the PHY ID) */
9799#define NVRAM_PARTITION_TYPE_PHY_MAX 0xaff
9800/* enum: Primary FPGA partition */
9801#define NVRAM_PARTITION_TYPE_FPGA 0xb00
9802/* enum: Secondary FPGA partition */
9803#define NVRAM_PARTITION_TYPE_FPGA_BACKUP 0xb01
9804/* enum: FC firmware partition */
9805#define NVRAM_PARTITION_TYPE_FC_FIRMWARE 0xb02
9806/* enum: FC License partition */
9807#define NVRAM_PARTITION_TYPE_FC_LICENSE 0xb03
9808/* enum: Non-volatile log output partition for FC */
9809#define NVRAM_PARTITION_TYPE_FC_LOG 0xb04
9810/* enum: FPGA Stage 1 bitstream */
9811#define NVRAM_PARTITION_TYPE_FPGA_STAGE1 0xb05
9812/* enum: FPGA Stage 2 bitstream */
9813#define NVRAM_PARTITION_TYPE_FPGA_STAGE2 0xb06
9814/* enum: FPGA User XCLBIN / Programmable Region 0 bitstream */
9815#define NVRAM_PARTITION_TYPE_FPGA_REGION0 0xb07
9816/* enum: FPGA User XCLBIN (this is intentionally an alias of FPGA_REGION0) */
9817#define NVRAM_PARTITION_TYPE_FPGA_XCLBIN_USER 0xb07
9818/* enum: FPGA jump instruction (a.k.a. boot) partition to select Stage1
9819 * bitstream
9820 */
9821#define NVRAM_PARTITION_TYPE_FPGA_JUMP 0xb08
9822/* enum: FPGA Validate XCLBIN */
9823#define NVRAM_PARTITION_TYPE_FPGA_XCLBIN_VALIDATE 0xb09
9824/* enum: FPGA XOCL Configuration information */
9825#define NVRAM_PARTITION_TYPE_FPGA_XOCL_CONFIG 0xb0a
9826/* enum: MUM firmware partition */
9827#define NVRAM_PARTITION_TYPE_MUM_FIRMWARE 0xc00
9828/* enum: SUC firmware partition (this is intentionally an alias of
9829 * MUM_FIRMWARE)
9830 */
9831#define NVRAM_PARTITION_TYPE_SUC_FIRMWARE 0xc00
9832/* enum: MUM Non-volatile log output partition. */
9833#define NVRAM_PARTITION_TYPE_MUM_LOG 0xc01
9834/* enum: SUC Non-volatile log output partition (this is intentionally an alias
9835 * of MUM_LOG).
9836 */
9837#define NVRAM_PARTITION_TYPE_SUC_LOG 0xc01
9838/* enum: MUM Application table partition. */
9839#define NVRAM_PARTITION_TYPE_MUM_APPTABLE 0xc02
9840/* enum: MUM boot rom partition. */
9841#define NVRAM_PARTITION_TYPE_MUM_BOOT_ROM 0xc03
9842/* enum: MUM production signatures & calibration rom partition. */
9843#define NVRAM_PARTITION_TYPE_MUM_PROD_ROM 0xc04
9844/* enum: MUM user signatures & calibration rom partition. */
9845#define NVRAM_PARTITION_TYPE_MUM_USER_ROM 0xc05
9846/* enum: MUM fuses and lockbits partition. */
9847#define NVRAM_PARTITION_TYPE_MUM_FUSELOCK 0xc06
9848/* enum: UEFI expansion ROM if separate from PXE */
9849#define NVRAM_PARTITION_TYPE_EXPANSION_UEFI 0xd00
9850/* enum: Used by the expansion ROM for logging */
9851#define NVRAM_PARTITION_TYPE_PXE_LOG 0x1000
9852/* enum: Non-volatile log output partition for Expansion ROM (this is
9853 * intentionally an alias of PXE_LOG).
9854 */
9855#define NVRAM_PARTITION_TYPE_EXPROM_LOG 0x1000
9856/* enum: Used for XIP code of shmbooted images */
9857#define NVRAM_PARTITION_TYPE_XIP_SCRATCH 0x1100
9858/* enum: Spare partition 2 */
9859#define NVRAM_PARTITION_TYPE_SPARE_2 0x1200
9860/* enum: Manufacturing partition. Used during manufacture to pass information
9861 * between XJTAG and Manftest.
9862 */
9863#define NVRAM_PARTITION_TYPE_MANUFACTURING 0x1300
9864/* enum: Deployment configuration TLV partition (this is intentionally an alias
9865 * of MANUFACTURING)
9866 */
9867#define NVRAM_PARTITION_TYPE_DEPLOYMENT_CONFIG 0x1300
9868/* enum: Spare partition 4 */
9869#define NVRAM_PARTITION_TYPE_SPARE_4 0x1400
9870/* enum: Spare partition 5 */
9871#define NVRAM_PARTITION_TYPE_SPARE_5 0x1500
9872/* enum: Partition for reporting MC status. See mc_flash_layout.h
9873 * medford_mc_status_hdr_t for layout on Medford.
9874 */
9875#define NVRAM_PARTITION_TYPE_STATUS 0x1600
9876/* enum: Spare partition 13 */
9877#define NVRAM_PARTITION_TYPE_SPARE_13 0x1700
9878/* enum: Spare partition 14 */
9879#define NVRAM_PARTITION_TYPE_SPARE_14 0x1800
9880/* enum: Spare partition 15 */
9881#define NVRAM_PARTITION_TYPE_SPARE_15 0x1900
9882/* enum: Spare partition 16 */
9883#define NVRAM_PARTITION_TYPE_SPARE_16 0x1a00
9884/* enum: Factory defaults for dynamic configuration */
9885#define NVRAM_PARTITION_TYPE_DYNCONFIG_DEFAULTS 0x1b00
9886/* enum: Factory defaults for expansion ROM configuration */
9887#define NVRAM_PARTITION_TYPE_ROMCONFIG_DEFAULTS 0x1c00
9888/* enum: Field Replaceable Unit inventory information for use on IPMI
9889 * platforms. See SF-119124-PS. The STATIC_CONFIG partition may contain a
9890 * subset of the information stored in this partition.
9891 */
9892#define NVRAM_PARTITION_TYPE_FRU_INFORMATION 0x1d00
9893/* enum: Bundle image partition */
9894#define NVRAM_PARTITION_TYPE_BUNDLE 0x1e00
9895/* enum: Bundle metadata partition that holds additional information related to
9896 * a bundle update in TLV format
9897 */
9898#define NVRAM_PARTITION_TYPE_BUNDLE_METADATA 0x1e01
9899/* enum: Bundle update non-volatile log output partition */
9900#define NVRAM_PARTITION_TYPE_BUNDLE_LOG 0x1e02
9901/* enum: Partition for Solarflare gPXE bootrom installed via Bundle update. */
9902#define NVRAM_PARTITION_TYPE_EXPANSION_ROM_INTERNAL 0x1e03
9903/* enum: Partition to store ASN.1 format Bundle Signature for checking. */
9904#define NVRAM_PARTITION_TYPE_BUNDLE_SIGNATURE 0x1e04
9905/* enum: Test partition on SmartNIC system microcontroller (SUC) */
9906#define NVRAM_PARTITION_TYPE_SUC_TEST 0x1f00
9907/* enum: System microcontroller access to primary FPGA flash. */
9908#define NVRAM_PARTITION_TYPE_SUC_FPGA_PRIMARY 0x1f01
9909/* enum: System microcontroller access to secondary FPGA flash (if present) */
9910#define NVRAM_PARTITION_TYPE_SUC_FPGA_SECONDARY 0x1f02
9911/* enum: System microcontroller access to primary System-on-Chip flash */
9912#define NVRAM_PARTITION_TYPE_SUC_SOC_PRIMARY 0x1f03
9913/* enum: System microcontroller access to secondary System-on-Chip flash (if
9914 * present)
9915 */
9916#define NVRAM_PARTITION_TYPE_SUC_SOC_SECONDARY 0x1f04
9917/* enum: System microcontroller critical failure logs. Contains structured
9918 * details of sensors leading up to a critical failure (where the board is shut
9919 * down).
9920 */
9921#define NVRAM_PARTITION_TYPE_SUC_FAILURE_LOG 0x1f05
9922/* enum: System-on-Chip configuration information (see XN-200467-PS). */
9923#define NVRAM_PARTITION_TYPE_SUC_SOC_CONFIG 0x1f07
9924/* enum: System-on-Chip update information. */
9925#define NVRAM_PARTITION_TYPE_SOC_UPDATE 0x2003
9926/* enum: Start of reserved value range (firmware may use for any purpose) */
9927#define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MIN 0xff00
9928/* enum: End of reserved value range (firmware may use for any purpose) */
9929#define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MAX 0xfffd
9930/* enum: Recovery partition map (provided if real map is missing or corrupt) */
9931#define NVRAM_PARTITION_TYPE_RECOVERY_MAP 0xfffe
9932/* enum: Recovery Flash Partition Table, see SF-122606-TC. (this is
9933 * intentionally an alias of RECOVERY_MAP)
9934 */
9935#define NVRAM_PARTITION_TYPE_RECOVERY_FPT 0xfffe
9936/* enum: Partition map (real map as stored in flash) */
9937#define NVRAM_PARTITION_TYPE_PARTITION_MAP 0xffff
9938/* enum: Flash Partition Table, see SF-122606-TC. (this is intentionally an
9939 * alias of PARTITION_MAP)
9940 */
9941#define NVRAM_PARTITION_TYPE_FPT 0xffff
9942#define NVRAM_PARTITION_TYPE_ID_LBN 0
9943#define NVRAM_PARTITION_TYPE_ID_WIDTH 16
9944
9945/* LICENSED_APP_ID structuredef */
9946#define LICENSED_APP_ID_LEN 4
9947#define LICENSED_APP_ID_ID_OFST 0
9948#define LICENSED_APP_ID_ID_LEN 4
9949/* enum: OpenOnload */
9950#define LICENSED_APP_ID_ONLOAD 0x1
9951/* enum: PTP timestamping */
9952#define LICENSED_APP_ID_PTP 0x2
9953/* enum: SolarCapture Pro */
9954#define LICENSED_APP_ID_SOLARCAPTURE_PRO 0x4
9955/* enum: SolarSecure filter engine */
9956#define LICENSED_APP_ID_SOLARSECURE 0x8
9957/* enum: Performance monitor */
9958#define LICENSED_APP_ID_PERF_MONITOR 0x10
9959/* enum: SolarCapture Live */
9960#define LICENSED_APP_ID_SOLARCAPTURE_LIVE 0x20
9961/* enum: Capture SolarSystem */
9962#define LICENSED_APP_ID_CAPTURE_SOLARSYSTEM 0x40
9963/* enum: Network Access Control */
9964#define LICENSED_APP_ID_NETWORK_ACCESS_CONTROL 0x80
9965/* enum: TCP Direct */
9966#define LICENSED_APP_ID_TCP_DIRECT 0x100
9967/* enum: Low Latency */
9968#define LICENSED_APP_ID_LOW_LATENCY 0x200
9969/* enum: SolarCapture Tap */
9970#define LICENSED_APP_ID_SOLARCAPTURE_TAP 0x400
9971/* enum: Capture SolarSystem 40G */
9972#define LICENSED_APP_ID_CAPTURE_SOLARSYSTEM_40G 0x800
9973/* enum: Capture SolarSystem 1G */
9974#define LICENSED_APP_ID_CAPTURE_SOLARSYSTEM_1G 0x1000
9975/* enum: ScaleOut Onload */
9976#define LICENSED_APP_ID_SCALEOUT_ONLOAD 0x2000
9977/* enum: SCS Network Analytics Dashboard */
9978#define LICENSED_APP_ID_DSHBRD 0x4000
9979/* enum: SolarCapture Trading Analytics */
9980#define LICENSED_APP_ID_SCATRD 0x8000
9981#define LICENSED_APP_ID_ID_LBN 0
9982#define LICENSED_APP_ID_ID_WIDTH 32
9983
9984/* LICENSED_FEATURES structuredef */
9985#define LICENSED_FEATURES_LEN 8
9986/* Bitmask of licensed firmware features */
9987#define LICENSED_FEATURES_MASK_OFST 0
9988#define LICENSED_FEATURES_MASK_LEN 8
9989#define LICENSED_FEATURES_MASK_LO_OFST 0
9990#define LICENSED_FEATURES_MASK_LO_LEN 4
9991#define LICENSED_FEATURES_MASK_LO_LBN 0
9992#define LICENSED_FEATURES_MASK_LO_WIDTH 32
9993#define LICENSED_FEATURES_MASK_HI_OFST 4
9994#define LICENSED_FEATURES_MASK_HI_LEN 4
9995#define LICENSED_FEATURES_MASK_HI_LBN 32
9996#define LICENSED_FEATURES_MASK_HI_WIDTH 32
9997#define LICENSED_FEATURES_RX_CUT_THROUGH_OFST 0
9998#define LICENSED_FEATURES_RX_CUT_THROUGH_LBN 0
9999#define LICENSED_FEATURES_RX_CUT_THROUGH_WIDTH 1
10000#define LICENSED_FEATURES_PIO_OFST 0
10001#define LICENSED_FEATURES_PIO_LBN 1
10002#define LICENSED_FEATURES_PIO_WIDTH 1
10003#define LICENSED_FEATURES_EVQ_TIMER_OFST 0
10004#define LICENSED_FEATURES_EVQ_TIMER_LBN 2
10005#define LICENSED_FEATURES_EVQ_TIMER_WIDTH 1
10006#define LICENSED_FEATURES_CLOCK_OFST 0
10007#define LICENSED_FEATURES_CLOCK_LBN 3
10008#define LICENSED_FEATURES_CLOCK_WIDTH 1
10009#define LICENSED_FEATURES_RX_TIMESTAMPS_OFST 0
10010#define LICENSED_FEATURES_RX_TIMESTAMPS_LBN 4
10011#define LICENSED_FEATURES_RX_TIMESTAMPS_WIDTH 1
10012#define LICENSED_FEATURES_TX_TIMESTAMPS_OFST 0
10013#define LICENSED_FEATURES_TX_TIMESTAMPS_LBN 5
10014#define LICENSED_FEATURES_TX_TIMESTAMPS_WIDTH 1
10015#define LICENSED_FEATURES_RX_SNIFF_OFST 0
10016#define LICENSED_FEATURES_RX_SNIFF_LBN 6
10017#define LICENSED_FEATURES_RX_SNIFF_WIDTH 1
10018#define LICENSED_FEATURES_TX_SNIFF_OFST 0
10019#define LICENSED_FEATURES_TX_SNIFF_LBN 7
10020#define LICENSED_FEATURES_TX_SNIFF_WIDTH 1
10021#define LICENSED_FEATURES_PROXY_FILTER_OPS_OFST 0
10022#define LICENSED_FEATURES_PROXY_FILTER_OPS_LBN 8
10023#define LICENSED_FEATURES_PROXY_FILTER_OPS_WIDTH 1
10024#define LICENSED_FEATURES_EVENT_CUT_THROUGH_OFST 0
10025#define LICENSED_FEATURES_EVENT_CUT_THROUGH_LBN 9
10026#define LICENSED_FEATURES_EVENT_CUT_THROUGH_WIDTH 1
10027#define LICENSED_FEATURES_MASK_LBN 0
10028#define LICENSED_FEATURES_MASK_WIDTH 64
10029
10030/* LICENSED_V3_APPS structuredef */
10031#define LICENSED_V3_APPS_LEN 8
10032/* Bitmask of licensed applications */
10033#define LICENSED_V3_APPS_MASK_OFST 0
10034#define LICENSED_V3_APPS_MASK_LEN 8
10035#define LICENSED_V3_APPS_MASK_LO_OFST 0
10036#define LICENSED_V3_APPS_MASK_LO_LEN 4
10037#define LICENSED_V3_APPS_MASK_LO_LBN 0
10038#define LICENSED_V3_APPS_MASK_LO_WIDTH 32
10039#define LICENSED_V3_APPS_MASK_HI_OFST 4
10040#define LICENSED_V3_APPS_MASK_HI_LEN 4
10041#define LICENSED_V3_APPS_MASK_HI_LBN 32
10042#define LICENSED_V3_APPS_MASK_HI_WIDTH 32
10043#define LICENSED_V3_APPS_ONLOAD_OFST 0
10044#define LICENSED_V3_APPS_ONLOAD_LBN 0
10045#define LICENSED_V3_APPS_ONLOAD_WIDTH 1
10046#define LICENSED_V3_APPS_PTP_OFST 0
10047#define LICENSED_V3_APPS_PTP_LBN 1
10048#define LICENSED_V3_APPS_PTP_WIDTH 1
10049#define LICENSED_V3_APPS_SOLARCAPTURE_PRO_OFST 0
10050#define LICENSED_V3_APPS_SOLARCAPTURE_PRO_LBN 2
10051#define LICENSED_V3_APPS_SOLARCAPTURE_PRO_WIDTH 1
10052#define LICENSED_V3_APPS_SOLARSECURE_OFST 0
10053#define LICENSED_V3_APPS_SOLARSECURE_LBN 3
10054#define LICENSED_V3_APPS_SOLARSECURE_WIDTH 1
10055#define LICENSED_V3_APPS_PERF_MONITOR_OFST 0
10056#define LICENSED_V3_APPS_PERF_MONITOR_LBN 4
10057#define LICENSED_V3_APPS_PERF_MONITOR_WIDTH 1
10058#define LICENSED_V3_APPS_SOLARCAPTURE_LIVE_OFST 0
10059#define LICENSED_V3_APPS_SOLARCAPTURE_LIVE_LBN 5
10060#define LICENSED_V3_APPS_SOLARCAPTURE_LIVE_WIDTH 1
10061#define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_OFST 0
10062#define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_LBN 6
10063#define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_WIDTH 1
10064#define LICENSED_V3_APPS_NETWORK_ACCESS_CONTROL_OFST 0
10065#define LICENSED_V3_APPS_NETWORK_ACCESS_CONTROL_LBN 7
10066#define LICENSED_V3_APPS_NETWORK_ACCESS_CONTROL_WIDTH 1
10067#define LICENSED_V3_APPS_TCP_DIRECT_OFST 0
10068#define LICENSED_V3_APPS_TCP_DIRECT_LBN 8
10069#define LICENSED_V3_APPS_TCP_DIRECT_WIDTH 1
10070#define LICENSED_V3_APPS_LOW_LATENCY_OFST 0
10071#define LICENSED_V3_APPS_LOW_LATENCY_LBN 9
10072#define LICENSED_V3_APPS_LOW_LATENCY_WIDTH 1
10073#define LICENSED_V3_APPS_SOLARCAPTURE_TAP_OFST 0
10074#define LICENSED_V3_APPS_SOLARCAPTURE_TAP_LBN 10
10075#define LICENSED_V3_APPS_SOLARCAPTURE_TAP_WIDTH 1
10076#define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_40G_OFST 0
10077#define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_40G_LBN 11
10078#define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_40G_WIDTH 1
10079#define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_1G_OFST 0
10080#define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_1G_LBN 12
10081#define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_1G_WIDTH 1
10082#define LICENSED_V3_APPS_SCALEOUT_ONLOAD_OFST 0
10083#define LICENSED_V3_APPS_SCALEOUT_ONLOAD_LBN 13
10084#define LICENSED_V3_APPS_SCALEOUT_ONLOAD_WIDTH 1
10085#define LICENSED_V3_APPS_DSHBRD_OFST 0
10086#define LICENSED_V3_APPS_DSHBRD_LBN 14
10087#define LICENSED_V3_APPS_DSHBRD_WIDTH 1
10088#define LICENSED_V3_APPS_SCATRD_OFST 0
10089#define LICENSED_V3_APPS_SCATRD_LBN 15
10090#define LICENSED_V3_APPS_SCATRD_WIDTH 1
10091#define LICENSED_V3_APPS_MASK_LBN 0
10092#define LICENSED_V3_APPS_MASK_WIDTH 64
10093
10094/* LICENSED_V3_FEATURES structuredef */
10095#define LICENSED_V3_FEATURES_LEN 8
10096/* Bitmask of licensed firmware features */
10097#define LICENSED_V3_FEATURES_MASK_OFST 0
10098#define LICENSED_V3_FEATURES_MASK_LEN 8
10099#define LICENSED_V3_FEATURES_MASK_LO_OFST 0
10100#define LICENSED_V3_FEATURES_MASK_LO_LEN 4
10101#define LICENSED_V3_FEATURES_MASK_LO_LBN 0
10102#define LICENSED_V3_FEATURES_MASK_LO_WIDTH 32
10103#define LICENSED_V3_FEATURES_MASK_HI_OFST 4
10104#define LICENSED_V3_FEATURES_MASK_HI_LEN 4
10105#define LICENSED_V3_FEATURES_MASK_HI_LBN 32
10106#define LICENSED_V3_FEATURES_MASK_HI_WIDTH 32
10107#define LICENSED_V3_FEATURES_RX_CUT_THROUGH_OFST 0
10108#define LICENSED_V3_FEATURES_RX_CUT_THROUGH_LBN 0
10109#define LICENSED_V3_FEATURES_RX_CUT_THROUGH_WIDTH 1
10110#define LICENSED_V3_FEATURES_PIO_OFST 0
10111#define LICENSED_V3_FEATURES_PIO_LBN 1
10112#define LICENSED_V3_FEATURES_PIO_WIDTH 1
10113#define LICENSED_V3_FEATURES_EVQ_TIMER_OFST 0
10114#define LICENSED_V3_FEATURES_EVQ_TIMER_LBN 2
10115#define LICENSED_V3_FEATURES_EVQ_TIMER_WIDTH 1
10116#define LICENSED_V3_FEATURES_CLOCK_OFST 0
10117#define LICENSED_V3_FEATURES_CLOCK_LBN 3
10118#define LICENSED_V3_FEATURES_CLOCK_WIDTH 1
10119#define LICENSED_V3_FEATURES_RX_TIMESTAMPS_OFST 0
10120#define LICENSED_V3_FEATURES_RX_TIMESTAMPS_LBN 4
10121#define LICENSED_V3_FEATURES_RX_TIMESTAMPS_WIDTH 1
10122#define LICENSED_V3_FEATURES_TX_TIMESTAMPS_OFST 0
10123#define LICENSED_V3_FEATURES_TX_TIMESTAMPS_LBN 5
10124#define LICENSED_V3_FEATURES_TX_TIMESTAMPS_WIDTH 1
10125#define LICENSED_V3_FEATURES_RX_SNIFF_OFST 0
10126#define LICENSED_V3_FEATURES_RX_SNIFF_LBN 6
10127#define LICENSED_V3_FEATURES_RX_SNIFF_WIDTH 1
10128#define LICENSED_V3_FEATURES_TX_SNIFF_OFST 0
10129#define LICENSED_V3_FEATURES_TX_SNIFF_LBN 7
10130#define LICENSED_V3_FEATURES_TX_SNIFF_WIDTH 1
10131#define LICENSED_V3_FEATURES_PROXY_FILTER_OPS_OFST 0
10132#define LICENSED_V3_FEATURES_PROXY_FILTER_OPS_LBN 8
10133#define LICENSED_V3_FEATURES_PROXY_FILTER_OPS_WIDTH 1
10134#define LICENSED_V3_FEATURES_EVENT_CUT_THROUGH_OFST 0
10135#define LICENSED_V3_FEATURES_EVENT_CUT_THROUGH_LBN 9
10136#define LICENSED_V3_FEATURES_EVENT_CUT_THROUGH_WIDTH 1
10137#define LICENSED_V3_FEATURES_MASK_LBN 0
10138#define LICENSED_V3_FEATURES_MASK_WIDTH 64
10139
10140/* TX_TIMESTAMP_EVENT structuredef */
10141#define TX_TIMESTAMP_EVENT_LEN 6
10142/* lower 16 bits of timestamp data */
10143#define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_OFST 0
10144#define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_LEN 2
10145#define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_LBN 0
10146#define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_WIDTH 16
10147/* Type of TX event, ordinary TX completion, low or high part of TX timestamp
10148 */
10149#define TX_TIMESTAMP_EVENT_TX_EV_TYPE_OFST 3
10150#define TX_TIMESTAMP_EVENT_TX_EV_TYPE_LEN 1
10151/* enum: This is a TX completion event, not a timestamp */
10152#define TX_TIMESTAMP_EVENT_TX_EV_COMPLETION 0x0
10153/* enum: This is a TX completion event for a CTPIO transmit. The event format
10154 * is the same as for TX_EV_COMPLETION.
10155 */
10156#define TX_TIMESTAMP_EVENT_TX_EV_CTPIO_COMPLETION 0x11
10157/* enum: This is the low part of a TX timestamp for a CTPIO transmission. The
10158 * event format is the same as for TX_EV_TSTAMP_LO
10159 */
10160#define TX_TIMESTAMP_EVENT_TX_EV_CTPIO_TS_LO 0x12
10161/* enum: This is the high part of a TX timestamp for a CTPIO transmission. The
10162 * event format is the same as for TX_EV_TSTAMP_HI
10163 */
10164#define TX_TIMESTAMP_EVENT_TX_EV_CTPIO_TS_HI 0x13
10165/* enum: This is the low part of a TX timestamp event */
10166#define TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_LO 0x51
10167/* enum: This is the high part of a TX timestamp event */
10168#define TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_HI 0x52
10169#define TX_TIMESTAMP_EVENT_TX_EV_TYPE_LBN 24
10170#define TX_TIMESTAMP_EVENT_TX_EV_TYPE_WIDTH 8
10171/* upper 16 bits of timestamp data */
10172#define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_OFST 4
10173#define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_LEN 2
10174#define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_LBN 32
10175#define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_WIDTH 16
10176
10177/* RSS_MODE structuredef */
10178#define RSS_MODE_LEN 1
10179/* The RSS mode for a particular packet type is a value from 0 - 15 which can
10180 * be considered as 4 bits selecting which fields are included in the hash. (A
10181 * value 0 effectively disables RSS spreading for the packet type.) The YAML
10182 * generation tools require this structure to be a whole number of bytes wide,
10183 * but only 4 bits are relevant.
10184 */
10185#define RSS_MODE_HASH_SELECTOR_OFST 0
10186#define RSS_MODE_HASH_SELECTOR_LEN 1
10187#define RSS_MODE_HASH_SRC_ADDR_OFST 0
10188#define RSS_MODE_HASH_SRC_ADDR_LBN 0
10189#define RSS_MODE_HASH_SRC_ADDR_WIDTH 1
10190#define RSS_MODE_HASH_DST_ADDR_OFST 0
10191#define RSS_MODE_HASH_DST_ADDR_LBN 1
10192#define RSS_MODE_HASH_DST_ADDR_WIDTH 1
10193#define RSS_MODE_HASH_SRC_PORT_OFST 0
10194#define RSS_MODE_HASH_SRC_PORT_LBN 2
10195#define RSS_MODE_HASH_SRC_PORT_WIDTH 1
10196#define RSS_MODE_HASH_DST_PORT_OFST 0
10197#define RSS_MODE_HASH_DST_PORT_LBN 3
10198#define RSS_MODE_HASH_DST_PORT_WIDTH 1
10199#define RSS_MODE_HASH_SELECTOR_LBN 0
10200#define RSS_MODE_HASH_SELECTOR_WIDTH 8
10201
10202/* CTPIO_STATS_MAP structuredef */
10203#define CTPIO_STATS_MAP_LEN 4
10204/* The (function relative) VI number */
10205#define CTPIO_STATS_MAP_VI_OFST 0
10206#define CTPIO_STATS_MAP_VI_LEN 2
10207#define CTPIO_STATS_MAP_VI_LBN 0
10208#define CTPIO_STATS_MAP_VI_WIDTH 16
10209/* The target bucket for the VI */
10210#define CTPIO_STATS_MAP_BUCKET_OFST 2
10211#define CTPIO_STATS_MAP_BUCKET_LEN 2
10212#define CTPIO_STATS_MAP_BUCKET_LBN 16
10213#define CTPIO_STATS_MAP_BUCKET_WIDTH 16
10214
10215
10216/***********************************/
10217/* MC_CMD_READ_REGS
10218 * Get a dump of the MCPU registers
10219 */
10220#define MC_CMD_READ_REGS 0x50
10221#undef MC_CMD_0x50_PRIVILEGE_CTG
10222
10223#define MC_CMD_0x50_PRIVILEGE_CTG SRIOV_CTG_INSECURE
10224
10225/* MC_CMD_READ_REGS_IN msgrequest */
10226#define MC_CMD_READ_REGS_IN_LEN 0
10227
10228/* MC_CMD_READ_REGS_OUT msgresponse */
10229#define MC_CMD_READ_REGS_OUT_LEN 308
10230/* Whether the corresponding register entry contains a valid value */
10231#define MC_CMD_READ_REGS_OUT_MASK_OFST 0
10232#define MC_CMD_READ_REGS_OUT_MASK_LEN 16
10233/* Same order as MIPS GDB (r0-r31, sr, lo, hi, bad, cause, 32 x float, fsr,
10234 * fir, fp)
10235 */
10236#define MC_CMD_READ_REGS_OUT_REGS_OFST 16
10237#define MC_CMD_READ_REGS_OUT_REGS_LEN 4
10238#define MC_CMD_READ_REGS_OUT_REGS_NUM 73
10239
10240
10241/***********************************/
10242/* MC_CMD_INIT_EVQ
10243 * Set up an event queue according to the supplied parameters. The IN arguments
10244 * end with an address for each 4k of host memory required to back the EVQ.
10245 */
10246#define MC_CMD_INIT_EVQ 0x80
10247#undef MC_CMD_0x80_PRIVILEGE_CTG
10248
10249#define MC_CMD_0x80_PRIVILEGE_CTG SRIOV_CTG_GENERAL
10250
10251/* MC_CMD_INIT_EVQ_IN msgrequest */
10252#define MC_CMD_INIT_EVQ_IN_LENMIN 44
10253#define MC_CMD_INIT_EVQ_IN_LENMAX 548
10254#define MC_CMD_INIT_EVQ_IN_LENMAX_MCDI2 548
10255#define MC_CMD_INIT_EVQ_IN_LEN(num) (36+8*(num))
10256#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_NUM(len) (((len)-36)/8)
10257/* Size, in entries */
10258#define MC_CMD_INIT_EVQ_IN_SIZE_OFST 0
10259#define MC_CMD_INIT_EVQ_IN_SIZE_LEN 4
10260/* Desired instance. Must be set to a specific instance, which is a function
10261 * local queue index. The calling client must be the currently-assigned user of
10262 * this VI (see MC_CMD_SET_VI_USER).
10263 */
10264#define MC_CMD_INIT_EVQ_IN_INSTANCE_OFST 4
10265#define MC_CMD_INIT_EVQ_IN_INSTANCE_LEN 4
10266/* The initial timer value. The load value is ignored if the timer mode is DIS.
10267 */
10268#define MC_CMD_INIT_EVQ_IN_TMR_LOAD_OFST 8
10269#define MC_CMD_INIT_EVQ_IN_TMR_LOAD_LEN 4
10270/* The reload value is ignored in one-shot modes */
10271#define MC_CMD_INIT_EVQ_IN_TMR_RELOAD_OFST 12
10272#define MC_CMD_INIT_EVQ_IN_TMR_RELOAD_LEN 4
10273/* tbd */
10274#define MC_CMD_INIT_EVQ_IN_FLAGS_OFST 16
10275#define MC_CMD_INIT_EVQ_IN_FLAGS_LEN 4
10276#define MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_OFST 16
10277#define MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_LBN 0
10278#define MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_WIDTH 1
10279#define MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_OFST 16
10280#define MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_LBN 1
10281#define MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_WIDTH 1
10282#define MC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_OFST 16
10283#define MC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_LBN 2
10284#define MC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_WIDTH 1
10285#define MC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_OFST 16
10286#define MC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_LBN 3
10287#define MC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_WIDTH 1
10288#define MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_OFST 16
10289#define MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_LBN 4
10290#define MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_WIDTH 1
10291#define MC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_OFST 16
10292#define MC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_LBN 5
10293#define MC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_WIDTH 1
10294#define MC_CMD_INIT_EVQ_IN_FLAG_USE_TIMER_OFST 16
10295#define MC_CMD_INIT_EVQ_IN_FLAG_USE_TIMER_LBN 6
10296#define MC_CMD_INIT_EVQ_IN_FLAG_USE_TIMER_WIDTH 1
10297#define MC_CMD_INIT_EVQ_IN_TMR_MODE_OFST 20
10298#define MC_CMD_INIT_EVQ_IN_TMR_MODE_LEN 4
10299/* enum: Disabled */
10300#define MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS 0x0
10301/* enum: Immediate */
10302#define MC_CMD_INIT_EVQ_IN_TMR_IMMED_START 0x1
10303/* enum: Triggered */
10304#define MC_CMD_INIT_EVQ_IN_TMR_TRIG_START 0x2
10305/* enum: Hold-off */
10306#define MC_CMD_INIT_EVQ_IN_TMR_INT_HLDOFF 0x3
10307/* Target EVQ for wakeups if in wakeup mode. */
10308#define MC_CMD_INIT_EVQ_IN_TARGET_EVQ_OFST 24
10309#define MC_CMD_INIT_EVQ_IN_TARGET_EVQ_LEN 4
10310/* Target interrupt if in interrupting mode (note union with target EVQ). Use
10311 * MC_CMD_RESOURCE_INSTANCE_ANY unless a specific one required for test
10312 * purposes.
10313 */
10314#define MC_CMD_INIT_EVQ_IN_IRQ_NUM_OFST 24
10315#define MC_CMD_INIT_EVQ_IN_IRQ_NUM_LEN 4
10316/* Event Counter Mode. */
10317#define MC_CMD_INIT_EVQ_IN_COUNT_MODE_OFST 28
10318#define MC_CMD_INIT_EVQ_IN_COUNT_MODE_LEN 4
10319/* enum: Disabled */
10320#define MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS 0x0
10321/* enum: Disabled */
10322#define MC_CMD_INIT_EVQ_IN_COUNT_MODE_RX 0x1
10323/* enum: Disabled */
10324#define MC_CMD_INIT_EVQ_IN_COUNT_MODE_TX 0x2
10325/* enum: Disabled */
10326#define MC_CMD_INIT_EVQ_IN_COUNT_MODE_RXTX 0x3
10327/* Event queue packet count threshold. */
10328#define MC_CMD_INIT_EVQ_IN_COUNT_THRSHLD_OFST 32
10329#define MC_CMD_INIT_EVQ_IN_COUNT_THRSHLD_LEN 4
10330/* 64-bit address of 4k of 4k-aligned host memory buffer */
10331#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_OFST 36
10332#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LEN 8
10333#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LO_OFST 36
10334#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LO_LEN 4
10335#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LO_LBN 288
10336#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LO_WIDTH 32
10337#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_HI_OFST 40
10338#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_HI_LEN 4
10339#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_HI_LBN 320
10340#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_HI_WIDTH 32
10341#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MINNUM 1
10342#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MAXNUM 64
10343#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MAXNUM_MCDI2 64
10344
10345/* MC_CMD_INIT_EVQ_OUT msgresponse */
10346#define MC_CMD_INIT_EVQ_OUT_LEN 4
10347/* Only valid if INTRFLAG was true */
10348#define MC_CMD_INIT_EVQ_OUT_IRQ_OFST 0
10349#define MC_CMD_INIT_EVQ_OUT_IRQ_LEN 4
10350
10351/* MC_CMD_INIT_EVQ_V2_IN msgrequest */
10352#define MC_CMD_INIT_EVQ_V2_IN_LENMIN 44
10353#define MC_CMD_INIT_EVQ_V2_IN_LENMAX 548
10354#define MC_CMD_INIT_EVQ_V2_IN_LENMAX_MCDI2 548
10355#define MC_CMD_INIT_EVQ_V2_IN_LEN(num) (36+8*(num))
10356#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_NUM(len) (((len)-36)/8)
10357/* Size, in entries */
10358#define MC_CMD_INIT_EVQ_V2_IN_SIZE_OFST 0
10359#define MC_CMD_INIT_EVQ_V2_IN_SIZE_LEN 4
10360/* Desired instance. Must be set to a specific instance, which is a function
10361 * local queue index. The calling client must be the currently-assigned user of
10362 * this VI (see MC_CMD_SET_VI_USER).
10363 */
10364#define MC_CMD_INIT_EVQ_V2_IN_INSTANCE_OFST 4
10365#define MC_CMD_INIT_EVQ_V2_IN_INSTANCE_LEN 4
10366/* The initial timer value. The load value is ignored if the timer mode is DIS.
10367 */
10368#define MC_CMD_INIT_EVQ_V2_IN_TMR_LOAD_OFST 8
10369#define MC_CMD_INIT_EVQ_V2_IN_TMR_LOAD_LEN 4
10370/* The reload value is ignored in one-shot modes */
10371#define MC_CMD_INIT_EVQ_V2_IN_TMR_RELOAD_OFST 12
10372#define MC_CMD_INIT_EVQ_V2_IN_TMR_RELOAD_LEN 4
10373/* tbd */
10374#define MC_CMD_INIT_EVQ_V2_IN_FLAGS_OFST 16
10375#define MC_CMD_INIT_EVQ_V2_IN_FLAGS_LEN 4
10376#define MC_CMD_INIT_EVQ_V2_IN_FLAG_INTERRUPTING_OFST 16
10377#define MC_CMD_INIT_EVQ_V2_IN_FLAG_INTERRUPTING_LBN 0
10378#define MC_CMD_INIT_EVQ_V2_IN_FLAG_INTERRUPTING_WIDTH 1
10379#define MC_CMD_INIT_EVQ_V2_IN_FLAG_RPTR_DOS_OFST 16
10380#define MC_CMD_INIT_EVQ_V2_IN_FLAG_RPTR_DOS_LBN 1
10381#define MC_CMD_INIT_EVQ_V2_IN_FLAG_RPTR_DOS_WIDTH 1
10382#define MC_CMD_INIT_EVQ_V2_IN_FLAG_INT_ARMD_OFST 16
10383#define MC_CMD_INIT_EVQ_V2_IN_FLAG_INT_ARMD_LBN 2
10384#define MC_CMD_INIT_EVQ_V2_IN_FLAG_INT_ARMD_WIDTH 1
10385#define MC_CMD_INIT_EVQ_V2_IN_FLAG_CUT_THRU_OFST 16
10386#define MC_CMD_INIT_EVQ_V2_IN_FLAG_CUT_THRU_LBN 3
10387#define MC_CMD_INIT_EVQ_V2_IN_FLAG_CUT_THRU_WIDTH 1
10388#define MC_CMD_INIT_EVQ_V2_IN_FLAG_RX_MERGE_OFST 16
10389#define MC_CMD_INIT_EVQ_V2_IN_FLAG_RX_MERGE_LBN 4
10390#define MC_CMD_INIT_EVQ_V2_IN_FLAG_RX_MERGE_WIDTH 1
10391#define MC_CMD_INIT_EVQ_V2_IN_FLAG_TX_MERGE_OFST 16
10392#define MC_CMD_INIT_EVQ_V2_IN_FLAG_TX_MERGE_LBN 5
10393#define MC_CMD_INIT_EVQ_V2_IN_FLAG_TX_MERGE_WIDTH 1
10394#define MC_CMD_INIT_EVQ_V2_IN_FLAG_USE_TIMER_OFST 16
10395#define MC_CMD_INIT_EVQ_V2_IN_FLAG_USE_TIMER_LBN 6
10396#define MC_CMD_INIT_EVQ_V2_IN_FLAG_USE_TIMER_WIDTH 1
10397#define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_OFST 16
10398#define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_LBN 7
10399#define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_WIDTH 4
10400/* enum: All initialisation flags specified by host. */
10401#define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_MANUAL 0x0
10402/* enum: MEDFORD only. Certain initialisation flags specified by host may be
10403 * over-ridden by firmware based on licenses and firmware variant in order to
10404 * provide the lowest latency achievable. See
10405 * MC_CMD_INIT_EVQ_V2/MC_CMD_INIT_EVQ_V2_OUT/FLAGS for list of affected flags.
10406 */
10407#define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_LOW_LATENCY 0x1
10408/* enum: MEDFORD only. Certain initialisation flags specified by host may be
10409 * over-ridden by firmware based on licenses and firmware variant in order to
10410 * provide the best throughput achievable. See
10411 * MC_CMD_INIT_EVQ_V2/MC_CMD_INIT_EVQ_V2_OUT/FLAGS for list of affected flags.
10412 */
10413#define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_THROUGHPUT 0x2
10414/* enum: MEDFORD only. Certain initialisation flags may be over-ridden by
10415 * firmware based on licenses and firmware variant. See
10416 * MC_CMD_INIT_EVQ_V2/MC_CMD_INIT_EVQ_V2_OUT/FLAGS for list of affected flags.
10417 */
10418#define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_AUTO 0x3
10419#define MC_CMD_INIT_EVQ_V2_IN_FLAG_EXT_WIDTH_OFST 16
10420#define MC_CMD_INIT_EVQ_V2_IN_FLAG_EXT_WIDTH_LBN 11
10421#define MC_CMD_INIT_EVQ_V2_IN_FLAG_EXT_WIDTH_WIDTH 1
10422#define MC_CMD_INIT_EVQ_V2_IN_TMR_MODE_OFST 20
10423#define MC_CMD_INIT_EVQ_V2_IN_TMR_MODE_LEN 4
10424/* enum: Disabled */
10425#define MC_CMD_INIT_EVQ_V2_IN_TMR_MODE_DIS 0x0
10426/* enum: Immediate */
10427#define MC_CMD_INIT_EVQ_V2_IN_TMR_IMMED_START 0x1
10428/* enum: Triggered */
10429#define MC_CMD_INIT_EVQ_V2_IN_TMR_TRIG_START 0x2
10430/* enum: Hold-off */
10431#define MC_CMD_INIT_EVQ_V2_IN_TMR_INT_HLDOFF 0x3
10432/* Target EVQ for wakeups if in wakeup mode. */
10433#define MC_CMD_INIT_EVQ_V2_IN_TARGET_EVQ_OFST 24
10434#define MC_CMD_INIT_EVQ_V2_IN_TARGET_EVQ_LEN 4
10435/* Target interrupt if in interrupting mode (note union with target EVQ). Use
10436 * MC_CMD_RESOURCE_INSTANCE_ANY unless a specific one required for test
10437 * purposes.
10438 */
10439#define MC_CMD_INIT_EVQ_V2_IN_IRQ_NUM_OFST 24
10440#define MC_CMD_INIT_EVQ_V2_IN_IRQ_NUM_LEN 4
10441/* Event Counter Mode. */
10442#define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_OFST 28
10443#define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_LEN 4
10444/* enum: Disabled */
10445#define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_DIS 0x0
10446/* enum: Disabled */
10447#define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_RX 0x1
10448/* enum: Disabled */
10449#define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_TX 0x2
10450/* enum: Disabled */
10451#define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_RXTX 0x3
10452/* Event queue packet count threshold. */
10453#define MC_CMD_INIT_EVQ_V2_IN_COUNT_THRSHLD_OFST 32
10454#define MC_CMD_INIT_EVQ_V2_IN_COUNT_THRSHLD_LEN 4
10455/* 64-bit address of 4k of 4k-aligned host memory buffer */
10456#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_OFST 36
10457#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_LEN 8
10458#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_LO_OFST 36
10459#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_LO_LEN 4
10460#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_LO_LBN 288
10461#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_LO_WIDTH 32
10462#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_HI_OFST 40
10463#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_HI_LEN 4
10464#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_HI_LBN 320
10465#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_HI_WIDTH 32
10466#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_MINNUM 1
10467#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_MAXNUM 64
10468#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_MAXNUM_MCDI2 64
10469
10470/* MC_CMD_INIT_EVQ_V2_OUT msgresponse */
10471#define MC_CMD_INIT_EVQ_V2_OUT_LEN 8
10472/* Only valid if INTRFLAG was true */
10473#define MC_CMD_INIT_EVQ_V2_OUT_IRQ_OFST 0
10474#define MC_CMD_INIT_EVQ_V2_OUT_IRQ_LEN 4
10475/* Actual configuration applied on the card */
10476#define MC_CMD_INIT_EVQ_V2_OUT_FLAGS_OFST 4
10477#define MC_CMD_INIT_EVQ_V2_OUT_FLAGS_LEN 4
10478#define MC_CMD_INIT_EVQ_V2_OUT_FLAG_CUT_THRU_OFST 4
10479#define MC_CMD_INIT_EVQ_V2_OUT_FLAG_CUT_THRU_LBN 0
10480#define MC_CMD_INIT_EVQ_V2_OUT_FLAG_CUT_THRU_WIDTH 1
10481#define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RX_MERGE_OFST 4
10482#define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RX_MERGE_LBN 1
10483#define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RX_MERGE_WIDTH 1
10484#define MC_CMD_INIT_EVQ_V2_OUT_FLAG_TX_MERGE_OFST 4
10485#define MC_CMD_INIT_EVQ_V2_OUT_FLAG_TX_MERGE_LBN 2
10486#define MC_CMD_INIT_EVQ_V2_OUT_FLAG_TX_MERGE_WIDTH 1
10487#define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RXQ_FORCE_EV_MERGING_OFST 4
10488#define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RXQ_FORCE_EV_MERGING_LBN 3
10489#define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RXQ_FORCE_EV_MERGING_WIDTH 1
10490
10491/* MC_CMD_INIT_EVQ_V3_IN msgrequest: Extended request to specify per-queue
10492 * event merge timeouts.
10493 */
10494#define MC_CMD_INIT_EVQ_V3_IN_LEN 556
10495/* Size, in entries */
10496#define MC_CMD_INIT_EVQ_V3_IN_SIZE_OFST 0
10497#define MC_CMD_INIT_EVQ_V3_IN_SIZE_LEN 4
10498/* Desired instance. Must be set to a specific instance, which is a function
10499 * local queue index. The calling client must be the currently-assigned user of
10500 * this VI (see MC_CMD_SET_VI_USER).
10501 */
10502#define MC_CMD_INIT_EVQ_V3_IN_INSTANCE_OFST 4
10503#define MC_CMD_INIT_EVQ_V3_IN_INSTANCE_LEN 4
10504/* The initial timer value. The load value is ignored if the timer mode is DIS.
10505 */
10506#define MC_CMD_INIT_EVQ_V3_IN_TMR_LOAD_OFST 8
10507#define MC_CMD_INIT_EVQ_V3_IN_TMR_LOAD_LEN 4
10508/* The reload value is ignored in one-shot modes */
10509#define MC_CMD_INIT_EVQ_V3_IN_TMR_RELOAD_OFST 12
10510#define MC_CMD_INIT_EVQ_V3_IN_TMR_RELOAD_LEN 4
10511/* tbd */
10512#define MC_CMD_INIT_EVQ_V3_IN_FLAGS_OFST 16
10513#define MC_CMD_INIT_EVQ_V3_IN_FLAGS_LEN 4
10514#define MC_CMD_INIT_EVQ_V3_IN_FLAG_INTERRUPTING_OFST 16
10515#define MC_CMD_INIT_EVQ_V3_IN_FLAG_INTERRUPTING_LBN 0
10516#define MC_CMD_INIT_EVQ_V3_IN_FLAG_INTERRUPTING_WIDTH 1
10517#define MC_CMD_INIT_EVQ_V3_IN_FLAG_RPTR_DOS_OFST 16
10518#define MC_CMD_INIT_EVQ_V3_IN_FLAG_RPTR_DOS_LBN 1
10519#define MC_CMD_INIT_EVQ_V3_IN_FLAG_RPTR_DOS_WIDTH 1
10520#define MC_CMD_INIT_EVQ_V3_IN_FLAG_INT_ARMD_OFST 16
10521#define MC_CMD_INIT_EVQ_V3_IN_FLAG_INT_ARMD_LBN 2
10522#define MC_CMD_INIT_EVQ_V3_IN_FLAG_INT_ARMD_WIDTH 1
10523#define MC_CMD_INIT_EVQ_V3_IN_FLAG_CUT_THRU_OFST 16
10524#define MC_CMD_INIT_EVQ_V3_IN_FLAG_CUT_THRU_LBN 3
10525#define MC_CMD_INIT_EVQ_V3_IN_FLAG_CUT_THRU_WIDTH 1
10526#define MC_CMD_INIT_EVQ_V3_IN_FLAG_RX_MERGE_OFST 16
10527#define MC_CMD_INIT_EVQ_V3_IN_FLAG_RX_MERGE_LBN 4
10528#define MC_CMD_INIT_EVQ_V3_IN_FLAG_RX_MERGE_WIDTH 1
10529#define MC_CMD_INIT_EVQ_V3_IN_FLAG_TX_MERGE_OFST 16
10530#define MC_CMD_INIT_EVQ_V3_IN_FLAG_TX_MERGE_LBN 5
10531#define MC_CMD_INIT_EVQ_V3_IN_FLAG_TX_MERGE_WIDTH 1
10532#define MC_CMD_INIT_EVQ_V3_IN_FLAG_USE_TIMER_OFST 16
10533#define MC_CMD_INIT_EVQ_V3_IN_FLAG_USE_TIMER_LBN 6
10534#define MC_CMD_INIT_EVQ_V3_IN_FLAG_USE_TIMER_WIDTH 1
10535#define MC_CMD_INIT_EVQ_V3_IN_FLAG_TYPE_OFST 16
10536#define MC_CMD_INIT_EVQ_V3_IN_FLAG_TYPE_LBN 7
10537#define MC_CMD_INIT_EVQ_V3_IN_FLAG_TYPE_WIDTH 4
10538/* enum: All initialisation flags specified by host. */
10539#define MC_CMD_INIT_EVQ_V3_IN_FLAG_TYPE_MANUAL 0x0
10540/* enum: MEDFORD only. Certain initialisation flags specified by host may be
10541 * over-ridden by firmware based on licenses and firmware variant in order to
10542 * provide the lowest latency achievable. See
10543 * MC_CMD_INIT_EVQ_V2/MC_CMD_INIT_EVQ_V2_OUT/FLAGS for list of affected flags.
10544 */
10545#define MC_CMD_INIT_EVQ_V3_IN_FLAG_TYPE_LOW_LATENCY 0x1
10546/* enum: MEDFORD only. Certain initialisation flags specified by host may be
10547 * over-ridden by firmware based on licenses and firmware variant in order to
10548 * provide the best throughput achievable. See
10549 * MC_CMD_INIT_EVQ_V2/MC_CMD_INIT_EVQ_V2_OUT/FLAGS for list of affected flags.
10550 */
10551#define MC_CMD_INIT_EVQ_V3_IN_FLAG_TYPE_THROUGHPUT 0x2
10552/* enum: MEDFORD only. Certain initialisation flags may be over-ridden by
10553 * firmware based on licenses and firmware variant. See
10554 * MC_CMD_INIT_EVQ_V2/MC_CMD_INIT_EVQ_V2_OUT/FLAGS for list of affected flags.
10555 */
10556#define MC_CMD_INIT_EVQ_V3_IN_FLAG_TYPE_AUTO 0x3
10557#define MC_CMD_INIT_EVQ_V3_IN_FLAG_EXT_WIDTH_OFST 16
10558#define MC_CMD_INIT_EVQ_V3_IN_FLAG_EXT_WIDTH_LBN 11
10559#define MC_CMD_INIT_EVQ_V3_IN_FLAG_EXT_WIDTH_WIDTH 1
10560#define MC_CMD_INIT_EVQ_V3_IN_TMR_MODE_OFST 20
10561#define MC_CMD_INIT_EVQ_V3_IN_TMR_MODE_LEN 4
10562/* enum: Disabled */
10563#define MC_CMD_INIT_EVQ_V3_IN_TMR_MODE_DIS 0x0
10564/* enum: Immediate */
10565#define MC_CMD_INIT_EVQ_V3_IN_TMR_IMMED_START 0x1
10566/* enum: Triggered */
10567#define MC_CMD_INIT_EVQ_V3_IN_TMR_TRIG_START 0x2
10568/* enum: Hold-off */
10569#define MC_CMD_INIT_EVQ_V3_IN_TMR_INT_HLDOFF 0x3
10570/* Target EVQ for wakeups if in wakeup mode. */
10571#define MC_CMD_INIT_EVQ_V3_IN_TARGET_EVQ_OFST 24
10572#define MC_CMD_INIT_EVQ_V3_IN_TARGET_EVQ_LEN 4
10573/* Target interrupt if in interrupting mode (note union with target EVQ). Use
10574 * MC_CMD_RESOURCE_INSTANCE_ANY unless a specific one required for test
10575 * purposes.
10576 */
10577#define MC_CMD_INIT_EVQ_V3_IN_IRQ_NUM_OFST 24
10578#define MC_CMD_INIT_EVQ_V3_IN_IRQ_NUM_LEN 4
10579/* Event Counter Mode. */
10580#define MC_CMD_INIT_EVQ_V3_IN_COUNT_MODE_OFST 28
10581#define MC_CMD_INIT_EVQ_V3_IN_COUNT_MODE_LEN 4
10582/* enum: Disabled */
10583#define MC_CMD_INIT_EVQ_V3_IN_COUNT_MODE_DIS 0x0
10584/* enum: Disabled */
10585#define MC_CMD_INIT_EVQ_V3_IN_COUNT_MODE_RX 0x1
10586/* enum: Disabled */
10587#define MC_CMD_INIT_EVQ_V3_IN_COUNT_MODE_TX 0x2
10588/* enum: Disabled */
10589#define MC_CMD_INIT_EVQ_V3_IN_COUNT_MODE_RXTX 0x3
10590/* Event queue packet count threshold. */
10591#define MC_CMD_INIT_EVQ_V3_IN_COUNT_THRSHLD_OFST 32
10592#define MC_CMD_INIT_EVQ_V3_IN_COUNT_THRSHLD_LEN 4
10593/* 64-bit address of 4k of 4k-aligned host memory buffer */
10594#define MC_CMD_INIT_EVQ_V3_IN_DMA_ADDR_OFST 36
10595#define MC_CMD_INIT_EVQ_V3_IN_DMA_ADDR_LEN 8
10596#define MC_CMD_INIT_EVQ_V3_IN_DMA_ADDR_LO_OFST 36
10597#define MC_CMD_INIT_EVQ_V3_IN_DMA_ADDR_LO_LEN 4
10598#define MC_CMD_INIT_EVQ_V3_IN_DMA_ADDR_LO_LBN 288
10599#define MC_CMD_INIT_EVQ_V3_IN_DMA_ADDR_LO_WIDTH 32
10600#define MC_CMD_INIT_EVQ_V3_IN_DMA_ADDR_HI_OFST 40
10601#define MC_CMD_INIT_EVQ_V3_IN_DMA_ADDR_HI_LEN 4
10602#define MC_CMD_INIT_EVQ_V3_IN_DMA_ADDR_HI_LBN 320
10603#define MC_CMD_INIT_EVQ_V3_IN_DMA_ADDR_HI_WIDTH 32
10604#define MC_CMD_INIT_EVQ_V3_IN_DMA_ADDR_MINNUM 1
10605#define MC_CMD_INIT_EVQ_V3_IN_DMA_ADDR_MAXNUM 64
10606#define MC_CMD_INIT_EVQ_V3_IN_DMA_ADDR_MAXNUM_MCDI2 64
10607/* Receive event merge timeout to configure, in nanoseconds. The valid range
10608 * and granularity are device specific. Specify 0 to use the firmware's default
10609 * value. This field is ignored and per-queue merging is disabled if
10610 * MC_CMD_INIT_EVQ/MC_CMD_INIT_EVQ_IN/FLAG_RX_MERGE is not set.
10611 */
10612#define MC_CMD_INIT_EVQ_V3_IN_RX_MERGE_TIMEOUT_NS_OFST 548
10613#define MC_CMD_INIT_EVQ_V3_IN_RX_MERGE_TIMEOUT_NS_LEN 4
10614/* Transmit event merge timeout to configure, in nanoseconds. The valid range
10615 * and granularity are device specific. Specify 0 to use the firmware's default
10616 * value. This field is ignored and per-queue merging is disabled if
10617 * MC_CMD_INIT_EVQ/MC_CMD_INIT_EVQ_IN/FLAG_TX_MERGE is not set.
10618 */
10619#define MC_CMD_INIT_EVQ_V3_IN_TX_MERGE_TIMEOUT_NS_OFST 552
10620#define MC_CMD_INIT_EVQ_V3_IN_TX_MERGE_TIMEOUT_NS_LEN 4
10621
10622/* MC_CMD_INIT_EVQ_V3_OUT msgresponse */
10623#define MC_CMD_INIT_EVQ_V3_OUT_LEN 8
10624/* Only valid if INTRFLAG was true */
10625#define MC_CMD_INIT_EVQ_V3_OUT_IRQ_OFST 0
10626#define MC_CMD_INIT_EVQ_V3_OUT_IRQ_LEN 4
10627/* Actual configuration applied on the card */
10628#define MC_CMD_INIT_EVQ_V3_OUT_FLAGS_OFST 4
10629#define MC_CMD_INIT_EVQ_V3_OUT_FLAGS_LEN 4
10630#define MC_CMD_INIT_EVQ_V3_OUT_FLAG_CUT_THRU_OFST 4
10631#define MC_CMD_INIT_EVQ_V3_OUT_FLAG_CUT_THRU_LBN 0
10632#define MC_CMD_INIT_EVQ_V3_OUT_FLAG_CUT_THRU_WIDTH 1
10633#define MC_CMD_INIT_EVQ_V3_OUT_FLAG_RX_MERGE_OFST 4
10634#define MC_CMD_INIT_EVQ_V3_OUT_FLAG_RX_MERGE_LBN 1
10635#define MC_CMD_INIT_EVQ_V3_OUT_FLAG_RX_MERGE_WIDTH 1
10636#define MC_CMD_INIT_EVQ_V3_OUT_FLAG_TX_MERGE_OFST 4
10637#define MC_CMD_INIT_EVQ_V3_OUT_FLAG_TX_MERGE_LBN 2
10638#define MC_CMD_INIT_EVQ_V3_OUT_FLAG_TX_MERGE_WIDTH 1
10639#define MC_CMD_INIT_EVQ_V3_OUT_FLAG_RXQ_FORCE_EV_MERGING_OFST 4
10640#define MC_CMD_INIT_EVQ_V3_OUT_FLAG_RXQ_FORCE_EV_MERGING_LBN 3
10641#define MC_CMD_INIT_EVQ_V3_OUT_FLAG_RXQ_FORCE_EV_MERGING_WIDTH 1
10642
10643/* QUEUE_CRC_MODE structuredef */
10644#define QUEUE_CRC_MODE_LEN 1
10645#define QUEUE_CRC_MODE_MODE_LBN 0
10646#define QUEUE_CRC_MODE_MODE_WIDTH 4
10647/* enum: No CRC. */
10648#define QUEUE_CRC_MODE_NONE 0x0
10649/* enum: CRC Fiber channel over ethernet. */
10650#define QUEUE_CRC_MODE_FCOE 0x1
10651/* enum: CRC (digest) iSCSI header only. */
10652#define QUEUE_CRC_MODE_ISCSI_HDR 0x2
10653/* enum: CRC (digest) iSCSI header and payload. */
10654#define QUEUE_CRC_MODE_ISCSI 0x3
10655/* enum: CRC Fiber channel over IP over ethernet. */
10656#define QUEUE_CRC_MODE_FCOIPOE 0x4
10657/* enum: CRC MPA. */
10658#define QUEUE_CRC_MODE_MPA 0x5
10659#define QUEUE_CRC_MODE_SPARE_LBN 4
10660#define QUEUE_CRC_MODE_SPARE_WIDTH 4
10661
10662
10663/***********************************/
10664/* MC_CMD_INIT_RXQ
10665 * set up a receive queue according to the supplied parameters. The IN
10666 * arguments end with an address for each 4k of host memory required to back
10667 * the RXQ.
10668 */
10669#define MC_CMD_INIT_RXQ 0x81
10670#undef MC_CMD_0x81_PRIVILEGE_CTG
10671
10672#define MC_CMD_0x81_PRIVILEGE_CTG SRIOV_CTG_GENERAL
10673
10674/* MC_CMD_INIT_RXQ_IN msgrequest: Legacy RXQ_INIT request. Use extended version
10675 * in new code.
10676 */
10677#define MC_CMD_INIT_RXQ_IN_LENMIN 36
10678#define MC_CMD_INIT_RXQ_IN_LENMAX 252
10679#define MC_CMD_INIT_RXQ_IN_LENMAX_MCDI2 1020
10680#define MC_CMD_INIT_RXQ_IN_LEN(num) (28+8*(num))
10681#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_NUM(len) (((len)-28)/8)
10682/* Size, in entries */
10683#define MC_CMD_INIT_RXQ_IN_SIZE_OFST 0
10684#define MC_CMD_INIT_RXQ_IN_SIZE_LEN 4
10685/* The EVQ to send events to. This is an index originally specified to INIT_EVQ
10686 */
10687#define MC_CMD_INIT_RXQ_IN_TARGET_EVQ_OFST 4
10688#define MC_CMD_INIT_RXQ_IN_TARGET_EVQ_LEN 4
10689/* The value to put in the event data. Check hardware spec. for valid range. */
10690#define MC_CMD_INIT_RXQ_IN_LABEL_OFST 8
10691#define MC_CMD_INIT_RXQ_IN_LABEL_LEN 4
10692/* Desired instance. Must be set to a specific instance, which is a function
10693 * local queue index. The calling client must be the currently-assigned user of
10694 * this VI (see MC_CMD_SET_VI_USER).
10695 */
10696#define MC_CMD_INIT_RXQ_IN_INSTANCE_OFST 12
10697#define MC_CMD_INIT_RXQ_IN_INSTANCE_LEN 4
10698/* There will be more flags here. */
10699#define MC_CMD_INIT_RXQ_IN_FLAGS_OFST 16
10700#define MC_CMD_INIT_RXQ_IN_FLAGS_LEN 4
10701#define MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_OFST 16
10702#define MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_LBN 0
10703#define MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_WIDTH 1
10704#define MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_OFST 16
10705#define MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_LBN 1
10706#define MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_WIDTH 1
10707#define MC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_OFST 16
10708#define MC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_LBN 2
10709#define MC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_WIDTH 1
10710#define MC_CMD_INIT_RXQ_IN_CRC_MODE_OFST 16
10711#define MC_CMD_INIT_RXQ_IN_CRC_MODE_LBN 3
10712#define MC_CMD_INIT_RXQ_IN_CRC_MODE_WIDTH 4
10713#define MC_CMD_INIT_RXQ_IN_FLAG_CHAIN_OFST 16
10714#define MC_CMD_INIT_RXQ_IN_FLAG_CHAIN_LBN 7
10715#define MC_CMD_INIT_RXQ_IN_FLAG_CHAIN_WIDTH 1
10716#define MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_OFST 16
10717#define MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_LBN 8
10718#define MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_WIDTH 1
10719#define MC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_OFST 16
10720#define MC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_LBN 9
10721#define MC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_WIDTH 1
10722#define MC_CMD_INIT_RXQ_IN_UNUSED_OFST 16
10723#define MC_CMD_INIT_RXQ_IN_UNUSED_LBN 10
10724#define MC_CMD_INIT_RXQ_IN_UNUSED_WIDTH 1
10725/* Owner ID to use if in buffer mode (zero if physical) */
10726#define MC_CMD_INIT_RXQ_IN_OWNER_ID_OFST 20
10727#define MC_CMD_INIT_RXQ_IN_OWNER_ID_LEN 4
10728/* The port ID associated with the v-adaptor which should contain this DMAQ. */
10729#define MC_CMD_INIT_RXQ_IN_PORT_ID_OFST 24
10730#define MC_CMD_INIT_RXQ_IN_PORT_ID_LEN 4
10731/* 64-bit address of 4k of 4k-aligned host memory buffer */
10732#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_OFST 28
10733#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LEN 8
10734#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LO_OFST 28
10735#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LO_LEN 4
10736#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LO_LBN 224
10737#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LO_WIDTH 32
10738#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_HI_OFST 32
10739#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_HI_LEN 4
10740#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_HI_LBN 256
10741#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_HI_WIDTH 32
10742#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MINNUM 1
10743#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MAXNUM 28
10744#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MAXNUM_MCDI2 124
10745
10746/* MC_CMD_INIT_RXQ_EXT_IN msgrequest: Extended RXQ_INIT with additional mode
10747 * flags
10748 */
10749#define MC_CMD_INIT_RXQ_EXT_IN_LEN 544
10750/* Size, in entries */
10751#define MC_CMD_INIT_RXQ_EXT_IN_SIZE_OFST 0
10752#define MC_CMD_INIT_RXQ_EXT_IN_SIZE_LEN 4
10753/* The EVQ to send events to. This is an index originally specified to
10754 * INIT_EVQ. If DMA_MODE == PACKED_STREAM this must be equal to INSTANCE.
10755 */
10756#define MC_CMD_INIT_RXQ_EXT_IN_TARGET_EVQ_OFST 4
10757#define MC_CMD_INIT_RXQ_EXT_IN_TARGET_EVQ_LEN 4
10758/* The value to put in the event data. Check hardware spec. for valid range.
10759 * This field is ignored if DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER or DMA_MODE
10760 * == PACKED_STREAM.
10761 */
10762#define MC_CMD_INIT_RXQ_EXT_IN_LABEL_OFST 8
10763#define MC_CMD_INIT_RXQ_EXT_IN_LABEL_LEN 4
10764/* Desired instance. Must be set to a specific instance, which is a function
10765 * local queue index. The calling client must be the currently-assigned user of
10766 * this VI (see MC_CMD_SET_VI_USER).
10767 */
10768#define MC_CMD_INIT_RXQ_EXT_IN_INSTANCE_OFST 12
10769#define MC_CMD_INIT_RXQ_EXT_IN_INSTANCE_LEN 4
10770/* There will be more flags here. */
10771#define MC_CMD_INIT_RXQ_EXT_IN_FLAGS_OFST 16
10772#define MC_CMD_INIT_RXQ_EXT_IN_FLAGS_LEN 4
10773#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_BUFF_MODE_OFST 16
10774#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_BUFF_MODE_LBN 0
10775#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_BUFF_MODE_WIDTH 1
10776#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT_OFST 16
10777#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT_LBN 1
10778#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT_WIDTH 1
10779#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_TIMESTAMP_OFST 16
10780#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_TIMESTAMP_LBN 2
10781#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_TIMESTAMP_WIDTH 1
10782#define MC_CMD_INIT_RXQ_EXT_IN_CRC_MODE_OFST 16
10783#define MC_CMD_INIT_RXQ_EXT_IN_CRC_MODE_LBN 3
10784#define MC_CMD_INIT_RXQ_EXT_IN_CRC_MODE_WIDTH 4
10785#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_CHAIN_OFST 16
10786#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_CHAIN_LBN 7
10787#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_CHAIN_WIDTH 1
10788#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_PREFIX_OFST 16
10789#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_PREFIX_LBN 8
10790#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_PREFIX_WIDTH 1
10791#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER_OFST 16
10792#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER_LBN 9
10793#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER_WIDTH 1
10794#define MC_CMD_INIT_RXQ_EXT_IN_DMA_MODE_OFST 16
10795#define MC_CMD_INIT_RXQ_EXT_IN_DMA_MODE_LBN 10
10796#define MC_CMD_INIT_RXQ_EXT_IN_DMA_MODE_WIDTH 4
10797/* enum: One packet per descriptor (for normal networking) */
10798#define MC_CMD_INIT_RXQ_EXT_IN_SINGLE_PACKET 0x0
10799/* enum: Pack multiple packets into large descriptors (for SolarCapture) */
10800#define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM 0x1
10801/* enum: Pack multiple packets into large descriptors using the format designed
10802 * to maximise packet rate. This mode uses 1 "bucket" per descriptor with
10803 * multiple fixed-size packet buffers within each bucket. For a full
10804 * description see SF-119419-TC. This mode is only supported by "dpdk" datapath
10805 * firmware.
10806 */
10807#define MC_CMD_INIT_RXQ_EXT_IN_EQUAL_STRIDE_SUPER_BUFFER 0x2
10808/* enum: Deprecated name for EQUAL_STRIDE_SUPER_BUFFER. */
10809#define MC_CMD_INIT_RXQ_EXT_IN_EQUAL_STRIDE_PACKED_STREAM 0x2
10810#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_SNAPSHOT_MODE_OFST 16
10811#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_SNAPSHOT_MODE_LBN 14
10812#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_SNAPSHOT_MODE_WIDTH 1
10813#define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE_OFST 16
10814#define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE_LBN 15
10815#define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE_WIDTH 3
10816#define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_1M 0x0 /* enum */
10817#define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_512K 0x1 /* enum */
10818#define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_256K 0x2 /* enum */
10819#define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_128K 0x3 /* enum */
10820#define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_64K 0x4 /* enum */
10821#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES_OFST 16
10822#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES_LBN 18
10823#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES_WIDTH 1
10824#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_FORCE_EV_MERGING_OFST 16
10825#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_FORCE_EV_MERGING_LBN 19
10826#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_FORCE_EV_MERGING_WIDTH 1
10827#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_NO_CONT_EV_OFST 16
10828#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_NO_CONT_EV_LBN 20
10829#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_NO_CONT_EV_WIDTH 1
10830/* Owner ID to use if in buffer mode (zero if physical) */
10831#define MC_CMD_INIT_RXQ_EXT_IN_OWNER_ID_OFST 20
10832#define MC_CMD_INIT_RXQ_EXT_IN_OWNER_ID_LEN 4
10833/* The port ID associated with the v-adaptor which should contain this DMAQ. */
10834#define MC_CMD_INIT_RXQ_EXT_IN_PORT_ID_OFST 24
10835#define MC_CMD_INIT_RXQ_EXT_IN_PORT_ID_LEN 4
10836/* 64-bit address of 4k of 4k-aligned host memory buffer */
10837#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_OFST 28
10838#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LEN 8
10839#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LO_OFST 28
10840#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LO_LEN 4
10841#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LO_LBN 224
10842#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LO_WIDTH 32
10843#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_HI_OFST 32
10844#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_HI_LEN 4
10845#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_HI_LBN 256
10846#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_HI_WIDTH 32
10847#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_MINNUM 0
10848#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_MAXNUM 64
10849#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_MAXNUM_MCDI2 64
10850/* Maximum length of packet to receive, if SNAPSHOT_MODE flag is set */
10851#define MC_CMD_INIT_RXQ_EXT_IN_SNAPSHOT_LENGTH_OFST 540
10852#define MC_CMD_INIT_RXQ_EXT_IN_SNAPSHOT_LENGTH_LEN 4
10853
10854/* MC_CMD_INIT_RXQ_V3_IN msgrequest */
10855#define MC_CMD_INIT_RXQ_V3_IN_LEN 560
10856/* Size, in entries */
10857#define MC_CMD_INIT_RXQ_V3_IN_SIZE_OFST 0
10858#define MC_CMD_INIT_RXQ_V3_IN_SIZE_LEN 4
10859/* The EVQ to send events to. This is an index originally specified to
10860 * INIT_EVQ. If DMA_MODE == PACKED_STREAM this must be equal to INSTANCE.
10861 */
10862#define MC_CMD_INIT_RXQ_V3_IN_TARGET_EVQ_OFST 4
10863#define MC_CMD_INIT_RXQ_V3_IN_TARGET_EVQ_LEN 4
10864/* The value to put in the event data. Check hardware spec. for valid range.
10865 * This field is ignored if DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER or DMA_MODE
10866 * == PACKED_STREAM.
10867 */
10868#define MC_CMD_INIT_RXQ_V3_IN_LABEL_OFST 8
10869#define MC_CMD_INIT_RXQ_V3_IN_LABEL_LEN 4
10870/* Desired instance. Must be set to a specific instance, which is a function
10871 * local queue index. The calling client must be the currently-assigned user of
10872 * this VI (see MC_CMD_SET_VI_USER).
10873 */
10874#define MC_CMD_INIT_RXQ_V3_IN_INSTANCE_OFST 12
10875#define MC_CMD_INIT_RXQ_V3_IN_INSTANCE_LEN 4
10876/* There will be more flags here. */
10877#define MC_CMD_INIT_RXQ_V3_IN_FLAGS_OFST 16
10878#define MC_CMD_INIT_RXQ_V3_IN_FLAGS_LEN 4
10879#define MC_CMD_INIT_RXQ_V3_IN_FLAG_BUFF_MODE_OFST 16
10880#define MC_CMD_INIT_RXQ_V3_IN_FLAG_BUFF_MODE_LBN 0
10881#define MC_CMD_INIT_RXQ_V3_IN_FLAG_BUFF_MODE_WIDTH 1
10882#define MC_CMD_INIT_RXQ_V3_IN_FLAG_HDR_SPLIT_OFST 16
10883#define MC_CMD_INIT_RXQ_V3_IN_FLAG_HDR_SPLIT_LBN 1
10884#define MC_CMD_INIT_RXQ_V3_IN_FLAG_HDR_SPLIT_WIDTH 1
10885#define MC_CMD_INIT_RXQ_V3_IN_FLAG_TIMESTAMP_OFST 16
10886#define MC_CMD_INIT_RXQ_V3_IN_FLAG_TIMESTAMP_LBN 2
10887#define MC_CMD_INIT_RXQ_V3_IN_FLAG_TIMESTAMP_WIDTH 1
10888#define MC_CMD_INIT_RXQ_V3_IN_CRC_MODE_OFST 16
10889#define MC_CMD_INIT_RXQ_V3_IN_CRC_MODE_LBN 3
10890#define MC_CMD_INIT_RXQ_V3_IN_CRC_MODE_WIDTH 4
10891#define MC_CMD_INIT_RXQ_V3_IN_FLAG_CHAIN_OFST 16
10892#define MC_CMD_INIT_RXQ_V3_IN_FLAG_CHAIN_LBN 7
10893#define MC_CMD_INIT_RXQ_V3_IN_FLAG_CHAIN_WIDTH 1
10894#define MC_CMD_INIT_RXQ_V3_IN_FLAG_PREFIX_OFST 16
10895#define MC_CMD_INIT_RXQ_V3_IN_FLAG_PREFIX_LBN 8
10896#define MC_CMD_INIT_RXQ_V3_IN_FLAG_PREFIX_WIDTH 1
10897#define MC_CMD_INIT_RXQ_V3_IN_FLAG_DISABLE_SCATTER_OFST 16
10898#define MC_CMD_INIT_RXQ_V3_IN_FLAG_DISABLE_SCATTER_LBN 9
10899#define MC_CMD_INIT_RXQ_V3_IN_FLAG_DISABLE_SCATTER_WIDTH 1
10900#define MC_CMD_INIT_RXQ_V3_IN_DMA_MODE_OFST 16
10901#define MC_CMD_INIT_RXQ_V3_IN_DMA_MODE_LBN 10
10902#define MC_CMD_INIT_RXQ_V3_IN_DMA_MODE_WIDTH 4
10903/* enum: One packet per descriptor (for normal networking) */
10904#define MC_CMD_INIT_RXQ_V3_IN_SINGLE_PACKET 0x0
10905/* enum: Pack multiple packets into large descriptors (for SolarCapture) */
10906#define MC_CMD_INIT_RXQ_V3_IN_PACKED_STREAM 0x1
10907/* enum: Pack multiple packets into large descriptors using the format designed
10908 * to maximise packet rate. This mode uses 1 "bucket" per descriptor with
10909 * multiple fixed-size packet buffers within each bucket. For a full
10910 * description see SF-119419-TC. This mode is only supported by "dpdk" datapath
10911 * firmware.
10912 */
10913#define MC_CMD_INIT_RXQ_V3_IN_EQUAL_STRIDE_SUPER_BUFFER 0x2
10914/* enum: Deprecated name for EQUAL_STRIDE_SUPER_BUFFER. */
10915#define MC_CMD_INIT_RXQ_V3_IN_EQUAL_STRIDE_PACKED_STREAM 0x2
10916#define MC_CMD_INIT_RXQ_V3_IN_FLAG_SNAPSHOT_MODE_OFST 16
10917#define MC_CMD_INIT_RXQ_V3_IN_FLAG_SNAPSHOT_MODE_LBN 14
10918#define MC_CMD_INIT_RXQ_V3_IN_FLAG_SNAPSHOT_MODE_WIDTH 1
10919#define MC_CMD_INIT_RXQ_V3_IN_PACKED_STREAM_BUFF_SIZE_OFST 16
10920#define MC_CMD_INIT_RXQ_V3_IN_PACKED_STREAM_BUFF_SIZE_LBN 15
10921#define MC_CMD_INIT_RXQ_V3_IN_PACKED_STREAM_BUFF_SIZE_WIDTH 3
10922#define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_1M 0x0 /* enum */
10923#define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_512K 0x1 /* enum */
10924#define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_256K 0x2 /* enum */
10925#define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_128K 0x3 /* enum */
10926#define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_64K 0x4 /* enum */
10927#define MC_CMD_INIT_RXQ_V3_IN_FLAG_WANT_OUTER_CLASSES_OFST 16
10928#define MC_CMD_INIT_RXQ_V3_IN_FLAG_WANT_OUTER_CLASSES_LBN 18
10929#define MC_CMD_INIT_RXQ_V3_IN_FLAG_WANT_OUTER_CLASSES_WIDTH 1
10930#define MC_CMD_INIT_RXQ_V3_IN_FLAG_FORCE_EV_MERGING_OFST 16
10931#define MC_CMD_INIT_RXQ_V3_IN_FLAG_FORCE_EV_MERGING_LBN 19
10932#define MC_CMD_INIT_RXQ_V3_IN_FLAG_FORCE_EV_MERGING_WIDTH 1
10933#define MC_CMD_INIT_RXQ_V3_IN_FLAG_NO_CONT_EV_OFST 16
10934#define MC_CMD_INIT_RXQ_V3_IN_FLAG_NO_CONT_EV_LBN 20
10935#define MC_CMD_INIT_RXQ_V3_IN_FLAG_NO_CONT_EV_WIDTH 1
10936/* Owner ID to use if in buffer mode (zero if physical) */
10937#define MC_CMD_INIT_RXQ_V3_IN_OWNER_ID_OFST 20
10938#define MC_CMD_INIT_RXQ_V3_IN_OWNER_ID_LEN 4
10939/* The port ID associated with the v-adaptor which should contain this DMAQ. */
10940#define MC_CMD_INIT_RXQ_V3_IN_PORT_ID_OFST 24
10941#define MC_CMD_INIT_RXQ_V3_IN_PORT_ID_LEN 4
10942/* 64-bit address of 4k of 4k-aligned host memory buffer */
10943#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_OFST 28
10944#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_LEN 8
10945#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_LO_OFST 28
10946#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_LO_LEN 4
10947#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_LO_LBN 224
10948#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_LO_WIDTH 32
10949#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_HI_OFST 32
10950#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_HI_LEN 4
10951#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_HI_LBN 256
10952#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_HI_WIDTH 32
10953#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_MINNUM 0
10954#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_MAXNUM 64
10955#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_MAXNUM_MCDI2 64
10956/* Maximum length of packet to receive, if SNAPSHOT_MODE flag is set */
10957#define MC_CMD_INIT_RXQ_V3_IN_SNAPSHOT_LENGTH_OFST 540
10958#define MC_CMD_INIT_RXQ_V3_IN_SNAPSHOT_LENGTH_LEN 4
10959/* The number of packet buffers that will be contained within each
10960 * EQUAL_STRIDE_SUPER_BUFFER format bucket supplied by the driver. This field
10961 * is ignored unless DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.
10962 */
10963#define MC_CMD_INIT_RXQ_V3_IN_ES_PACKET_BUFFERS_PER_BUCKET_OFST 544
10964#define MC_CMD_INIT_RXQ_V3_IN_ES_PACKET_BUFFERS_PER_BUCKET_LEN 4
10965/* The length in bytes of the area in each packet buffer that can be written to
10966 * by the adapter. This is used to store the packet prefix and the packet
10967 * payload. This length does not include any end padding added by the driver.
10968 * This field is ignored unless DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.
10969 */
10970#define MC_CMD_INIT_RXQ_V3_IN_ES_MAX_DMA_LEN_OFST 548
10971#define MC_CMD_INIT_RXQ_V3_IN_ES_MAX_DMA_LEN_LEN 4
10972/* The length in bytes of a single packet buffer within a
10973 * EQUAL_STRIDE_SUPER_BUFFER format bucket. This field is ignored unless
10974 * DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.
10975 */
10976#define MC_CMD_INIT_RXQ_V3_IN_ES_PACKET_STRIDE_OFST 552
10977#define MC_CMD_INIT_RXQ_V3_IN_ES_PACKET_STRIDE_LEN 4
10978/* The maximum time in nanoseconds that the datapath will be backpressured if
10979 * there are no RX descriptors available. If the timeout is reached and there
10980 * are still no descriptors then the packet will be dropped. A timeout of 0
10981 * means the datapath will never be blocked. This field is ignored unless
10982 * DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.
10983 */
10984#define MC_CMD_INIT_RXQ_V3_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_OFST 556
10985#define MC_CMD_INIT_RXQ_V3_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_LEN 4
10986
10987/* MC_CMD_INIT_RXQ_V4_IN msgrequest: INIT_RXQ request with new field required
10988 * for systems with a QDMA (currently, Riverhead)
10989 */
10990#define MC_CMD_INIT_RXQ_V4_IN_LEN 564
10991/* Size, in entries */
10992#define MC_CMD_INIT_RXQ_V4_IN_SIZE_OFST 0
10993#define MC_CMD_INIT_RXQ_V4_IN_SIZE_LEN 4
10994/* The EVQ to send events to. This is an index originally specified to
10995 * INIT_EVQ. If DMA_MODE == PACKED_STREAM this must be equal to INSTANCE.
10996 */
10997#define MC_CMD_INIT_RXQ_V4_IN_TARGET_EVQ_OFST 4
10998#define MC_CMD_INIT_RXQ_V4_IN_TARGET_EVQ_LEN 4
10999/* The value to put in the event data. Check hardware spec. for valid range.
11000 * This field is ignored if DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER or DMA_MODE
11001 * == PACKED_STREAM.
11002 */
11003#define MC_CMD_INIT_RXQ_V4_IN_LABEL_OFST 8
11004#define MC_CMD_INIT_RXQ_V4_IN_LABEL_LEN 4
11005/* Desired instance. Must be set to a specific instance, which is a function
11006 * local queue index. The calling client must be the currently-assigned user of
11007 * this VI (see MC_CMD_SET_VI_USER).
11008 */
11009#define MC_CMD_INIT_RXQ_V4_IN_INSTANCE_OFST 12
11010#define MC_CMD_INIT_RXQ_V4_IN_INSTANCE_LEN 4
11011/* There will be more flags here. */
11012#define MC_CMD_INIT_RXQ_V4_IN_FLAGS_OFST 16
11013#define MC_CMD_INIT_RXQ_V4_IN_FLAGS_LEN 4
11014#define MC_CMD_INIT_RXQ_V4_IN_FLAG_BUFF_MODE_OFST 16
11015#define MC_CMD_INIT_RXQ_V4_IN_FLAG_BUFF_MODE_LBN 0
11016#define MC_CMD_INIT_RXQ_V4_IN_FLAG_BUFF_MODE_WIDTH 1
11017#define MC_CMD_INIT_RXQ_V4_IN_FLAG_HDR_SPLIT_OFST 16
11018#define MC_CMD_INIT_RXQ_V4_IN_FLAG_HDR_SPLIT_LBN 1
11019#define MC_CMD_INIT_RXQ_V4_IN_FLAG_HDR_SPLIT_WIDTH 1
11020#define MC_CMD_INIT_RXQ_V4_IN_FLAG_TIMESTAMP_OFST 16
11021#define MC_CMD_INIT_RXQ_V4_IN_FLAG_TIMESTAMP_LBN 2
11022#define MC_CMD_INIT_RXQ_V4_IN_FLAG_TIMESTAMP_WIDTH 1
11023#define MC_CMD_INIT_RXQ_V4_IN_CRC_MODE_OFST 16
11024#define MC_CMD_INIT_RXQ_V4_IN_CRC_MODE_LBN 3
11025#define MC_CMD_INIT_RXQ_V4_IN_CRC_MODE_WIDTH 4
11026#define MC_CMD_INIT_RXQ_V4_IN_FLAG_CHAIN_OFST 16
11027#define MC_CMD_INIT_RXQ_V4_IN_FLAG_CHAIN_LBN 7
11028#define MC_CMD_INIT_RXQ_V4_IN_FLAG_CHAIN_WIDTH 1
11029#define MC_CMD_INIT_RXQ_V4_IN_FLAG_PREFIX_OFST 16
11030#define MC_CMD_INIT_RXQ_V4_IN_FLAG_PREFIX_LBN 8
11031#define MC_CMD_INIT_RXQ_V4_IN_FLAG_PREFIX_WIDTH 1
11032#define MC_CMD_INIT_RXQ_V4_IN_FLAG_DISABLE_SCATTER_OFST 16
11033#define MC_CMD_INIT_RXQ_V4_IN_FLAG_DISABLE_SCATTER_LBN 9
11034#define MC_CMD_INIT_RXQ_V4_IN_FLAG_DISABLE_SCATTER_WIDTH 1
11035#define MC_CMD_INIT_RXQ_V4_IN_DMA_MODE_OFST 16
11036#define MC_CMD_INIT_RXQ_V4_IN_DMA_MODE_LBN 10
11037#define MC_CMD_INIT_RXQ_V4_IN_DMA_MODE_WIDTH 4
11038/* enum: One packet per descriptor (for normal networking) */
11039#define MC_CMD_INIT_RXQ_V4_IN_SINGLE_PACKET 0x0
11040/* enum: Pack multiple packets into large descriptors (for SolarCapture) */
11041#define MC_CMD_INIT_RXQ_V4_IN_PACKED_STREAM 0x1
11042/* enum: Pack multiple packets into large descriptors using the format designed
11043 * to maximise packet rate. This mode uses 1 "bucket" per descriptor with
11044 * multiple fixed-size packet buffers within each bucket. For a full
11045 * description see SF-119419-TC. This mode is only supported by "dpdk" datapath
11046 * firmware.
11047 */
11048#define MC_CMD_INIT_RXQ_V4_IN_EQUAL_STRIDE_SUPER_BUFFER 0x2
11049/* enum: Deprecated name for EQUAL_STRIDE_SUPER_BUFFER. */
11050#define MC_CMD_INIT_RXQ_V4_IN_EQUAL_STRIDE_PACKED_STREAM 0x2
11051#define MC_CMD_INIT_RXQ_V4_IN_FLAG_SNAPSHOT_MODE_OFST 16
11052#define MC_CMD_INIT_RXQ_V4_IN_FLAG_SNAPSHOT_MODE_LBN 14
11053#define MC_CMD_INIT_RXQ_V4_IN_FLAG_SNAPSHOT_MODE_WIDTH 1
11054#define MC_CMD_INIT_RXQ_V4_IN_PACKED_STREAM_BUFF_SIZE_OFST 16
11055#define MC_CMD_INIT_RXQ_V4_IN_PACKED_STREAM_BUFF_SIZE_LBN 15
11056#define MC_CMD_INIT_RXQ_V4_IN_PACKED_STREAM_BUFF_SIZE_WIDTH 3
11057#define MC_CMD_INIT_RXQ_V4_IN_PS_BUFF_1M 0x0 /* enum */
11058#define MC_CMD_INIT_RXQ_V4_IN_PS_BUFF_512K 0x1 /* enum */
11059#define MC_CMD_INIT_RXQ_V4_IN_PS_BUFF_256K 0x2 /* enum */
11060#define MC_CMD_INIT_RXQ_V4_IN_PS_BUFF_128K 0x3 /* enum */
11061#define MC_CMD_INIT_RXQ_V4_IN_PS_BUFF_64K 0x4 /* enum */
11062#define MC_CMD_INIT_RXQ_V4_IN_FLAG_WANT_OUTER_CLASSES_OFST 16
11063#define MC_CMD_INIT_RXQ_V4_IN_FLAG_WANT_OUTER_CLASSES_LBN 18
11064#define MC_CMD_INIT_RXQ_V4_IN_FLAG_WANT_OUTER_CLASSES_WIDTH 1
11065#define MC_CMD_INIT_RXQ_V4_IN_FLAG_FORCE_EV_MERGING_OFST 16
11066#define MC_CMD_INIT_RXQ_V4_IN_FLAG_FORCE_EV_MERGING_LBN 19
11067#define MC_CMD_INIT_RXQ_V4_IN_FLAG_FORCE_EV_MERGING_WIDTH 1
11068#define MC_CMD_INIT_RXQ_V4_IN_FLAG_NO_CONT_EV_OFST 16
11069#define MC_CMD_INIT_RXQ_V4_IN_FLAG_NO_CONT_EV_LBN 20
11070#define MC_CMD_INIT_RXQ_V4_IN_FLAG_NO_CONT_EV_WIDTH 1
11071/* Owner ID to use if in buffer mode (zero if physical) */
11072#define MC_CMD_INIT_RXQ_V4_IN_OWNER_ID_OFST 20
11073#define MC_CMD_INIT_RXQ_V4_IN_OWNER_ID_LEN 4
11074/* The port ID associated with the v-adaptor which should contain this DMAQ. */
11075#define MC_CMD_INIT_RXQ_V4_IN_PORT_ID_OFST 24
11076#define MC_CMD_INIT_RXQ_V4_IN_PORT_ID_LEN 4
11077/* 64-bit address of 4k of 4k-aligned host memory buffer */
11078#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_OFST 28
11079#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_LEN 8
11080#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_LO_OFST 28
11081#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_LO_LEN 4
11082#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_LO_LBN 224
11083#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_LO_WIDTH 32
11084#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_HI_OFST 32
11085#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_HI_LEN 4
11086#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_HI_LBN 256
11087#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_HI_WIDTH 32
11088#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_MINNUM 0
11089#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_MAXNUM 64
11090#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_MAXNUM_MCDI2 64
11091/* Maximum length of packet to receive, if SNAPSHOT_MODE flag is set */
11092#define MC_CMD_INIT_RXQ_V4_IN_SNAPSHOT_LENGTH_OFST 540
11093#define MC_CMD_INIT_RXQ_V4_IN_SNAPSHOT_LENGTH_LEN 4
11094/* The number of packet buffers that will be contained within each
11095 * EQUAL_STRIDE_SUPER_BUFFER format bucket supplied by the driver. This field
11096 * is ignored unless DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.
11097 */
11098#define MC_CMD_INIT_RXQ_V4_IN_ES_PACKET_BUFFERS_PER_BUCKET_OFST 544
11099#define MC_CMD_INIT_RXQ_V4_IN_ES_PACKET_BUFFERS_PER_BUCKET_LEN 4
11100/* The length in bytes of the area in each packet buffer that can be written to
11101 * by the adapter. This is used to store the packet prefix and the packet
11102 * payload. This length does not include any end padding added by the driver.
11103 * This field is ignored unless DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.
11104 */
11105#define MC_CMD_INIT_RXQ_V4_IN_ES_MAX_DMA_LEN_OFST 548
11106#define MC_CMD_INIT_RXQ_V4_IN_ES_MAX_DMA_LEN_LEN 4
11107/* The length in bytes of a single packet buffer within a
11108 * EQUAL_STRIDE_SUPER_BUFFER format bucket. This field is ignored unless
11109 * DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.
11110 */
11111#define MC_CMD_INIT_RXQ_V4_IN_ES_PACKET_STRIDE_OFST 552
11112#define MC_CMD_INIT_RXQ_V4_IN_ES_PACKET_STRIDE_LEN 4
11113/* The maximum time in nanoseconds that the datapath will be backpressured if
11114 * there are no RX descriptors available. If the timeout is reached and there
11115 * are still no descriptors then the packet will be dropped. A timeout of 0
11116 * means the datapath will never be blocked. This field is ignored unless
11117 * DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.
11118 */
11119#define MC_CMD_INIT_RXQ_V4_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_OFST 556
11120#define MC_CMD_INIT_RXQ_V4_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_LEN 4
11121/* V4 message data */
11122#define MC_CMD_INIT_RXQ_V4_IN_V4_DATA_OFST 560
11123#define MC_CMD_INIT_RXQ_V4_IN_V4_DATA_LEN 4
11124/* Size in bytes of buffers attached to descriptors posted to this queue. Set
11125 * to zero if using this message on non-QDMA based platforms. Currently in
11126 * Riverhead there is a global limit of eight different buffer sizes across all
11127 * active queues. A 2KB and 4KB buffer is guaranteed to be available, but a
11128 * request for a different buffer size will fail if there are already eight
11129 * other buffer sizes in use. In future Riverhead this limit will go away and
11130 * any size will be accepted.
11131 */
11132#define MC_CMD_INIT_RXQ_V4_IN_BUFFER_SIZE_BYTES_OFST 560
11133#define MC_CMD_INIT_RXQ_V4_IN_BUFFER_SIZE_BYTES_LEN 4
11134
11135/* MC_CMD_INIT_RXQ_V5_IN msgrequest: INIT_RXQ request with ability to request a
11136 * different RX packet prefix
11137 */
11138#define MC_CMD_INIT_RXQ_V5_IN_LEN 568
11139/* Size, in entries */
11140#define MC_CMD_INIT_RXQ_V5_IN_SIZE_OFST 0
11141#define MC_CMD_INIT_RXQ_V5_IN_SIZE_LEN 4
11142/* The EVQ to send events to. This is an index originally specified to
11143 * INIT_EVQ. If DMA_MODE == PACKED_STREAM this must be equal to INSTANCE.
11144 */
11145#define MC_CMD_INIT_RXQ_V5_IN_TARGET_EVQ_OFST 4
11146#define MC_CMD_INIT_RXQ_V5_IN_TARGET_EVQ_LEN 4
11147/* The value to put in the event data. Check hardware spec. for valid range.
11148 * This field is ignored if DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER or DMA_MODE
11149 * == PACKED_STREAM.
11150 */
11151#define MC_CMD_INIT_RXQ_V5_IN_LABEL_OFST 8
11152#define MC_CMD_INIT_RXQ_V5_IN_LABEL_LEN 4
11153/* Desired instance. Must be set to a specific instance, which is a function
11154 * local queue index. The calling client must be the currently-assigned user of
11155 * this VI (see MC_CMD_SET_VI_USER).
11156 */
11157#define MC_CMD_INIT_RXQ_V5_IN_INSTANCE_OFST 12
11158#define MC_CMD_INIT_RXQ_V5_IN_INSTANCE_LEN 4
11159/* There will be more flags here. */
11160#define MC_CMD_INIT_RXQ_V5_IN_FLAGS_OFST 16
11161#define MC_CMD_INIT_RXQ_V5_IN_FLAGS_LEN 4
11162#define MC_CMD_INIT_RXQ_V5_IN_FLAG_BUFF_MODE_OFST 16
11163#define MC_CMD_INIT_RXQ_V5_IN_FLAG_BUFF_MODE_LBN 0
11164#define MC_CMD_INIT_RXQ_V5_IN_FLAG_BUFF_MODE_WIDTH 1
11165#define MC_CMD_INIT_RXQ_V5_IN_FLAG_HDR_SPLIT_OFST 16
11166#define MC_CMD_INIT_RXQ_V5_IN_FLAG_HDR_SPLIT_LBN 1
11167#define MC_CMD_INIT_RXQ_V5_IN_FLAG_HDR_SPLIT_WIDTH 1
11168#define MC_CMD_INIT_RXQ_V5_IN_FLAG_TIMESTAMP_OFST 16
11169#define MC_CMD_INIT_RXQ_V5_IN_FLAG_TIMESTAMP_LBN 2
11170#define MC_CMD_INIT_RXQ_V5_IN_FLAG_TIMESTAMP_WIDTH 1
11171#define MC_CMD_INIT_RXQ_V5_IN_CRC_MODE_OFST 16
11172#define MC_CMD_INIT_RXQ_V5_IN_CRC_MODE_LBN 3
11173#define MC_CMD_INIT_RXQ_V5_IN_CRC_MODE_WIDTH 4
11174#define MC_CMD_INIT_RXQ_V5_IN_FLAG_CHAIN_OFST 16
11175#define MC_CMD_INIT_RXQ_V5_IN_FLAG_CHAIN_LBN 7
11176#define MC_CMD_INIT_RXQ_V5_IN_FLAG_CHAIN_WIDTH 1
11177#define MC_CMD_INIT_RXQ_V5_IN_FLAG_PREFIX_OFST 16
11178#define MC_CMD_INIT_RXQ_V5_IN_FLAG_PREFIX_LBN 8
11179#define MC_CMD_INIT_RXQ_V5_IN_FLAG_PREFIX_WIDTH 1
11180#define MC_CMD_INIT_RXQ_V5_IN_FLAG_DISABLE_SCATTER_OFST 16
11181#define MC_CMD_INIT_RXQ_V5_IN_FLAG_DISABLE_SCATTER_LBN 9
11182#define MC_CMD_INIT_RXQ_V5_IN_FLAG_DISABLE_SCATTER_WIDTH 1
11183#define MC_CMD_INIT_RXQ_V5_IN_DMA_MODE_OFST 16
11184#define MC_CMD_INIT_RXQ_V5_IN_DMA_MODE_LBN 10
11185#define MC_CMD_INIT_RXQ_V5_IN_DMA_MODE_WIDTH 4
11186/* enum: One packet per descriptor (for normal networking) */
11187#define MC_CMD_INIT_RXQ_V5_IN_SINGLE_PACKET 0x0
11188/* enum: Pack multiple packets into large descriptors (for SolarCapture) */
11189#define MC_CMD_INIT_RXQ_V5_IN_PACKED_STREAM 0x1
11190/* enum: Pack multiple packets into large descriptors using the format designed
11191 * to maximise packet rate. This mode uses 1 "bucket" per descriptor with
11192 * multiple fixed-size packet buffers within each bucket. For a full
11193 * description see SF-119419-TC. This mode is only supported by "dpdk" datapath
11194 * firmware.
11195 */
11196#define MC_CMD_INIT_RXQ_V5_IN_EQUAL_STRIDE_SUPER_BUFFER 0x2
11197/* enum: Deprecated name for EQUAL_STRIDE_SUPER_BUFFER. */
11198#define MC_CMD_INIT_RXQ_V5_IN_EQUAL_STRIDE_PACKED_STREAM 0x2
11199#define MC_CMD_INIT_RXQ_V5_IN_FLAG_SNAPSHOT_MODE_OFST 16
11200#define MC_CMD_INIT_RXQ_V5_IN_FLAG_SNAPSHOT_MODE_LBN 14
11201#define MC_CMD_INIT_RXQ_V5_IN_FLAG_SNAPSHOT_MODE_WIDTH 1
11202#define MC_CMD_INIT_RXQ_V5_IN_PACKED_STREAM_BUFF_SIZE_OFST 16
11203#define MC_CMD_INIT_RXQ_V5_IN_PACKED_STREAM_BUFF_SIZE_LBN 15
11204#define MC_CMD_INIT_RXQ_V5_IN_PACKED_STREAM_BUFF_SIZE_WIDTH 3
11205#define MC_CMD_INIT_RXQ_V5_IN_PS_BUFF_1M 0x0 /* enum */
11206#define MC_CMD_INIT_RXQ_V5_IN_PS_BUFF_512K 0x1 /* enum */
11207#define MC_CMD_INIT_RXQ_V5_IN_PS_BUFF_256K 0x2 /* enum */
11208#define MC_CMD_INIT_RXQ_V5_IN_PS_BUFF_128K 0x3 /* enum */
11209#define MC_CMD_INIT_RXQ_V5_IN_PS_BUFF_64K 0x4 /* enum */
11210#define MC_CMD_INIT_RXQ_V5_IN_FLAG_WANT_OUTER_CLASSES_OFST 16
11211#define MC_CMD_INIT_RXQ_V5_IN_FLAG_WANT_OUTER_CLASSES_LBN 18
11212#define MC_CMD_INIT_RXQ_V5_IN_FLAG_WANT_OUTER_CLASSES_WIDTH 1
11213#define MC_CMD_INIT_RXQ_V5_IN_FLAG_FORCE_EV_MERGING_OFST 16
11214#define MC_CMD_INIT_RXQ_V5_IN_FLAG_FORCE_EV_MERGING_LBN 19
11215#define MC_CMD_INIT_RXQ_V5_IN_FLAG_FORCE_EV_MERGING_WIDTH 1
11216#define MC_CMD_INIT_RXQ_V5_IN_FLAG_NO_CONT_EV_OFST 16
11217#define MC_CMD_INIT_RXQ_V5_IN_FLAG_NO_CONT_EV_LBN 20
11218#define MC_CMD_INIT_RXQ_V5_IN_FLAG_NO_CONT_EV_WIDTH 1
11219/* Owner ID to use if in buffer mode (zero if physical) */
11220#define MC_CMD_INIT_RXQ_V5_IN_OWNER_ID_OFST 20
11221#define MC_CMD_INIT_RXQ_V5_IN_OWNER_ID_LEN 4
11222/* The port ID associated with the v-adaptor which should contain this DMAQ. */
11223#define MC_CMD_INIT_RXQ_V5_IN_PORT_ID_OFST 24
11224#define MC_CMD_INIT_RXQ_V5_IN_PORT_ID_LEN 4
11225/* 64-bit address of 4k of 4k-aligned host memory buffer */
11226#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_OFST 28
11227#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_LEN 8
11228#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_LO_OFST 28
11229#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_LO_LEN 4
11230#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_LO_LBN 224
11231#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_LO_WIDTH 32
11232#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_HI_OFST 32
11233#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_HI_LEN 4
11234#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_HI_LBN 256
11235#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_HI_WIDTH 32
11236#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_MINNUM 0
11237#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_MAXNUM 64
11238#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_MAXNUM_MCDI2 64
11239/* Maximum length of packet to receive, if SNAPSHOT_MODE flag is set */
11240#define MC_CMD_INIT_RXQ_V5_IN_SNAPSHOT_LENGTH_OFST 540
11241#define MC_CMD_INIT_RXQ_V5_IN_SNAPSHOT_LENGTH_LEN 4
11242/* The number of packet buffers that will be contained within each
11243 * EQUAL_STRIDE_SUPER_BUFFER format bucket supplied by the driver. This field
11244 * is ignored unless DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.
11245 */
11246#define MC_CMD_INIT_RXQ_V5_IN_ES_PACKET_BUFFERS_PER_BUCKET_OFST 544
11247#define MC_CMD_INIT_RXQ_V5_IN_ES_PACKET_BUFFERS_PER_BUCKET_LEN 4
11248/* The length in bytes of the area in each packet buffer that can be written to
11249 * by the adapter. This is used to store the packet prefix and the packet
11250 * payload. This length does not include any end padding added by the driver.
11251 * This field is ignored unless DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.
11252 */
11253#define MC_CMD_INIT_RXQ_V5_IN_ES_MAX_DMA_LEN_OFST 548
11254#define MC_CMD_INIT_RXQ_V5_IN_ES_MAX_DMA_LEN_LEN 4
11255/* The length in bytes of a single packet buffer within a
11256 * EQUAL_STRIDE_SUPER_BUFFER format bucket. This field is ignored unless
11257 * DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.
11258 */
11259#define MC_CMD_INIT_RXQ_V5_IN_ES_PACKET_STRIDE_OFST 552
11260#define MC_CMD_INIT_RXQ_V5_IN_ES_PACKET_STRIDE_LEN 4
11261/* The maximum time in nanoseconds that the datapath will be backpressured if
11262 * there are no RX descriptors available. If the timeout is reached and there
11263 * are still no descriptors then the packet will be dropped. A timeout of 0
11264 * means the datapath will never be blocked. This field is ignored unless
11265 * DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.
11266 */
11267#define MC_CMD_INIT_RXQ_V5_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_OFST 556
11268#define MC_CMD_INIT_RXQ_V5_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_LEN 4
11269/* V4 message data */
11270#define MC_CMD_INIT_RXQ_V5_IN_V4_DATA_OFST 560
11271#define MC_CMD_INIT_RXQ_V5_IN_V4_DATA_LEN 4
11272/* Size in bytes of buffers attached to descriptors posted to this queue. Set
11273 * to zero if using this message on non-QDMA based platforms. Currently in
11274 * Riverhead there is a global limit of eight different buffer sizes across all
11275 * active queues. A 2KB and 4KB buffer is guaranteed to be available, but a
11276 * request for a different buffer size will fail if there are already eight
11277 * other buffer sizes in use. In future Riverhead this limit will go away and
11278 * any size will be accepted.
11279 */
11280#define MC_CMD_INIT_RXQ_V5_IN_BUFFER_SIZE_BYTES_OFST 560
11281#define MC_CMD_INIT_RXQ_V5_IN_BUFFER_SIZE_BYTES_LEN 4
11282/* Prefix id for the RX prefix format to use on packets delivered this queue.
11283 * Zero is always a valid prefix id and means the default prefix format
11284 * documented for the platform. Other prefix ids can be obtained by calling
11285 * MC_CMD_GET_RX_PREFIX_ID with a requested set of prefix fields.
11286 */
11287#define MC_CMD_INIT_RXQ_V5_IN_RX_PREFIX_ID_OFST 564
11288#define MC_CMD_INIT_RXQ_V5_IN_RX_PREFIX_ID_LEN 4
11289
11290/* MC_CMD_INIT_RXQ_OUT msgresponse */
11291#define MC_CMD_INIT_RXQ_OUT_LEN 0
11292
11293/* MC_CMD_INIT_RXQ_EXT_OUT msgresponse */
11294#define MC_CMD_INIT_RXQ_EXT_OUT_LEN 0
11295
11296/* MC_CMD_INIT_RXQ_V3_OUT msgresponse */
11297#define MC_CMD_INIT_RXQ_V3_OUT_LEN 0
11298
11299/* MC_CMD_INIT_RXQ_V4_OUT msgresponse */
11300#define MC_CMD_INIT_RXQ_V4_OUT_LEN 0
11301
11302/* MC_CMD_INIT_RXQ_V5_OUT msgresponse */
11303#define MC_CMD_INIT_RXQ_V5_OUT_LEN 0
11304
11305
11306/***********************************/
11307/* MC_CMD_INIT_TXQ
11308 */
11309#define MC_CMD_INIT_TXQ 0x82
11310#undef MC_CMD_0x82_PRIVILEGE_CTG
11311
11312#define MC_CMD_0x82_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11313
11314/* MC_CMD_INIT_TXQ_IN msgrequest: Legacy INIT_TXQ request. Use extended version
11315 * in new code.
11316 */
11317#define MC_CMD_INIT_TXQ_IN_LENMIN 36
11318#define MC_CMD_INIT_TXQ_IN_LENMAX 252
11319#define MC_CMD_INIT_TXQ_IN_LENMAX_MCDI2 1020
11320#define MC_CMD_INIT_TXQ_IN_LEN(num) (28+8*(num))
11321#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_NUM(len) (((len)-28)/8)
11322/* Size, in entries */
11323#define MC_CMD_INIT_TXQ_IN_SIZE_OFST 0
11324#define MC_CMD_INIT_TXQ_IN_SIZE_LEN 4
11325/* The EVQ to send events to. This is an index originally specified to
11326 * INIT_EVQ.
11327 */
11328#define MC_CMD_INIT_TXQ_IN_TARGET_EVQ_OFST 4
11329#define MC_CMD_INIT_TXQ_IN_TARGET_EVQ_LEN 4
11330/* The value to put in the event data. Check hardware spec. for valid range. */
11331#define MC_CMD_INIT_TXQ_IN_LABEL_OFST 8
11332#define MC_CMD_INIT_TXQ_IN_LABEL_LEN 4
11333/* Desired instance. Must be set to a specific instance, which is a function
11334 * local queue index. The calling client must be the currently-assigned user of
11335 * this VI (see MC_CMD_SET_VI_USER).
11336 */
11337#define MC_CMD_INIT_TXQ_IN_INSTANCE_OFST 12
11338#define MC_CMD_INIT_TXQ_IN_INSTANCE_LEN 4
11339/* There will be more flags here. */
11340#define MC_CMD_INIT_TXQ_IN_FLAGS_OFST 16
11341#define MC_CMD_INIT_TXQ_IN_FLAGS_LEN 4
11342#define MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_OFST 16
11343#define MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_LBN 0
11344#define MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_WIDTH 1
11345#define MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_OFST 16
11346#define MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_LBN 1
11347#define MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_WIDTH 1
11348#define MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_OFST 16
11349#define MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_LBN 2
11350#define MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_WIDTH 1
11351#define MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_OFST 16
11352#define MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_LBN 3
11353#define MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_WIDTH 1
11354#define MC_CMD_INIT_TXQ_IN_CRC_MODE_OFST 16
11355#define MC_CMD_INIT_TXQ_IN_CRC_MODE_LBN 4
11356#define MC_CMD_INIT_TXQ_IN_CRC_MODE_WIDTH 4
11357#define MC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_OFST 16
11358#define MC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_LBN 8
11359#define MC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_WIDTH 1
11360#define MC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_OFST 16
11361#define MC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_LBN 9
11362#define MC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_WIDTH 1
11363#define MC_CMD_INIT_TXQ_IN_FLAG_INNER_IP_CSUM_EN_OFST 16
11364#define MC_CMD_INIT_TXQ_IN_FLAG_INNER_IP_CSUM_EN_LBN 10
11365#define MC_CMD_INIT_TXQ_IN_FLAG_INNER_IP_CSUM_EN_WIDTH 1
11366#define MC_CMD_INIT_TXQ_IN_FLAG_INNER_TCP_CSUM_EN_OFST 16
11367#define MC_CMD_INIT_TXQ_IN_FLAG_INNER_TCP_CSUM_EN_LBN 11
11368#define MC_CMD_INIT_TXQ_IN_FLAG_INNER_TCP_CSUM_EN_WIDTH 1
11369/* Owner ID to use if in buffer mode (zero if physical) */
11370#define MC_CMD_INIT_TXQ_IN_OWNER_ID_OFST 20
11371#define MC_CMD_INIT_TXQ_IN_OWNER_ID_LEN 4
11372/* The port ID associated with the v-adaptor which should contain this DMAQ. */
11373#define MC_CMD_INIT_TXQ_IN_PORT_ID_OFST 24
11374#define MC_CMD_INIT_TXQ_IN_PORT_ID_LEN 4
11375/* 64-bit address of 4k of 4k-aligned host memory buffer */
11376#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_OFST 28
11377#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LEN 8
11378#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LO_OFST 28
11379#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LO_LEN 4
11380#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LO_LBN 224
11381#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LO_WIDTH 32
11382#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_HI_OFST 32
11383#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_HI_LEN 4
11384#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_HI_LBN 256
11385#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_HI_WIDTH 32
11386#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MINNUM 1
11387#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MAXNUM 28
11388#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MAXNUM_MCDI2 124
11389
11390/* MC_CMD_INIT_TXQ_EXT_IN msgrequest: Extended INIT_TXQ with additional mode
11391 * flags
11392 */
11393#define MC_CMD_INIT_TXQ_EXT_IN_LEN 544
11394/* Size, in entries */
11395#define MC_CMD_INIT_TXQ_EXT_IN_SIZE_OFST 0
11396#define MC_CMD_INIT_TXQ_EXT_IN_SIZE_LEN 4
11397/* The EVQ to send events to. This is an index originally specified to
11398 * INIT_EVQ.
11399 */
11400#define MC_CMD_INIT_TXQ_EXT_IN_TARGET_EVQ_OFST 4
11401#define MC_CMD_INIT_TXQ_EXT_IN_TARGET_EVQ_LEN 4
11402/* The value to put in the event data. Check hardware spec. for valid range. */
11403#define MC_CMD_INIT_TXQ_EXT_IN_LABEL_OFST 8
11404#define MC_CMD_INIT_TXQ_EXT_IN_LABEL_LEN 4
11405/* Desired instance. Must be set to a specific instance, which is a function
11406 * local queue index. The calling client must be the currently-assigned user of
11407 * this VI (see MC_CMD_SET_VI_USER).
11408 */
11409#define MC_CMD_INIT_TXQ_EXT_IN_INSTANCE_OFST 12
11410#define MC_CMD_INIT_TXQ_EXT_IN_INSTANCE_LEN 4
11411/* There will be more flags here. */
11412#define MC_CMD_INIT_TXQ_EXT_IN_FLAGS_OFST 16
11413#define MC_CMD_INIT_TXQ_EXT_IN_FLAGS_LEN 4
11414#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_BUFF_MODE_OFST 16
11415#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_BUFF_MODE_LBN 0
11416#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_BUFF_MODE_WIDTH 1
11417#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_IP_CSUM_DIS_OFST 16
11418#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_IP_CSUM_DIS_LBN 1
11419#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_IP_CSUM_DIS_WIDTH 1
11420#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_CSUM_DIS_OFST 16
11421#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_CSUM_DIS_LBN 2
11422#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_CSUM_DIS_WIDTH 1
11423#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_UDP_ONLY_OFST 16
11424#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_UDP_ONLY_LBN 3
11425#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_UDP_ONLY_WIDTH 1
11426#define MC_CMD_INIT_TXQ_EXT_IN_CRC_MODE_OFST 16
11427#define MC_CMD_INIT_TXQ_EXT_IN_CRC_MODE_LBN 4
11428#define MC_CMD_INIT_TXQ_EXT_IN_CRC_MODE_WIDTH 4
11429#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TIMESTAMP_OFST 16
11430#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TIMESTAMP_LBN 8
11431#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TIMESTAMP_WIDTH 1
11432#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_PACER_BYPASS_OFST 16
11433#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_PACER_BYPASS_LBN 9
11434#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_PACER_BYPASS_WIDTH 1
11435#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_IP_CSUM_EN_OFST 16
11436#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_IP_CSUM_EN_LBN 10
11437#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_IP_CSUM_EN_WIDTH 1
11438#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_TCP_CSUM_EN_OFST 16
11439#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_TCP_CSUM_EN_LBN 11
11440#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_TCP_CSUM_EN_WIDTH 1
11441#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TSOV2_EN_OFST 16
11442#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TSOV2_EN_LBN 12
11443#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TSOV2_EN_WIDTH 1
11444#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_OFST 16
11445#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_LBN 13
11446#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_WIDTH 1
11447#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_UTHRESH_OFST 16
11448#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_UTHRESH_LBN 14
11449#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_UTHRESH_WIDTH 1
11450#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_M2M_D2C_OFST 16
11451#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_M2M_D2C_LBN 15
11452#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_M2M_D2C_WIDTH 1
11453#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_DESC_PROXY_OFST 16
11454#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_DESC_PROXY_LBN 16
11455#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_DESC_PROXY_WIDTH 1
11456#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_ABS_TARGET_EVQ_OFST 16
11457#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_ABS_TARGET_EVQ_LBN 17
11458#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_ABS_TARGET_EVQ_WIDTH 1
11459/* Owner ID to use if in buffer mode (zero if physical) */
11460#define MC_CMD_INIT_TXQ_EXT_IN_OWNER_ID_OFST 20
11461#define MC_CMD_INIT_TXQ_EXT_IN_OWNER_ID_LEN 4
11462/* The port ID associated with the v-adaptor which should contain this DMAQ. */
11463#define MC_CMD_INIT_TXQ_EXT_IN_PORT_ID_OFST 24
11464#define MC_CMD_INIT_TXQ_EXT_IN_PORT_ID_LEN 4
11465/* 64-bit address of 4k of 4k-aligned host memory buffer */
11466#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_OFST 28
11467#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LEN 8
11468#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LO_OFST 28
11469#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LO_LEN 4
11470#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LO_LBN 224
11471#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LO_WIDTH 32
11472#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_HI_OFST 32
11473#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_HI_LEN 4
11474#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_HI_LBN 256
11475#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_HI_WIDTH 32
11476#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MINNUM 0
11477#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MAXNUM 64
11478#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MAXNUM_MCDI2 64
11479/* Flags related to Qbb flow control mode. */
11480#define MC_CMD_INIT_TXQ_EXT_IN_QBB_FLAGS_OFST 540
11481#define MC_CMD_INIT_TXQ_EXT_IN_QBB_FLAGS_LEN 4
11482#define MC_CMD_INIT_TXQ_EXT_IN_QBB_ENABLE_OFST 540
11483#define MC_CMD_INIT_TXQ_EXT_IN_QBB_ENABLE_LBN 0
11484#define MC_CMD_INIT_TXQ_EXT_IN_QBB_ENABLE_WIDTH 1
11485#define MC_CMD_INIT_TXQ_EXT_IN_QBB_PRIORITY_OFST 540
11486#define MC_CMD_INIT_TXQ_EXT_IN_QBB_PRIORITY_LBN 1
11487#define MC_CMD_INIT_TXQ_EXT_IN_QBB_PRIORITY_WIDTH 3
11488
11489/* MC_CMD_INIT_TXQ_OUT msgresponse */
11490#define MC_CMD_INIT_TXQ_OUT_LEN 0
11491
11492
11493/***********************************/
11494/* MC_CMD_FINI_EVQ
11495 * Teardown an EVQ.
11496 *
11497 * All DMAQs or EVQs that point to the EVQ to tear down must be torn down first
11498 * or the operation will fail with EBUSY
11499 */
11500#define MC_CMD_FINI_EVQ 0x83
11501#undef MC_CMD_0x83_PRIVILEGE_CTG
11502
11503#define MC_CMD_0x83_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11504
11505/* MC_CMD_FINI_EVQ_IN msgrequest */
11506#define MC_CMD_FINI_EVQ_IN_LEN 4
11507/* Instance of EVQ to destroy. Should be the same instance as that previously
11508 * passed to INIT_EVQ
11509 */
11510#define MC_CMD_FINI_EVQ_IN_INSTANCE_OFST 0
11511#define MC_CMD_FINI_EVQ_IN_INSTANCE_LEN 4
11512
11513/* MC_CMD_FINI_EVQ_OUT msgresponse */
11514#define MC_CMD_FINI_EVQ_OUT_LEN 0
11515
11516
11517/***********************************/
11518/* MC_CMD_FINI_RXQ
11519 * Teardown a RXQ.
11520 */
11521#define MC_CMD_FINI_RXQ 0x84
11522#undef MC_CMD_0x84_PRIVILEGE_CTG
11523
11524#define MC_CMD_0x84_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11525
11526/* MC_CMD_FINI_RXQ_IN msgrequest */
11527#define MC_CMD_FINI_RXQ_IN_LEN 4
11528/* Instance of RXQ to destroy */
11529#define MC_CMD_FINI_RXQ_IN_INSTANCE_OFST 0
11530#define MC_CMD_FINI_RXQ_IN_INSTANCE_LEN 4
11531
11532/* MC_CMD_FINI_RXQ_OUT msgresponse */
11533#define MC_CMD_FINI_RXQ_OUT_LEN 0
11534
11535
11536/***********************************/
11537/* MC_CMD_FINI_TXQ
11538 * Teardown a TXQ.
11539 */
11540#define MC_CMD_FINI_TXQ 0x85
11541#undef MC_CMD_0x85_PRIVILEGE_CTG
11542
11543#define MC_CMD_0x85_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11544
11545/* MC_CMD_FINI_TXQ_IN msgrequest */
11546#define MC_CMD_FINI_TXQ_IN_LEN 4
11547/* Instance of TXQ to destroy */
11548#define MC_CMD_FINI_TXQ_IN_INSTANCE_OFST 0
11549#define MC_CMD_FINI_TXQ_IN_INSTANCE_LEN 4
11550
11551/* MC_CMD_FINI_TXQ_OUT msgresponse */
11552#define MC_CMD_FINI_TXQ_OUT_LEN 0
11553
11554
11555/***********************************/
11556/* MC_CMD_DRIVER_EVENT
11557 * Generate an event on an EVQ belonging to the function issuing the command.
11558 */
11559#define MC_CMD_DRIVER_EVENT 0x86
11560#undef MC_CMD_0x86_PRIVILEGE_CTG
11561
11562#define MC_CMD_0x86_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11563
11564/* MC_CMD_DRIVER_EVENT_IN msgrequest */
11565#define MC_CMD_DRIVER_EVENT_IN_LEN 12
11566/* Handle of target EVQ */
11567#define MC_CMD_DRIVER_EVENT_IN_EVQ_OFST 0
11568#define MC_CMD_DRIVER_EVENT_IN_EVQ_LEN 4
11569/* Bits 0 - 63 of event */
11570#define MC_CMD_DRIVER_EVENT_IN_DATA_OFST 4
11571#define MC_CMD_DRIVER_EVENT_IN_DATA_LEN 8
11572#define MC_CMD_DRIVER_EVENT_IN_DATA_LO_OFST 4
11573#define MC_CMD_DRIVER_EVENT_IN_DATA_LO_LEN 4
11574#define MC_CMD_DRIVER_EVENT_IN_DATA_LO_LBN 32
11575#define MC_CMD_DRIVER_EVENT_IN_DATA_LO_WIDTH 32
11576#define MC_CMD_DRIVER_EVENT_IN_DATA_HI_OFST 8
11577#define MC_CMD_DRIVER_EVENT_IN_DATA_HI_LEN 4
11578#define MC_CMD_DRIVER_EVENT_IN_DATA_HI_LBN 64
11579#define MC_CMD_DRIVER_EVENT_IN_DATA_HI_WIDTH 32
11580
11581/* MC_CMD_DRIVER_EVENT_OUT msgresponse */
11582#define MC_CMD_DRIVER_EVENT_OUT_LEN 0
11583
11584
11585/***********************************/
11586/* MC_CMD_PROXY_CMD
11587 * Execute an arbitrary MCDI command on behalf of a different function, subject
11588 * to security restrictions. The command to be proxied follows immediately
11589 * afterward in the host buffer (or on the UART). This command supercedes
11590 * MC_CMD_SET_FUNC, which remains available for Siena but now deprecated.
11591 */
11592#define MC_CMD_PROXY_CMD 0x5b
11593#undef MC_CMD_0x5b_PRIVILEGE_CTG
11594
11595#define MC_CMD_0x5b_PRIVILEGE_CTG SRIOV_CTG_ADMIN
11596
11597/* MC_CMD_PROXY_CMD_IN msgrequest */
11598#define MC_CMD_PROXY_CMD_IN_LEN 4
11599/* The handle of the target function. */
11600#define MC_CMD_PROXY_CMD_IN_TARGET_OFST 0
11601#define MC_CMD_PROXY_CMD_IN_TARGET_LEN 4
11602#define MC_CMD_PROXY_CMD_IN_TARGET_PF_OFST 0
11603#define MC_CMD_PROXY_CMD_IN_TARGET_PF_LBN 0
11604#define MC_CMD_PROXY_CMD_IN_TARGET_PF_WIDTH 16
11605#define MC_CMD_PROXY_CMD_IN_TARGET_VF_OFST 0
11606#define MC_CMD_PROXY_CMD_IN_TARGET_VF_LBN 16
11607#define MC_CMD_PROXY_CMD_IN_TARGET_VF_WIDTH 16
11608#define MC_CMD_PROXY_CMD_IN_VF_NULL 0xffff /* enum */
11609
11610/* MC_CMD_PROXY_CMD_OUT msgresponse */
11611#define MC_CMD_PROXY_CMD_OUT_LEN 0
11612
11613/* MC_PROXY_STATUS_BUFFER structuredef: Host memory status buffer used to
11614 * manage proxied requests
11615 */
11616#define MC_PROXY_STATUS_BUFFER_LEN 16
11617/* Handle allocated by the firmware for this proxy transaction */
11618#define MC_PROXY_STATUS_BUFFER_HANDLE_OFST 0
11619#define MC_PROXY_STATUS_BUFFER_HANDLE_LEN 4
11620/* enum: An invalid handle. */
11621#define MC_PROXY_STATUS_BUFFER_HANDLE_INVALID 0x0
11622#define MC_PROXY_STATUS_BUFFER_HANDLE_LBN 0
11623#define MC_PROXY_STATUS_BUFFER_HANDLE_WIDTH 32
11624/* The requesting physical function number */
11625#define MC_PROXY_STATUS_BUFFER_PF_OFST 4
11626#define MC_PROXY_STATUS_BUFFER_PF_LEN 2
11627#define MC_PROXY_STATUS_BUFFER_PF_LBN 32
11628#define MC_PROXY_STATUS_BUFFER_PF_WIDTH 16
11629/* The requesting virtual function number. Set to VF_NULL if the target is a
11630 * PF.
11631 */
11632#define MC_PROXY_STATUS_BUFFER_VF_OFST 6
11633#define MC_PROXY_STATUS_BUFFER_VF_LEN 2
11634#define MC_PROXY_STATUS_BUFFER_VF_LBN 48
11635#define MC_PROXY_STATUS_BUFFER_VF_WIDTH 16
11636/* The target function RID. */
11637#define MC_PROXY_STATUS_BUFFER_RID_OFST 8
11638#define MC_PROXY_STATUS_BUFFER_RID_LEN 2
11639#define MC_PROXY_STATUS_BUFFER_RID_LBN 64
11640#define MC_PROXY_STATUS_BUFFER_RID_WIDTH 16
11641/* The status of the proxy as described in MC_CMD_PROXY_COMPLETE. */
11642#define MC_PROXY_STATUS_BUFFER_STATUS_OFST 10
11643#define MC_PROXY_STATUS_BUFFER_STATUS_LEN 2
11644#define MC_PROXY_STATUS_BUFFER_STATUS_LBN 80
11645#define MC_PROXY_STATUS_BUFFER_STATUS_WIDTH 16
11646/* If a request is authorized rather than carried out by the host, this is the
11647 * elevated privilege mask granted to the requesting function.
11648 */
11649#define MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_OFST 12
11650#define MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_LEN 4
11651#define MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_LBN 96
11652#define MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_WIDTH 32
11653
11654
11655/***********************************/
11656/* MC_CMD_PROXY_CONFIGURE
11657 * Enable/disable authorization of MCDI requests from unprivileged functions by
11658 * a designated admin function
11659 */
11660#define MC_CMD_PROXY_CONFIGURE 0x58
11661#undef MC_CMD_0x58_PRIVILEGE_CTG
11662
11663#define MC_CMD_0x58_PRIVILEGE_CTG SRIOV_CTG_ADMIN
11664
11665/* MC_CMD_PROXY_CONFIGURE_IN msgrequest */
11666#define MC_CMD_PROXY_CONFIGURE_IN_LEN 108
11667#define MC_CMD_PROXY_CONFIGURE_IN_FLAGS_OFST 0
11668#define MC_CMD_PROXY_CONFIGURE_IN_FLAGS_LEN 4
11669#define MC_CMD_PROXY_CONFIGURE_IN_ENABLE_OFST 0
11670#define MC_CMD_PROXY_CONFIGURE_IN_ENABLE_LBN 0
11671#define MC_CMD_PROXY_CONFIGURE_IN_ENABLE_WIDTH 1
11672/* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS
11673 * of blocks, each of the size REQUEST_BLOCK_SIZE.
11674 */
11675#define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_OFST 4
11676#define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LEN 8
11677#define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LO_OFST 4
11678#define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LO_LEN 4
11679#define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LO_LBN 32
11680#define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LO_WIDTH 32
11681#define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_HI_OFST 8
11682#define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_HI_LEN 4
11683#define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_HI_LBN 64
11684#define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_HI_WIDTH 32
11685/* Must be a power of 2 */
11686#define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BLOCK_SIZE_OFST 12
11687#define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BLOCK_SIZE_LEN 4
11688/* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS
11689 * of blocks, each of the size REPLY_BLOCK_SIZE.
11690 */
11691#define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_OFST 16
11692#define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LEN 8
11693#define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LO_OFST 16
11694#define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LO_LEN 4
11695#define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LO_LBN 128
11696#define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LO_WIDTH 32
11697#define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_HI_OFST 20
11698#define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_HI_LEN 4
11699#define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_HI_LBN 160
11700#define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_HI_WIDTH 32
11701/* Must be a power of 2 */
11702#define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BLOCK_SIZE_OFST 24
11703#define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BLOCK_SIZE_LEN 4
11704/* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS
11705 * of blocks, each of the size STATUS_BLOCK_SIZE. This buffer is only needed if
11706 * host intends to complete proxied operations by using MC_CMD_PROXY_CMD.
11707 */
11708#define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_OFST 28
11709#define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LEN 8
11710#define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LO_OFST 28
11711#define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LO_LEN 4
11712#define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LO_LBN 224
11713#define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LO_WIDTH 32
11714#define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_HI_OFST 32
11715#define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_HI_LEN 4
11716#define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_HI_LBN 256
11717#define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_HI_WIDTH 32
11718/* Must be a power of 2, or zero if this buffer is not provided */
11719#define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BLOCK_SIZE_OFST 36
11720#define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BLOCK_SIZE_LEN 4
11721/* Applies to all three buffers */
11722#define MC_CMD_PROXY_CONFIGURE_IN_NUM_BLOCKS_OFST 40
11723#define MC_CMD_PROXY_CONFIGURE_IN_NUM_BLOCKS_LEN 4
11724/* A bit mask defining which MCDI operations may be proxied */
11725#define MC_CMD_PROXY_CONFIGURE_IN_ALLOWED_MCDI_MASK_OFST 44
11726#define MC_CMD_PROXY_CONFIGURE_IN_ALLOWED_MCDI_MASK_LEN 64
11727
11728/* MC_CMD_PROXY_CONFIGURE_EXT_IN msgrequest */
11729#define MC_CMD_PROXY_CONFIGURE_EXT_IN_LEN 112
11730#define MC_CMD_PROXY_CONFIGURE_EXT_IN_FLAGS_OFST 0
11731#define MC_CMD_PROXY_CONFIGURE_EXT_IN_FLAGS_LEN 4
11732#define MC_CMD_PROXY_CONFIGURE_EXT_IN_ENABLE_OFST 0
11733#define MC_CMD_PROXY_CONFIGURE_EXT_IN_ENABLE_LBN 0
11734#define MC_CMD_PROXY_CONFIGURE_EXT_IN_ENABLE_WIDTH 1
11735/* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS
11736 * of blocks, each of the size REQUEST_BLOCK_SIZE.
11737 */
11738#define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_OFST 4
11739#define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_LEN 8
11740#define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_LO_OFST 4
11741#define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_LO_LEN 4
11742#define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_LO_LBN 32
11743#define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_LO_WIDTH 32
11744#define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_HI_OFST 8
11745#define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_HI_LEN 4
11746#define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_HI_LBN 64
11747#define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_HI_WIDTH 32
11748/* Must be a power of 2 */
11749#define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BLOCK_SIZE_OFST 12
11750#define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BLOCK_SIZE_LEN 4
11751/* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS
11752 * of blocks, each of the size REPLY_BLOCK_SIZE.
11753 */
11754#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_OFST 16
11755#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_LEN 8
11756#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_LO_OFST 16
11757#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_LO_LEN 4
11758#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_LO_LBN 128
11759#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_LO_WIDTH 32
11760#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_HI_OFST 20
11761#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_HI_LEN 4
11762#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_HI_LBN 160
11763#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_HI_WIDTH 32
11764/* Must be a power of 2 */
11765#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BLOCK_SIZE_OFST 24
11766#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BLOCK_SIZE_LEN 4
11767/* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS
11768 * of blocks, each of the size STATUS_BLOCK_SIZE. This buffer is only needed if
11769 * host intends to complete proxied operations by using MC_CMD_PROXY_CMD.
11770 */
11771#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_OFST 28
11772#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_LEN 8
11773#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_LO_OFST 28
11774#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_LO_LEN 4
11775#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_LO_LBN 224
11776#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_LO_WIDTH 32
11777#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_HI_OFST 32
11778#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_HI_LEN 4
11779#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_HI_LBN 256
11780#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_HI_WIDTH 32
11781/* Must be a power of 2, or zero if this buffer is not provided */
11782#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BLOCK_SIZE_OFST 36
11783#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BLOCK_SIZE_LEN 4
11784/* Applies to all three buffers */
11785#define MC_CMD_PROXY_CONFIGURE_EXT_IN_NUM_BLOCKS_OFST 40
11786#define MC_CMD_PROXY_CONFIGURE_EXT_IN_NUM_BLOCKS_LEN 4
11787/* A bit mask defining which MCDI operations may be proxied */
11788#define MC_CMD_PROXY_CONFIGURE_EXT_IN_ALLOWED_MCDI_MASK_OFST 44
11789#define MC_CMD_PROXY_CONFIGURE_EXT_IN_ALLOWED_MCDI_MASK_LEN 64
11790#define MC_CMD_PROXY_CONFIGURE_EXT_IN_RESERVED_OFST 108
11791#define MC_CMD_PROXY_CONFIGURE_EXT_IN_RESERVED_LEN 4
11792
11793/* MC_CMD_PROXY_CONFIGURE_OUT msgresponse */
11794#define MC_CMD_PROXY_CONFIGURE_OUT_LEN 0
11795
11796
11797/***********************************/
11798/* MC_CMD_PROXY_COMPLETE
11799 * Tells FW that a requested proxy operation has either been completed (by
11800 * using MC_CMD_PROXY_CMD) or authorized/declined. May only be sent by the
11801 * function that enabled proxying/authorization (by using
11802 * MC_CMD_PROXY_CONFIGURE).
11803 */
11804#define MC_CMD_PROXY_COMPLETE 0x5f
11805#undef MC_CMD_0x5f_PRIVILEGE_CTG
11806
11807#define MC_CMD_0x5f_PRIVILEGE_CTG SRIOV_CTG_ADMIN
11808
11809/* MC_CMD_PROXY_COMPLETE_IN msgrequest */
11810#define MC_CMD_PROXY_COMPLETE_IN_LEN 12
11811#define MC_CMD_PROXY_COMPLETE_IN_BLOCK_INDEX_OFST 0
11812#define MC_CMD_PROXY_COMPLETE_IN_BLOCK_INDEX_LEN 4
11813#define MC_CMD_PROXY_COMPLETE_IN_STATUS_OFST 4
11814#define MC_CMD_PROXY_COMPLETE_IN_STATUS_LEN 4
11815/* enum: The operation has been completed by using MC_CMD_PROXY_CMD, the reply
11816 * is stored in the REPLY_BUFF.
11817 */
11818#define MC_CMD_PROXY_COMPLETE_IN_COMPLETE 0x0
11819/* enum: The operation has been authorized. The originating function may now
11820 * try again.
11821 */
11822#define MC_CMD_PROXY_COMPLETE_IN_AUTHORIZED 0x1
11823/* enum: The operation has been declined. */
11824#define MC_CMD_PROXY_COMPLETE_IN_DECLINED 0x2
11825/* enum: The authorization failed because the relevant application did not
11826 * respond in time.
11827 */
11828#define MC_CMD_PROXY_COMPLETE_IN_TIMEDOUT 0x3
11829#define MC_CMD_PROXY_COMPLETE_IN_HANDLE_OFST 8
11830#define MC_CMD_PROXY_COMPLETE_IN_HANDLE_LEN 4
11831
11832/* MC_CMD_PROXY_COMPLETE_OUT msgresponse */
11833#define MC_CMD_PROXY_COMPLETE_OUT_LEN 0
11834
11835
11836/***********************************/
11837/* MC_CMD_ALLOC_BUFTBL_CHUNK
11838 * Allocate a set of buffer table entries using the specified owner ID. This
11839 * operation allocates the required buffer table entries (and fails if it
11840 * cannot do so). The buffer table entries will initially be zeroed.
11841 */
11842#define MC_CMD_ALLOC_BUFTBL_CHUNK 0x87
11843#undef MC_CMD_0x87_PRIVILEGE_CTG
11844
11845#define MC_CMD_0x87_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
11846
11847/* MC_CMD_ALLOC_BUFTBL_CHUNK_IN msgrequest */
11848#define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_LEN 8
11849/* Owner ID to use */
11850#define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_OWNER_OFST 0
11851#define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_OWNER_LEN 4
11852/* Size of buffer table pages to use, in bytes (note that only a few values are
11853 * legal on any specific hardware).
11854 */
11855#define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_PAGE_SIZE_OFST 4
11856#define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_PAGE_SIZE_LEN 4
11857
11858/* MC_CMD_ALLOC_BUFTBL_CHUNK_OUT msgresponse */
11859#define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_LEN 12
11860#define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_HANDLE_OFST 0
11861#define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_HANDLE_LEN 4
11862#define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_NUMENTRIES_OFST 4
11863#define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_NUMENTRIES_LEN 4
11864/* Buffer table IDs for use in DMA descriptors. */
11865#define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_ID_OFST 8
11866#define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_ID_LEN 4
11867
11868
11869/***********************************/
11870/* MC_CMD_PROGRAM_BUFTBL_ENTRIES
11871 * Reprogram a set of buffer table entries in the specified chunk.
11872 */
11873#define MC_CMD_PROGRAM_BUFTBL_ENTRIES 0x88
11874#undef MC_CMD_0x88_PRIVILEGE_CTG
11875
11876#define MC_CMD_0x88_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
11877
11878/* MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN msgrequest */
11879#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMIN 20
11880#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMAX 268
11881#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMAX_MCDI2 268
11882#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LEN(num) (12+8*(num))
11883#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_NUM(len) (((len)-12)/8)
11884#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_HANDLE_OFST 0
11885#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_HANDLE_LEN 4
11886/* ID */
11887#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_FIRSTID_OFST 4
11888#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_FIRSTID_LEN 4
11889/* Num entries */
11890#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_NUMENTRIES_OFST 8
11891#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_NUMENTRIES_LEN 4
11892/* Buffer table entry address */
11893#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_OFST 12
11894#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LEN 8
11895#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LO_OFST 12
11896#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LO_LEN 4
11897#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LO_LBN 96
11898#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LO_WIDTH 32
11899#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_HI_OFST 16
11900#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_HI_LEN 4
11901#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_HI_LBN 128
11902#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_HI_WIDTH 32
11903#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MINNUM 1
11904#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MAXNUM 32
11905#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MAXNUM_MCDI2 32
11906
11907/* MC_CMD_PROGRAM_BUFTBL_ENTRIES_OUT msgresponse */
11908#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_OUT_LEN 0
11909
11910
11911/***********************************/
11912/* MC_CMD_FREE_BUFTBL_CHUNK
11913 */
11914#define MC_CMD_FREE_BUFTBL_CHUNK 0x89
11915#undef MC_CMD_0x89_PRIVILEGE_CTG
11916
11917#define MC_CMD_0x89_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
11918
11919/* MC_CMD_FREE_BUFTBL_CHUNK_IN msgrequest */
11920#define MC_CMD_FREE_BUFTBL_CHUNK_IN_LEN 4
11921#define MC_CMD_FREE_BUFTBL_CHUNK_IN_HANDLE_OFST 0
11922#define MC_CMD_FREE_BUFTBL_CHUNK_IN_HANDLE_LEN 4
11923
11924/* MC_CMD_FREE_BUFTBL_CHUNK_OUT msgresponse */
11925#define MC_CMD_FREE_BUFTBL_CHUNK_OUT_LEN 0
11926
11927
11928/***********************************/
11929/* MC_CMD_FILTER_OP
11930 * Multiplexed MCDI call for filter operations
11931 */
11932#define MC_CMD_FILTER_OP 0x8a
11933#undef MC_CMD_0x8a_PRIVILEGE_CTG
11934
11935#define MC_CMD_0x8a_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11936
11937/* MC_CMD_FILTER_OP_IN msgrequest */
11938#define MC_CMD_FILTER_OP_IN_LEN 108
11939/* identifies the type of operation requested */
11940#define MC_CMD_FILTER_OP_IN_OP_OFST 0
11941#define MC_CMD_FILTER_OP_IN_OP_LEN 4
11942/* enum: single-recipient filter insert */
11943#define MC_CMD_FILTER_OP_IN_OP_INSERT 0x0
11944/* enum: single-recipient filter remove */
11945#define MC_CMD_FILTER_OP_IN_OP_REMOVE 0x1
11946/* enum: multi-recipient filter subscribe */
11947#define MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE 0x2
11948/* enum: multi-recipient filter unsubscribe */
11949#define MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE 0x3
11950/* enum: replace one recipient with another (warning - the filter handle may
11951 * change)
11952 */
11953#define MC_CMD_FILTER_OP_IN_OP_REPLACE 0x4
11954/* filter handle (for remove / unsubscribe operations) */
11955#define MC_CMD_FILTER_OP_IN_HANDLE_OFST 4
11956#define MC_CMD_FILTER_OP_IN_HANDLE_LEN 8
11957#define MC_CMD_FILTER_OP_IN_HANDLE_LO_OFST 4
11958#define MC_CMD_FILTER_OP_IN_HANDLE_LO_LEN 4
11959#define MC_CMD_FILTER_OP_IN_HANDLE_LO_LBN 32
11960#define MC_CMD_FILTER_OP_IN_HANDLE_LO_WIDTH 32
11961#define MC_CMD_FILTER_OP_IN_HANDLE_HI_OFST 8
11962#define MC_CMD_FILTER_OP_IN_HANDLE_HI_LEN 4
11963#define MC_CMD_FILTER_OP_IN_HANDLE_HI_LBN 64
11964#define MC_CMD_FILTER_OP_IN_HANDLE_HI_WIDTH 32
11965/* The port ID associated with the v-adaptor which should contain this filter.
11966 */
11967#define MC_CMD_FILTER_OP_IN_PORT_ID_OFST 12
11968#define MC_CMD_FILTER_OP_IN_PORT_ID_LEN 4
11969/* fields to include in match criteria */
11970#define MC_CMD_FILTER_OP_IN_MATCH_FIELDS_OFST 16
11971#define MC_CMD_FILTER_OP_IN_MATCH_FIELDS_LEN 4
11972#define MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_OFST 16
11973#define MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_LBN 0
11974#define MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_WIDTH 1
11975#define MC_CMD_FILTER_OP_IN_MATCH_DST_IP_OFST 16
11976#define MC_CMD_FILTER_OP_IN_MATCH_DST_IP_LBN 1
11977#define MC_CMD_FILTER_OP_IN_MATCH_DST_IP_WIDTH 1
11978#define MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_OFST 16
11979#define MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_LBN 2
11980#define MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_WIDTH 1
11981#define MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_OFST 16
11982#define MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_LBN 3
11983#define MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_WIDTH 1
11984#define MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_OFST 16
11985#define MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_LBN 4
11986#define MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_WIDTH 1
11987#define MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_OFST 16
11988#define MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_LBN 5
11989#define MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_WIDTH 1
11990#define MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_OFST 16
11991#define MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_LBN 6
11992#define MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_WIDTH 1
11993#define MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_OFST 16
11994#define MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_LBN 7
11995#define MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_WIDTH 1
11996#define MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_OFST 16
11997#define MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_LBN 8
11998#define MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_WIDTH 1
11999#define MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_OFST 16
12000#define MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_LBN 9
12001#define MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_WIDTH 1
12002#define MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_OFST 16
12003#define MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_LBN 10
12004#define MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_WIDTH 1
12005#define MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_OFST 16
12006#define MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_LBN 11
12007#define MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_WIDTH 1
12008#define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_IPV4_MCAST_DST_OFST 16
12009#define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_IPV4_MCAST_DST_LBN 29
12010#define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_IPV4_MCAST_DST_WIDTH 1
12011#define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_OFST 16
12012#define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN 30
12013#define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1
12014#define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_OFST 16
12015#define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN 31
12016#define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1
12017/* receive destination */
12018#define MC_CMD_FILTER_OP_IN_RX_DEST_OFST 20
12019#define MC_CMD_FILTER_OP_IN_RX_DEST_LEN 4
12020/* enum: drop packets */
12021#define MC_CMD_FILTER_OP_IN_RX_DEST_DROP 0x0
12022/* enum: receive to host */
12023#define MC_CMD_FILTER_OP_IN_RX_DEST_HOST 0x1
12024/* enum: receive to MC */
12025#define MC_CMD_FILTER_OP_IN_RX_DEST_MC 0x2
12026/* enum: loop back to TXDP 0 */
12027#define MC_CMD_FILTER_OP_IN_RX_DEST_TX0 0x3
12028/* enum: loop back to TXDP 1 */
12029#define MC_CMD_FILTER_OP_IN_RX_DEST_TX1 0x4
12030/* receive queue handle (for multiple queue modes, this is the base queue) */
12031#define MC_CMD_FILTER_OP_IN_RX_QUEUE_OFST 24
12032#define MC_CMD_FILTER_OP_IN_RX_QUEUE_LEN 4
12033/* receive mode */
12034#define MC_CMD_FILTER_OP_IN_RX_MODE_OFST 28
12035#define MC_CMD_FILTER_OP_IN_RX_MODE_LEN 4
12036/* enum: receive to just the specified queue */
12037#define MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE 0x0
12038/* enum: receive to multiple queues using RSS context */
12039#define MC_CMD_FILTER_OP_IN_RX_MODE_RSS 0x1
12040/* enum: receive to multiple queues using .1p mapping */
12041#define MC_CMD_FILTER_OP_IN_RX_MODE_DOT1P_MAPPING 0x2
12042/* enum: install a filter entry that will never match; for test purposes only
12043 */
12044#define MC_CMD_FILTER_OP_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000
12045/* RSS context (for RX_MODE_RSS) or .1p mapping handle (for
12046 * RX_MODE_DOT1P_MAPPING), as returned by MC_CMD_RSS_CONTEXT_ALLOC or
12047 * MC_CMD_DOT1P_MAPPING_ALLOC.
12048 */
12049#define MC_CMD_FILTER_OP_IN_RX_CONTEXT_OFST 32
12050#define MC_CMD_FILTER_OP_IN_RX_CONTEXT_LEN 4
12051/* transmit domain (reserved; set to 0) */
12052#define MC_CMD_FILTER_OP_IN_TX_DOMAIN_OFST 36
12053#define MC_CMD_FILTER_OP_IN_TX_DOMAIN_LEN 4
12054/* transmit destination (either set the MAC and/or PM bits for explicit
12055 * control, or set this field to TX_DEST_DEFAULT for sensible default
12056 * behaviour)
12057 */
12058#define MC_CMD_FILTER_OP_IN_TX_DEST_OFST 40
12059#define MC_CMD_FILTER_OP_IN_TX_DEST_LEN 4
12060/* enum: request default behaviour (based on filter type) */
12061#define MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT 0xffffffff
12062#define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_OFST 40
12063#define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_LBN 0
12064#define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_WIDTH 1
12065#define MC_CMD_FILTER_OP_IN_TX_DEST_PM_OFST 40
12066#define MC_CMD_FILTER_OP_IN_TX_DEST_PM_LBN 1
12067#define MC_CMD_FILTER_OP_IN_TX_DEST_PM_WIDTH 1
12068/* source MAC address to match (as bytes in network order) */
12069#define MC_CMD_FILTER_OP_IN_SRC_MAC_OFST 44
12070#define MC_CMD_FILTER_OP_IN_SRC_MAC_LEN 6
12071/* source port to match (as bytes in network order) */
12072#define MC_CMD_FILTER_OP_IN_SRC_PORT_OFST 50
12073#define MC_CMD_FILTER_OP_IN_SRC_PORT_LEN 2
12074/* destination MAC address to match (as bytes in network order) */
12075#define MC_CMD_FILTER_OP_IN_DST_MAC_OFST 52
12076#define MC_CMD_FILTER_OP_IN_DST_MAC_LEN 6
12077/* destination port to match (as bytes in network order) */
12078#define MC_CMD_FILTER_OP_IN_DST_PORT_OFST 58
12079#define MC_CMD_FILTER_OP_IN_DST_PORT_LEN 2
12080/* Ethernet type to match (as bytes in network order) */
12081#define MC_CMD_FILTER_OP_IN_ETHER_TYPE_OFST 60
12082#define MC_CMD_FILTER_OP_IN_ETHER_TYPE_LEN 2
12083/* Inner VLAN tag to match (as bytes in network order) */
12084#define MC_CMD_FILTER_OP_IN_INNER_VLAN_OFST 62
12085#define MC_CMD_FILTER_OP_IN_INNER_VLAN_LEN 2
12086/* Outer VLAN tag to match (as bytes in network order) */
12087#define MC_CMD_FILTER_OP_IN_OUTER_VLAN_OFST 64
12088#define MC_CMD_FILTER_OP_IN_OUTER_VLAN_LEN 2
12089/* IP protocol to match (in low byte; set high byte to 0) */
12090#define MC_CMD_FILTER_OP_IN_IP_PROTO_OFST 66
12091#define MC_CMD_FILTER_OP_IN_IP_PROTO_LEN 2
12092/* Firmware defined register 0 to match (reserved; set to 0) */
12093#define MC_CMD_FILTER_OP_IN_FWDEF0_OFST 68
12094#define MC_CMD_FILTER_OP_IN_FWDEF0_LEN 4
12095/* Firmware defined register 1 to match (reserved; set to 0) */
12096#define MC_CMD_FILTER_OP_IN_FWDEF1_OFST 72
12097#define MC_CMD_FILTER_OP_IN_FWDEF1_LEN 4
12098/* source IP address to match (as bytes in network order; set last 12 bytes to
12099 * 0 for IPv4 address)
12100 */
12101#define MC_CMD_FILTER_OP_IN_SRC_IP_OFST 76
12102#define MC_CMD_FILTER_OP_IN_SRC_IP_LEN 16
12103/* destination IP address to match (as bytes in network order; set last 12
12104 * bytes to 0 for IPv4 address)
12105 */
12106#define MC_CMD_FILTER_OP_IN_DST_IP_OFST 92
12107#define MC_CMD_FILTER_OP_IN_DST_IP_LEN 16
12108
12109/* MC_CMD_FILTER_OP_EXT_IN msgrequest: Extension to MC_CMD_FILTER_OP_IN to
12110 * include handling of VXLAN/NVGRE encapsulated frame filtering (which is
12111 * supported on Medford only).
12112 */
12113#define MC_CMD_FILTER_OP_EXT_IN_LEN 172
12114/* identifies the type of operation requested */
12115#define MC_CMD_FILTER_OP_EXT_IN_OP_OFST 0
12116#define MC_CMD_FILTER_OP_EXT_IN_OP_LEN 4
12117/* Enum values, see field(s): */
12118/* MC_CMD_FILTER_OP_IN/OP */
12119/* filter handle (for remove / unsubscribe operations) */
12120#define MC_CMD_FILTER_OP_EXT_IN_HANDLE_OFST 4
12121#define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LEN 8
12122#define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LO_OFST 4
12123#define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LO_LEN 4
12124#define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LO_LBN 32
12125#define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LO_WIDTH 32
12126#define MC_CMD_FILTER_OP_EXT_IN_HANDLE_HI_OFST 8
12127#define MC_CMD_FILTER_OP_EXT_IN_HANDLE_HI_LEN 4
12128#define MC_CMD_FILTER_OP_EXT_IN_HANDLE_HI_LBN 64
12129#define MC_CMD_FILTER_OP_EXT_IN_HANDLE_HI_WIDTH 32
12130/* The port ID associated with the v-adaptor which should contain this filter.
12131 */
12132#define MC_CMD_FILTER_OP_EXT_IN_PORT_ID_OFST 12
12133#define MC_CMD_FILTER_OP_EXT_IN_PORT_ID_LEN 4
12134/* fields to include in match criteria */
12135#define MC_CMD_FILTER_OP_EXT_IN_MATCH_FIELDS_OFST 16
12136#define MC_CMD_FILTER_OP_EXT_IN_MATCH_FIELDS_LEN 4
12137#define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_IP_OFST 16
12138#define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_IP_LBN 0
12139#define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_IP_WIDTH 1
12140#define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_IP_OFST 16
12141#define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_IP_LBN 1
12142#define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_IP_WIDTH 1
12143#define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_MAC_OFST 16
12144#define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_MAC_LBN 2
12145#define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_MAC_WIDTH 1
12146#define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_PORT_OFST 16
12147#define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_PORT_LBN 3
12148#define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_PORT_WIDTH 1
12149#define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_MAC_OFST 16
12150#define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_MAC_LBN 4
12151#define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_MAC_WIDTH 1
12152#define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_PORT_OFST 16
12153#define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_PORT_LBN 5
12154#define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_PORT_WIDTH 1
12155#define MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_OFST 16
12156#define MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_LBN 6
12157#define MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_WIDTH 1
12158#define MC_CMD_FILTER_OP_EXT_IN_MATCH_INNER_VLAN_OFST 16
12159#define MC_CMD_FILTER_OP_EXT_IN_MATCH_INNER_VLAN_LBN 7
12160#define MC_CMD_FILTER_OP_EXT_IN_MATCH_INNER_VLAN_WIDTH 1
12161#define MC_CMD_FILTER_OP_EXT_IN_MATCH_OUTER_VLAN_OFST 16
12162#define MC_CMD_FILTER_OP_EXT_IN_MATCH_OUTER_VLAN_LBN 8
12163#define MC_CMD_FILTER_OP_EXT_IN_MATCH_OUTER_VLAN_WIDTH 1
12164#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_OFST 16
12165#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_LBN 9
12166#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_WIDTH 1
12167#define MC_CMD_FILTER_OP_EXT_IN_MATCH_FWDEF0_OFST 16
12168#define MC_CMD_FILTER_OP_EXT_IN_MATCH_FWDEF0_LBN 10
12169#define MC_CMD_FILTER_OP_EXT_IN_MATCH_FWDEF0_WIDTH 1
12170#define MC_CMD_FILTER_OP_EXT_IN_MATCH_VNI_OR_VSID_OFST 16
12171#define MC_CMD_FILTER_OP_EXT_IN_MATCH_VNI_OR_VSID_LBN 11
12172#define MC_CMD_FILTER_OP_EXT_IN_MATCH_VNI_OR_VSID_WIDTH 1
12173#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_IP_OFST 16
12174#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_IP_LBN 12
12175#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_IP_WIDTH 1
12176#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_IP_OFST 16
12177#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_IP_LBN 13
12178#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_IP_WIDTH 1
12179#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_MAC_OFST 16
12180#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_MAC_LBN 14
12181#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_MAC_WIDTH 1
12182#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_PORT_OFST 16
12183#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_PORT_LBN 15
12184#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_PORT_WIDTH 1
12185#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_MAC_OFST 16
12186#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_MAC_LBN 16
12187#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_MAC_WIDTH 1
12188#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_PORT_OFST 16
12189#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_PORT_LBN 17
12190#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_PORT_WIDTH 1
12191#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ETHER_TYPE_OFST 16
12192#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ETHER_TYPE_LBN 18
12193#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ETHER_TYPE_WIDTH 1
12194#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_INNER_VLAN_OFST 16
12195#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_INNER_VLAN_LBN 19
12196#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_INNER_VLAN_WIDTH 1
12197#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_OUTER_VLAN_OFST 16
12198#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_OUTER_VLAN_LBN 20
12199#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_OUTER_VLAN_WIDTH 1
12200#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_IP_PROTO_OFST 16
12201#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_IP_PROTO_LBN 21
12202#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_IP_PROTO_WIDTH 1
12203#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF0_OFST 16
12204#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF0_LBN 22
12205#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF0_WIDTH 1
12206#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF1_OFST 16
12207#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF1_LBN 23
12208#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF1_WIDTH 1
12209#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_OFST 16
12210#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_LBN 24
12211#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_WIDTH 1
12212#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_OFST 16
12213#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_LBN 25
12214#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_WIDTH 1
12215#define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_IPV4_MCAST_DST_OFST 16
12216#define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_IPV4_MCAST_DST_LBN 29
12217#define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_IPV4_MCAST_DST_WIDTH 1
12218#define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_OFST 16
12219#define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_LBN 30
12220#define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1
12221#define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_OFST 16
12222#define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_LBN 31
12223#define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1
12224/* receive destination */
12225#define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_OFST 20
12226#define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_LEN 4
12227/* enum: drop packets */
12228#define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_DROP 0x0
12229/* enum: receive to host */
12230#define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_HOST 0x1
12231/* enum: receive to MC */
12232#define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_MC 0x2
12233/* enum: loop back to TXDP 0 */
12234#define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_TX0 0x3
12235/* enum: loop back to TXDP 1 */
12236#define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_TX1 0x4
12237/* receive queue handle (for multiple queue modes, this is the base queue) */
12238#define MC_CMD_FILTER_OP_EXT_IN_RX_QUEUE_OFST 24
12239#define MC_CMD_FILTER_OP_EXT_IN_RX_QUEUE_LEN 4
12240/* receive mode */
12241#define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_OFST 28
12242#define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_LEN 4
12243/* enum: receive to just the specified queue */
12244#define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_SIMPLE 0x0
12245/* enum: receive to multiple queues using RSS context */
12246#define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_RSS 0x1
12247/* enum: receive to multiple queues using .1p mapping */
12248#define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_DOT1P_MAPPING 0x2
12249/* enum: install a filter entry that will never match; for test purposes only
12250 */
12251#define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000
12252/* RSS context (for RX_MODE_RSS) or .1p mapping handle (for
12253 * RX_MODE_DOT1P_MAPPING), as returned by MC_CMD_RSS_CONTEXT_ALLOC or
12254 * MC_CMD_DOT1P_MAPPING_ALLOC.
12255 */
12256#define MC_CMD_FILTER_OP_EXT_IN_RX_CONTEXT_OFST 32
12257#define MC_CMD_FILTER_OP_EXT_IN_RX_CONTEXT_LEN 4
12258/* transmit domain (reserved; set to 0) */
12259#define MC_CMD_FILTER_OP_EXT_IN_TX_DOMAIN_OFST 36
12260#define MC_CMD_FILTER_OP_EXT_IN_TX_DOMAIN_LEN 4
12261/* transmit destination (either set the MAC and/or PM bits for explicit
12262 * control, or set this field to TX_DEST_DEFAULT for sensible default
12263 * behaviour)
12264 */
12265#define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_OFST 40
12266#define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_LEN 4
12267/* enum: request default behaviour (based on filter type) */
12268#define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_DEFAULT 0xffffffff
12269#define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_OFST 40
12270#define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_LBN 0
12271#define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_WIDTH 1
12272#define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_PM_OFST 40
12273#define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_PM_LBN 1
12274#define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_PM_WIDTH 1
12275/* source MAC address to match (as bytes in network order) */
12276#define MC_CMD_FILTER_OP_EXT_IN_SRC_MAC_OFST 44
12277#define MC_CMD_FILTER_OP_EXT_IN_SRC_MAC_LEN 6
12278/* source port to match (as bytes in network order) */
12279#define MC_CMD_FILTER_OP_EXT_IN_SRC_PORT_OFST 50
12280#define MC_CMD_FILTER_OP_EXT_IN_SRC_PORT_LEN 2
12281/* destination MAC address to match (as bytes in network order) */
12282#define MC_CMD_FILTER_OP_EXT_IN_DST_MAC_OFST 52
12283#define MC_CMD_FILTER_OP_EXT_IN_DST_MAC_LEN 6
12284/* destination port to match (as bytes in network order) */
12285#define MC_CMD_FILTER_OP_EXT_IN_DST_PORT_OFST 58
12286#define MC_CMD_FILTER_OP_EXT_IN_DST_PORT_LEN 2
12287/* Ethernet type to match (as bytes in network order) */
12288#define MC_CMD_FILTER_OP_EXT_IN_ETHER_TYPE_OFST 60
12289#define MC_CMD_FILTER_OP_EXT_IN_ETHER_TYPE_LEN 2
12290/* Inner VLAN tag to match (as bytes in network order) */
12291#define MC_CMD_FILTER_OP_EXT_IN_INNER_VLAN_OFST 62
12292#define MC_CMD_FILTER_OP_EXT_IN_INNER_VLAN_LEN 2
12293/* Outer VLAN tag to match (as bytes in network order) */
12294#define MC_CMD_FILTER_OP_EXT_IN_OUTER_VLAN_OFST 64
12295#define MC_CMD_FILTER_OP_EXT_IN_OUTER_VLAN_LEN 2
12296/* IP protocol to match (in low byte; set high byte to 0) */
12297#define MC_CMD_FILTER_OP_EXT_IN_IP_PROTO_OFST 66
12298#define MC_CMD_FILTER_OP_EXT_IN_IP_PROTO_LEN 2
12299/* Firmware defined register 0 to match (reserved; set to 0) */
12300#define MC_CMD_FILTER_OP_EXT_IN_FWDEF0_OFST 68
12301#define MC_CMD_FILTER_OP_EXT_IN_FWDEF0_LEN 4
12302/* VNI (for VXLAN/Geneve, when IP protocol is UDP) or VSID (for NVGRE, when IP
12303 * protocol is GRE) to match (as bytes in network order; set last byte to 0 for
12304 * VXLAN/NVGRE, or 1 for Geneve)
12305 */
12306#define MC_CMD_FILTER_OP_EXT_IN_VNI_OR_VSID_OFST 72
12307#define MC_CMD_FILTER_OP_EXT_IN_VNI_OR_VSID_LEN 4
12308#define MC_CMD_FILTER_OP_EXT_IN_VNI_VALUE_OFST 72
12309#define MC_CMD_FILTER_OP_EXT_IN_VNI_VALUE_LBN 0
12310#define MC_CMD_FILTER_OP_EXT_IN_VNI_VALUE_WIDTH 24
12311#define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_OFST 72
12312#define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_LBN 24
12313#define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_WIDTH 8
12314/* enum: Match VXLAN traffic with this VNI */
12315#define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_VXLAN 0x0
12316/* enum: Match Geneve traffic with this VNI */
12317#define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_GENEVE 0x1
12318/* enum: Reserved for experimental development use */
12319#define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_EXPERIMENTAL 0xfe
12320#define MC_CMD_FILTER_OP_EXT_IN_VSID_VALUE_OFST 72
12321#define MC_CMD_FILTER_OP_EXT_IN_VSID_VALUE_LBN 0
12322#define MC_CMD_FILTER_OP_EXT_IN_VSID_VALUE_WIDTH 24
12323#define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_OFST 72
12324#define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_LBN 24
12325#define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_WIDTH 8
12326/* enum: Match NVGRE traffic with this VSID */
12327#define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_NVGRE 0x0
12328/* source IP address to match (as bytes in network order; set last 12 bytes to
12329 * 0 for IPv4 address)
12330 */
12331#define MC_CMD_FILTER_OP_EXT_IN_SRC_IP_OFST 76
12332#define MC_CMD_FILTER_OP_EXT_IN_SRC_IP_LEN 16
12333/* destination IP address to match (as bytes in network order; set last 12
12334 * bytes to 0 for IPv4 address)
12335 */
12336#define MC_CMD_FILTER_OP_EXT_IN_DST_IP_OFST 92
12337#define MC_CMD_FILTER_OP_EXT_IN_DST_IP_LEN 16
12338/* VXLAN/NVGRE inner frame source MAC address to match (as bytes in network
12339 * order)
12340 */
12341#define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_MAC_OFST 108
12342#define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_MAC_LEN 6
12343/* VXLAN/NVGRE inner frame source port to match (as bytes in network order) */
12344#define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_PORT_OFST 114
12345#define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_PORT_LEN 2
12346/* VXLAN/NVGRE inner frame destination MAC address to match (as bytes in
12347 * network order)
12348 */
12349#define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_MAC_OFST 116
12350#define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_MAC_LEN 6
12351/* VXLAN/NVGRE inner frame destination port to match (as bytes in network
12352 * order)
12353 */
12354#define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_PORT_OFST 122
12355#define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_PORT_LEN 2
12356/* VXLAN/NVGRE inner frame Ethernet type to match (as bytes in network order)
12357 */
12358#define MC_CMD_FILTER_OP_EXT_IN_IFRM_ETHER_TYPE_OFST 124
12359#define MC_CMD_FILTER_OP_EXT_IN_IFRM_ETHER_TYPE_LEN 2
12360/* VXLAN/NVGRE inner frame Inner VLAN tag to match (as bytes in network order)
12361 */
12362#define MC_CMD_FILTER_OP_EXT_IN_IFRM_INNER_VLAN_OFST 126
12363#define MC_CMD_FILTER_OP_EXT_IN_IFRM_INNER_VLAN_LEN 2
12364/* VXLAN/NVGRE inner frame Outer VLAN tag to match (as bytes in network order)
12365 */
12366#define MC_CMD_FILTER_OP_EXT_IN_IFRM_OUTER_VLAN_OFST 128
12367#define MC_CMD_FILTER_OP_EXT_IN_IFRM_OUTER_VLAN_LEN 2
12368/* VXLAN/NVGRE inner frame IP protocol to match (in low byte; set high byte to
12369 * 0)
12370 */
12371#define MC_CMD_FILTER_OP_EXT_IN_IFRM_IP_PROTO_OFST 130
12372#define MC_CMD_FILTER_OP_EXT_IN_IFRM_IP_PROTO_LEN 2
12373/* VXLAN/NVGRE inner frame Firmware defined register 0 to match (reserved; set
12374 * to 0)
12375 */
12376#define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF0_OFST 132
12377#define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF0_LEN 4
12378/* VXLAN/NVGRE inner frame Firmware defined register 1 to match (reserved; set
12379 * to 0)
12380 */
12381#define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF1_OFST 136
12382#define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF1_LEN 4
12383/* VXLAN/NVGRE inner frame source IP address to match (as bytes in network
12384 * order; set last 12 bytes to 0 for IPv4 address)
12385 */
12386#define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_IP_OFST 140
12387#define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_IP_LEN 16
12388/* VXLAN/NVGRE inner frame destination IP address to match (as bytes in network
12389 * order; set last 12 bytes to 0 for IPv4 address)
12390 */
12391#define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_IP_OFST 156
12392#define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_IP_LEN 16
12393
12394/* MC_CMD_FILTER_OP_V3_IN msgrequest: FILTER_OP extension to support additional
12395 * filter actions for EF100. Some of these actions are also supported on EF10,
12396 * for Intel's DPDK (Data Plane Development Kit, dpdk.org) via its rte_flow
12397 * API. In the latter case, this extension is only useful with the sfc_efx
12398 * driver included as part of DPDK, used in conjunction with the dpdk datapath
12399 * firmware variant.
12400 */
12401#define MC_CMD_FILTER_OP_V3_IN_LEN 180
12402/* identifies the type of operation requested */
12403#define MC_CMD_FILTER_OP_V3_IN_OP_OFST 0
12404#define MC_CMD_FILTER_OP_V3_IN_OP_LEN 4
12405/* Enum values, see field(s): */
12406/* MC_CMD_FILTER_OP_IN/OP */
12407/* filter handle (for remove / unsubscribe operations) */
12408#define MC_CMD_FILTER_OP_V3_IN_HANDLE_OFST 4
12409#define MC_CMD_FILTER_OP_V3_IN_HANDLE_LEN 8
12410#define MC_CMD_FILTER_OP_V3_IN_HANDLE_LO_OFST 4
12411#define MC_CMD_FILTER_OP_V3_IN_HANDLE_LO_LEN 4
12412#define MC_CMD_FILTER_OP_V3_IN_HANDLE_LO_LBN 32
12413#define MC_CMD_FILTER_OP_V3_IN_HANDLE_LO_WIDTH 32
12414#define MC_CMD_FILTER_OP_V3_IN_HANDLE_HI_OFST 8
12415#define MC_CMD_FILTER_OP_V3_IN_HANDLE_HI_LEN 4
12416#define MC_CMD_FILTER_OP_V3_IN_HANDLE_HI_LBN 64
12417#define MC_CMD_FILTER_OP_V3_IN_HANDLE_HI_WIDTH 32
12418/* The port ID associated with the v-adaptor which should contain this filter.
12419 */
12420#define MC_CMD_FILTER_OP_V3_IN_PORT_ID_OFST 12
12421#define MC_CMD_FILTER_OP_V3_IN_PORT_ID_LEN 4
12422/* fields to include in match criteria */
12423#define MC_CMD_FILTER_OP_V3_IN_MATCH_FIELDS_OFST 16
12424#define MC_CMD_FILTER_OP_V3_IN_MATCH_FIELDS_LEN 4
12425#define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_IP_OFST 16
12426#define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_IP_LBN 0
12427#define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_IP_WIDTH 1
12428#define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_IP_OFST 16
12429#define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_IP_LBN 1
12430#define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_IP_WIDTH 1
12431#define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_MAC_OFST 16
12432#define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_MAC_LBN 2
12433#define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_MAC_WIDTH 1
12434#define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_PORT_OFST 16
12435#define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_PORT_LBN 3
12436#define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_PORT_WIDTH 1
12437#define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_MAC_OFST 16
12438#define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_MAC_LBN 4
12439#define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_MAC_WIDTH 1
12440#define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_PORT_OFST 16
12441#define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_PORT_LBN 5
12442#define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_PORT_WIDTH 1
12443#define MC_CMD_FILTER_OP_V3_IN_MATCH_ETHER_TYPE_OFST 16
12444#define MC_CMD_FILTER_OP_V3_IN_MATCH_ETHER_TYPE_LBN 6
12445#define MC_CMD_FILTER_OP_V3_IN_MATCH_ETHER_TYPE_WIDTH 1
12446#define MC_CMD_FILTER_OP_V3_IN_MATCH_INNER_VLAN_OFST 16
12447#define MC_CMD_FILTER_OP_V3_IN_MATCH_INNER_VLAN_LBN 7
12448#define MC_CMD_FILTER_OP_V3_IN_MATCH_INNER_VLAN_WIDTH 1
12449#define MC_CMD_FILTER_OP_V3_IN_MATCH_OUTER_VLAN_OFST 16
12450#define MC_CMD_FILTER_OP_V3_IN_MATCH_OUTER_VLAN_LBN 8
12451#define MC_CMD_FILTER_OP_V3_IN_MATCH_OUTER_VLAN_WIDTH 1
12452#define MC_CMD_FILTER_OP_V3_IN_MATCH_IP_PROTO_OFST 16
12453#define MC_CMD_FILTER_OP_V3_IN_MATCH_IP_PROTO_LBN 9
12454#define MC_CMD_FILTER_OP_V3_IN_MATCH_IP_PROTO_WIDTH 1
12455#define MC_CMD_FILTER_OP_V3_IN_MATCH_FWDEF0_OFST 16
12456#define MC_CMD_FILTER_OP_V3_IN_MATCH_FWDEF0_LBN 10
12457#define MC_CMD_FILTER_OP_V3_IN_MATCH_FWDEF0_WIDTH 1
12458#define MC_CMD_FILTER_OP_V3_IN_MATCH_VNI_OR_VSID_OFST 16
12459#define MC_CMD_FILTER_OP_V3_IN_MATCH_VNI_OR_VSID_LBN 11
12460#define MC_CMD_FILTER_OP_V3_IN_MATCH_VNI_OR_VSID_WIDTH 1
12461#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_IP_OFST 16
12462#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_IP_LBN 12
12463#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_IP_WIDTH 1
12464#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_IP_OFST 16
12465#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_IP_LBN 13
12466#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_IP_WIDTH 1
12467#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_MAC_OFST 16
12468#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_MAC_LBN 14
12469#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_MAC_WIDTH 1
12470#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_PORT_OFST 16
12471#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_PORT_LBN 15
12472#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_PORT_WIDTH 1
12473#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_MAC_OFST 16
12474#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_MAC_LBN 16
12475#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_MAC_WIDTH 1
12476#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_PORT_OFST 16
12477#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_PORT_LBN 17
12478#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_PORT_WIDTH 1
12479#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_ETHER_TYPE_OFST 16
12480#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_ETHER_TYPE_LBN 18
12481#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_ETHER_TYPE_WIDTH 1
12482#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_INNER_VLAN_OFST 16
12483#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_INNER_VLAN_LBN 19
12484#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_INNER_VLAN_WIDTH 1
12485#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_OUTER_VLAN_OFST 16
12486#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_OUTER_VLAN_LBN 20
12487#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_OUTER_VLAN_WIDTH 1
12488#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_IP_PROTO_OFST 16
12489#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_IP_PROTO_LBN 21
12490#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_IP_PROTO_WIDTH 1
12491#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF0_OFST 16
12492#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF0_LBN 22
12493#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF0_WIDTH 1
12494#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF1_OFST 16
12495#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF1_LBN 23
12496#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF1_WIDTH 1
12497#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_OFST 16
12498#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_LBN 24
12499#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_WIDTH 1
12500#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_OFST 16
12501#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_LBN 25
12502#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_WIDTH 1
12503#define MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_IPV4_MCAST_DST_OFST 16
12504#define MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_IPV4_MCAST_DST_LBN 29
12505#define MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_IPV4_MCAST_DST_WIDTH 1
12506#define MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_MCAST_DST_OFST 16
12507#define MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_MCAST_DST_LBN 30
12508#define MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1
12509#define MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_UCAST_DST_OFST 16
12510#define MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_UCAST_DST_LBN 31
12511#define MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1
12512/* receive destination */
12513#define MC_CMD_FILTER_OP_V3_IN_RX_DEST_OFST 20
12514#define MC_CMD_FILTER_OP_V3_IN_RX_DEST_LEN 4
12515/* enum: drop packets */
12516#define MC_CMD_FILTER_OP_V3_IN_RX_DEST_DROP 0x0
12517/* enum: receive to host */
12518#define MC_CMD_FILTER_OP_V3_IN_RX_DEST_HOST 0x1
12519/* enum: receive to MC */
12520#define MC_CMD_FILTER_OP_V3_IN_RX_DEST_MC 0x2
12521/* enum: loop back to TXDP 0 */
12522#define MC_CMD_FILTER_OP_V3_IN_RX_DEST_TX0 0x3
12523/* enum: loop back to TXDP 1 */
12524#define MC_CMD_FILTER_OP_V3_IN_RX_DEST_TX1 0x4
12525/* receive queue handle (for multiple queue modes, this is the base queue) */
12526#define MC_CMD_FILTER_OP_V3_IN_RX_QUEUE_OFST 24
12527#define MC_CMD_FILTER_OP_V3_IN_RX_QUEUE_LEN 4
12528/* receive mode */
12529#define MC_CMD_FILTER_OP_V3_IN_RX_MODE_OFST 28
12530#define MC_CMD_FILTER_OP_V3_IN_RX_MODE_LEN 4
12531/* enum: receive to just the specified queue */
12532#define MC_CMD_FILTER_OP_V3_IN_RX_MODE_SIMPLE 0x0
12533/* enum: receive to multiple queues using RSS context */
12534#define MC_CMD_FILTER_OP_V3_IN_RX_MODE_RSS 0x1
12535/* enum: receive to multiple queues using .1p mapping */
12536#define MC_CMD_FILTER_OP_V3_IN_RX_MODE_DOT1P_MAPPING 0x2
12537/* enum: install a filter entry that will never match; for test purposes only
12538 */
12539#define MC_CMD_FILTER_OP_V3_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000
12540/* RSS context (for RX_MODE_RSS) or .1p mapping handle (for
12541 * RX_MODE_DOT1P_MAPPING), as returned by MC_CMD_RSS_CONTEXT_ALLOC or
12542 * MC_CMD_DOT1P_MAPPING_ALLOC.
12543 */
12544#define MC_CMD_FILTER_OP_V3_IN_RX_CONTEXT_OFST 32
12545#define MC_CMD_FILTER_OP_V3_IN_RX_CONTEXT_LEN 4
12546/* transmit domain (reserved; set to 0) */
12547#define MC_CMD_FILTER_OP_V3_IN_TX_DOMAIN_OFST 36
12548#define MC_CMD_FILTER_OP_V3_IN_TX_DOMAIN_LEN 4
12549/* transmit destination (either set the MAC and/or PM bits for explicit
12550 * control, or set this field to TX_DEST_DEFAULT for sensible default
12551 * behaviour)
12552 */
12553#define MC_CMD_FILTER_OP_V3_IN_TX_DEST_OFST 40
12554#define MC_CMD_FILTER_OP_V3_IN_TX_DEST_LEN 4
12555/* enum: request default behaviour (based on filter type) */
12556#define MC_CMD_FILTER_OP_V3_IN_TX_DEST_DEFAULT 0xffffffff
12557#define MC_CMD_FILTER_OP_V3_IN_TX_DEST_MAC_OFST 40
12558#define MC_CMD_FILTER_OP_V3_IN_TX_DEST_MAC_LBN 0
12559#define MC_CMD_FILTER_OP_V3_IN_TX_DEST_MAC_WIDTH 1
12560#define MC_CMD_FILTER_OP_V3_IN_TX_DEST_PM_OFST 40
12561#define MC_CMD_FILTER_OP_V3_IN_TX_DEST_PM_LBN 1
12562#define MC_CMD_FILTER_OP_V3_IN_TX_DEST_PM_WIDTH 1
12563/* source MAC address to match (as bytes in network order) */
12564#define MC_CMD_FILTER_OP_V3_IN_SRC_MAC_OFST 44
12565#define MC_CMD_FILTER_OP_V3_IN_SRC_MAC_LEN 6
12566/* source port to match (as bytes in network order) */
12567#define MC_CMD_FILTER_OP_V3_IN_SRC_PORT_OFST 50
12568#define MC_CMD_FILTER_OP_V3_IN_SRC_PORT_LEN 2
12569/* destination MAC address to match (as bytes in network order) */
12570#define MC_CMD_FILTER_OP_V3_IN_DST_MAC_OFST 52
12571#define MC_CMD_FILTER_OP_V3_IN_DST_MAC_LEN 6
12572/* destination port to match (as bytes in network order) */
12573#define MC_CMD_FILTER_OP_V3_IN_DST_PORT_OFST 58
12574#define MC_CMD_FILTER_OP_V3_IN_DST_PORT_LEN 2
12575/* Ethernet type to match (as bytes in network order) */
12576#define MC_CMD_FILTER_OP_V3_IN_ETHER_TYPE_OFST 60
12577#define MC_CMD_FILTER_OP_V3_IN_ETHER_TYPE_LEN 2
12578/* Inner VLAN tag to match (as bytes in network order) */
12579#define MC_CMD_FILTER_OP_V3_IN_INNER_VLAN_OFST 62
12580#define MC_CMD_FILTER_OP_V3_IN_INNER_VLAN_LEN 2
12581/* Outer VLAN tag to match (as bytes in network order) */
12582#define MC_CMD_FILTER_OP_V3_IN_OUTER_VLAN_OFST 64
12583#define MC_CMD_FILTER_OP_V3_IN_OUTER_VLAN_LEN 2
12584/* IP protocol to match (in low byte; set high byte to 0) */
12585#define MC_CMD_FILTER_OP_V3_IN_IP_PROTO_OFST 66
12586#define MC_CMD_FILTER_OP_V3_IN_IP_PROTO_LEN 2
12587/* Firmware defined register 0 to match (reserved; set to 0) */
12588#define MC_CMD_FILTER_OP_V3_IN_FWDEF0_OFST 68
12589#define MC_CMD_FILTER_OP_V3_IN_FWDEF0_LEN 4
12590/* VNI (for VXLAN/Geneve, when IP protocol is UDP) or VSID (for NVGRE, when IP
12591 * protocol is GRE) to match (as bytes in network order; set last byte to 0 for
12592 * VXLAN/NVGRE, or 1 for Geneve)
12593 */
12594#define MC_CMD_FILTER_OP_V3_IN_VNI_OR_VSID_OFST 72
12595#define MC_CMD_FILTER_OP_V3_IN_VNI_OR_VSID_LEN 4
12596#define MC_CMD_FILTER_OP_V3_IN_VNI_VALUE_OFST 72
12597#define MC_CMD_FILTER_OP_V3_IN_VNI_VALUE_LBN 0
12598#define MC_CMD_FILTER_OP_V3_IN_VNI_VALUE_WIDTH 24
12599#define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_OFST 72
12600#define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_LBN 24
12601#define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_WIDTH 8
12602/* enum: Match VXLAN traffic with this VNI */
12603#define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_VXLAN 0x0
12604/* enum: Match Geneve traffic with this VNI */
12605#define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_GENEVE 0x1
12606/* enum: Reserved for experimental development use */
12607#define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_EXPERIMENTAL 0xfe
12608#define MC_CMD_FILTER_OP_V3_IN_VSID_VALUE_OFST 72
12609#define MC_CMD_FILTER_OP_V3_IN_VSID_VALUE_LBN 0
12610#define MC_CMD_FILTER_OP_V3_IN_VSID_VALUE_WIDTH 24
12611#define MC_CMD_FILTER_OP_V3_IN_VSID_TYPE_OFST 72
12612#define MC_CMD_FILTER_OP_V3_IN_VSID_TYPE_LBN 24
12613#define MC_CMD_FILTER_OP_V3_IN_VSID_TYPE_WIDTH 8
12614/* enum: Match NVGRE traffic with this VSID */
12615#define MC_CMD_FILTER_OP_V3_IN_VSID_TYPE_NVGRE 0x0
12616/* source IP address to match (as bytes in network order; set last 12 bytes to
12617 * 0 for IPv4 address)
12618 */
12619#define MC_CMD_FILTER_OP_V3_IN_SRC_IP_OFST 76
12620#define MC_CMD_FILTER_OP_V3_IN_SRC_IP_LEN 16
12621/* destination IP address to match (as bytes in network order; set last 12
12622 * bytes to 0 for IPv4 address)
12623 */
12624#define MC_CMD_FILTER_OP_V3_IN_DST_IP_OFST 92
12625#define MC_CMD_FILTER_OP_V3_IN_DST_IP_LEN 16
12626/* VXLAN/NVGRE inner frame source MAC address to match (as bytes in network
12627 * order)
12628 */
12629#define MC_CMD_FILTER_OP_V3_IN_IFRM_SRC_MAC_OFST 108
12630#define MC_CMD_FILTER_OP_V3_IN_IFRM_SRC_MAC_LEN 6
12631/* VXLAN/NVGRE inner frame source port to match (as bytes in network order) */
12632#define MC_CMD_FILTER_OP_V3_IN_IFRM_SRC_PORT_OFST 114
12633#define MC_CMD_FILTER_OP_V3_IN_IFRM_SRC_PORT_LEN 2
12634/* VXLAN/NVGRE inner frame destination MAC address to match (as bytes in
12635 * network order)
12636 */
12637#define MC_CMD_FILTER_OP_V3_IN_IFRM_DST_MAC_OFST 116
12638#define MC_CMD_FILTER_OP_V3_IN_IFRM_DST_MAC_LEN 6
12639/* VXLAN/NVGRE inner frame destination port to match (as bytes in network
12640 * order)
12641 */
12642#define MC_CMD_FILTER_OP_V3_IN_IFRM_DST_PORT_OFST 122
12643#define MC_CMD_FILTER_OP_V3_IN_IFRM_DST_PORT_LEN 2
12644/* VXLAN/NVGRE inner frame Ethernet type to match (as bytes in network order)
12645 */
12646#define MC_CMD_FILTER_OP_V3_IN_IFRM_ETHER_TYPE_OFST 124
12647#define MC_CMD_FILTER_OP_V3_IN_IFRM_ETHER_TYPE_LEN 2
12648/* VXLAN/NVGRE inner frame Inner VLAN tag to match (as bytes in network order)
12649 */
12650#define MC_CMD_FILTER_OP_V3_IN_IFRM_INNER_VLAN_OFST 126
12651#define MC_CMD_FILTER_OP_V3_IN_IFRM_INNER_VLAN_LEN 2
12652/* VXLAN/NVGRE inner frame Outer VLAN tag to match (as bytes in network order)
12653 */
12654#define MC_CMD_FILTER_OP_V3_IN_IFRM_OUTER_VLAN_OFST 128
12655#define MC_CMD_FILTER_OP_V3_IN_IFRM_OUTER_VLAN_LEN 2
12656/* VXLAN/NVGRE inner frame IP protocol to match (in low byte; set high byte to
12657 * 0)
12658 */
12659#define MC_CMD_FILTER_OP_V3_IN_IFRM_IP_PROTO_OFST 130
12660#define MC_CMD_FILTER_OP_V3_IN_IFRM_IP_PROTO_LEN 2
12661/* VXLAN/NVGRE inner frame Firmware defined register 0 to match (reserved; set
12662 * to 0)
12663 */
12664#define MC_CMD_FILTER_OP_V3_IN_IFRM_FWDEF0_OFST 132
12665#define MC_CMD_FILTER_OP_V3_IN_IFRM_FWDEF0_LEN 4
12666/* VXLAN/NVGRE inner frame Firmware defined register 1 to match (reserved; set
12667 * to 0)
12668 */
12669#define MC_CMD_FILTER_OP_V3_IN_IFRM_FWDEF1_OFST 136
12670#define MC_CMD_FILTER_OP_V3_IN_IFRM_FWDEF1_LEN 4
12671/* VXLAN/NVGRE inner frame source IP address to match (as bytes in network
12672 * order; set last 12 bytes to 0 for IPv4 address)
12673 */
12674#define MC_CMD_FILTER_OP_V3_IN_IFRM_SRC_IP_OFST 140
12675#define MC_CMD_FILTER_OP_V3_IN_IFRM_SRC_IP_LEN 16
12676/* VXLAN/NVGRE inner frame destination IP address to match (as bytes in network
12677 * order; set last 12 bytes to 0 for IPv4 address)
12678 */
12679#define MC_CMD_FILTER_OP_V3_IN_IFRM_DST_IP_OFST 156
12680#define MC_CMD_FILTER_OP_V3_IN_IFRM_DST_IP_LEN 16
12681/* Flags controlling mutations of the packet and/or metadata when the filter is
12682 * matched. The user_mark and user_flag fields' logic is as follows: if
12683 * (req.MATCH_BITOR_FLAG == 1) user_flag = req.MATCH_SET_FLAG bit_or user_flag;
12684 * else user_flag = req.MATCH_SET_FLAG; if (req.MATCH_SET_MARK == 0) user_mark
12685 * = 0; else if (req.MATCH_BITOR_MARK == 1) user_mark = req.MATCH_SET_MARK
12686 * bit_or user_mark; else user_mark = req.MATCH_SET_MARK; N.B. These flags
12687 * overlap with the MATCH_ACTION field, which is deprecated in favour of this
12688 * field. For the cases where these flags induce a valid encoding of the
12689 * MATCH_ACTION field, the semantics agree.
12690 */
12691#define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_FLAGS_OFST 172
12692#define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_FLAGS_LEN 4
12693#define MC_CMD_FILTER_OP_V3_IN_MATCH_SET_FLAG_OFST 172
12694#define MC_CMD_FILTER_OP_V3_IN_MATCH_SET_FLAG_LBN 0
12695#define MC_CMD_FILTER_OP_V3_IN_MATCH_SET_FLAG_WIDTH 1
12696#define MC_CMD_FILTER_OP_V3_IN_MATCH_SET_MARK_OFST 172
12697#define MC_CMD_FILTER_OP_V3_IN_MATCH_SET_MARK_LBN 1
12698#define MC_CMD_FILTER_OP_V3_IN_MATCH_SET_MARK_WIDTH 1
12699#define MC_CMD_FILTER_OP_V3_IN_MATCH_BITOR_FLAG_OFST 172
12700#define MC_CMD_FILTER_OP_V3_IN_MATCH_BITOR_FLAG_LBN 2
12701#define MC_CMD_FILTER_OP_V3_IN_MATCH_BITOR_FLAG_WIDTH 1
12702#define MC_CMD_FILTER_OP_V3_IN_MATCH_BITOR_MARK_OFST 172
12703#define MC_CMD_FILTER_OP_V3_IN_MATCH_BITOR_MARK_LBN 3
12704#define MC_CMD_FILTER_OP_V3_IN_MATCH_BITOR_MARK_WIDTH 1
12705#define MC_CMD_FILTER_OP_V3_IN_MATCH_STRIP_VLAN_OFST 172
12706#define MC_CMD_FILTER_OP_V3_IN_MATCH_STRIP_VLAN_LBN 4
12707#define MC_CMD_FILTER_OP_V3_IN_MATCH_STRIP_VLAN_WIDTH 1
12708/* Deprecated: the overlapping MATCH_ACTION_FLAGS field exposes all of the
12709 * functionality of this field in an ABI-backwards-compatible manner, and
12710 * should be used instead. Any future extensions should be made to the
12711 * MATCH_ACTION_FLAGS field, and not to this field. Set an action for all
12712 * packets matching this filter. The DPDK driver and (on EF10) dpdk f/w variant
12713 * use their own specific delivery structures, which are documented in the DPDK
12714 * Firmware Driver Interface (SF-119419-TC). Requesting anything other than
12715 * MATCH_ACTION_NONE on an EF10 NIC running another f/w variant will cause the
12716 * filter insertion to fail with ENOTSUP.
12717 */
12718#define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_OFST 172
12719#define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_LEN 4
12720/* enum: do nothing extra */
12721#define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_NONE 0x0
12722/* enum: Set the match flag in the packet prefix for packets matching the
12723 * filter (only with dpdk firmware, otherwise fails with ENOTSUP). Used to
12724 * support the DPDK rte_flow "FLAG" action.
12725 */
12726#define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_FLAG 0x1
12727/* enum: Insert MATCH_MARK_VALUE into the packet prefix for packets matching
12728 * the filter (only with dpdk firmware, otherwise fails with ENOTSUP). Used to
12729 * support the DPDK rte_flow "MARK" action.
12730 */
12731#define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_MARK 0x2
12732/* the mark value for MATCH_ACTION_MARK. Requesting a value larger than the
12733 * maximum (obtained from MC_CMD_GET_CAPABILITIES_V5/FILTER_ACTION_MARK_MAX)
12734 * will cause the filter insertion to fail with EINVAL.
12735 */
12736#define MC_CMD_FILTER_OP_V3_IN_MATCH_MARK_VALUE_OFST 176
12737#define MC_CMD_FILTER_OP_V3_IN_MATCH_MARK_VALUE_LEN 4
12738
12739/* MC_CMD_FILTER_OP_OUT msgresponse */
12740#define MC_CMD_FILTER_OP_OUT_LEN 12
12741/* identifies the type of operation requested */
12742#define MC_CMD_FILTER_OP_OUT_OP_OFST 0
12743#define MC_CMD_FILTER_OP_OUT_OP_LEN 4
12744/* Enum values, see field(s): */
12745/* MC_CMD_FILTER_OP_IN/OP */
12746/* Returned filter handle (for insert / subscribe operations). Note that these
12747 * handles should be considered opaque to the host, although a value of
12748 * 0xFFFFFFFF_FFFFFFFF is guaranteed never to be a valid handle.
12749 */
12750#define MC_CMD_FILTER_OP_OUT_HANDLE_OFST 4
12751#define MC_CMD_FILTER_OP_OUT_HANDLE_LEN 8
12752#define MC_CMD_FILTER_OP_OUT_HANDLE_LO_OFST 4
12753#define MC_CMD_FILTER_OP_OUT_HANDLE_LO_LEN 4
12754#define MC_CMD_FILTER_OP_OUT_HANDLE_LO_LBN 32
12755#define MC_CMD_FILTER_OP_OUT_HANDLE_LO_WIDTH 32
12756#define MC_CMD_FILTER_OP_OUT_HANDLE_HI_OFST 8
12757#define MC_CMD_FILTER_OP_OUT_HANDLE_HI_LEN 4
12758#define MC_CMD_FILTER_OP_OUT_HANDLE_HI_LBN 64
12759#define MC_CMD_FILTER_OP_OUT_HANDLE_HI_WIDTH 32
12760/* enum: guaranteed invalid filter handle (low 32 bits) */
12761#define MC_CMD_FILTER_OP_OUT_HANDLE_LO_INVALID 0xffffffff
12762/* enum: guaranteed invalid filter handle (high 32 bits) */
12763#define MC_CMD_FILTER_OP_OUT_HANDLE_HI_INVALID 0xffffffff
12764
12765/* MC_CMD_FILTER_OP_EXT_OUT msgresponse */
12766#define MC_CMD_FILTER_OP_EXT_OUT_LEN 12
12767/* identifies the type of operation requested */
12768#define MC_CMD_FILTER_OP_EXT_OUT_OP_OFST 0
12769#define MC_CMD_FILTER_OP_EXT_OUT_OP_LEN 4
12770/* Enum values, see field(s): */
12771/* MC_CMD_FILTER_OP_EXT_IN/OP */
12772/* Returned filter handle (for insert / subscribe operations). Note that these
12773 * handles should be considered opaque to the host, although a value of
12774 * 0xFFFFFFFF_FFFFFFFF is guaranteed never to be a valid handle.
12775 */
12776#define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_OFST 4
12777#define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LEN 8
12778#define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LO_OFST 4
12779#define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LO_LEN 4
12780#define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LO_LBN 32
12781#define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LO_WIDTH 32
12782#define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_HI_OFST 8
12783#define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_HI_LEN 4
12784#define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_HI_LBN 64
12785#define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_HI_WIDTH 32
12786/* Enum values, see field(s): */
12787/* MC_CMD_FILTER_OP_OUT/HANDLE */
12788
12789
12790/***********************************/
12791/* MC_CMD_GET_PARSER_DISP_INFO
12792 * Get information related to the parser-dispatcher subsystem
12793 */
12794#define MC_CMD_GET_PARSER_DISP_INFO 0xe4
12795#undef MC_CMD_0xe4_PRIVILEGE_CTG
12796
12797#define MC_CMD_0xe4_PRIVILEGE_CTG SRIOV_CTG_GENERAL
12798
12799/* MC_CMD_GET_PARSER_DISP_INFO_IN msgrequest */
12800#define MC_CMD_GET_PARSER_DISP_INFO_IN_LEN 4
12801/* identifies the type of operation requested */
12802#define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_OFST 0
12803#define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_LEN 4
12804/* enum: read the list of supported RX filter matches */
12805#define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES 0x1
12806/* enum: read flags indicating restrictions on filter insertion for the calling
12807 * client
12808 */
12809#define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_RESTRICTIONS 0x2
12810/* enum: read properties relating to security rules (Medford-only; for use by
12811 * SolarSecure apps, not directly by drivers. See SF-114946-SW.)
12812 */
12813#define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SECURITY_RULE_INFO 0x3
12814/* enum: read the list of supported RX filter matches for VXLAN/NVGRE
12815 * encapsulated frames, which follow a different match sequence to normal
12816 * frames (Medford only)
12817 */
12818#define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_ENCAP_RX_MATCHES 0x4
12819/* enum: read the list of supported matches for the encapsulation detection
12820 * rules inserted by MC_CMD_VNIC_ENCAP_RULE_ADD. (ef100 and later)
12821 */
12822#define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_VNIC_ENCAP_MATCHES 0x5
12823/* enum: read the supported encapsulation types for the VNIC */
12824#define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_VNIC_ENCAP_TYPES 0x6
12825
12826/* MC_CMD_GET_PARSER_DISP_INFO_OUT msgresponse */
12827#define MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMIN 8
12828#define MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX 252
12829#define MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX_MCDI2 1020
12830#define MC_CMD_GET_PARSER_DISP_INFO_OUT_LEN(num) (8+4*(num))
12831#define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_NUM(len) (((len)-8)/4)
12832/* identifies the type of operation requested */
12833#define MC_CMD_GET_PARSER_DISP_INFO_OUT_OP_OFST 0
12834#define MC_CMD_GET_PARSER_DISP_INFO_OUT_OP_LEN 4
12835/* Enum values, see field(s): */
12836/* MC_CMD_GET_PARSER_DISP_INFO_IN/OP */
12837/* number of supported match types */
12838#define MC_CMD_GET_PARSER_DISP_INFO_OUT_NUM_SUPPORTED_MATCHES_OFST 4
12839#define MC_CMD_GET_PARSER_DISP_INFO_OUT_NUM_SUPPORTED_MATCHES_LEN 4
12840/* array of supported match types (valid MATCH_FIELDS values for
12841 * MC_CMD_FILTER_OP) sorted in decreasing priority order
12842 */
12843#define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_OFST 8
12844#define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_LEN 4
12845#define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MINNUM 0
12846#define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM 61
12847#define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM_MCDI2 253
12848
12849/* MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT msgresponse */
12850#define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_LEN 8
12851/* identifies the type of operation requested */
12852#define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_OP_OFST 0
12853#define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_OP_LEN 4
12854/* Enum values, see field(s): */
12855/* MC_CMD_GET_PARSER_DISP_INFO_IN/OP */
12856/* bitfield of filter insertion restrictions */
12857#define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_RESTRICTION_FLAGS_OFST 4
12858#define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_RESTRICTION_FLAGS_LEN 4
12859#define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_OFST 4
12860#define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_LBN 0
12861#define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_WIDTH 1
12862
12863/* MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT msgresponse: This response is
12864 * returned if a MC_CMD_GET_PARSER_DISP_INFO_IN request is sent with OP value
12865 * OP_GET_SUPPORTED_VNIC_ENCAP_MATCHES. It contains information about the
12866 * supported match types that can be used in the encapsulation detection rules
12867 * inserted by MC_CMD_VNIC_ENCAP_RULE_ADD.
12868 */
12869#define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_LENMIN 8
12870#define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_LENMAX 252
12871#define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_LENMAX_MCDI2 1020
12872#define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_LEN(num) (8+4*(num))
12873#define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_SUPPORTED_MATCHES_NUM(len) (((len)-8)/4)
12874/* The op code OP_GET_SUPPORTED_VNIC_ENCAP_MATCHES is returned. */
12875#define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_OP_OFST 0
12876#define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_OP_LEN 4
12877/* Enum values, see field(s): */
12878/* MC_CMD_GET_PARSER_DISP_INFO_IN/OP */
12879/* number of supported match types */
12880#define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_NUM_SUPPORTED_MATCHES_OFST 4
12881#define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_NUM_SUPPORTED_MATCHES_LEN 4
12882/* array of supported match types (valid MATCH_FLAGS values for
12883 * MC_CMD_VNIC_ENCAP_RULE_ADD) sorted in decreasing priority order
12884 */
12885#define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_SUPPORTED_MATCHES_OFST 8
12886#define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_SUPPORTED_MATCHES_LEN 4
12887#define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_SUPPORTED_MATCHES_MINNUM 0
12888#define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_SUPPORTED_MATCHES_MAXNUM 61
12889#define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_SUPPORTED_MATCHES_MAXNUM_MCDI2 253
12890
12891/* MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT msgresponse: Returns
12892 * the supported encapsulation types for the VNIC
12893 */
12894#define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_LEN 8
12895/* The op code OP_GET_SUPPORTED_VNIC_ENCAP_TYPES is returned */
12896#define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_OP_OFST 0
12897#define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_OP_LEN 4
12898/* Enum values, see field(s): */
12899/* MC_CMD_GET_PARSER_DISP_INFO_IN/OP */
12900#define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_ENCAP_TYPES_SUPPORTED_OFST 4
12901#define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_ENCAP_TYPES_SUPPORTED_LEN 4
12902#define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_ENCAP_TYPE_VXLAN_OFST 4
12903#define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_ENCAP_TYPE_VXLAN_LBN 0
12904#define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_ENCAP_TYPE_VXLAN_WIDTH 1
12905#define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_ENCAP_TYPE_NVGRE_OFST 4
12906#define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_ENCAP_TYPE_NVGRE_LBN 1
12907#define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_ENCAP_TYPE_NVGRE_WIDTH 1
12908#define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_ENCAP_TYPE_GENEVE_OFST 4
12909#define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_ENCAP_TYPE_GENEVE_LBN 2
12910#define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_ENCAP_TYPE_GENEVE_WIDTH 1
12911#define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_ENCAP_TYPE_L2GRE_OFST 4
12912#define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_ENCAP_TYPE_L2GRE_LBN 3
12913#define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_ENCAP_TYPE_L2GRE_WIDTH 1
12914
12915
12916/***********************************/
12917/* MC_CMD_PARSER_DISP_RW
12918 * Direct read/write of parser-dispatcher state (DICPUs and LUE) for debugging.
12919 * Please note that this interface is only of use to debug tools which have
12920 * knowledge of firmware and hardware data structures; nothing here is intended
12921 * for use by normal driver code. Note that although this command is in the
12922 * Admin privilege group, in tamperproof adapters, only read operations are
12923 * permitted.
12924 */
12925#define MC_CMD_PARSER_DISP_RW 0xe5
12926#undef MC_CMD_0xe5_PRIVILEGE_CTG
12927
12928#define MC_CMD_0xe5_PRIVILEGE_CTG SRIOV_CTG_ADMIN
12929
12930/* MC_CMD_PARSER_DISP_RW_IN msgrequest */
12931#define MC_CMD_PARSER_DISP_RW_IN_LEN 32
12932/* identifies the target of the operation */
12933#define MC_CMD_PARSER_DISP_RW_IN_TARGET_OFST 0
12934#define MC_CMD_PARSER_DISP_RW_IN_TARGET_LEN 4
12935/* enum: RX dispatcher CPU */
12936#define MC_CMD_PARSER_DISP_RW_IN_RX_DICPU 0x0
12937/* enum: TX dispatcher CPU */
12938#define MC_CMD_PARSER_DISP_RW_IN_TX_DICPU 0x1
12939/* enum: Lookup engine (with original metadata format). Deprecated; used only
12940 * by cmdclient as a fallback for very old Huntington firmware, and not
12941 * supported in firmware beyond v6.4.0.1005. Use LUE_VERSIONED_METADATA
12942 * instead.
12943 */
12944#define MC_CMD_PARSER_DISP_RW_IN_LUE 0x2
12945/* enum: Lookup engine (with requested metadata format) */
12946#define MC_CMD_PARSER_DISP_RW_IN_LUE_VERSIONED_METADATA 0x3
12947/* enum: RX0 dispatcher CPU (alias for RX_DICPU; Medford has 2 RX DICPUs) */
12948#define MC_CMD_PARSER_DISP_RW_IN_RX0_DICPU 0x0
12949/* enum: RX1 dispatcher CPU (only valid for Medford) */
12950#define MC_CMD_PARSER_DISP_RW_IN_RX1_DICPU 0x4
12951/* enum: Miscellaneous other state (only valid for Medford) */
12952#define MC_CMD_PARSER_DISP_RW_IN_MISC_STATE 0x5
12953/* identifies the type of operation requested */
12954#define MC_CMD_PARSER_DISP_RW_IN_OP_OFST 4
12955#define MC_CMD_PARSER_DISP_RW_IN_OP_LEN 4
12956/* enum: Read a word of DICPU DMEM or a LUE entry */
12957#define MC_CMD_PARSER_DISP_RW_IN_READ 0x0
12958/* enum: Write a word of DICPU DMEM or a LUE entry. Not permitted on
12959 * tamperproof adapters.
12960 */
12961#define MC_CMD_PARSER_DISP_RW_IN_WRITE 0x1
12962/* enum: Read-modify-write a word of DICPU DMEM (not valid for LUE). Not
12963 * permitted on tamperproof adapters.
12964 */
12965#define MC_CMD_PARSER_DISP_RW_IN_RMW 0x2
12966/* data memory address (DICPU targets) or LUE index (LUE targets) */
12967#define MC_CMD_PARSER_DISP_RW_IN_ADDRESS_OFST 8
12968#define MC_CMD_PARSER_DISP_RW_IN_ADDRESS_LEN 4
12969/* selector (for MISC_STATE target) */
12970#define MC_CMD_PARSER_DISP_RW_IN_SELECTOR_OFST 8
12971#define MC_CMD_PARSER_DISP_RW_IN_SELECTOR_LEN 4
12972/* enum: Port to datapath mapping */
12973#define MC_CMD_PARSER_DISP_RW_IN_PORT_DP_MAPPING 0x1
12974/* value to write (for DMEM writes) */
12975#define MC_CMD_PARSER_DISP_RW_IN_DMEM_WRITE_VALUE_OFST 12
12976#define MC_CMD_PARSER_DISP_RW_IN_DMEM_WRITE_VALUE_LEN 4
12977/* XOR value (for DMEM read-modify-writes: new = (old & mask) ^ value) */
12978#define MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_XOR_VALUE_OFST 12
12979#define MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_XOR_VALUE_LEN 4
12980/* AND mask (for DMEM read-modify-writes: new = (old & mask) ^ value) */
12981#define MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_AND_MASK_OFST 16
12982#define MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_AND_MASK_LEN 4
12983/* metadata format (for LUE reads using LUE_VERSIONED_METADATA) */
12984#define MC_CMD_PARSER_DISP_RW_IN_LUE_READ_METADATA_VERSION_OFST 12
12985#define MC_CMD_PARSER_DISP_RW_IN_LUE_READ_METADATA_VERSION_LEN 4
12986/* value to write (for LUE writes) */
12987#define MC_CMD_PARSER_DISP_RW_IN_LUE_WRITE_VALUE_OFST 12
12988#define MC_CMD_PARSER_DISP_RW_IN_LUE_WRITE_VALUE_LEN 20
12989
12990/* MC_CMD_PARSER_DISP_RW_OUT msgresponse */
12991#define MC_CMD_PARSER_DISP_RW_OUT_LEN 52
12992/* value read (for DMEM reads) */
12993#define MC_CMD_PARSER_DISP_RW_OUT_DMEM_READ_VALUE_OFST 0
12994#define MC_CMD_PARSER_DISP_RW_OUT_DMEM_READ_VALUE_LEN 4
12995/* value read (for LUE reads) */
12996#define MC_CMD_PARSER_DISP_RW_OUT_LUE_READ_VALUE_OFST 0
12997#define MC_CMD_PARSER_DISP_RW_OUT_LUE_READ_VALUE_LEN 20
12998/* up to 8 32-bit words of additional soft state from the LUE manager (the
12999 * exact content is firmware-dependent and intended only for debug use)
13000 */
13001#define MC_CMD_PARSER_DISP_RW_OUT_LUE_MGR_STATE_OFST 20
13002#define MC_CMD_PARSER_DISP_RW_OUT_LUE_MGR_STATE_LEN 32
13003/* datapath(s) used for each port (for MISC_STATE PORT_DP_MAPPING selector) */
13004#define MC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_OFST 0
13005#define MC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_LEN 4
13006#define MC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_NUM 4
13007#define MC_CMD_PARSER_DISP_RW_OUT_DP0 0x1 /* enum */
13008#define MC_CMD_PARSER_DISP_RW_OUT_DP1 0x2 /* enum */
13009
13010
13011/***********************************/
13012/* MC_CMD_GET_PF_COUNT
13013 * Get number of PFs on the device.
13014 */
13015#define MC_CMD_GET_PF_COUNT 0xb6
13016#undef MC_CMD_0xb6_PRIVILEGE_CTG
13017
13018#define MC_CMD_0xb6_PRIVILEGE_CTG SRIOV_CTG_GENERAL
13019
13020/* MC_CMD_GET_PF_COUNT_IN msgrequest */
13021#define MC_CMD_GET_PF_COUNT_IN_LEN 0
13022
13023/* MC_CMD_GET_PF_COUNT_OUT msgresponse */
13024#define MC_CMD_GET_PF_COUNT_OUT_LEN 1
13025/* Identifies the number of PFs on the device. */
13026#define MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_OFST 0
13027#define MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_LEN 1
13028
13029
13030/***********************************/
13031/* MC_CMD_SET_PF_COUNT
13032 * Set number of PFs on the device.
13033 */
13034#define MC_CMD_SET_PF_COUNT 0xb7
13035
13036/* MC_CMD_SET_PF_COUNT_IN msgrequest */
13037#define MC_CMD_SET_PF_COUNT_IN_LEN 4
13038/* New number of PFs on the device. */
13039#define MC_CMD_SET_PF_COUNT_IN_PF_COUNT_OFST 0
13040#define MC_CMD_SET_PF_COUNT_IN_PF_COUNT_LEN 4
13041
13042/* MC_CMD_SET_PF_COUNT_OUT msgresponse */
13043#define MC_CMD_SET_PF_COUNT_OUT_LEN 0
13044
13045
13046/***********************************/
13047/* MC_CMD_GET_PORT_ASSIGNMENT
13048 * Get port assignment for current PCI function.
13049 */
13050#define MC_CMD_GET_PORT_ASSIGNMENT 0xb8
13051#undef MC_CMD_0xb8_PRIVILEGE_CTG
13052
13053#define MC_CMD_0xb8_PRIVILEGE_CTG SRIOV_CTG_GENERAL
13054
13055/* MC_CMD_GET_PORT_ASSIGNMENT_IN msgrequest */
13056#define MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN 0
13057
13058/* MC_CMD_GET_PORT_ASSIGNMENT_OUT msgresponse */
13059#define MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN 4
13060/* Identifies the port assignment for this function. On EF100, it is possible
13061 * for the function to have no network port assigned (either because it is not
13062 * yet configured, or assigning a port to a given function personality makes no
13063 * sense - e.g. virtio-blk), in which case the return value is NULL_PORT.
13064 */
13065#define MC_CMD_GET_PORT_ASSIGNMENT_OUT_PORT_OFST 0
13066#define MC_CMD_GET_PORT_ASSIGNMENT_OUT_PORT_LEN 4
13067/* enum: Special value to indicate no port is assigned to a function. */
13068#define MC_CMD_GET_PORT_ASSIGNMENT_OUT_NULL_PORT 0xffffffff
13069
13070
13071/***********************************/
13072/* MC_CMD_SET_PORT_ASSIGNMENT
13073 * Set port assignment for current PCI function.
13074 */
13075#define MC_CMD_SET_PORT_ASSIGNMENT 0xb9
13076#undef MC_CMD_0xb9_PRIVILEGE_CTG
13077
13078#define MC_CMD_0xb9_PRIVILEGE_CTG SRIOV_CTG_ADMIN
13079
13080/* MC_CMD_SET_PORT_ASSIGNMENT_IN msgrequest */
13081#define MC_CMD_SET_PORT_ASSIGNMENT_IN_LEN 4
13082/* Identifies the port assignment for this function. */
13083#define MC_CMD_SET_PORT_ASSIGNMENT_IN_PORT_OFST 0
13084#define MC_CMD_SET_PORT_ASSIGNMENT_IN_PORT_LEN 4
13085
13086/* MC_CMD_SET_PORT_ASSIGNMENT_OUT msgresponse */
13087#define MC_CMD_SET_PORT_ASSIGNMENT_OUT_LEN 0
13088
13089
13090/***********************************/
13091/* MC_CMD_ALLOC_VIS
13092 * Allocate VIs for current PCI function.
13093 */
13094#define MC_CMD_ALLOC_VIS 0x8b
13095#undef MC_CMD_0x8b_PRIVILEGE_CTG
13096
13097#define MC_CMD_0x8b_PRIVILEGE_CTG SRIOV_CTG_GENERAL
13098
13099/* MC_CMD_ALLOC_VIS_IN msgrequest */
13100#define MC_CMD_ALLOC_VIS_IN_LEN 8
13101/* The minimum number of VIs that is acceptable */
13102#define MC_CMD_ALLOC_VIS_IN_MIN_VI_COUNT_OFST 0
13103#define MC_CMD_ALLOC_VIS_IN_MIN_VI_COUNT_LEN 4
13104/* The maximum number of VIs that would be useful */
13105#define MC_CMD_ALLOC_VIS_IN_MAX_VI_COUNT_OFST 4
13106#define MC_CMD_ALLOC_VIS_IN_MAX_VI_COUNT_LEN 4
13107
13108/* MC_CMD_ALLOC_VIS_OUT msgresponse: Huntington-compatible VI_ALLOC request.
13109 * Use extended version in new code.
13110 */
13111#define MC_CMD_ALLOC_VIS_OUT_LEN 8
13112/* The number of VIs allocated on this function */
13113#define MC_CMD_ALLOC_VIS_OUT_VI_COUNT_OFST 0
13114#define MC_CMD_ALLOC_VIS_OUT_VI_COUNT_LEN 4
13115/* The base absolute VI number allocated to this function. Required to
13116 * correctly interpret wakeup events.
13117 */
13118#define MC_CMD_ALLOC_VIS_OUT_VI_BASE_OFST 4
13119#define MC_CMD_ALLOC_VIS_OUT_VI_BASE_LEN 4
13120
13121/* MC_CMD_ALLOC_VIS_EXT_OUT msgresponse */
13122#define MC_CMD_ALLOC_VIS_EXT_OUT_LEN 12
13123/* The number of VIs allocated on this function */
13124#define MC_CMD_ALLOC_VIS_EXT_OUT_VI_COUNT_OFST 0
13125#define MC_CMD_ALLOC_VIS_EXT_OUT_VI_COUNT_LEN 4
13126/* The base absolute VI number allocated to this function. Required to
13127 * correctly interpret wakeup events.
13128 */
13129#define MC_CMD_ALLOC_VIS_EXT_OUT_VI_BASE_OFST 4
13130#define MC_CMD_ALLOC_VIS_EXT_OUT_VI_BASE_LEN 4
13131/* Function's port vi_shift value (always 0 on Huntington) */
13132#define MC_CMD_ALLOC_VIS_EXT_OUT_VI_SHIFT_OFST 8
13133#define MC_CMD_ALLOC_VIS_EXT_OUT_VI_SHIFT_LEN 4
13134
13135
13136/***********************************/
13137/* MC_CMD_FREE_VIS
13138 * Free VIs for current PCI function. Any linked PIO buffers will be unlinked,
13139 * but not freed.
13140 */
13141#define MC_CMD_FREE_VIS 0x8c
13142#undef MC_CMD_0x8c_PRIVILEGE_CTG
13143
13144#define MC_CMD_0x8c_PRIVILEGE_CTG SRIOV_CTG_GENERAL
13145
13146/* MC_CMD_FREE_VIS_IN msgrequest */
13147#define MC_CMD_FREE_VIS_IN_LEN 0
13148
13149/* MC_CMD_FREE_VIS_OUT msgresponse */
13150#define MC_CMD_FREE_VIS_OUT_LEN 0
13151
13152
13153/***********************************/
13154/* MC_CMD_GET_SRIOV_CFG
13155 * Get SRIOV config for this PF.
13156 */
13157#define MC_CMD_GET_SRIOV_CFG 0xba
13158#undef MC_CMD_0xba_PRIVILEGE_CTG
13159
13160#define MC_CMD_0xba_PRIVILEGE_CTG SRIOV_CTG_GENERAL
13161
13162/* MC_CMD_GET_SRIOV_CFG_IN msgrequest */
13163#define MC_CMD_GET_SRIOV_CFG_IN_LEN 0
13164
13165/* MC_CMD_GET_SRIOV_CFG_OUT msgresponse */
13166#define MC_CMD_GET_SRIOV_CFG_OUT_LEN 20
13167/* Number of VFs currently enabled. */
13168#define MC_CMD_GET_SRIOV_CFG_OUT_VF_CURRENT_OFST 0
13169#define MC_CMD_GET_SRIOV_CFG_OUT_VF_CURRENT_LEN 4
13170/* Max number of VFs before sriov stride and offset may need to be changed. */
13171#define MC_CMD_GET_SRIOV_CFG_OUT_VF_MAX_OFST 4
13172#define MC_CMD_GET_SRIOV_CFG_OUT_VF_MAX_LEN 4
13173#define MC_CMD_GET_SRIOV_CFG_OUT_FLAGS_OFST 8
13174#define MC_CMD_GET_SRIOV_CFG_OUT_FLAGS_LEN 4
13175#define MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_OFST 8
13176#define MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_LBN 0
13177#define MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_WIDTH 1
13178/* RID offset of first VF from PF. */
13179#define MC_CMD_GET_SRIOV_CFG_OUT_VF_OFFSET_OFST 12
13180#define MC_CMD_GET_SRIOV_CFG_OUT_VF_OFFSET_LEN 4
13181/* RID offset of each subsequent VF from the previous. */
13182#define MC_CMD_GET_SRIOV_CFG_OUT_VF_STRIDE_OFST 16
13183#define MC_CMD_GET_SRIOV_CFG_OUT_VF_STRIDE_LEN 4
13184
13185
13186/***********************************/
13187/* MC_CMD_SET_SRIOV_CFG
13188 * Set SRIOV config for this PF.
13189 */
13190#define MC_CMD_SET_SRIOV_CFG 0xbb
13191#undef MC_CMD_0xbb_PRIVILEGE_CTG
13192
13193#define MC_CMD_0xbb_PRIVILEGE_CTG SRIOV_CTG_ADMIN
13194
13195/* MC_CMD_SET_SRIOV_CFG_IN msgrequest */
13196#define MC_CMD_SET_SRIOV_CFG_IN_LEN 20
13197/* Number of VFs currently enabled. */
13198#define MC_CMD_SET_SRIOV_CFG_IN_VF_CURRENT_OFST 0
13199#define MC_CMD_SET_SRIOV_CFG_IN_VF_CURRENT_LEN 4
13200/* Max number of VFs before sriov stride and offset may need to be changed. */
13201#define MC_CMD_SET_SRIOV_CFG_IN_VF_MAX_OFST 4
13202#define MC_CMD_SET_SRIOV_CFG_IN_VF_MAX_LEN 4
13203#define MC_CMD_SET_SRIOV_CFG_IN_FLAGS_OFST 8
13204#define MC_CMD_SET_SRIOV_CFG_IN_FLAGS_LEN 4
13205#define MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_OFST 8
13206#define MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_LBN 0
13207#define MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_WIDTH 1
13208/* RID offset of first VF from PF, or 0 for no change, or
13209 * MC_CMD_RESOURCE_INSTANCE_ANY to allow the system to allocate an offset.
13210 */
13211#define MC_CMD_SET_SRIOV_CFG_IN_VF_OFFSET_OFST 12
13212#define MC_CMD_SET_SRIOV_CFG_IN_VF_OFFSET_LEN 4
13213/* RID offset of each subsequent VF from the previous, 0 for no change, or
13214 * MC_CMD_RESOURCE_INSTANCE_ANY to allow the system to allocate a stride.
13215 */
13216#define MC_CMD_SET_SRIOV_CFG_IN_VF_STRIDE_OFST 16
13217#define MC_CMD_SET_SRIOV_CFG_IN_VF_STRIDE_LEN 4
13218
13219/* MC_CMD_SET_SRIOV_CFG_OUT msgresponse */
13220#define MC_CMD_SET_SRIOV_CFG_OUT_LEN 0
13221
13222
13223/***********************************/
13224/* MC_CMD_GET_VI_ALLOC_INFO
13225 * Get information about number of VI's and base VI number allocated to this
13226 * function. This message is not available to dynamic clients created by
13227 * MC_CMD_CLIENT_ALLOC.
13228 */
13229#define MC_CMD_GET_VI_ALLOC_INFO 0x8d
13230#undef MC_CMD_0x8d_PRIVILEGE_CTG
13231
13232#define MC_CMD_0x8d_PRIVILEGE_CTG SRIOV_CTG_GENERAL
13233
13234/* MC_CMD_GET_VI_ALLOC_INFO_IN msgrequest */
13235#define MC_CMD_GET_VI_ALLOC_INFO_IN_LEN 0
13236
13237/* MC_CMD_GET_VI_ALLOC_INFO_OUT msgresponse */
13238#define MC_CMD_GET_VI_ALLOC_INFO_OUT_LEN 12
13239/* The number of VIs allocated on this function */
13240#define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_COUNT_OFST 0
13241#define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_COUNT_LEN 4
13242/* The base absolute VI number allocated to this function. Required to
13243 * correctly interpret wakeup events.
13244 */
13245#define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_BASE_OFST 4
13246#define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_BASE_LEN 4
13247/* Function's port vi_shift value (always 0 on Huntington) */
13248#define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_SHIFT_OFST 8
13249#define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_SHIFT_LEN 4
13250
13251
13252/***********************************/
13253/* MC_CMD_DUMP_VI_STATE
13254 * For CmdClient use. Dump pertinent information on a specific absolute VI. The
13255 * VI must be owned by the calling client or one of its ancestors; usership of
13256 * the VI (as set by MC_CMD_SET_VI_USER) is not sufficient.
13257 */
13258#define MC_CMD_DUMP_VI_STATE 0x8e
13259#undef MC_CMD_0x8e_PRIVILEGE_CTG
13260
13261#define MC_CMD_0x8e_PRIVILEGE_CTG SRIOV_CTG_GENERAL
13262
13263/* MC_CMD_DUMP_VI_STATE_IN msgrequest */
13264#define MC_CMD_DUMP_VI_STATE_IN_LEN 4
13265/* The VI number to query. */
13266#define MC_CMD_DUMP_VI_STATE_IN_VI_NUMBER_OFST 0
13267#define MC_CMD_DUMP_VI_STATE_IN_VI_NUMBER_LEN 4
13268
13269/* MC_CMD_DUMP_VI_STATE_OUT msgresponse */
13270#define MC_CMD_DUMP_VI_STATE_OUT_LEN 100
13271/* The PF part of the function owning this VI. */
13272#define MC_CMD_DUMP_VI_STATE_OUT_OWNER_PF_OFST 0
13273#define MC_CMD_DUMP_VI_STATE_OUT_OWNER_PF_LEN 2
13274/* The VF part of the function owning this VI. */
13275#define MC_CMD_DUMP_VI_STATE_OUT_OWNER_VF_OFST 2
13276#define MC_CMD_DUMP_VI_STATE_OUT_OWNER_VF_LEN 2
13277/* Base of VIs allocated to this function. */
13278#define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_BASE_OFST 4
13279#define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_BASE_LEN 2
13280/* Count of VIs allocated to the owner function. */
13281#define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_COUNT_OFST 6
13282#define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_COUNT_LEN 2
13283/* Base interrupt vector allocated to this function. */
13284#define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_BASE_OFST 8
13285#define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_BASE_LEN 2
13286/* Number of interrupt vectors allocated to this function. */
13287#define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_COUNT_OFST 10
13288#define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_COUNT_LEN 2
13289/* Raw evq ptr table data. */
13290#define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_OFST 12
13291#define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LEN 8
13292#define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LO_OFST 12
13293#define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LO_LEN 4
13294#define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LO_LBN 96
13295#define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LO_WIDTH 32
13296#define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_HI_OFST 16
13297#define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_HI_LEN 4
13298#define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_HI_LBN 128
13299#define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_HI_WIDTH 32
13300/* Raw evq timer table data. */
13301#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_OFST 20
13302#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LEN 8
13303#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LO_OFST 20
13304#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LO_LEN 4
13305#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LO_LBN 160
13306#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LO_WIDTH 32
13307#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_HI_OFST 24
13308#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_HI_LEN 4
13309#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_HI_LBN 192
13310#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_HI_WIDTH 32
13311/* Combined metadata field. */
13312#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_OFST 28
13313#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_LEN 4
13314#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_OFST 28
13315#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_LBN 0
13316#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_WIDTH 16
13317#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_OFST 28
13318#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_LBN 16
13319#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_WIDTH 8
13320#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_OFST 28
13321#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_LBN 24
13322#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_WIDTH 8
13323/* TXDPCPU raw table data for queue. */
13324#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_OFST 32
13325#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LEN 8
13326#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LO_OFST 32
13327#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LO_LEN 4
13328#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LO_LBN 256
13329#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LO_WIDTH 32
13330#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_HI_OFST 36
13331#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_HI_LEN 4
13332#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_HI_LBN 288
13333#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_HI_WIDTH 32
13334/* TXDPCPU raw table data for queue. */
13335#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_OFST 40
13336#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LEN 8
13337#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LO_OFST 40
13338#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LO_LEN 4
13339#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LO_LBN 320
13340#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LO_WIDTH 32
13341#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_HI_OFST 44
13342#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_HI_LEN 4
13343#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_HI_LBN 352
13344#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_HI_WIDTH 32
13345/* TXDPCPU raw table data for queue. */
13346#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_OFST 48
13347#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LEN 8
13348#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LO_OFST 48
13349#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LO_LEN 4
13350#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LO_LBN 384
13351#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LO_WIDTH 32
13352#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_HI_OFST 52
13353#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_HI_LEN 4
13354#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_HI_LBN 416
13355#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_HI_WIDTH 32
13356/* Combined metadata field. */
13357#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_OFST 56
13358#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LEN 8
13359#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LO_OFST 56
13360#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LO_LEN 4
13361#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LO_LBN 448
13362#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LO_WIDTH 32
13363#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_HI_OFST 60
13364#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_HI_LEN 4
13365#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_HI_LBN 480
13366#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_HI_WIDTH 32
13367#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_OFST 56
13368#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_LBN 0
13369#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_WIDTH 16
13370#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_OFST 56
13371#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_LBN 16
13372#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_WIDTH 8
13373#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_OFST 56
13374#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_LBN 24
13375#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_WIDTH 8
13376#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_OFST 56
13377#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_LBN 32
13378#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_WIDTH 8
13379#define MC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_OFST 56
13380#define MC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_LBN 40
13381#define MC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_WIDTH 24
13382/* RXDPCPU raw table data for queue. */
13383#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_OFST 64
13384#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LEN 8
13385#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LO_OFST 64
13386#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LO_LEN 4
13387#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LO_LBN 512
13388#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LO_WIDTH 32
13389#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_HI_OFST 68
13390#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_HI_LEN 4
13391#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_HI_LBN 544
13392#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_HI_WIDTH 32
13393/* RXDPCPU raw table data for queue. */
13394#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_OFST 72
13395#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LEN 8
13396#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LO_OFST 72
13397#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LO_LEN 4
13398#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LO_LBN 576
13399#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LO_WIDTH 32
13400#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_HI_OFST 76
13401#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_HI_LEN 4
13402#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_HI_LBN 608
13403#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_HI_WIDTH 32
13404/* Reserved, currently 0. */
13405#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_OFST 80
13406#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LEN 8
13407#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LO_OFST 80
13408#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LO_LEN 4
13409#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LO_LBN 640
13410#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LO_WIDTH 32
13411#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_HI_OFST 84
13412#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_HI_LEN 4
13413#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_HI_LBN 672
13414#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_HI_WIDTH 32
13415/* Combined metadata field. */
13416#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_OFST 88
13417#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LEN 8
13418#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LO_OFST 88
13419#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LO_LEN 4
13420#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LO_LBN 704
13421#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LO_WIDTH 32
13422#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_HI_OFST 92
13423#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_HI_LEN 4
13424#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_HI_LBN 736
13425#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_HI_WIDTH 32
13426#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_OFST 88
13427#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_LBN 0
13428#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_WIDTH 16
13429#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_OFST 88
13430#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_LBN 16
13431#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_WIDTH 8
13432#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_OFST 88
13433#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_LBN 24
13434#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_WIDTH 8
13435#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_OFST 88
13436#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_LBN 32
13437#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_WIDTH 8
13438/* Current user, as assigned by MC_CMD_SET_VI_USER. */
13439#define MC_CMD_DUMP_VI_STATE_OUT_USER_CLIENT_ID_OFST 96
13440#define MC_CMD_DUMP_VI_STATE_OUT_USER_CLIENT_ID_LEN 4
13441
13442
13443/***********************************/
13444/* MC_CMD_ALLOC_PIOBUF
13445 * Allocate a push I/O buffer for later use with a tx queue.
13446 */
13447#define MC_CMD_ALLOC_PIOBUF 0x8f
13448#undef MC_CMD_0x8f_PRIVILEGE_CTG
13449
13450#define MC_CMD_0x8f_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
13451
13452/* MC_CMD_ALLOC_PIOBUF_IN msgrequest */
13453#define MC_CMD_ALLOC_PIOBUF_IN_LEN 0
13454
13455/* MC_CMD_ALLOC_PIOBUF_OUT msgresponse */
13456#define MC_CMD_ALLOC_PIOBUF_OUT_LEN 4
13457/* Handle for allocated push I/O buffer. */
13458#define MC_CMD_ALLOC_PIOBUF_OUT_PIOBUF_HANDLE_OFST 0
13459#define MC_CMD_ALLOC_PIOBUF_OUT_PIOBUF_HANDLE_LEN 4
13460
13461
13462/***********************************/
13463/* MC_CMD_FREE_PIOBUF
13464 * Free a push I/O buffer.
13465 */
13466#define MC_CMD_FREE_PIOBUF 0x90
13467#undef MC_CMD_0x90_PRIVILEGE_CTG
13468
13469#define MC_CMD_0x90_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
13470
13471/* MC_CMD_FREE_PIOBUF_IN msgrequest */
13472#define MC_CMD_FREE_PIOBUF_IN_LEN 4
13473/* Handle for allocated push I/O buffer. */
13474#define MC_CMD_FREE_PIOBUF_IN_PIOBUF_HANDLE_OFST 0
13475#define MC_CMD_FREE_PIOBUF_IN_PIOBUF_HANDLE_LEN 4
13476
13477/* MC_CMD_FREE_PIOBUF_OUT msgresponse */
13478#define MC_CMD_FREE_PIOBUF_OUT_LEN 0
13479
13480
13481/***********************************/
13482/* MC_CMD_GET_VI_TLP_PROCESSING
13483 * Get TLP steering and ordering information for a VI. The caller must have the
13484 * GRP_FUNC_DMA privilege and must be the currently-assigned user of this VI or
13485 * an ancestor of the current user (see MC_CMD_SET_VI_USER).
13486 */
13487#define MC_CMD_GET_VI_TLP_PROCESSING 0xb0
13488#undef MC_CMD_0xb0_PRIVILEGE_CTG
13489
13490#define MC_CMD_0xb0_PRIVILEGE_CTG SRIOV_CTG_GENERAL
13491
13492/* MC_CMD_GET_VI_TLP_PROCESSING_IN msgrequest */
13493#define MC_CMD_GET_VI_TLP_PROCESSING_IN_LEN 4
13494/* VI number to get information for. */
13495#define MC_CMD_GET_VI_TLP_PROCESSING_IN_INSTANCE_OFST 0
13496#define MC_CMD_GET_VI_TLP_PROCESSING_IN_INSTANCE_LEN 4
13497
13498/* MC_CMD_GET_VI_TLP_PROCESSING_OUT msgresponse */
13499#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_LEN 4
13500/* Transaction processing steering hint 1 for use with the Rx Queue. */
13501#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG1_RX_OFST 0
13502#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG1_RX_LEN 1
13503/* Transaction processing steering hint 2 for use with the Ev Queue. */
13504#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG2_EV_OFST 1
13505#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG2_EV_LEN 1
13506/* Use Relaxed ordering model for TLPs on this VI. */
13507#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_RELAXED_ORDERING_LBN 16
13508#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_RELAXED_ORDERING_WIDTH 1
13509/* Use ID based ordering for TLPs on this VI. */
13510#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_ID_BASED_ORDERING_LBN 17
13511#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_ID_BASED_ORDERING_WIDTH 1
13512/* Set no snoop bit for TLPs on this VI. */
13513#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_NO_SNOOP_LBN 18
13514#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_NO_SNOOP_WIDTH 1
13515/* Enable TPH for TLPs on this VI. */
13516#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_ON_LBN 19
13517#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_ON_WIDTH 1
13518#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_DATA_OFST 0
13519#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_DATA_LEN 4
13520
13521
13522/***********************************/
13523/* MC_CMD_SET_VI_TLP_PROCESSING
13524 * Set TLP steering and ordering information for a VI. The caller must have the
13525 * GRP_FUNC_DMA privilege and must be the currently-assigned user of this VI or
13526 * an ancestor of the current user (see MC_CMD_SET_VI_USER).
13527 */
13528#define MC_CMD_SET_VI_TLP_PROCESSING 0xb1
13529#undef MC_CMD_0xb1_PRIVILEGE_CTG
13530
13531#define MC_CMD_0xb1_PRIVILEGE_CTG SRIOV_CTG_GENERAL
13532
13533/* MC_CMD_SET_VI_TLP_PROCESSING_IN msgrequest */
13534#define MC_CMD_SET_VI_TLP_PROCESSING_IN_LEN 8
13535/* VI number to set information for. */
13536#define MC_CMD_SET_VI_TLP_PROCESSING_IN_INSTANCE_OFST 0
13537#define MC_CMD_SET_VI_TLP_PROCESSING_IN_INSTANCE_LEN 4
13538/* Transaction processing steering hint 1 for use with the Rx Queue. */
13539#define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG1_RX_OFST 4
13540#define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG1_RX_LEN 1
13541/* Transaction processing steering hint 2 for use with the Ev Queue. */
13542#define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG2_EV_OFST 5
13543#define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG2_EV_LEN 1
13544/* Use Relaxed ordering model for TLPs on this VI. */
13545#define MC_CMD_SET_VI_TLP_PROCESSING_IN_RELAXED_ORDERING_LBN 48
13546#define MC_CMD_SET_VI_TLP_PROCESSING_IN_RELAXED_ORDERING_WIDTH 1
13547/* Use ID based ordering for TLPs on this VI. */
13548#define MC_CMD_SET_VI_TLP_PROCESSING_IN_ID_BASED_ORDERING_LBN 49
13549#define MC_CMD_SET_VI_TLP_PROCESSING_IN_ID_BASED_ORDERING_WIDTH 1
13550/* Set the no snoop bit for TLPs on this VI. */
13551#define MC_CMD_SET_VI_TLP_PROCESSING_IN_NO_SNOOP_LBN 50
13552#define MC_CMD_SET_VI_TLP_PROCESSING_IN_NO_SNOOP_WIDTH 1
13553/* Enable TPH for TLPs on this VI. */
13554#define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_ON_LBN 51
13555#define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_ON_WIDTH 1
13556#define MC_CMD_SET_VI_TLP_PROCESSING_IN_DATA_OFST 4
13557#define MC_CMD_SET_VI_TLP_PROCESSING_IN_DATA_LEN 4
13558
13559/* MC_CMD_SET_VI_TLP_PROCESSING_OUT msgresponse */
13560#define MC_CMD_SET_VI_TLP_PROCESSING_OUT_LEN 0
13561
13562
13563/***********************************/
13564/* MC_CMD_GET_TLP_PROCESSING_GLOBALS
13565 * Get global PCIe steering and transaction processing configuration.
13566 */
13567#define MC_CMD_GET_TLP_PROCESSING_GLOBALS 0xbc
13568#undef MC_CMD_0xbc_PRIVILEGE_CTG
13569
13570#define MC_CMD_0xbc_PRIVILEGE_CTG SRIOV_CTG_ADMIN
13571
13572/* MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN msgrequest */
13573#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_LEN 4
13574#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_OFST 0
13575#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_LEN 4
13576/* enum: MISC. */
13577#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_MISC 0x0
13578/* enum: IDO. */
13579#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_IDO 0x1
13580/* enum: RO. */
13581#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_RO 0x2
13582/* enum: TPH Type. */
13583#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_TPH_TYPE 0x3
13584
13585/* MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT msgresponse */
13586#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_LEN 8
13587#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_GLOBAL_CATEGORY_OFST 0
13588#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_GLOBAL_CATEGORY_LEN 4
13589/* Enum values, see field(s): */
13590/* MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN/TLP_GLOBAL_CATEGORY */
13591/* Amalgamated TLP info word. */
13592#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_WORD_OFST 4
13593#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_WORD_LEN 4
13594#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_OFST 4
13595#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_LBN 0
13596#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_WIDTH 1
13597#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_OFST 4
13598#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_LBN 1
13599#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_WIDTH 31
13600#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_OFST 4
13601#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_LBN 0
13602#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_WIDTH 1
13603#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_TX_EN_OFST 4
13604#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_TX_EN_LBN 1
13605#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_TX_EN_WIDTH 1
13606#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_EV_EN_OFST 4
13607#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_EV_EN_LBN 2
13608#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_EV_EN_WIDTH 1
13609#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_OFST 4
13610#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_LBN 3
13611#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_WIDTH 1
13612#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_OFST 4
13613#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_LBN 4
13614#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_WIDTH 28
13615#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_OFST 4
13616#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_LBN 0
13617#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_WIDTH 1
13618#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_TXDMA_EN_OFST 4
13619#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_TXDMA_EN_LBN 1
13620#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_TXDMA_EN_WIDTH 1
13621#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_OFST 4
13622#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_LBN 2
13623#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_WIDTH 1
13624#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_OFST 4
13625#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_LBN 3
13626#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_WIDTH 29
13627#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_OFST 4
13628#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_LBN 0
13629#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_WIDTH 2
13630#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_DL_OFST 4
13631#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_DL_LBN 2
13632#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_DL_WIDTH 2
13633#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_TX_OFST 4
13634#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_TX_LBN 4
13635#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_TX_WIDTH 2
13636#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_EV_OFST 4
13637#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_EV_LBN 6
13638#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_EV_WIDTH 2
13639#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_OFST 4
13640#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_LBN 8
13641#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_WIDTH 2
13642#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_OFST 4
13643#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_LBN 9
13644#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_WIDTH 23
13645
13646
13647/***********************************/
13648/* MC_CMD_SET_TLP_PROCESSING_GLOBALS
13649 * Set global PCIe steering and transaction processing configuration.
13650 */
13651#define MC_CMD_SET_TLP_PROCESSING_GLOBALS 0xbd
13652#undef MC_CMD_0xbd_PRIVILEGE_CTG
13653
13654#define MC_CMD_0xbd_PRIVILEGE_CTG SRIOV_CTG_ADMIN
13655
13656/* MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN msgrequest */
13657#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_LEN 8
13658#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_OFST 0
13659#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_LEN 4
13660/* Enum values, see field(s): */
13661/* MC_CMD_GET_TLP_PROCESSING_GLOBALS/MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN/TLP_GLOBAL_CATEGORY */
13662/* Amalgamated TLP info word. */
13663#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_WORD_OFST 4
13664#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_WORD_LEN 4
13665#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_OFST 4
13666#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_LBN 0
13667#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_WIDTH 1
13668#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_OFST 4
13669#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_LBN 0
13670#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_WIDTH 1
13671#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_TX_EN_OFST 4
13672#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_TX_EN_LBN 1
13673#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_TX_EN_WIDTH 1
13674#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_EV_EN_OFST 4
13675#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_EV_EN_LBN 2
13676#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_EV_EN_WIDTH 1
13677#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_RX_EN_OFST 4
13678#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_RX_EN_LBN 3
13679#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_RX_EN_WIDTH 1
13680#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_RXDMA_EN_OFST 4
13681#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_RXDMA_EN_LBN 0
13682#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_RXDMA_EN_WIDTH 1
13683#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_TXDMA_EN_OFST 4
13684#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_TXDMA_EN_LBN 1
13685#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_TXDMA_EN_WIDTH 1
13686#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_DL_EN_OFST 4
13687#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_DL_EN_LBN 2
13688#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_DL_EN_WIDTH 1
13689#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_MSIX_OFST 4
13690#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_MSIX_LBN 0
13691#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_MSIX_WIDTH 2
13692#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_DL_OFST 4
13693#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_DL_LBN 2
13694#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_DL_WIDTH 2
13695#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_TX_OFST 4
13696#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_TX_LBN 4
13697#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_TX_WIDTH 2
13698#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_EV_OFST 4
13699#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_EV_LBN 6
13700#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_EV_WIDTH 2
13701#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_OFST 4
13702#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_LBN 8
13703#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_WIDTH 2
13704#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_OFST 4
13705#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_LBN 10
13706#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_WIDTH 22
13707
13708/* MC_CMD_SET_TLP_PROCESSING_GLOBALS_OUT msgresponse */
13709#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_OUT_LEN 0
13710
13711
13712/***********************************/
13713/* MC_CMD_SATELLITE_DOWNLOAD
13714 * Download a new set of images to the satellite CPUs from the host.
13715 */
13716#define MC_CMD_SATELLITE_DOWNLOAD 0x91
13717#undef MC_CMD_0x91_PRIVILEGE_CTG
13718
13719#define MC_CMD_0x91_PRIVILEGE_CTG SRIOV_CTG_ADMIN
13720
13721/* MC_CMD_SATELLITE_DOWNLOAD_IN msgrequest: The reset requirements for the CPUs
13722 * are subtle, and so downloads must proceed in a number of phases.
13723 *
13724 * 1) PHASE_RESET with a target of TARGET_ALL and chunk ID/length of 0.
13725 *
13726 * 2) PHASE_IMEMS for each of the IMEM targets (target IDs 0-11). Each download
13727 * may consist of multiple chunks. The final chunk (with CHUNK_ID_LAST) should
13728 * be a checksum (a simple 32-bit sum) of the transferred data. An individual
13729 * download may be aborted using CHUNK_ID_ABORT.
13730 *
13731 * 3) PHASE_VECTORS for each of the vector table targets (target IDs 12-15),
13732 * similar to PHASE_IMEMS.
13733 *
13734 * 4) PHASE_READY with a target of TARGET_ALL and chunk ID/length of 0.
13735 *
13736 * After any error (a requested abort is not considered to be an error) the
13737 * sequence must be restarted from PHASE_RESET.
13738 */
13739#define MC_CMD_SATELLITE_DOWNLOAD_IN_LENMIN 20
13740#define MC_CMD_SATELLITE_DOWNLOAD_IN_LENMAX 252
13741#define MC_CMD_SATELLITE_DOWNLOAD_IN_LENMAX_MCDI2 1020
13742#define MC_CMD_SATELLITE_DOWNLOAD_IN_LEN(num) (16+4*(num))
13743#define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_NUM(len) (((len)-16)/4)
13744/* Download phase. (Note: the IDLE phase is used internally and is never valid
13745 * in a command from the host.)
13746 */
13747#define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_OFST 0
13748#define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_LEN 4
13749#define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_IDLE 0x0 /* enum */
13750#define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_RESET 0x1 /* enum */
13751#define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_IMEMS 0x2 /* enum */
13752#define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_VECTORS 0x3 /* enum */
13753#define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_READY 0x4 /* enum */
13754/* Target for download. (These match the blob numbers defined in
13755 * mc_flash_layout.h.)
13756 */
13757#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_OFST 4
13758#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_LEN 4
13759/* enum: Valid in phase 2 (PHASE_IMEMS) only */
13760#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_TEXT 0x0
13761/* enum: Valid in phase 2 (PHASE_IMEMS) only */
13762#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_TEXT 0x1
13763/* enum: Valid in phase 2 (PHASE_IMEMS) only */
13764#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDP_TEXT 0x2
13765/* enum: Valid in phase 2 (PHASE_IMEMS) only */
13766#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDP_TEXT 0x3
13767/* enum: Valid in phase 2 (PHASE_IMEMS) only */
13768#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_LUT 0x4
13769/* enum: Valid in phase 2 (PHASE_IMEMS) only */
13770#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_LUT_CFG 0x5
13771/* enum: Valid in phase 2 (PHASE_IMEMS) only */
13772#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_LUT 0x6
13773/* enum: Valid in phase 2 (PHASE_IMEMS) only */
13774#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_LUT_CFG 0x7
13775/* enum: Valid in phase 2 (PHASE_IMEMS) only */
13776#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_PGM 0x8
13777/* enum: Valid in phase 2 (PHASE_IMEMS) only */
13778#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_SL_PGM 0x9
13779/* enum: Valid in phase 2 (PHASE_IMEMS) only */
13780#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_PGM 0xa
13781/* enum: Valid in phase 2 (PHASE_IMEMS) only */
13782#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_SL_PGM 0xb
13783/* enum: Valid in phase 3 (PHASE_VECTORS) only */
13784#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_VTBL0 0xc
13785/* enum: Valid in phase 3 (PHASE_VECTORS) only */
13786#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_VTBL0 0xd
13787/* enum: Valid in phase 3 (PHASE_VECTORS) only */
13788#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_VTBL1 0xe
13789/* enum: Valid in phase 3 (PHASE_VECTORS) only */
13790#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_VTBL1 0xf
13791/* enum: Valid in phases 1 (PHASE_RESET) and 4 (PHASE_READY) only */
13792#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_ALL 0xffffffff
13793/* Chunk ID, or CHUNK_ID_LAST or CHUNK_ID_ABORT */
13794#define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_OFST 8
13795#define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_LEN 4
13796/* enum: Last chunk, containing checksum rather than data */
13797#define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_LAST 0xffffffff
13798/* enum: Abort download of this item */
13799#define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_ABORT 0xfffffffe
13800/* Length of this chunk in bytes */
13801#define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_LEN_OFST 12
13802#define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_LEN_LEN 4
13803/* Data for this chunk */
13804#define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_OFST 16
13805#define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_LEN 4
13806#define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_MINNUM 1
13807#define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_MAXNUM 59
13808#define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_MAXNUM_MCDI2 251
13809
13810/* MC_CMD_SATELLITE_DOWNLOAD_OUT msgresponse */
13811#define MC_CMD_SATELLITE_DOWNLOAD_OUT_LEN 8
13812/* Same as MC_CMD_ERR field, but included as 0 in success cases */
13813#define MC_CMD_SATELLITE_DOWNLOAD_OUT_RESULT_OFST 0
13814#define MC_CMD_SATELLITE_DOWNLOAD_OUT_RESULT_LEN 4
13815/* Extra status information */
13816#define MC_CMD_SATELLITE_DOWNLOAD_OUT_INFO_OFST 4
13817#define MC_CMD_SATELLITE_DOWNLOAD_OUT_INFO_LEN 4
13818/* enum: Code download OK, completed. */
13819#define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_COMPLETE 0x0
13820/* enum: Code download aborted as requested. */
13821#define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_ABORTED 0x1
13822/* enum: Code download OK so far, send next chunk. */
13823#define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_NEXT_CHUNK 0x2
13824/* enum: Download phases out of sequence */
13825#define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_PHASE 0x100
13826/* enum: Bad target for this phase */
13827#define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_TARGET 0x101
13828/* enum: Chunk ID out of sequence */
13829#define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHUNK_ID 0x200
13830/* enum: Chunk length zero or too large */
13831#define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHUNK_LEN 0x201
13832/* enum: Checksum was incorrect */
13833#define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHECKSUM 0x300
13834
13835
13836/***********************************/
13837/* MC_CMD_GET_CAPABILITIES
13838 * Get device capabilities.
13839 *
13840 * This is supplementary to the MC_CMD_GET_BOARD_CFG command, and intended to
13841 * reference inherent device capabilities as opposed to current NVRAM config.
13842 */
13843#define MC_CMD_GET_CAPABILITIES 0xbe
13844#undef MC_CMD_0xbe_PRIVILEGE_CTG
13845
13846#define MC_CMD_0xbe_PRIVILEGE_CTG SRIOV_CTG_GENERAL
13847
13848/* MC_CMD_GET_CAPABILITIES_IN msgrequest */
13849#define MC_CMD_GET_CAPABILITIES_IN_LEN 0
13850
13851/* MC_CMD_GET_CAPABILITIES_OUT msgresponse */
13852#define MC_CMD_GET_CAPABILITIES_OUT_LEN 20
13853/* First word of flags. */
13854#define MC_CMD_GET_CAPABILITIES_OUT_FLAGS1_OFST 0
13855#define MC_CMD_GET_CAPABILITIES_OUT_FLAGS1_LEN 4
13856#define MC_CMD_GET_CAPABILITIES_OUT_VPORT_RECONFIGURE_OFST 0
13857#define MC_CMD_GET_CAPABILITIES_OUT_VPORT_RECONFIGURE_LBN 3
13858#define MC_CMD_GET_CAPABILITIES_OUT_VPORT_RECONFIGURE_WIDTH 1
13859#define MC_CMD_GET_CAPABILITIES_OUT_TX_STRIPING_OFST 0
13860#define MC_CMD_GET_CAPABILITIES_OUT_TX_STRIPING_LBN 4
13861#define MC_CMD_GET_CAPABILITIES_OUT_TX_STRIPING_WIDTH 1
13862#define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_OFST 0
13863#define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_LBN 5
13864#define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_WIDTH 1
13865#define MC_CMD_GET_CAPABILITIES_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
13866#define MC_CMD_GET_CAPABILITIES_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6
13867#define MC_CMD_GET_CAPABILITIES_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
13868#define MC_CMD_GET_CAPABILITIES_OUT_DRV_ATTACH_PREBOOT_OFST 0
13869#define MC_CMD_GET_CAPABILITIES_OUT_DRV_ATTACH_PREBOOT_LBN 7
13870#define MC_CMD_GET_CAPABILITIES_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
13871#define MC_CMD_GET_CAPABILITIES_OUT_RX_FORCE_EVENT_MERGING_OFST 0
13872#define MC_CMD_GET_CAPABILITIES_OUT_RX_FORCE_EVENT_MERGING_LBN 8
13873#define MC_CMD_GET_CAPABILITIES_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
13874#define MC_CMD_GET_CAPABILITIES_OUT_SET_MAC_ENHANCED_OFST 0
13875#define MC_CMD_GET_CAPABILITIES_OUT_SET_MAC_ENHANCED_LBN 9
13876#define MC_CMD_GET_CAPABILITIES_OUT_SET_MAC_ENHANCED_WIDTH 1
13877#define MC_CMD_GET_CAPABILITIES_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
13878#define MC_CMD_GET_CAPABILITIES_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10
13879#define MC_CMD_GET_CAPABILITIES_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
13880#define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
13881#define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11
13882#define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
13883#define MC_CMD_GET_CAPABILITIES_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
13884#define MC_CMD_GET_CAPABILITIES_OUT_TX_MAC_SECURITY_FILTERING_LBN 12
13885#define MC_CMD_GET_CAPABILITIES_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
13886#define MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_OFST 0
13887#define MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_LBN 13
13888#define MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
13889#define MC_CMD_GET_CAPABILITIES_OUT_QBB_OFST 0
13890#define MC_CMD_GET_CAPABILITIES_OUT_QBB_LBN 14
13891#define MC_CMD_GET_CAPABILITIES_OUT_QBB_WIDTH 1
13892#define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
13893#define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15
13894#define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
13895#define MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_OFST 0
13896#define MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_LBN 16
13897#define MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_WIDTH 1
13898#define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_OFST 0
13899#define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_LBN 17
13900#define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_WIDTH 1
13901#define MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_OFST 0
13902#define MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_LBN 18
13903#define MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_WIDTH 1
13904#define MC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_OFST 0
13905#define MC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_LBN 19
13906#define MC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_WIDTH 1
13907#define MC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_OFST 0
13908#define MC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_LBN 20
13909#define MC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_WIDTH 1
13910#define MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_OFST 0
13911#define MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN 21
13912#define MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_WIDTH 1
13913#define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_OFST 0
13914#define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_LBN 22
13915#define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_WIDTH 1
13916#define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_OFST 0
13917#define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN 23
13918#define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_WIDTH 1
13919#define MC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_OFST 0
13920#define MC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_LBN 24
13921#define MC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_WIDTH 1
13922#define MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_OFST 0
13923#define MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN 25
13924#define MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_WIDTH 1
13925#define MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_OFST 0
13926#define MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_LBN 26
13927#define MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_WIDTH 1
13928#define MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_OFST 0
13929#define MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN 27
13930#define MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
13931#define MC_CMD_GET_CAPABILITIES_OUT_RX_DISABLE_SCATTER_OFST 0
13932#define MC_CMD_GET_CAPABILITIES_OUT_RX_DISABLE_SCATTER_LBN 28
13933#define MC_CMD_GET_CAPABILITIES_OUT_RX_DISABLE_SCATTER_WIDTH 1
13934#define MC_CMD_GET_CAPABILITIES_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
13935#define MC_CMD_GET_CAPABILITIES_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29
13936#define MC_CMD_GET_CAPABILITIES_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
13937#define MC_CMD_GET_CAPABILITIES_OUT_EVB_OFST 0
13938#define MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN 30
13939#define MC_CMD_GET_CAPABILITIES_OUT_EVB_WIDTH 1
13940#define MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_OFST 0
13941#define MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN 31
13942#define MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_WIDTH 1
13943/* RxDPCPU firmware id. */
13944#define MC_CMD_GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID_OFST 4
13945#define MC_CMD_GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID_LEN 2
13946/* enum: Standard RXDP firmware */
13947#define MC_CMD_GET_CAPABILITIES_OUT_RXDP 0x0
13948/* enum: Low latency RXDP firmware */
13949#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_LOW_LATENCY 0x1
13950/* enum: Packed stream RXDP firmware */
13951#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_PACKED_STREAM 0x2
13952/* enum: Rules engine RXDP firmware */
13953#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_RULES_ENGINE 0x5
13954/* enum: DPDK RXDP firmware */
13955#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_DPDK 0x6
13956/* enum: BIST RXDP firmware */
13957#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_BIST 0x10a
13958/* enum: RXDP Test firmware image 1 */
13959#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
13960/* enum: RXDP Test firmware image 2 */
13961#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
13962/* enum: RXDP Test firmware image 3 */
13963#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
13964/* enum: RXDP Test firmware image 4 */
13965#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
13966/* enum: RXDP Test firmware image 5 */
13967#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_BACKPRESSURE 0x105
13968/* enum: RXDP Test firmware image 6 */
13969#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
13970/* enum: RXDP Test firmware image 7 */
13971#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
13972/* enum: RXDP Test firmware image 8 */
13973#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
13974/* enum: RXDP Test firmware image 9 */
13975#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
13976/* enum: RXDP Test firmware image 10 */
13977#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_SLOW 0x10c
13978/* TxDPCPU firmware id. */
13979#define MC_CMD_GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID_OFST 6
13980#define MC_CMD_GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID_LEN 2
13981/* enum: Standard TXDP firmware */
13982#define MC_CMD_GET_CAPABILITIES_OUT_TXDP 0x0
13983/* enum: Low latency TXDP firmware */
13984#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_LOW_LATENCY 0x1
13985/* enum: High packet rate TXDP firmware */
13986#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_HIGH_PACKET_RATE 0x3
13987/* enum: Rules engine TXDP firmware */
13988#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_RULES_ENGINE 0x5
13989/* enum: DPDK TXDP firmware */
13990#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_DPDK 0x6
13991/* enum: BIST TXDP firmware */
13992#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_BIST 0x12d
13993/* enum: TXDP Test firmware image 1 */
13994#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
13995/* enum: TXDP Test firmware image 2 */
13996#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
13997/* enum: TXDP CSR bus test firmware */
13998#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_CSR 0x103
13999#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_OFST 8
14000#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_LEN 2
14001#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_OFST 8
14002#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_LBN 0
14003#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_WIDTH 12
14004#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_OFST 8
14005#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_LBN 12
14006#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
14007/* enum: reserved value - do not use (may indicate alternative interpretation
14008 * of REV field in future)
14009 */
14010#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_RESERVED 0x0
14011/* enum: Trivial RX PD firmware for early Huntington development (Huntington
14012 * development only)
14013 */
14014#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
14015/* enum: RX PD firmware for telemetry prototyping (Medford2 development only)
14016 */
14017#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
14018/* enum: RX PD firmware with approximately Siena-compatible behaviour
14019 * (Huntington development only)
14020 */
14021#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
14022/* enum: Full featured RX PD production firmware */
14023#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
14024/* enum: (deprecated original name for the FULL_FEATURED variant) */
14025#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_VSWITCH 0x3
14026/* enum: siena_compat variant RX PD firmware using PM rather than MAC
14027 * (Huntington development only)
14028 */
14029#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
14030/* enum: Low latency RX PD production firmware */
14031#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
14032/* enum: Packed stream RX PD production firmware */
14033#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
14034/* enum: RX PD firmware handling layer 2 only for high packet rate performance
14035 * tests (Medford development only)
14036 */
14037#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
14038/* enum: Rules engine RX PD production firmware */
14039#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
14040/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
14041#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_L3XUDP 0x9
14042/* enum: DPDK RX PD production firmware */
14043#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_DPDK 0xa
14044/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
14045#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
14046/* enum: RX PD firmware parsing but not filtering network overlay tunnel
14047 * encapsulations (Medford development only)
14048 */
14049#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
14050#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_OFST 10
14051#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_LEN 2
14052#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_OFST 10
14053#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_LBN 0
14054#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_WIDTH 12
14055#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_OFST 10
14056#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_LBN 12
14057#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
14058/* enum: reserved value - do not use (may indicate alternative interpretation
14059 * of REV field in future)
14060 */
14061#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_RESERVED 0x0
14062/* enum: Trivial TX PD firmware for early Huntington development (Huntington
14063 * development only)
14064 */
14065#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
14066/* enum: TX PD firmware for telemetry prototyping (Medford2 development only)
14067 */
14068#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
14069/* enum: TX PD firmware with approximately Siena-compatible behaviour
14070 * (Huntington development only)
14071 */
14072#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
14073/* enum: Full featured TX PD production firmware */
14074#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
14075/* enum: (deprecated original name for the FULL_FEATURED variant) */
14076#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_VSWITCH 0x3
14077/* enum: siena_compat variant TX PD firmware using PM rather than MAC
14078 * (Huntington development only)
14079 */
14080#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
14081#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
14082/* enum: TX PD firmware handling layer 2 only for high packet rate performance
14083 * tests (Medford development only)
14084 */
14085#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
14086/* enum: Rules engine TX PD production firmware */
14087#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
14088/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
14089#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_L3XUDP 0x9
14090/* enum: DPDK TX PD production firmware */
14091#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_DPDK 0xa
14092/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
14093#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
14094/* Hardware capabilities of NIC */
14095#define MC_CMD_GET_CAPABILITIES_OUT_HW_CAPABILITIES_OFST 12
14096#define MC_CMD_GET_CAPABILITIES_OUT_HW_CAPABILITIES_LEN 4
14097/* Licensed capabilities */
14098#define MC_CMD_GET_CAPABILITIES_OUT_LICENSE_CAPABILITIES_OFST 16
14099#define MC_CMD_GET_CAPABILITIES_OUT_LICENSE_CAPABILITIES_LEN 4
14100
14101/* MC_CMD_GET_CAPABILITIES_V2_IN msgrequest */
14102#define MC_CMD_GET_CAPABILITIES_V2_IN_LEN 0
14103
14104/* MC_CMD_GET_CAPABILITIES_V2_OUT msgresponse */
14105#define MC_CMD_GET_CAPABILITIES_V2_OUT_LEN 72
14106/* First word of flags. */
14107#define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS1_OFST 0
14108#define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS1_LEN 4
14109#define MC_CMD_GET_CAPABILITIES_V2_OUT_VPORT_RECONFIGURE_OFST 0
14110#define MC_CMD_GET_CAPABILITIES_V2_OUT_VPORT_RECONFIGURE_LBN 3
14111#define MC_CMD_GET_CAPABILITIES_V2_OUT_VPORT_RECONFIGURE_WIDTH 1
14112#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_STRIPING_OFST 0
14113#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_STRIPING_LBN 4
14114#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_STRIPING_WIDTH 1
14115#define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_QUERY_OFST 0
14116#define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_QUERY_LBN 5
14117#define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_QUERY_WIDTH 1
14118#define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
14119#define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6
14120#define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
14121#define MC_CMD_GET_CAPABILITIES_V2_OUT_DRV_ATTACH_PREBOOT_OFST 0
14122#define MC_CMD_GET_CAPABILITIES_V2_OUT_DRV_ATTACH_PREBOOT_LBN 7
14123#define MC_CMD_GET_CAPABILITIES_V2_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
14124#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_FORCE_EVENT_MERGING_OFST 0
14125#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_FORCE_EVENT_MERGING_LBN 8
14126#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
14127#define MC_CMD_GET_CAPABILITIES_V2_OUT_SET_MAC_ENHANCED_OFST 0
14128#define MC_CMD_GET_CAPABILITIES_V2_OUT_SET_MAC_ENHANCED_LBN 9
14129#define MC_CMD_GET_CAPABILITIES_V2_OUT_SET_MAC_ENHANCED_WIDTH 1
14130#define MC_CMD_GET_CAPABILITIES_V2_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
14131#define MC_CMD_GET_CAPABILITIES_V2_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10
14132#define MC_CMD_GET_CAPABILITIES_V2_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
14133#define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
14134#define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11
14135#define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
14136#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
14137#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_SECURITY_FILTERING_LBN 12
14138#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
14139#define MC_CMD_GET_CAPABILITIES_V2_OUT_ADDITIONAL_RSS_MODES_OFST 0
14140#define MC_CMD_GET_CAPABILITIES_V2_OUT_ADDITIONAL_RSS_MODES_LBN 13
14141#define MC_CMD_GET_CAPABILITIES_V2_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
14142#define MC_CMD_GET_CAPABILITIES_V2_OUT_QBB_OFST 0
14143#define MC_CMD_GET_CAPABILITIES_V2_OUT_QBB_LBN 14
14144#define MC_CMD_GET_CAPABILITIES_V2_OUT_QBB_WIDTH 1
14145#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
14146#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15
14147#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
14148#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_RSS_LIMITED_OFST 0
14149#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_RSS_LIMITED_LBN 16
14150#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_RSS_LIMITED_WIDTH 1
14151#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_OFST 0
14152#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_LBN 17
14153#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_WIDTH 1
14154#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_INCLUDE_FCS_OFST 0
14155#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_INCLUDE_FCS_LBN 18
14156#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_INCLUDE_FCS_WIDTH 1
14157#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VLAN_INSERTION_OFST 0
14158#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VLAN_INSERTION_LBN 19
14159#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VLAN_INSERTION_WIDTH 1
14160#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_VLAN_STRIPPING_OFST 0
14161#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_VLAN_STRIPPING_LBN 20
14162#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_VLAN_STRIPPING_WIDTH 1
14163#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_OFST 0
14164#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_LBN 21
14165#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_WIDTH 1
14166#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_0_OFST 0
14167#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_0_LBN 22
14168#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_0_WIDTH 1
14169#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_14_OFST 0
14170#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_14_LBN 23
14171#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_14_WIDTH 1
14172#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_TIMESTAMP_OFST 0
14173#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_TIMESTAMP_LBN 24
14174#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_TIMESTAMP_WIDTH 1
14175#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_BATCHING_OFST 0
14176#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_BATCHING_LBN 25
14177#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_BATCHING_WIDTH 1
14178#define MC_CMD_GET_CAPABILITIES_V2_OUT_MCAST_FILTER_CHAINING_OFST 0
14179#define MC_CMD_GET_CAPABILITIES_V2_OUT_MCAST_FILTER_CHAINING_LBN 26
14180#define MC_CMD_GET_CAPABILITIES_V2_OUT_MCAST_FILTER_CHAINING_WIDTH 1
14181#define MC_CMD_GET_CAPABILITIES_V2_OUT_PM_AND_RXDP_COUNTERS_OFST 0
14182#define MC_CMD_GET_CAPABILITIES_V2_OUT_PM_AND_RXDP_COUNTERS_LBN 27
14183#define MC_CMD_GET_CAPABILITIES_V2_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
14184#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DISABLE_SCATTER_OFST 0
14185#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DISABLE_SCATTER_LBN 28
14186#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DISABLE_SCATTER_WIDTH 1
14187#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
14188#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29
14189#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
14190#define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_OFST 0
14191#define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_LBN 30
14192#define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_WIDTH 1
14193#define MC_CMD_GET_CAPABILITIES_V2_OUT_VXLAN_NVGRE_OFST 0
14194#define MC_CMD_GET_CAPABILITIES_V2_OUT_VXLAN_NVGRE_LBN 31
14195#define MC_CMD_GET_CAPABILITIES_V2_OUT_VXLAN_NVGRE_WIDTH 1
14196/* RxDPCPU firmware id. */
14197#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DPCPU_FW_ID_OFST 4
14198#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DPCPU_FW_ID_LEN 2
14199/* enum: Standard RXDP firmware */
14200#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP 0x0
14201/* enum: Low latency RXDP firmware */
14202#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_LOW_LATENCY 0x1
14203/* enum: Packed stream RXDP firmware */
14204#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_PACKED_STREAM 0x2
14205/* enum: Rules engine RXDP firmware */
14206#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_RULES_ENGINE 0x5
14207/* enum: DPDK RXDP firmware */
14208#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_DPDK 0x6
14209/* enum: BIST RXDP firmware */
14210#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_BIST 0x10a
14211/* enum: RXDP Test firmware image 1 */
14212#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
14213/* enum: RXDP Test firmware image 2 */
14214#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
14215/* enum: RXDP Test firmware image 3 */
14216#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
14217/* enum: RXDP Test firmware image 4 */
14218#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
14219/* enum: RXDP Test firmware image 5 */
14220#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_BACKPRESSURE 0x105
14221/* enum: RXDP Test firmware image 6 */
14222#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
14223/* enum: RXDP Test firmware image 7 */
14224#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
14225/* enum: RXDP Test firmware image 8 */
14226#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
14227/* enum: RXDP Test firmware image 9 */
14228#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
14229/* enum: RXDP Test firmware image 10 */
14230#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_SLOW 0x10c
14231/* TxDPCPU firmware id. */
14232#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DPCPU_FW_ID_OFST 6
14233#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DPCPU_FW_ID_LEN 2
14234/* enum: Standard TXDP firmware */
14235#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP 0x0
14236/* enum: Low latency TXDP firmware */
14237#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_LOW_LATENCY 0x1
14238/* enum: High packet rate TXDP firmware */
14239#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_HIGH_PACKET_RATE 0x3
14240/* enum: Rules engine TXDP firmware */
14241#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_RULES_ENGINE 0x5
14242/* enum: DPDK TXDP firmware */
14243#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_DPDK 0x6
14244/* enum: BIST TXDP firmware */
14245#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_BIST 0x12d
14246/* enum: TXDP Test firmware image 1 */
14247#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
14248/* enum: TXDP Test firmware image 2 */
14249#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
14250/* enum: TXDP CSR bus test firmware */
14251#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_CSR 0x103
14252#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_OFST 8
14253#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_LEN 2
14254#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_REV_OFST 8
14255#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_REV_LBN 0
14256#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_REV_WIDTH 12
14257#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_TYPE_OFST 8
14258#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_TYPE_LBN 12
14259#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
14260/* enum: reserved value - do not use (may indicate alternative interpretation
14261 * of REV field in future)
14262 */
14263#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_RESERVED 0x0
14264/* enum: Trivial RX PD firmware for early Huntington development (Huntington
14265 * development only)
14266 */
14267#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
14268/* enum: RX PD firmware for telemetry prototyping (Medford2 development only)
14269 */
14270#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
14271/* enum: RX PD firmware with approximately Siena-compatible behaviour
14272 * (Huntington development only)
14273 */
14274#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
14275/* enum: Full featured RX PD production firmware */
14276#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
14277/* enum: (deprecated original name for the FULL_FEATURED variant) */
14278#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_VSWITCH 0x3
14279/* enum: siena_compat variant RX PD firmware using PM rather than MAC
14280 * (Huntington development only)
14281 */
14282#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
14283/* enum: Low latency RX PD production firmware */
14284#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
14285/* enum: Packed stream RX PD production firmware */
14286#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
14287/* enum: RX PD firmware handling layer 2 only for high packet rate performance
14288 * tests (Medford development only)
14289 */
14290#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
14291/* enum: Rules engine RX PD production firmware */
14292#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
14293/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
14294#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_L3XUDP 0x9
14295/* enum: DPDK RX PD production firmware */
14296#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_DPDK 0xa
14297/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
14298#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
14299/* enum: RX PD firmware parsing but not filtering network overlay tunnel
14300 * encapsulations (Medford development only)
14301 */
14302#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
14303#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_OFST 10
14304#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_LEN 2
14305#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_REV_OFST 10
14306#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_REV_LBN 0
14307#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_REV_WIDTH 12
14308#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_TYPE_OFST 10
14309#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_TYPE_LBN 12
14310#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
14311/* enum: reserved value - do not use (may indicate alternative interpretation
14312 * of REV field in future)
14313 */
14314#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_RESERVED 0x0
14315/* enum: Trivial TX PD firmware for early Huntington development (Huntington
14316 * development only)
14317 */
14318#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
14319/* enum: TX PD firmware for telemetry prototyping (Medford2 development only)
14320 */
14321#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
14322/* enum: TX PD firmware with approximately Siena-compatible behaviour
14323 * (Huntington development only)
14324 */
14325#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
14326/* enum: Full featured TX PD production firmware */
14327#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
14328/* enum: (deprecated original name for the FULL_FEATURED variant) */
14329#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_VSWITCH 0x3
14330/* enum: siena_compat variant TX PD firmware using PM rather than MAC
14331 * (Huntington development only)
14332 */
14333#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
14334#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
14335/* enum: TX PD firmware handling layer 2 only for high packet rate performance
14336 * tests (Medford development only)
14337 */
14338#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
14339/* enum: Rules engine TX PD production firmware */
14340#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
14341/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
14342#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_L3XUDP 0x9
14343/* enum: DPDK TX PD production firmware */
14344#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_DPDK 0xa
14345/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
14346#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
14347/* Hardware capabilities of NIC */
14348#define MC_CMD_GET_CAPABILITIES_V2_OUT_HW_CAPABILITIES_OFST 12
14349#define MC_CMD_GET_CAPABILITIES_V2_OUT_HW_CAPABILITIES_LEN 4
14350/* Licensed capabilities */
14351#define MC_CMD_GET_CAPABILITIES_V2_OUT_LICENSE_CAPABILITIES_OFST 16
14352#define MC_CMD_GET_CAPABILITIES_V2_OUT_LICENSE_CAPABILITIES_LEN 4
14353/* Second word of flags. Not present on older firmware (check the length). */
14354#define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS2_OFST 20
14355#define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS2_LEN 4
14356#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_OFST 20
14357#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN 0
14358#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_WIDTH 1
14359#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_ENCAP_OFST 20
14360#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_ENCAP_LBN 1
14361#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_ENCAP_WIDTH 1
14362#define MC_CMD_GET_CAPABILITIES_V2_OUT_EVQ_TIMER_CTRL_OFST 20
14363#define MC_CMD_GET_CAPABILITIES_V2_OUT_EVQ_TIMER_CTRL_LBN 2
14364#define MC_CMD_GET_CAPABILITIES_V2_OUT_EVQ_TIMER_CTRL_WIDTH 1
14365#define MC_CMD_GET_CAPABILITIES_V2_OUT_EVENT_CUT_THROUGH_OFST 20
14366#define MC_CMD_GET_CAPABILITIES_V2_OUT_EVENT_CUT_THROUGH_LBN 3
14367#define MC_CMD_GET_CAPABILITIES_V2_OUT_EVENT_CUT_THROUGH_WIDTH 1
14368#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_CUT_THROUGH_OFST 20
14369#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_CUT_THROUGH_LBN 4
14370#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_CUT_THROUGH_WIDTH 1
14371#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VFIFO_ULL_MODE_OFST 20
14372#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VFIFO_ULL_MODE_LBN 5
14373#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VFIFO_ULL_MODE_WIDTH 1
14374#define MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_OFST 20
14375#define MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6
14376#define MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1
14377#define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_TYPE_SUPPORTED_OFST 20
14378#define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_TYPE_SUPPORTED_LBN 7
14379#define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 1
14380#define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_OFST 20
14381#define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_LBN 7
14382#define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_WIDTH 1
14383#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_TIMESTAMPING_OFST 20
14384#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_TIMESTAMPING_LBN 8
14385#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_TIMESTAMPING_WIDTH 1
14386#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TIMESTAMP_OFST 20
14387#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TIMESTAMP_LBN 9
14388#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TIMESTAMP_WIDTH 1
14389#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_SNIFF_OFST 20
14390#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_SNIFF_LBN 10
14391#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_SNIFF_WIDTH 1
14392#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_SNIFF_OFST 20
14393#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_SNIFF_LBN 11
14394#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_SNIFF_WIDTH 1
14395#define MC_CMD_GET_CAPABILITIES_V2_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_OFST 20
14396#define MC_CMD_GET_CAPABILITIES_V2_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12
14397#define MC_CMD_GET_CAPABILITIES_V2_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1
14398#define MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_BACKGROUND_OFST 20
14399#define MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_BACKGROUND_LBN 13
14400#define MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_BACKGROUND_WIDTH 1
14401#define MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_DB_RETURN_OFST 20
14402#define MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_DB_RETURN_LBN 14
14403#define MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_DB_RETURN_WIDTH 1
14404#define MC_CMD_GET_CAPABILITIES_V2_OUT_CTPIO_OFST 20
14405#define MC_CMD_GET_CAPABILITIES_V2_OUT_CTPIO_LBN 15
14406#define MC_CMD_GET_CAPABILITIES_V2_OUT_CTPIO_WIDTH 1
14407#define MC_CMD_GET_CAPABILITIES_V2_OUT_TSA_SUPPORT_OFST 20
14408#define MC_CMD_GET_CAPABILITIES_V2_OUT_TSA_SUPPORT_LBN 16
14409#define MC_CMD_GET_CAPABILITIES_V2_OUT_TSA_SUPPORT_WIDTH 1
14410#define MC_CMD_GET_CAPABILITIES_V2_OUT_TSA_BOUND_OFST 20
14411#define MC_CMD_GET_CAPABILITIES_V2_OUT_TSA_BOUND_LBN 17
14412#define MC_CMD_GET_CAPABILITIES_V2_OUT_TSA_BOUND_WIDTH 1
14413#define MC_CMD_GET_CAPABILITIES_V2_OUT_SF_ADAPTER_AUTHENTICATION_OFST 20
14414#define MC_CMD_GET_CAPABILITIES_V2_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18
14415#define MC_CMD_GET_CAPABILITIES_V2_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1
14416#define MC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_FLAG_OFST 20
14417#define MC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_FLAG_LBN 19
14418#define MC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_FLAG_WIDTH 1
14419#define MC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_MARK_OFST 20
14420#define MC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_MARK_LBN 20
14421#define MC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_MARK_WIDTH 1
14422#define MC_CMD_GET_CAPABILITIES_V2_OUT_EQUAL_STRIDE_SUPER_BUFFER_OFST 20
14423#define MC_CMD_GET_CAPABILITIES_V2_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 21
14424#define MC_CMD_GET_CAPABILITIES_V2_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1
14425#define MC_CMD_GET_CAPABILITIES_V2_OUT_EQUAL_STRIDE_PACKED_STREAM_OFST 20
14426#define MC_CMD_GET_CAPABILITIES_V2_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21
14427#define MC_CMD_GET_CAPABILITIES_V2_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1
14428#define MC_CMD_GET_CAPABILITIES_V2_OUT_L3XUDP_SUPPORT_OFST 20
14429#define MC_CMD_GET_CAPABILITIES_V2_OUT_L3XUDP_SUPPORT_LBN 22
14430#define MC_CMD_GET_CAPABILITIES_V2_OUT_L3XUDP_SUPPORT_WIDTH 1
14431#define MC_CMD_GET_CAPABILITIES_V2_OUT_FW_SUBVARIANT_NO_TX_CSUM_OFST 20
14432#define MC_CMD_GET_CAPABILITIES_V2_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23
14433#define MC_CMD_GET_CAPABILITIES_V2_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1
14434#define MC_CMD_GET_CAPABILITIES_V2_OUT_VI_SPREADING_OFST 20
14435#define MC_CMD_GET_CAPABILITIES_V2_OUT_VI_SPREADING_LBN 24
14436#define MC_CMD_GET_CAPABILITIES_V2_OUT_VI_SPREADING_WIDTH 1
14437#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_HLB_IDLE_OFST 20
14438#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_HLB_IDLE_LBN 25
14439#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_HLB_IDLE_WIDTH 1
14440#define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_RXQ_NO_CONT_EV_OFST 20
14441#define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_RXQ_NO_CONT_EV_LBN 26
14442#define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1
14443#define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_RXQ_WITH_BUFFER_SIZE_OFST 20
14444#define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 27
14445#define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1
14446#define MC_CMD_GET_CAPABILITIES_V2_OUT_BUNDLE_UPDATE_OFST 20
14447#define MC_CMD_GET_CAPABILITIES_V2_OUT_BUNDLE_UPDATE_LBN 28
14448#define MC_CMD_GET_CAPABILITIES_V2_OUT_BUNDLE_UPDATE_WIDTH 1
14449#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V3_OFST 20
14450#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V3_LBN 29
14451#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V3_WIDTH 1
14452#define MC_CMD_GET_CAPABILITIES_V2_OUT_DYNAMIC_SENSORS_OFST 20
14453#define MC_CMD_GET_CAPABILITIES_V2_OUT_DYNAMIC_SENSORS_LBN 30
14454#define MC_CMD_GET_CAPABILITIES_V2_OUT_DYNAMIC_SENSORS_WIDTH 1
14455#define MC_CMD_GET_CAPABILITIES_V2_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_OFST 20
14456#define MC_CMD_GET_CAPABILITIES_V2_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 31
14457#define MC_CMD_GET_CAPABILITIES_V2_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1
14458/* Number of FATSOv2 contexts per datapath supported by this NIC (when
14459 * TX_TSO_V2 == 1). Not present on older firmware (check the length).
14460 */
14461#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24
14462#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2
14463/* One byte per PF containing the number of the external port assigned to this
14464 * PF, indexed by PF number. Special values indicate that a PF is either not
14465 * present or not assigned.
14466 */
14467#define MC_CMD_GET_CAPABILITIES_V2_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26
14468#define MC_CMD_GET_CAPABILITIES_V2_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1
14469#define MC_CMD_GET_CAPABILITIES_V2_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16
14470/* enum: The caller is not permitted to access information on this PF. */
14471#define MC_CMD_GET_CAPABILITIES_V2_OUT_ACCESS_NOT_PERMITTED 0xff
14472/* enum: PF does not exist. */
14473#define MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_PRESENT 0xfe
14474/* enum: PF does exist but is not assigned to any external port. */
14475#define MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_ASSIGNED 0xfd
14476/* enum: This value indicates that PF is assigned, but it cannot be expressed
14477 * in this field. It is intended for a possible future situation where a more
14478 * complex scheme of PFs to ports mapping is being used. The future driver
14479 * should look for a new field supporting the new scheme. The current/old
14480 * driver should treat this value as PF_NOT_ASSIGNED.
14481 */
14482#define MC_CMD_GET_CAPABILITIES_V2_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
14483/* One byte per PF containing the number of its VFs, indexed by PF number. A
14484 * special value indicates that a PF is not present.
14485 */
14486#define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VFS_PER_PF_OFST 42
14487#define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VFS_PER_PF_LEN 1
14488#define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VFS_PER_PF_NUM 16
14489/* enum: The caller is not permitted to access information on this PF. */
14490/* MC_CMD_GET_CAPABILITIES_V2_OUT_ACCESS_NOT_PERMITTED 0xff */
14491/* enum: PF does not exist. */
14492/* MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_PRESENT 0xfe */
14493/* Number of VIs available for each external port */
14494#define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_OFST 58
14495#define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_LEN 2
14496#define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_NUM 4
14497/* Size of RX descriptor cache expressed as binary logarithm The actual size
14498 * equals (2 ^ RX_DESC_CACHE_SIZE)
14499 */
14500#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DESC_CACHE_SIZE_OFST 66
14501#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DESC_CACHE_SIZE_LEN 1
14502/* Size of TX descriptor cache expressed as binary logarithm The actual size
14503 * equals (2 ^ TX_DESC_CACHE_SIZE)
14504 */
14505#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DESC_CACHE_SIZE_OFST 67
14506#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DESC_CACHE_SIZE_LEN 1
14507/* Total number of available PIO buffers */
14508#define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_PIO_BUFFS_OFST 68
14509#define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_PIO_BUFFS_LEN 2
14510/* Size of a single PIO buffer */
14511#define MC_CMD_GET_CAPABILITIES_V2_OUT_SIZE_PIO_BUFF_OFST 70
14512#define MC_CMD_GET_CAPABILITIES_V2_OUT_SIZE_PIO_BUFF_LEN 2
14513
14514/* MC_CMD_GET_CAPABILITIES_V3_OUT msgresponse */
14515#define MC_CMD_GET_CAPABILITIES_V3_OUT_LEN 76
14516/* First word of flags. */
14517#define MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS1_OFST 0
14518#define MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS1_LEN 4
14519#define MC_CMD_GET_CAPABILITIES_V3_OUT_VPORT_RECONFIGURE_OFST 0
14520#define MC_CMD_GET_CAPABILITIES_V3_OUT_VPORT_RECONFIGURE_LBN 3
14521#define MC_CMD_GET_CAPABILITIES_V3_OUT_VPORT_RECONFIGURE_WIDTH 1
14522#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_STRIPING_OFST 0
14523#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_STRIPING_LBN 4
14524#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_STRIPING_WIDTH 1
14525#define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_QUERY_OFST 0
14526#define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_QUERY_LBN 5
14527#define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_QUERY_WIDTH 1
14528#define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
14529#define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6
14530#define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
14531#define MC_CMD_GET_CAPABILITIES_V3_OUT_DRV_ATTACH_PREBOOT_OFST 0
14532#define MC_CMD_GET_CAPABILITIES_V3_OUT_DRV_ATTACH_PREBOOT_LBN 7
14533#define MC_CMD_GET_CAPABILITIES_V3_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
14534#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_FORCE_EVENT_MERGING_OFST 0
14535#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_FORCE_EVENT_MERGING_LBN 8
14536#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
14537#define MC_CMD_GET_CAPABILITIES_V3_OUT_SET_MAC_ENHANCED_OFST 0
14538#define MC_CMD_GET_CAPABILITIES_V3_OUT_SET_MAC_ENHANCED_LBN 9
14539#define MC_CMD_GET_CAPABILITIES_V3_OUT_SET_MAC_ENHANCED_WIDTH 1
14540#define MC_CMD_GET_CAPABILITIES_V3_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
14541#define MC_CMD_GET_CAPABILITIES_V3_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10
14542#define MC_CMD_GET_CAPABILITIES_V3_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
14543#define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
14544#define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11
14545#define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
14546#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
14547#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_SECURITY_FILTERING_LBN 12
14548#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
14549#define MC_CMD_GET_CAPABILITIES_V3_OUT_ADDITIONAL_RSS_MODES_OFST 0
14550#define MC_CMD_GET_CAPABILITIES_V3_OUT_ADDITIONAL_RSS_MODES_LBN 13
14551#define MC_CMD_GET_CAPABILITIES_V3_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
14552#define MC_CMD_GET_CAPABILITIES_V3_OUT_QBB_OFST 0
14553#define MC_CMD_GET_CAPABILITIES_V3_OUT_QBB_LBN 14
14554#define MC_CMD_GET_CAPABILITIES_V3_OUT_QBB_WIDTH 1
14555#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
14556#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15
14557#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
14558#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_RSS_LIMITED_OFST 0
14559#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_RSS_LIMITED_LBN 16
14560#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_RSS_LIMITED_WIDTH 1
14561#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_OFST 0
14562#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_LBN 17
14563#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_WIDTH 1
14564#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_INCLUDE_FCS_OFST 0
14565#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_INCLUDE_FCS_LBN 18
14566#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_INCLUDE_FCS_WIDTH 1
14567#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VLAN_INSERTION_OFST 0
14568#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VLAN_INSERTION_LBN 19
14569#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VLAN_INSERTION_WIDTH 1
14570#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_VLAN_STRIPPING_OFST 0
14571#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_VLAN_STRIPPING_LBN 20
14572#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_VLAN_STRIPPING_WIDTH 1
14573#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_OFST 0
14574#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_LBN 21
14575#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_WIDTH 1
14576#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_0_OFST 0
14577#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_0_LBN 22
14578#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_0_WIDTH 1
14579#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_14_OFST 0
14580#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_14_LBN 23
14581#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_14_WIDTH 1
14582#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_TIMESTAMP_OFST 0
14583#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_TIMESTAMP_LBN 24
14584#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_TIMESTAMP_WIDTH 1
14585#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_BATCHING_OFST 0
14586#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_BATCHING_LBN 25
14587#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_BATCHING_WIDTH 1
14588#define MC_CMD_GET_CAPABILITIES_V3_OUT_MCAST_FILTER_CHAINING_OFST 0
14589#define MC_CMD_GET_CAPABILITIES_V3_OUT_MCAST_FILTER_CHAINING_LBN 26
14590#define MC_CMD_GET_CAPABILITIES_V3_OUT_MCAST_FILTER_CHAINING_WIDTH 1
14591#define MC_CMD_GET_CAPABILITIES_V3_OUT_PM_AND_RXDP_COUNTERS_OFST 0
14592#define MC_CMD_GET_CAPABILITIES_V3_OUT_PM_AND_RXDP_COUNTERS_LBN 27
14593#define MC_CMD_GET_CAPABILITIES_V3_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
14594#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DISABLE_SCATTER_OFST 0
14595#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DISABLE_SCATTER_LBN 28
14596#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DISABLE_SCATTER_WIDTH 1
14597#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
14598#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29
14599#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
14600#define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_OFST 0
14601#define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_LBN 30
14602#define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_WIDTH 1
14603#define MC_CMD_GET_CAPABILITIES_V3_OUT_VXLAN_NVGRE_OFST 0
14604#define MC_CMD_GET_CAPABILITIES_V3_OUT_VXLAN_NVGRE_LBN 31
14605#define MC_CMD_GET_CAPABILITIES_V3_OUT_VXLAN_NVGRE_WIDTH 1
14606/* RxDPCPU firmware id. */
14607#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DPCPU_FW_ID_OFST 4
14608#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DPCPU_FW_ID_LEN 2
14609/* enum: Standard RXDP firmware */
14610#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP 0x0
14611/* enum: Low latency RXDP firmware */
14612#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_LOW_LATENCY 0x1
14613/* enum: Packed stream RXDP firmware */
14614#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_PACKED_STREAM 0x2
14615/* enum: Rules engine RXDP firmware */
14616#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_RULES_ENGINE 0x5
14617/* enum: DPDK RXDP firmware */
14618#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_DPDK 0x6
14619/* enum: BIST RXDP firmware */
14620#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_BIST 0x10a
14621/* enum: RXDP Test firmware image 1 */
14622#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
14623/* enum: RXDP Test firmware image 2 */
14624#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
14625/* enum: RXDP Test firmware image 3 */
14626#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
14627/* enum: RXDP Test firmware image 4 */
14628#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
14629/* enum: RXDP Test firmware image 5 */
14630#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_BACKPRESSURE 0x105
14631/* enum: RXDP Test firmware image 6 */
14632#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
14633/* enum: RXDP Test firmware image 7 */
14634#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
14635/* enum: RXDP Test firmware image 8 */
14636#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
14637/* enum: RXDP Test firmware image 9 */
14638#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
14639/* enum: RXDP Test firmware image 10 */
14640#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_SLOW 0x10c
14641/* TxDPCPU firmware id. */
14642#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_DPCPU_FW_ID_OFST 6
14643#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_DPCPU_FW_ID_LEN 2
14644/* enum: Standard TXDP firmware */
14645#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP 0x0
14646/* enum: Low latency TXDP firmware */
14647#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_LOW_LATENCY 0x1
14648/* enum: High packet rate TXDP firmware */
14649#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_HIGH_PACKET_RATE 0x3
14650/* enum: Rules engine TXDP firmware */
14651#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_RULES_ENGINE 0x5
14652/* enum: DPDK TXDP firmware */
14653#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_DPDK 0x6
14654/* enum: BIST TXDP firmware */
14655#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_BIST 0x12d
14656/* enum: TXDP Test firmware image 1 */
14657#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
14658/* enum: TXDP Test firmware image 2 */
14659#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
14660/* enum: TXDP CSR bus test firmware */
14661#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_CSR 0x103
14662#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_OFST 8
14663#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_LEN 2
14664#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_REV_OFST 8
14665#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_REV_LBN 0
14666#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_REV_WIDTH 12
14667#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_TYPE_OFST 8
14668#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_TYPE_LBN 12
14669#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
14670/* enum: reserved value - do not use (may indicate alternative interpretation
14671 * of REV field in future)
14672 */
14673#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_RESERVED 0x0
14674/* enum: Trivial RX PD firmware for early Huntington development (Huntington
14675 * development only)
14676 */
14677#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
14678/* enum: RX PD firmware for telemetry prototyping (Medford2 development only)
14679 */
14680#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
14681/* enum: RX PD firmware with approximately Siena-compatible behaviour
14682 * (Huntington development only)
14683 */
14684#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
14685/* enum: Full featured RX PD production firmware */
14686#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
14687/* enum: (deprecated original name for the FULL_FEATURED variant) */
14688#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_VSWITCH 0x3
14689/* enum: siena_compat variant RX PD firmware using PM rather than MAC
14690 * (Huntington development only)
14691 */
14692#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
14693/* enum: Low latency RX PD production firmware */
14694#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
14695/* enum: Packed stream RX PD production firmware */
14696#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
14697/* enum: RX PD firmware handling layer 2 only for high packet rate performance
14698 * tests (Medford development only)
14699 */
14700#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
14701/* enum: Rules engine RX PD production firmware */
14702#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
14703/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
14704#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_L3XUDP 0x9
14705/* enum: DPDK RX PD production firmware */
14706#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_DPDK 0xa
14707/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
14708#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
14709/* enum: RX PD firmware parsing but not filtering network overlay tunnel
14710 * encapsulations (Medford development only)
14711 */
14712#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
14713#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_OFST 10
14714#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_LEN 2
14715#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_REV_OFST 10
14716#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_REV_LBN 0
14717#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_REV_WIDTH 12
14718#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_TYPE_OFST 10
14719#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_TYPE_LBN 12
14720#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
14721/* enum: reserved value - do not use (may indicate alternative interpretation
14722 * of REV field in future)
14723 */
14724#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_RESERVED 0x0
14725/* enum: Trivial TX PD firmware for early Huntington development (Huntington
14726 * development only)
14727 */
14728#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
14729/* enum: TX PD firmware for telemetry prototyping (Medford2 development only)
14730 */
14731#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
14732/* enum: TX PD firmware with approximately Siena-compatible behaviour
14733 * (Huntington development only)
14734 */
14735#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
14736/* enum: Full featured TX PD production firmware */
14737#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
14738/* enum: (deprecated original name for the FULL_FEATURED variant) */
14739#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_VSWITCH 0x3
14740/* enum: siena_compat variant TX PD firmware using PM rather than MAC
14741 * (Huntington development only)
14742 */
14743#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
14744#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
14745/* enum: TX PD firmware handling layer 2 only for high packet rate performance
14746 * tests (Medford development only)
14747 */
14748#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
14749/* enum: Rules engine TX PD production firmware */
14750#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
14751/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
14752#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_L3XUDP 0x9
14753/* enum: DPDK TX PD production firmware */
14754#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_DPDK 0xa
14755/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
14756#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
14757/* Hardware capabilities of NIC */
14758#define MC_CMD_GET_CAPABILITIES_V3_OUT_HW_CAPABILITIES_OFST 12
14759#define MC_CMD_GET_CAPABILITIES_V3_OUT_HW_CAPABILITIES_LEN 4
14760/* Licensed capabilities */
14761#define MC_CMD_GET_CAPABILITIES_V3_OUT_LICENSE_CAPABILITIES_OFST 16
14762#define MC_CMD_GET_CAPABILITIES_V3_OUT_LICENSE_CAPABILITIES_LEN 4
14763/* Second word of flags. Not present on older firmware (check the length). */
14764#define MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS2_OFST 20
14765#define MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS2_LEN 4
14766#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_OFST 20
14767#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_LBN 0
14768#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_WIDTH 1
14769#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_ENCAP_OFST 20
14770#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_ENCAP_LBN 1
14771#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_ENCAP_WIDTH 1
14772#define MC_CMD_GET_CAPABILITIES_V3_OUT_EVQ_TIMER_CTRL_OFST 20
14773#define MC_CMD_GET_CAPABILITIES_V3_OUT_EVQ_TIMER_CTRL_LBN 2
14774#define MC_CMD_GET_CAPABILITIES_V3_OUT_EVQ_TIMER_CTRL_WIDTH 1
14775#define MC_CMD_GET_CAPABILITIES_V3_OUT_EVENT_CUT_THROUGH_OFST 20
14776#define MC_CMD_GET_CAPABILITIES_V3_OUT_EVENT_CUT_THROUGH_LBN 3
14777#define MC_CMD_GET_CAPABILITIES_V3_OUT_EVENT_CUT_THROUGH_WIDTH 1
14778#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_CUT_THROUGH_OFST 20
14779#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_CUT_THROUGH_LBN 4
14780#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_CUT_THROUGH_WIDTH 1
14781#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VFIFO_ULL_MODE_OFST 20
14782#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VFIFO_ULL_MODE_LBN 5
14783#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VFIFO_ULL_MODE_WIDTH 1
14784#define MC_CMD_GET_CAPABILITIES_V3_OUT_MAC_STATS_40G_TX_SIZE_BINS_OFST 20
14785#define MC_CMD_GET_CAPABILITIES_V3_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6
14786#define MC_CMD_GET_CAPABILITIES_V3_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1
14787#define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_EVQ_TYPE_SUPPORTED_OFST 20
14788#define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_EVQ_TYPE_SUPPORTED_LBN 7
14789#define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 1
14790#define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_EVQ_V2_OFST 20
14791#define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_EVQ_V2_LBN 7
14792#define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_EVQ_V2_WIDTH 1
14793#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_TIMESTAMPING_OFST 20
14794#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_TIMESTAMPING_LBN 8
14795#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_TIMESTAMPING_WIDTH 1
14796#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TIMESTAMP_OFST 20
14797#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TIMESTAMP_LBN 9
14798#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TIMESTAMP_WIDTH 1
14799#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_SNIFF_OFST 20
14800#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_SNIFF_LBN 10
14801#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_SNIFF_WIDTH 1
14802#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_SNIFF_OFST 20
14803#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_SNIFF_LBN 11
14804#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_SNIFF_WIDTH 1
14805#define MC_CMD_GET_CAPABILITIES_V3_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_OFST 20
14806#define MC_CMD_GET_CAPABILITIES_V3_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12
14807#define MC_CMD_GET_CAPABILITIES_V3_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1
14808#define MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_BACKGROUND_OFST 20
14809#define MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_BACKGROUND_LBN 13
14810#define MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_BACKGROUND_WIDTH 1
14811#define MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_DB_RETURN_OFST 20
14812#define MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_DB_RETURN_LBN 14
14813#define MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_DB_RETURN_WIDTH 1
14814#define MC_CMD_GET_CAPABILITIES_V3_OUT_CTPIO_OFST 20
14815#define MC_CMD_GET_CAPABILITIES_V3_OUT_CTPIO_LBN 15
14816#define MC_CMD_GET_CAPABILITIES_V3_OUT_CTPIO_WIDTH 1
14817#define MC_CMD_GET_CAPABILITIES_V3_OUT_TSA_SUPPORT_OFST 20
14818#define MC_CMD_GET_CAPABILITIES_V3_OUT_TSA_SUPPORT_LBN 16
14819#define MC_CMD_GET_CAPABILITIES_V3_OUT_TSA_SUPPORT_WIDTH 1
14820#define MC_CMD_GET_CAPABILITIES_V3_OUT_TSA_BOUND_OFST 20
14821#define MC_CMD_GET_CAPABILITIES_V3_OUT_TSA_BOUND_LBN 17
14822#define MC_CMD_GET_CAPABILITIES_V3_OUT_TSA_BOUND_WIDTH 1
14823#define MC_CMD_GET_CAPABILITIES_V3_OUT_SF_ADAPTER_AUTHENTICATION_OFST 20
14824#define MC_CMD_GET_CAPABILITIES_V3_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18
14825#define MC_CMD_GET_CAPABILITIES_V3_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1
14826#define MC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_FLAG_OFST 20
14827#define MC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_FLAG_LBN 19
14828#define MC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_FLAG_WIDTH 1
14829#define MC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_MARK_OFST 20
14830#define MC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_MARK_LBN 20
14831#define MC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_MARK_WIDTH 1
14832#define MC_CMD_GET_CAPABILITIES_V3_OUT_EQUAL_STRIDE_SUPER_BUFFER_OFST 20
14833#define MC_CMD_GET_CAPABILITIES_V3_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 21
14834#define MC_CMD_GET_CAPABILITIES_V3_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1
14835#define MC_CMD_GET_CAPABILITIES_V3_OUT_EQUAL_STRIDE_PACKED_STREAM_OFST 20
14836#define MC_CMD_GET_CAPABILITIES_V3_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21
14837#define MC_CMD_GET_CAPABILITIES_V3_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1
14838#define MC_CMD_GET_CAPABILITIES_V3_OUT_L3XUDP_SUPPORT_OFST 20
14839#define MC_CMD_GET_CAPABILITIES_V3_OUT_L3XUDP_SUPPORT_LBN 22
14840#define MC_CMD_GET_CAPABILITIES_V3_OUT_L3XUDP_SUPPORT_WIDTH 1
14841#define MC_CMD_GET_CAPABILITIES_V3_OUT_FW_SUBVARIANT_NO_TX_CSUM_OFST 20
14842#define MC_CMD_GET_CAPABILITIES_V3_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23
14843#define MC_CMD_GET_CAPABILITIES_V3_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1
14844#define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_SPREADING_OFST 20
14845#define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_SPREADING_LBN 24
14846#define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_SPREADING_WIDTH 1
14847#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_HLB_IDLE_OFST 20
14848#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_HLB_IDLE_LBN 25
14849#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_HLB_IDLE_WIDTH 1
14850#define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_RXQ_NO_CONT_EV_OFST 20
14851#define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_RXQ_NO_CONT_EV_LBN 26
14852#define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1
14853#define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_RXQ_WITH_BUFFER_SIZE_OFST 20
14854#define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 27
14855#define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1
14856#define MC_CMD_GET_CAPABILITIES_V3_OUT_BUNDLE_UPDATE_OFST 20
14857#define MC_CMD_GET_CAPABILITIES_V3_OUT_BUNDLE_UPDATE_LBN 28
14858#define MC_CMD_GET_CAPABILITIES_V3_OUT_BUNDLE_UPDATE_WIDTH 1
14859#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V3_OFST 20
14860#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V3_LBN 29
14861#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V3_WIDTH 1
14862#define MC_CMD_GET_CAPABILITIES_V3_OUT_DYNAMIC_SENSORS_OFST 20
14863#define MC_CMD_GET_CAPABILITIES_V3_OUT_DYNAMIC_SENSORS_LBN 30
14864#define MC_CMD_GET_CAPABILITIES_V3_OUT_DYNAMIC_SENSORS_WIDTH 1
14865#define MC_CMD_GET_CAPABILITIES_V3_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_OFST 20
14866#define MC_CMD_GET_CAPABILITIES_V3_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 31
14867#define MC_CMD_GET_CAPABILITIES_V3_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1
14868/* Number of FATSOv2 contexts per datapath supported by this NIC (when
14869 * TX_TSO_V2 == 1). Not present on older firmware (check the length).
14870 */
14871#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24
14872#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2
14873/* One byte per PF containing the number of the external port assigned to this
14874 * PF, indexed by PF number. Special values indicate that a PF is either not
14875 * present or not assigned.
14876 */
14877#define MC_CMD_GET_CAPABILITIES_V3_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26
14878#define MC_CMD_GET_CAPABILITIES_V3_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1
14879#define MC_CMD_GET_CAPABILITIES_V3_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16
14880/* enum: The caller is not permitted to access information on this PF. */
14881#define MC_CMD_GET_CAPABILITIES_V3_OUT_ACCESS_NOT_PERMITTED 0xff
14882/* enum: PF does not exist. */
14883#define MC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_PRESENT 0xfe
14884/* enum: PF does exist but is not assigned to any external port. */
14885#define MC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_ASSIGNED 0xfd
14886/* enum: This value indicates that PF is assigned, but it cannot be expressed
14887 * in this field. It is intended for a possible future situation where a more
14888 * complex scheme of PFs to ports mapping is being used. The future driver
14889 * should look for a new field supporting the new scheme. The current/old
14890 * driver should treat this value as PF_NOT_ASSIGNED.
14891 */
14892#define MC_CMD_GET_CAPABILITIES_V3_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
14893/* One byte per PF containing the number of its VFs, indexed by PF number. A
14894 * special value indicates that a PF is not present.
14895 */
14896#define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VFS_PER_PF_OFST 42
14897#define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VFS_PER_PF_LEN 1
14898#define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VFS_PER_PF_NUM 16
14899/* enum: The caller is not permitted to access information on this PF. */
14900/* MC_CMD_GET_CAPABILITIES_V3_OUT_ACCESS_NOT_PERMITTED 0xff */
14901/* enum: PF does not exist. */
14902/* MC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_PRESENT 0xfe */
14903/* Number of VIs available for each external port */
14904#define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VIS_PER_PORT_OFST 58
14905#define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VIS_PER_PORT_LEN 2
14906#define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VIS_PER_PORT_NUM 4
14907/* Size of RX descriptor cache expressed as binary logarithm The actual size
14908 * equals (2 ^ RX_DESC_CACHE_SIZE)
14909 */
14910#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DESC_CACHE_SIZE_OFST 66
14911#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DESC_CACHE_SIZE_LEN 1
14912/* Size of TX descriptor cache expressed as binary logarithm The actual size
14913 * equals (2 ^ TX_DESC_CACHE_SIZE)
14914 */
14915#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_DESC_CACHE_SIZE_OFST 67
14916#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_DESC_CACHE_SIZE_LEN 1
14917/* Total number of available PIO buffers */
14918#define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_PIO_BUFFS_OFST 68
14919#define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_PIO_BUFFS_LEN 2
14920/* Size of a single PIO buffer */
14921#define MC_CMD_GET_CAPABILITIES_V3_OUT_SIZE_PIO_BUFF_OFST 70
14922#define MC_CMD_GET_CAPABILITIES_V3_OUT_SIZE_PIO_BUFF_LEN 2
14923/* On chips later than Medford the amount of address space assigned to each VI
14924 * is configurable. This is a global setting that the driver must query to
14925 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
14926 * with 8k VI windows.
14927 */
14928#define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_OFST 72
14929#define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_LEN 1
14930/* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
14931 * CTPIO is not mapped.
14932 */
14933#define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_8K 0x0
14934/* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
14935#define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_16K 0x1
14936/* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
14937#define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_64K 0x2
14938/* Number of vFIFOs per adapter that can be used for VFIFO Stuffing
14939 * (SF-115995-SW) in the present configuration of firmware and port mode.
14940 */
14941#define MC_CMD_GET_CAPABILITIES_V3_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 73
14942#define MC_CMD_GET_CAPABILITIES_V3_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1
14943/* Number of buffers per adapter that can be used for VFIFO Stuffing
14944 * (SF-115995-SW) in the present configuration of firmware and port mode.
14945 */
14946#define MC_CMD_GET_CAPABILITIES_V3_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 74
14947#define MC_CMD_GET_CAPABILITIES_V3_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 2
14948
14949/* MC_CMD_GET_CAPABILITIES_V4_OUT msgresponse */
14950#define MC_CMD_GET_CAPABILITIES_V4_OUT_LEN 78
14951/* First word of flags. */
14952#define MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS1_OFST 0
14953#define MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS1_LEN 4
14954#define MC_CMD_GET_CAPABILITIES_V4_OUT_VPORT_RECONFIGURE_OFST 0
14955#define MC_CMD_GET_CAPABILITIES_V4_OUT_VPORT_RECONFIGURE_LBN 3
14956#define MC_CMD_GET_CAPABILITIES_V4_OUT_VPORT_RECONFIGURE_WIDTH 1
14957#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_STRIPING_OFST 0
14958#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_STRIPING_LBN 4
14959#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_STRIPING_WIDTH 1
14960#define MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_QUERY_OFST 0
14961#define MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_QUERY_LBN 5
14962#define MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_QUERY_WIDTH 1
14963#define MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
14964#define MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6
14965#define MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
14966#define MC_CMD_GET_CAPABILITIES_V4_OUT_DRV_ATTACH_PREBOOT_OFST 0
14967#define MC_CMD_GET_CAPABILITIES_V4_OUT_DRV_ATTACH_PREBOOT_LBN 7
14968#define MC_CMD_GET_CAPABILITIES_V4_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
14969#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_FORCE_EVENT_MERGING_OFST 0
14970#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_FORCE_EVENT_MERGING_LBN 8
14971#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
14972#define MC_CMD_GET_CAPABILITIES_V4_OUT_SET_MAC_ENHANCED_OFST 0
14973#define MC_CMD_GET_CAPABILITIES_V4_OUT_SET_MAC_ENHANCED_LBN 9
14974#define MC_CMD_GET_CAPABILITIES_V4_OUT_SET_MAC_ENHANCED_WIDTH 1
14975#define MC_CMD_GET_CAPABILITIES_V4_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
14976#define MC_CMD_GET_CAPABILITIES_V4_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10
14977#define MC_CMD_GET_CAPABILITIES_V4_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
14978#define MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
14979#define MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11
14980#define MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
14981#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
14982#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_SECURITY_FILTERING_LBN 12
14983#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
14984#define MC_CMD_GET_CAPABILITIES_V4_OUT_ADDITIONAL_RSS_MODES_OFST 0
14985#define MC_CMD_GET_CAPABILITIES_V4_OUT_ADDITIONAL_RSS_MODES_LBN 13
14986#define MC_CMD_GET_CAPABILITIES_V4_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
14987#define MC_CMD_GET_CAPABILITIES_V4_OUT_QBB_OFST 0
14988#define MC_CMD_GET_CAPABILITIES_V4_OUT_QBB_LBN 14
14989#define MC_CMD_GET_CAPABILITIES_V4_OUT_QBB_WIDTH 1
14990#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
14991#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15
14992#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
14993#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_RSS_LIMITED_OFST 0
14994#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_RSS_LIMITED_LBN 16
14995#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_RSS_LIMITED_WIDTH 1
14996#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_OFST 0
14997#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_LBN 17
14998#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_WIDTH 1
14999#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_INCLUDE_FCS_OFST 0
15000#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_INCLUDE_FCS_LBN 18
15001#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_INCLUDE_FCS_WIDTH 1
15002#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VLAN_INSERTION_OFST 0
15003#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VLAN_INSERTION_LBN 19
15004#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VLAN_INSERTION_WIDTH 1
15005#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_VLAN_STRIPPING_OFST 0
15006#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_VLAN_STRIPPING_LBN 20
15007#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_VLAN_STRIPPING_WIDTH 1
15008#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_OFST 0
15009#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_LBN 21
15010#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_WIDTH 1
15011#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_0_OFST 0
15012#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_0_LBN 22
15013#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_0_WIDTH 1
15014#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_14_OFST 0
15015#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_14_LBN 23
15016#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_14_WIDTH 1
15017#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_TIMESTAMP_OFST 0
15018#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_TIMESTAMP_LBN 24
15019#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_TIMESTAMP_WIDTH 1
15020#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_BATCHING_OFST 0
15021#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_BATCHING_LBN 25
15022#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_BATCHING_WIDTH 1
15023#define MC_CMD_GET_CAPABILITIES_V4_OUT_MCAST_FILTER_CHAINING_OFST 0
15024#define MC_CMD_GET_CAPABILITIES_V4_OUT_MCAST_FILTER_CHAINING_LBN 26
15025#define MC_CMD_GET_CAPABILITIES_V4_OUT_MCAST_FILTER_CHAINING_WIDTH 1
15026#define MC_CMD_GET_CAPABILITIES_V4_OUT_PM_AND_RXDP_COUNTERS_OFST 0
15027#define MC_CMD_GET_CAPABILITIES_V4_OUT_PM_AND_RXDP_COUNTERS_LBN 27
15028#define MC_CMD_GET_CAPABILITIES_V4_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
15029#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DISABLE_SCATTER_OFST 0
15030#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DISABLE_SCATTER_LBN 28
15031#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DISABLE_SCATTER_WIDTH 1
15032#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
15033#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29
15034#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
15035#define MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_OFST 0
15036#define MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_LBN 30
15037#define MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_WIDTH 1
15038#define MC_CMD_GET_CAPABILITIES_V4_OUT_VXLAN_NVGRE_OFST 0
15039#define MC_CMD_GET_CAPABILITIES_V4_OUT_VXLAN_NVGRE_LBN 31
15040#define MC_CMD_GET_CAPABILITIES_V4_OUT_VXLAN_NVGRE_WIDTH 1
15041/* RxDPCPU firmware id. */
15042#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DPCPU_FW_ID_OFST 4
15043#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DPCPU_FW_ID_LEN 2
15044/* enum: Standard RXDP firmware */
15045#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP 0x0
15046/* enum: Low latency RXDP firmware */
15047#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_LOW_LATENCY 0x1
15048/* enum: Packed stream RXDP firmware */
15049#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_PACKED_STREAM 0x2
15050/* enum: Rules engine RXDP firmware */
15051#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_RULES_ENGINE 0x5
15052/* enum: DPDK RXDP firmware */
15053#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_DPDK 0x6
15054/* enum: BIST RXDP firmware */
15055#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_BIST 0x10a
15056/* enum: RXDP Test firmware image 1 */
15057#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
15058/* enum: RXDP Test firmware image 2 */
15059#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
15060/* enum: RXDP Test firmware image 3 */
15061#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
15062/* enum: RXDP Test firmware image 4 */
15063#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
15064/* enum: RXDP Test firmware image 5 */
15065#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_BACKPRESSURE 0x105
15066/* enum: RXDP Test firmware image 6 */
15067#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
15068/* enum: RXDP Test firmware image 7 */
15069#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
15070/* enum: RXDP Test firmware image 8 */
15071#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
15072/* enum: RXDP Test firmware image 9 */
15073#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
15074/* enum: RXDP Test firmware image 10 */
15075#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_SLOW 0x10c
15076/* TxDPCPU firmware id. */
15077#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_DPCPU_FW_ID_OFST 6
15078#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_DPCPU_FW_ID_LEN 2
15079/* enum: Standard TXDP firmware */
15080#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP 0x0
15081/* enum: Low latency TXDP firmware */
15082#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_LOW_LATENCY 0x1
15083/* enum: High packet rate TXDP firmware */
15084#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_HIGH_PACKET_RATE 0x3
15085/* enum: Rules engine TXDP firmware */
15086#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_RULES_ENGINE 0x5
15087/* enum: DPDK TXDP firmware */
15088#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_DPDK 0x6
15089/* enum: BIST TXDP firmware */
15090#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_BIST 0x12d
15091/* enum: TXDP Test firmware image 1 */
15092#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
15093/* enum: TXDP Test firmware image 2 */
15094#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
15095/* enum: TXDP CSR bus test firmware */
15096#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_TEST_FW_CSR 0x103
15097#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_OFST 8
15098#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_LEN 2
15099#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_REV_OFST 8
15100#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_REV_LBN 0
15101#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_REV_WIDTH 12
15102#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_TYPE_OFST 8
15103#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_TYPE_LBN 12
15104#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
15105/* enum: reserved value - do not use (may indicate alternative interpretation
15106 * of REV field in future)
15107 */
15108#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_RESERVED 0x0
15109/* enum: Trivial RX PD firmware for early Huntington development (Huntington
15110 * development only)
15111 */
15112#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
15113/* enum: RX PD firmware for telemetry prototyping (Medford2 development only)
15114 */
15115#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
15116/* enum: RX PD firmware with approximately Siena-compatible behaviour
15117 * (Huntington development only)
15118 */
15119#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
15120/* enum: Full featured RX PD production firmware */
15121#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
15122/* enum: (deprecated original name for the FULL_FEATURED variant) */
15123#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_VSWITCH 0x3
15124/* enum: siena_compat variant RX PD firmware using PM rather than MAC
15125 * (Huntington development only)
15126 */
15127#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
15128/* enum: Low latency RX PD production firmware */
15129#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
15130/* enum: Packed stream RX PD production firmware */
15131#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
15132/* enum: RX PD firmware handling layer 2 only for high packet rate performance
15133 * tests (Medford development only)
15134 */
15135#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
15136/* enum: Rules engine RX PD production firmware */
15137#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
15138/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
15139#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_L3XUDP 0x9
15140/* enum: DPDK RX PD production firmware */
15141#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_DPDK 0xa
15142/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
15143#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
15144/* enum: RX PD firmware parsing but not filtering network overlay tunnel
15145 * encapsulations (Medford development only)
15146 */
15147#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
15148#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_OFST 10
15149#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_LEN 2
15150#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_REV_OFST 10
15151#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_REV_LBN 0
15152#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_REV_WIDTH 12
15153#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_TYPE_OFST 10
15154#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_TYPE_LBN 12
15155#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
15156/* enum: reserved value - do not use (may indicate alternative interpretation
15157 * of REV field in future)
15158 */
15159#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_RESERVED 0x0
15160/* enum: Trivial TX PD firmware for early Huntington development (Huntington
15161 * development only)
15162 */
15163#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
15164/* enum: TX PD firmware for telemetry prototyping (Medford2 development only)
15165 */
15166#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
15167/* enum: TX PD firmware with approximately Siena-compatible behaviour
15168 * (Huntington development only)
15169 */
15170#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
15171/* enum: Full featured TX PD production firmware */
15172#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
15173/* enum: (deprecated original name for the FULL_FEATURED variant) */
15174#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_VSWITCH 0x3
15175/* enum: siena_compat variant TX PD firmware using PM rather than MAC
15176 * (Huntington development only)
15177 */
15178#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
15179#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
15180/* enum: TX PD firmware handling layer 2 only for high packet rate performance
15181 * tests (Medford development only)
15182 */
15183#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
15184/* enum: Rules engine TX PD production firmware */
15185#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
15186/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
15187#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_L3XUDP 0x9
15188/* enum: DPDK TX PD production firmware */
15189#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_DPDK 0xa
15190/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
15191#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
15192/* Hardware capabilities of NIC */
15193#define MC_CMD_GET_CAPABILITIES_V4_OUT_HW_CAPABILITIES_OFST 12
15194#define MC_CMD_GET_CAPABILITIES_V4_OUT_HW_CAPABILITIES_LEN 4
15195/* Licensed capabilities */
15196#define MC_CMD_GET_CAPABILITIES_V4_OUT_LICENSE_CAPABILITIES_OFST 16
15197#define MC_CMD_GET_CAPABILITIES_V4_OUT_LICENSE_CAPABILITIES_LEN 4
15198/* Second word of flags. Not present on older firmware (check the length). */
15199#define MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS2_OFST 20
15200#define MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS2_LEN 4
15201#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_OFST 20
15202#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_LBN 0
15203#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_WIDTH 1
15204#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_ENCAP_OFST 20
15205#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_ENCAP_LBN 1
15206#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_ENCAP_WIDTH 1
15207#define MC_CMD_GET_CAPABILITIES_V4_OUT_EVQ_TIMER_CTRL_OFST 20
15208#define MC_CMD_GET_CAPABILITIES_V4_OUT_EVQ_TIMER_CTRL_LBN 2
15209#define MC_CMD_GET_CAPABILITIES_V4_OUT_EVQ_TIMER_CTRL_WIDTH 1
15210#define MC_CMD_GET_CAPABILITIES_V4_OUT_EVENT_CUT_THROUGH_OFST 20
15211#define MC_CMD_GET_CAPABILITIES_V4_OUT_EVENT_CUT_THROUGH_LBN 3
15212#define MC_CMD_GET_CAPABILITIES_V4_OUT_EVENT_CUT_THROUGH_WIDTH 1
15213#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_CUT_THROUGH_OFST 20
15214#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_CUT_THROUGH_LBN 4
15215#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_CUT_THROUGH_WIDTH 1
15216#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VFIFO_ULL_MODE_OFST 20
15217#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VFIFO_ULL_MODE_LBN 5
15218#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VFIFO_ULL_MODE_WIDTH 1
15219#define MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_40G_TX_SIZE_BINS_OFST 20
15220#define MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6
15221#define MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1
15222#define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_EVQ_TYPE_SUPPORTED_OFST 20
15223#define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_EVQ_TYPE_SUPPORTED_LBN 7
15224#define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 1
15225#define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_EVQ_V2_OFST 20
15226#define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_EVQ_V2_LBN 7
15227#define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_EVQ_V2_WIDTH 1
15228#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_TIMESTAMPING_OFST 20
15229#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_TIMESTAMPING_LBN 8
15230#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_TIMESTAMPING_WIDTH 1
15231#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TIMESTAMP_OFST 20
15232#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TIMESTAMP_LBN 9
15233#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TIMESTAMP_WIDTH 1
15234#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_SNIFF_OFST 20
15235#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_SNIFF_LBN 10
15236#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_SNIFF_WIDTH 1
15237#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_SNIFF_OFST 20
15238#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_SNIFF_LBN 11
15239#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_SNIFF_WIDTH 1
15240#define MC_CMD_GET_CAPABILITIES_V4_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_OFST 20
15241#define MC_CMD_GET_CAPABILITIES_V4_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12
15242#define MC_CMD_GET_CAPABILITIES_V4_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1
15243#define MC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_BACKGROUND_OFST 20
15244#define MC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_BACKGROUND_LBN 13
15245#define MC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_BACKGROUND_WIDTH 1
15246#define MC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_DB_RETURN_OFST 20
15247#define MC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_DB_RETURN_LBN 14
15248#define MC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_DB_RETURN_WIDTH 1
15249#define MC_CMD_GET_CAPABILITIES_V4_OUT_CTPIO_OFST 20
15250#define MC_CMD_GET_CAPABILITIES_V4_OUT_CTPIO_LBN 15
15251#define MC_CMD_GET_CAPABILITIES_V4_OUT_CTPIO_WIDTH 1
15252#define MC_CMD_GET_CAPABILITIES_V4_OUT_TSA_SUPPORT_OFST 20
15253#define MC_CMD_GET_CAPABILITIES_V4_OUT_TSA_SUPPORT_LBN 16
15254#define MC_CMD_GET_CAPABILITIES_V4_OUT_TSA_SUPPORT_WIDTH 1
15255#define MC_CMD_GET_CAPABILITIES_V4_OUT_TSA_BOUND_OFST 20
15256#define MC_CMD_GET_CAPABILITIES_V4_OUT_TSA_BOUND_LBN 17
15257#define MC_CMD_GET_CAPABILITIES_V4_OUT_TSA_BOUND_WIDTH 1
15258#define MC_CMD_GET_CAPABILITIES_V4_OUT_SF_ADAPTER_AUTHENTICATION_OFST 20
15259#define MC_CMD_GET_CAPABILITIES_V4_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18
15260#define MC_CMD_GET_CAPABILITIES_V4_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1
15261#define MC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_FLAG_OFST 20
15262#define MC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_FLAG_LBN 19
15263#define MC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_FLAG_WIDTH 1
15264#define MC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_MARK_OFST 20
15265#define MC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_MARK_LBN 20
15266#define MC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_MARK_WIDTH 1
15267#define MC_CMD_GET_CAPABILITIES_V4_OUT_EQUAL_STRIDE_SUPER_BUFFER_OFST 20
15268#define MC_CMD_GET_CAPABILITIES_V4_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 21
15269#define MC_CMD_GET_CAPABILITIES_V4_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1
15270#define MC_CMD_GET_CAPABILITIES_V4_OUT_EQUAL_STRIDE_PACKED_STREAM_OFST 20
15271#define MC_CMD_GET_CAPABILITIES_V4_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21
15272#define MC_CMD_GET_CAPABILITIES_V4_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1
15273#define MC_CMD_GET_CAPABILITIES_V4_OUT_L3XUDP_SUPPORT_OFST 20
15274#define MC_CMD_GET_CAPABILITIES_V4_OUT_L3XUDP_SUPPORT_LBN 22
15275#define MC_CMD_GET_CAPABILITIES_V4_OUT_L3XUDP_SUPPORT_WIDTH 1
15276#define MC_CMD_GET_CAPABILITIES_V4_OUT_FW_SUBVARIANT_NO_TX_CSUM_OFST 20
15277#define MC_CMD_GET_CAPABILITIES_V4_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23
15278#define MC_CMD_GET_CAPABILITIES_V4_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1
15279#define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_SPREADING_OFST 20
15280#define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_SPREADING_LBN 24
15281#define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_SPREADING_WIDTH 1
15282#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_HLB_IDLE_OFST 20
15283#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_HLB_IDLE_LBN 25
15284#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_HLB_IDLE_WIDTH 1
15285#define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_RXQ_NO_CONT_EV_OFST 20
15286#define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_RXQ_NO_CONT_EV_LBN 26
15287#define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1
15288#define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_RXQ_WITH_BUFFER_SIZE_OFST 20
15289#define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 27
15290#define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1
15291#define MC_CMD_GET_CAPABILITIES_V4_OUT_BUNDLE_UPDATE_OFST 20
15292#define MC_CMD_GET_CAPABILITIES_V4_OUT_BUNDLE_UPDATE_LBN 28
15293#define MC_CMD_GET_CAPABILITIES_V4_OUT_BUNDLE_UPDATE_WIDTH 1
15294#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V3_OFST 20
15295#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V3_LBN 29
15296#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V3_WIDTH 1
15297#define MC_CMD_GET_CAPABILITIES_V4_OUT_DYNAMIC_SENSORS_OFST 20
15298#define MC_CMD_GET_CAPABILITIES_V4_OUT_DYNAMIC_SENSORS_LBN 30
15299#define MC_CMD_GET_CAPABILITIES_V4_OUT_DYNAMIC_SENSORS_WIDTH 1
15300#define MC_CMD_GET_CAPABILITIES_V4_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_OFST 20
15301#define MC_CMD_GET_CAPABILITIES_V4_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 31
15302#define MC_CMD_GET_CAPABILITIES_V4_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1
15303/* Number of FATSOv2 contexts per datapath supported by this NIC (when
15304 * TX_TSO_V2 == 1). Not present on older firmware (check the length).
15305 */
15306#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24
15307#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2
15308/* One byte per PF containing the number of the external port assigned to this
15309 * PF, indexed by PF number. Special values indicate that a PF is either not
15310 * present or not assigned.
15311 */
15312#define MC_CMD_GET_CAPABILITIES_V4_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26
15313#define MC_CMD_GET_CAPABILITIES_V4_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1
15314#define MC_CMD_GET_CAPABILITIES_V4_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16
15315/* enum: The caller is not permitted to access information on this PF. */
15316#define MC_CMD_GET_CAPABILITIES_V4_OUT_ACCESS_NOT_PERMITTED 0xff
15317/* enum: PF does not exist. */
15318#define MC_CMD_GET_CAPABILITIES_V4_OUT_PF_NOT_PRESENT 0xfe
15319/* enum: PF does exist but is not assigned to any external port. */
15320#define MC_CMD_GET_CAPABILITIES_V4_OUT_PF_NOT_ASSIGNED 0xfd
15321/* enum: This value indicates that PF is assigned, but it cannot be expressed
15322 * in this field. It is intended for a possible future situation where a more
15323 * complex scheme of PFs to ports mapping is being used. The future driver
15324 * should look for a new field supporting the new scheme. The current/old
15325 * driver should treat this value as PF_NOT_ASSIGNED.
15326 */
15327#define MC_CMD_GET_CAPABILITIES_V4_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
15328/* One byte per PF containing the number of its VFs, indexed by PF number. A
15329 * special value indicates that a PF is not present.
15330 */
15331#define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VFS_PER_PF_OFST 42
15332#define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VFS_PER_PF_LEN 1
15333#define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VFS_PER_PF_NUM 16
15334/* enum: The caller is not permitted to access information on this PF. */
15335/* MC_CMD_GET_CAPABILITIES_V4_OUT_ACCESS_NOT_PERMITTED 0xff */
15336/* enum: PF does not exist. */
15337/* MC_CMD_GET_CAPABILITIES_V4_OUT_PF_NOT_PRESENT 0xfe */
15338/* Number of VIs available for each external port */
15339#define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VIS_PER_PORT_OFST 58
15340#define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VIS_PER_PORT_LEN 2
15341#define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VIS_PER_PORT_NUM 4
15342/* Size of RX descriptor cache expressed as binary logarithm The actual size
15343 * equals (2 ^ RX_DESC_CACHE_SIZE)
15344 */
15345#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DESC_CACHE_SIZE_OFST 66
15346#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DESC_CACHE_SIZE_LEN 1
15347/* Size of TX descriptor cache expressed as binary logarithm The actual size
15348 * equals (2 ^ TX_DESC_CACHE_SIZE)
15349 */
15350#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_DESC_CACHE_SIZE_OFST 67
15351#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_DESC_CACHE_SIZE_LEN 1
15352/* Total number of available PIO buffers */
15353#define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_PIO_BUFFS_OFST 68
15354#define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_PIO_BUFFS_LEN 2
15355/* Size of a single PIO buffer */
15356#define MC_CMD_GET_CAPABILITIES_V4_OUT_SIZE_PIO_BUFF_OFST 70
15357#define MC_CMD_GET_CAPABILITIES_V4_OUT_SIZE_PIO_BUFF_LEN 2
15358/* On chips later than Medford the amount of address space assigned to each VI
15359 * is configurable. This is a global setting that the driver must query to
15360 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
15361 * with 8k VI windows.
15362 */
15363#define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_OFST 72
15364#define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_LEN 1
15365/* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
15366 * CTPIO is not mapped.
15367 */
15368#define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_8K 0x0
15369/* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
15370#define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_16K 0x1
15371/* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
15372#define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_64K 0x2
15373/* Number of vFIFOs per adapter that can be used for VFIFO Stuffing
15374 * (SF-115995-SW) in the present configuration of firmware and port mode.
15375 */
15376#define MC_CMD_GET_CAPABILITIES_V4_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 73
15377#define MC_CMD_GET_CAPABILITIES_V4_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1
15378/* Number of buffers per adapter that can be used for VFIFO Stuffing
15379 * (SF-115995-SW) in the present configuration of firmware and port mode.
15380 */
15381#define MC_CMD_GET_CAPABILITIES_V4_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 74
15382#define MC_CMD_GET_CAPABILITIES_V4_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 2
15383/* Entry count in the MAC stats array, including the final GENERATION_END
15384 * entry. For MAC stats DMA, drivers should allocate a buffer large enough to
15385 * hold at least this many 64-bit stats values, if they wish to receive all
15386 * available stats. If the buffer is shorter than MAC_STATS_NUM_STATS * 8, the
15387 * stats array returned will be truncated.
15388 */
15389#define MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS_OFST 76
15390#define MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS_LEN 2
15391
15392/* MC_CMD_GET_CAPABILITIES_V5_OUT msgresponse */
15393#define MC_CMD_GET_CAPABILITIES_V5_OUT_LEN 84
15394/* First word of flags. */
15395#define MC_CMD_GET_CAPABILITIES_V5_OUT_FLAGS1_OFST 0
15396#define MC_CMD_GET_CAPABILITIES_V5_OUT_FLAGS1_LEN 4
15397#define MC_CMD_GET_CAPABILITIES_V5_OUT_VPORT_RECONFIGURE_OFST 0
15398#define MC_CMD_GET_CAPABILITIES_V5_OUT_VPORT_RECONFIGURE_LBN 3
15399#define MC_CMD_GET_CAPABILITIES_V5_OUT_VPORT_RECONFIGURE_WIDTH 1
15400#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_STRIPING_OFST 0
15401#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_STRIPING_LBN 4
15402#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_STRIPING_WIDTH 1
15403#define MC_CMD_GET_CAPABILITIES_V5_OUT_VADAPTOR_QUERY_OFST 0
15404#define MC_CMD_GET_CAPABILITIES_V5_OUT_VADAPTOR_QUERY_LBN 5
15405#define MC_CMD_GET_CAPABILITIES_V5_OUT_VADAPTOR_QUERY_WIDTH 1
15406#define MC_CMD_GET_CAPABILITIES_V5_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
15407#define MC_CMD_GET_CAPABILITIES_V5_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6
15408#define MC_CMD_GET_CAPABILITIES_V5_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
15409#define MC_CMD_GET_CAPABILITIES_V5_OUT_DRV_ATTACH_PREBOOT_OFST 0
15410#define MC_CMD_GET_CAPABILITIES_V5_OUT_DRV_ATTACH_PREBOOT_LBN 7
15411#define MC_CMD_GET_CAPABILITIES_V5_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
15412#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_FORCE_EVENT_MERGING_OFST 0
15413#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_FORCE_EVENT_MERGING_LBN 8
15414#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
15415#define MC_CMD_GET_CAPABILITIES_V5_OUT_SET_MAC_ENHANCED_OFST 0
15416#define MC_CMD_GET_CAPABILITIES_V5_OUT_SET_MAC_ENHANCED_LBN 9
15417#define MC_CMD_GET_CAPABILITIES_V5_OUT_SET_MAC_ENHANCED_WIDTH 1
15418#define MC_CMD_GET_CAPABILITIES_V5_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
15419#define MC_CMD_GET_CAPABILITIES_V5_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10
15420#define MC_CMD_GET_CAPABILITIES_V5_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
15421#define MC_CMD_GET_CAPABILITIES_V5_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
15422#define MC_CMD_GET_CAPABILITIES_V5_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11
15423#define MC_CMD_GET_CAPABILITIES_V5_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
15424#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
15425#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MAC_SECURITY_FILTERING_LBN 12
15426#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
15427#define MC_CMD_GET_CAPABILITIES_V5_OUT_ADDITIONAL_RSS_MODES_OFST 0
15428#define MC_CMD_GET_CAPABILITIES_V5_OUT_ADDITIONAL_RSS_MODES_LBN 13
15429#define MC_CMD_GET_CAPABILITIES_V5_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
15430#define MC_CMD_GET_CAPABILITIES_V5_OUT_QBB_OFST 0
15431#define MC_CMD_GET_CAPABILITIES_V5_OUT_QBB_LBN 14
15432#define MC_CMD_GET_CAPABILITIES_V5_OUT_QBB_WIDTH 1
15433#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
15434#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15
15435#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
15436#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_RSS_LIMITED_OFST 0
15437#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_RSS_LIMITED_LBN 16
15438#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_RSS_LIMITED_WIDTH 1
15439#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PACKED_STREAM_OFST 0
15440#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PACKED_STREAM_LBN 17
15441#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PACKED_STREAM_WIDTH 1
15442#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_INCLUDE_FCS_OFST 0
15443#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_INCLUDE_FCS_LBN 18
15444#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_INCLUDE_FCS_WIDTH 1
15445#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_VLAN_INSERTION_OFST 0
15446#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_VLAN_INSERTION_LBN 19
15447#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_VLAN_INSERTION_WIDTH 1
15448#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_VLAN_STRIPPING_OFST 0
15449#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_VLAN_STRIPPING_LBN 20
15450#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_VLAN_STRIPPING_WIDTH 1
15451#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_OFST 0
15452#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_LBN 21
15453#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_WIDTH 1
15454#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PREFIX_LEN_0_OFST 0
15455#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PREFIX_LEN_0_LBN 22
15456#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PREFIX_LEN_0_WIDTH 1
15457#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PREFIX_LEN_14_OFST 0
15458#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PREFIX_LEN_14_LBN 23
15459#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PREFIX_LEN_14_WIDTH 1
15460#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_TIMESTAMP_OFST 0
15461#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_TIMESTAMP_LBN 24
15462#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_TIMESTAMP_WIDTH 1
15463#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_BATCHING_OFST 0
15464#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_BATCHING_LBN 25
15465#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_BATCHING_WIDTH 1
15466#define MC_CMD_GET_CAPABILITIES_V5_OUT_MCAST_FILTER_CHAINING_OFST 0
15467#define MC_CMD_GET_CAPABILITIES_V5_OUT_MCAST_FILTER_CHAINING_LBN 26
15468#define MC_CMD_GET_CAPABILITIES_V5_OUT_MCAST_FILTER_CHAINING_WIDTH 1
15469#define MC_CMD_GET_CAPABILITIES_V5_OUT_PM_AND_RXDP_COUNTERS_OFST 0
15470#define MC_CMD_GET_CAPABILITIES_V5_OUT_PM_AND_RXDP_COUNTERS_LBN 27
15471#define MC_CMD_GET_CAPABILITIES_V5_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
15472#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_DISABLE_SCATTER_OFST 0
15473#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_DISABLE_SCATTER_LBN 28
15474#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_DISABLE_SCATTER_WIDTH 1
15475#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
15476#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29
15477#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
15478#define MC_CMD_GET_CAPABILITIES_V5_OUT_EVB_OFST 0
15479#define MC_CMD_GET_CAPABILITIES_V5_OUT_EVB_LBN 30
15480#define MC_CMD_GET_CAPABILITIES_V5_OUT_EVB_WIDTH 1
15481#define MC_CMD_GET_CAPABILITIES_V5_OUT_VXLAN_NVGRE_OFST 0
15482#define MC_CMD_GET_CAPABILITIES_V5_OUT_VXLAN_NVGRE_LBN 31
15483#define MC_CMD_GET_CAPABILITIES_V5_OUT_VXLAN_NVGRE_WIDTH 1
15484/* RxDPCPU firmware id. */
15485#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_DPCPU_FW_ID_OFST 4
15486#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_DPCPU_FW_ID_LEN 2
15487/* enum: Standard RXDP firmware */
15488#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP 0x0
15489/* enum: Low latency RXDP firmware */
15490#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_LOW_LATENCY 0x1
15491/* enum: Packed stream RXDP firmware */
15492#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_PACKED_STREAM 0x2
15493/* enum: Rules engine RXDP firmware */
15494#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_RULES_ENGINE 0x5
15495/* enum: DPDK RXDP firmware */
15496#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_DPDK 0x6
15497/* enum: BIST RXDP firmware */
15498#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_BIST 0x10a
15499/* enum: RXDP Test firmware image 1 */
15500#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
15501/* enum: RXDP Test firmware image 2 */
15502#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
15503/* enum: RXDP Test firmware image 3 */
15504#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
15505/* enum: RXDP Test firmware image 4 */
15506#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
15507/* enum: RXDP Test firmware image 5 */
15508#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_BACKPRESSURE 0x105
15509/* enum: RXDP Test firmware image 6 */
15510#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
15511/* enum: RXDP Test firmware image 7 */
15512#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
15513/* enum: RXDP Test firmware image 8 */
15514#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
15515/* enum: RXDP Test firmware image 9 */
15516#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
15517/* enum: RXDP Test firmware image 10 */
15518#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_SLOW 0x10c
15519/* TxDPCPU firmware id. */
15520#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_DPCPU_FW_ID_OFST 6
15521#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_DPCPU_FW_ID_LEN 2
15522/* enum: Standard TXDP firmware */
15523#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP 0x0
15524/* enum: Low latency TXDP firmware */
15525#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_LOW_LATENCY 0x1
15526/* enum: High packet rate TXDP firmware */
15527#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_HIGH_PACKET_RATE 0x3
15528/* enum: Rules engine TXDP firmware */
15529#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_RULES_ENGINE 0x5
15530/* enum: DPDK TXDP firmware */
15531#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_DPDK 0x6
15532/* enum: BIST TXDP firmware */
15533#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_BIST 0x12d
15534/* enum: TXDP Test firmware image 1 */
15535#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
15536/* enum: TXDP Test firmware image 2 */
15537#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
15538/* enum: TXDP CSR bus test firmware */
15539#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_TEST_FW_CSR 0x103
15540#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_OFST 8
15541#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_LEN 2
15542#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_REV_OFST 8
15543#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_REV_LBN 0
15544#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_REV_WIDTH 12
15545#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_TYPE_OFST 8
15546#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_TYPE_LBN 12
15547#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
15548/* enum: reserved value - do not use (may indicate alternative interpretation
15549 * of REV field in future)
15550 */
15551#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_RESERVED 0x0
15552/* enum: Trivial RX PD firmware for early Huntington development (Huntington
15553 * development only)
15554 */
15555#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
15556/* enum: RX PD firmware for telemetry prototyping (Medford2 development only)
15557 */
15558#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
15559/* enum: RX PD firmware with approximately Siena-compatible behaviour
15560 * (Huntington development only)
15561 */
15562#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
15563/* enum: Full featured RX PD production firmware */
15564#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
15565/* enum: (deprecated original name for the FULL_FEATURED variant) */
15566#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_VSWITCH 0x3
15567/* enum: siena_compat variant RX PD firmware using PM rather than MAC
15568 * (Huntington development only)
15569 */
15570#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
15571/* enum: Low latency RX PD production firmware */
15572#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
15573/* enum: Packed stream RX PD production firmware */
15574#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
15575/* enum: RX PD firmware handling layer 2 only for high packet rate performance
15576 * tests (Medford development only)
15577 */
15578#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
15579/* enum: Rules engine RX PD production firmware */
15580#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
15581/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
15582#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_L3XUDP 0x9
15583/* enum: DPDK RX PD production firmware */
15584#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_DPDK 0xa
15585/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
15586#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
15587/* enum: RX PD firmware parsing but not filtering network overlay tunnel
15588 * encapsulations (Medford development only)
15589 */
15590#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
15591#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_OFST 10
15592#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_LEN 2
15593#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_REV_OFST 10
15594#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_REV_LBN 0
15595#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_REV_WIDTH 12
15596#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_TYPE_OFST 10
15597#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_TYPE_LBN 12
15598#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
15599/* enum: reserved value - do not use (may indicate alternative interpretation
15600 * of REV field in future)
15601 */
15602#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_RESERVED 0x0
15603/* enum: Trivial TX PD firmware for early Huntington development (Huntington
15604 * development only)
15605 */
15606#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
15607/* enum: TX PD firmware for telemetry prototyping (Medford2 development only)
15608 */
15609#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
15610/* enum: TX PD firmware with approximately Siena-compatible behaviour
15611 * (Huntington development only)
15612 */
15613#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
15614/* enum: Full featured TX PD production firmware */
15615#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
15616/* enum: (deprecated original name for the FULL_FEATURED variant) */
15617#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_VSWITCH 0x3
15618/* enum: siena_compat variant TX PD firmware using PM rather than MAC
15619 * (Huntington development only)
15620 */
15621#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
15622#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
15623/* enum: TX PD firmware handling layer 2 only for high packet rate performance
15624 * tests (Medford development only)
15625 */
15626#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
15627/* enum: Rules engine TX PD production firmware */
15628#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
15629/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
15630#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_L3XUDP 0x9
15631/* enum: DPDK TX PD production firmware */
15632#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_DPDK 0xa
15633/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
15634#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
15635/* Hardware capabilities of NIC */
15636#define MC_CMD_GET_CAPABILITIES_V5_OUT_HW_CAPABILITIES_OFST 12
15637#define MC_CMD_GET_CAPABILITIES_V5_OUT_HW_CAPABILITIES_LEN 4
15638/* Licensed capabilities */
15639#define MC_CMD_GET_CAPABILITIES_V5_OUT_LICENSE_CAPABILITIES_OFST 16
15640#define MC_CMD_GET_CAPABILITIES_V5_OUT_LICENSE_CAPABILITIES_LEN 4
15641/* Second word of flags. Not present on older firmware (check the length). */
15642#define MC_CMD_GET_CAPABILITIES_V5_OUT_FLAGS2_OFST 20
15643#define MC_CMD_GET_CAPABILITIES_V5_OUT_FLAGS2_LEN 4
15644#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_OFST 20
15645#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_LBN 0
15646#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_WIDTH 1
15647#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_ENCAP_OFST 20
15648#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_ENCAP_LBN 1
15649#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_ENCAP_WIDTH 1
15650#define MC_CMD_GET_CAPABILITIES_V5_OUT_EVQ_TIMER_CTRL_OFST 20
15651#define MC_CMD_GET_CAPABILITIES_V5_OUT_EVQ_TIMER_CTRL_LBN 2
15652#define MC_CMD_GET_CAPABILITIES_V5_OUT_EVQ_TIMER_CTRL_WIDTH 1
15653#define MC_CMD_GET_CAPABILITIES_V5_OUT_EVENT_CUT_THROUGH_OFST 20
15654#define MC_CMD_GET_CAPABILITIES_V5_OUT_EVENT_CUT_THROUGH_LBN 3
15655#define MC_CMD_GET_CAPABILITIES_V5_OUT_EVENT_CUT_THROUGH_WIDTH 1
15656#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_CUT_THROUGH_OFST 20
15657#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_CUT_THROUGH_LBN 4
15658#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_CUT_THROUGH_WIDTH 1
15659#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_VFIFO_ULL_MODE_OFST 20
15660#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_VFIFO_ULL_MODE_LBN 5
15661#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_VFIFO_ULL_MODE_WIDTH 1
15662#define MC_CMD_GET_CAPABILITIES_V5_OUT_MAC_STATS_40G_TX_SIZE_BINS_OFST 20
15663#define MC_CMD_GET_CAPABILITIES_V5_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6
15664#define MC_CMD_GET_CAPABILITIES_V5_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1
15665#define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_EVQ_TYPE_SUPPORTED_OFST 20
15666#define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_EVQ_TYPE_SUPPORTED_LBN 7
15667#define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 1
15668#define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_EVQ_V2_OFST 20
15669#define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_EVQ_V2_LBN 7
15670#define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_EVQ_V2_WIDTH 1
15671#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MAC_TIMESTAMPING_OFST 20
15672#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MAC_TIMESTAMPING_LBN 8
15673#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MAC_TIMESTAMPING_WIDTH 1
15674#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TIMESTAMP_OFST 20
15675#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TIMESTAMP_LBN 9
15676#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TIMESTAMP_WIDTH 1
15677#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_SNIFF_OFST 20
15678#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_SNIFF_LBN 10
15679#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_SNIFF_WIDTH 1
15680#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_SNIFF_OFST 20
15681#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_SNIFF_LBN 11
15682#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_SNIFF_WIDTH 1
15683#define MC_CMD_GET_CAPABILITIES_V5_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_OFST 20
15684#define MC_CMD_GET_CAPABILITIES_V5_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12
15685#define MC_CMD_GET_CAPABILITIES_V5_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1
15686#define MC_CMD_GET_CAPABILITIES_V5_OUT_MCDI_BACKGROUND_OFST 20
15687#define MC_CMD_GET_CAPABILITIES_V5_OUT_MCDI_BACKGROUND_LBN 13
15688#define MC_CMD_GET_CAPABILITIES_V5_OUT_MCDI_BACKGROUND_WIDTH 1
15689#define MC_CMD_GET_CAPABILITIES_V5_OUT_MCDI_DB_RETURN_OFST 20
15690#define MC_CMD_GET_CAPABILITIES_V5_OUT_MCDI_DB_RETURN_LBN 14
15691#define MC_CMD_GET_CAPABILITIES_V5_OUT_MCDI_DB_RETURN_WIDTH 1
15692#define MC_CMD_GET_CAPABILITIES_V5_OUT_CTPIO_OFST 20
15693#define MC_CMD_GET_CAPABILITIES_V5_OUT_CTPIO_LBN 15
15694#define MC_CMD_GET_CAPABILITIES_V5_OUT_CTPIO_WIDTH 1
15695#define MC_CMD_GET_CAPABILITIES_V5_OUT_TSA_SUPPORT_OFST 20
15696#define MC_CMD_GET_CAPABILITIES_V5_OUT_TSA_SUPPORT_LBN 16
15697#define MC_CMD_GET_CAPABILITIES_V5_OUT_TSA_SUPPORT_WIDTH 1
15698#define MC_CMD_GET_CAPABILITIES_V5_OUT_TSA_BOUND_OFST 20
15699#define MC_CMD_GET_CAPABILITIES_V5_OUT_TSA_BOUND_LBN 17
15700#define MC_CMD_GET_CAPABILITIES_V5_OUT_TSA_BOUND_WIDTH 1
15701#define MC_CMD_GET_CAPABILITIES_V5_OUT_SF_ADAPTER_AUTHENTICATION_OFST 20
15702#define MC_CMD_GET_CAPABILITIES_V5_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18
15703#define MC_CMD_GET_CAPABILITIES_V5_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1
15704#define MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_FLAG_OFST 20
15705#define MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_FLAG_LBN 19
15706#define MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_FLAG_WIDTH 1
15707#define MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_MARK_OFST 20
15708#define MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_MARK_LBN 20
15709#define MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_MARK_WIDTH 1
15710#define MC_CMD_GET_CAPABILITIES_V5_OUT_EQUAL_STRIDE_SUPER_BUFFER_OFST 20
15711#define MC_CMD_GET_CAPABILITIES_V5_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 21
15712#define MC_CMD_GET_CAPABILITIES_V5_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1
15713#define MC_CMD_GET_CAPABILITIES_V5_OUT_EQUAL_STRIDE_PACKED_STREAM_OFST 20
15714#define MC_CMD_GET_CAPABILITIES_V5_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21
15715#define MC_CMD_GET_CAPABILITIES_V5_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1
15716#define MC_CMD_GET_CAPABILITIES_V5_OUT_L3XUDP_SUPPORT_OFST 20
15717#define MC_CMD_GET_CAPABILITIES_V5_OUT_L3XUDP_SUPPORT_LBN 22
15718#define MC_CMD_GET_CAPABILITIES_V5_OUT_L3XUDP_SUPPORT_WIDTH 1
15719#define MC_CMD_GET_CAPABILITIES_V5_OUT_FW_SUBVARIANT_NO_TX_CSUM_OFST 20
15720#define MC_CMD_GET_CAPABILITIES_V5_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23
15721#define MC_CMD_GET_CAPABILITIES_V5_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1
15722#define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_SPREADING_OFST 20
15723#define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_SPREADING_LBN 24
15724#define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_SPREADING_WIDTH 1
15725#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_HLB_IDLE_OFST 20
15726#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_HLB_IDLE_LBN 25
15727#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_HLB_IDLE_WIDTH 1
15728#define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_RXQ_NO_CONT_EV_OFST 20
15729#define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_RXQ_NO_CONT_EV_LBN 26
15730#define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1
15731#define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_RXQ_WITH_BUFFER_SIZE_OFST 20
15732#define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 27
15733#define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1
15734#define MC_CMD_GET_CAPABILITIES_V5_OUT_BUNDLE_UPDATE_OFST 20
15735#define MC_CMD_GET_CAPABILITIES_V5_OUT_BUNDLE_UPDATE_LBN 28
15736#define MC_CMD_GET_CAPABILITIES_V5_OUT_BUNDLE_UPDATE_WIDTH 1
15737#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V3_OFST 20
15738#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V3_LBN 29
15739#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V3_WIDTH 1
15740#define MC_CMD_GET_CAPABILITIES_V5_OUT_DYNAMIC_SENSORS_OFST 20
15741#define MC_CMD_GET_CAPABILITIES_V5_OUT_DYNAMIC_SENSORS_LBN 30
15742#define MC_CMD_GET_CAPABILITIES_V5_OUT_DYNAMIC_SENSORS_WIDTH 1
15743#define MC_CMD_GET_CAPABILITIES_V5_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_OFST 20
15744#define MC_CMD_GET_CAPABILITIES_V5_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 31
15745#define MC_CMD_GET_CAPABILITIES_V5_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1
15746/* Number of FATSOv2 contexts per datapath supported by this NIC (when
15747 * TX_TSO_V2 == 1). Not present on older firmware (check the length).
15748 */
15749#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24
15750#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2
15751/* One byte per PF containing the number of the external port assigned to this
15752 * PF, indexed by PF number. Special values indicate that a PF is either not
15753 * present or not assigned.
15754 */
15755#define MC_CMD_GET_CAPABILITIES_V5_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26
15756#define MC_CMD_GET_CAPABILITIES_V5_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1
15757#define MC_CMD_GET_CAPABILITIES_V5_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16
15758/* enum: The caller is not permitted to access information on this PF. */
15759#define MC_CMD_GET_CAPABILITIES_V5_OUT_ACCESS_NOT_PERMITTED 0xff
15760/* enum: PF does not exist. */
15761#define MC_CMD_GET_CAPABILITIES_V5_OUT_PF_NOT_PRESENT 0xfe
15762/* enum: PF does exist but is not assigned to any external port. */
15763#define MC_CMD_GET_CAPABILITIES_V5_OUT_PF_NOT_ASSIGNED 0xfd
15764/* enum: This value indicates that PF is assigned, but it cannot be expressed
15765 * in this field. It is intended for a possible future situation where a more
15766 * complex scheme of PFs to ports mapping is being used. The future driver
15767 * should look for a new field supporting the new scheme. The current/old
15768 * driver should treat this value as PF_NOT_ASSIGNED.
15769 */
15770#define MC_CMD_GET_CAPABILITIES_V5_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
15771/* One byte per PF containing the number of its VFs, indexed by PF number. A
15772 * special value indicates that a PF is not present.
15773 */
15774#define MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_VFS_PER_PF_OFST 42
15775#define MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_VFS_PER_PF_LEN 1
15776#define MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_VFS_PER_PF_NUM 16
15777/* enum: The caller is not permitted to access information on this PF. */
15778/* MC_CMD_GET_CAPABILITIES_V5_OUT_ACCESS_NOT_PERMITTED 0xff */
15779/* enum: PF does not exist. */
15780/* MC_CMD_GET_CAPABILITIES_V5_OUT_PF_NOT_PRESENT 0xfe */
15781/* Number of VIs available for each external port */
15782#define MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_VIS_PER_PORT_OFST 58
15783#define MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_VIS_PER_PORT_LEN 2
15784#define MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_VIS_PER_PORT_NUM 4
15785/* Size of RX descriptor cache expressed as binary logarithm The actual size
15786 * equals (2 ^ RX_DESC_CACHE_SIZE)
15787 */
15788#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_DESC_CACHE_SIZE_OFST 66
15789#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_DESC_CACHE_SIZE_LEN 1
15790/* Size of TX descriptor cache expressed as binary logarithm The actual size
15791 * equals (2 ^ TX_DESC_CACHE_SIZE)
15792 */
15793#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_DESC_CACHE_SIZE_OFST 67
15794#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_DESC_CACHE_SIZE_LEN 1
15795/* Total number of available PIO buffers */
15796#define MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_PIO_BUFFS_OFST 68
15797#define MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_PIO_BUFFS_LEN 2
15798/* Size of a single PIO buffer */
15799#define MC_CMD_GET_CAPABILITIES_V5_OUT_SIZE_PIO_BUFF_OFST 70
15800#define MC_CMD_GET_CAPABILITIES_V5_OUT_SIZE_PIO_BUFF_LEN 2
15801/* On chips later than Medford the amount of address space assigned to each VI
15802 * is configurable. This is a global setting that the driver must query to
15803 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
15804 * with 8k VI windows.
15805 */
15806#define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_WINDOW_MODE_OFST 72
15807#define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_WINDOW_MODE_LEN 1
15808/* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
15809 * CTPIO is not mapped.
15810 */
15811#define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_WINDOW_MODE_8K 0x0
15812/* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
15813#define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_WINDOW_MODE_16K 0x1
15814/* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
15815#define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_WINDOW_MODE_64K 0x2
15816/* Number of vFIFOs per adapter that can be used for VFIFO Stuffing
15817 * (SF-115995-SW) in the present configuration of firmware and port mode.
15818 */
15819#define MC_CMD_GET_CAPABILITIES_V5_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 73
15820#define MC_CMD_GET_CAPABILITIES_V5_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1
15821/* Number of buffers per adapter that can be used for VFIFO Stuffing
15822 * (SF-115995-SW) in the present configuration of firmware and port mode.
15823 */
15824#define MC_CMD_GET_CAPABILITIES_V5_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 74
15825#define MC_CMD_GET_CAPABILITIES_V5_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 2
15826/* Entry count in the MAC stats array, including the final GENERATION_END
15827 * entry. For MAC stats DMA, drivers should allocate a buffer large enough to
15828 * hold at least this many 64-bit stats values, if they wish to receive all
15829 * available stats. If the buffer is shorter than MAC_STATS_NUM_STATS * 8, the
15830 * stats array returned will be truncated.
15831 */
15832#define MC_CMD_GET_CAPABILITIES_V5_OUT_MAC_STATS_NUM_STATS_OFST 76
15833#define MC_CMD_GET_CAPABILITIES_V5_OUT_MAC_STATS_NUM_STATS_LEN 2
15834/* Maximum supported value for MC_CMD_FILTER_OP_V3/MATCH_MARK_VALUE. This field
15835 * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set.
15836 */
15837#define MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_MARK_MAX_OFST 80
15838#define MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_MARK_MAX_LEN 4
15839
15840/* MC_CMD_GET_CAPABILITIES_V6_OUT msgresponse */
15841#define MC_CMD_GET_CAPABILITIES_V6_OUT_LEN 148
15842/* First word of flags. */
15843#define MC_CMD_GET_CAPABILITIES_V6_OUT_FLAGS1_OFST 0
15844#define MC_CMD_GET_CAPABILITIES_V6_OUT_FLAGS1_LEN 4
15845#define MC_CMD_GET_CAPABILITIES_V6_OUT_VPORT_RECONFIGURE_OFST 0
15846#define MC_CMD_GET_CAPABILITIES_V6_OUT_VPORT_RECONFIGURE_LBN 3
15847#define MC_CMD_GET_CAPABILITIES_V6_OUT_VPORT_RECONFIGURE_WIDTH 1
15848#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_STRIPING_OFST 0
15849#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_STRIPING_LBN 4
15850#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_STRIPING_WIDTH 1
15851#define MC_CMD_GET_CAPABILITIES_V6_OUT_VADAPTOR_QUERY_OFST 0
15852#define MC_CMD_GET_CAPABILITIES_V6_OUT_VADAPTOR_QUERY_LBN 5
15853#define MC_CMD_GET_CAPABILITIES_V6_OUT_VADAPTOR_QUERY_WIDTH 1
15854#define MC_CMD_GET_CAPABILITIES_V6_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
15855#define MC_CMD_GET_CAPABILITIES_V6_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6
15856#define MC_CMD_GET_CAPABILITIES_V6_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
15857#define MC_CMD_GET_CAPABILITIES_V6_OUT_DRV_ATTACH_PREBOOT_OFST 0
15858#define MC_CMD_GET_CAPABILITIES_V6_OUT_DRV_ATTACH_PREBOOT_LBN 7
15859#define MC_CMD_GET_CAPABILITIES_V6_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
15860#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_FORCE_EVENT_MERGING_OFST 0
15861#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_FORCE_EVENT_MERGING_LBN 8
15862#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
15863#define MC_CMD_GET_CAPABILITIES_V6_OUT_SET_MAC_ENHANCED_OFST 0
15864#define MC_CMD_GET_CAPABILITIES_V6_OUT_SET_MAC_ENHANCED_LBN 9
15865#define MC_CMD_GET_CAPABILITIES_V6_OUT_SET_MAC_ENHANCED_WIDTH 1
15866#define MC_CMD_GET_CAPABILITIES_V6_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
15867#define MC_CMD_GET_CAPABILITIES_V6_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10
15868#define MC_CMD_GET_CAPABILITIES_V6_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
15869#define MC_CMD_GET_CAPABILITIES_V6_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
15870#define MC_CMD_GET_CAPABILITIES_V6_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11
15871#define MC_CMD_GET_CAPABILITIES_V6_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
15872#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
15873#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MAC_SECURITY_FILTERING_LBN 12
15874#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
15875#define MC_CMD_GET_CAPABILITIES_V6_OUT_ADDITIONAL_RSS_MODES_OFST 0
15876#define MC_CMD_GET_CAPABILITIES_V6_OUT_ADDITIONAL_RSS_MODES_LBN 13
15877#define MC_CMD_GET_CAPABILITIES_V6_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
15878#define MC_CMD_GET_CAPABILITIES_V6_OUT_QBB_OFST 0
15879#define MC_CMD_GET_CAPABILITIES_V6_OUT_QBB_LBN 14
15880#define MC_CMD_GET_CAPABILITIES_V6_OUT_QBB_WIDTH 1
15881#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
15882#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15
15883#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
15884#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_RSS_LIMITED_OFST 0
15885#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_RSS_LIMITED_LBN 16
15886#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_RSS_LIMITED_WIDTH 1
15887#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PACKED_STREAM_OFST 0
15888#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PACKED_STREAM_LBN 17
15889#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PACKED_STREAM_WIDTH 1
15890#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_INCLUDE_FCS_OFST 0
15891#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_INCLUDE_FCS_LBN 18
15892#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_INCLUDE_FCS_WIDTH 1
15893#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_VLAN_INSERTION_OFST 0
15894#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_VLAN_INSERTION_LBN 19
15895#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_VLAN_INSERTION_WIDTH 1
15896#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_VLAN_STRIPPING_OFST 0
15897#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_VLAN_STRIPPING_LBN 20
15898#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_VLAN_STRIPPING_WIDTH 1
15899#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_OFST 0
15900#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_LBN 21
15901#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_WIDTH 1
15902#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PREFIX_LEN_0_OFST 0
15903#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PREFIX_LEN_0_LBN 22
15904#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PREFIX_LEN_0_WIDTH 1
15905#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PREFIX_LEN_14_OFST 0
15906#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PREFIX_LEN_14_LBN 23
15907#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PREFIX_LEN_14_WIDTH 1
15908#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_TIMESTAMP_OFST 0
15909#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_TIMESTAMP_LBN 24
15910#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_TIMESTAMP_WIDTH 1
15911#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_BATCHING_OFST 0
15912#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_BATCHING_LBN 25
15913#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_BATCHING_WIDTH 1
15914#define MC_CMD_GET_CAPABILITIES_V6_OUT_MCAST_FILTER_CHAINING_OFST 0
15915#define MC_CMD_GET_CAPABILITIES_V6_OUT_MCAST_FILTER_CHAINING_LBN 26
15916#define MC_CMD_GET_CAPABILITIES_V6_OUT_MCAST_FILTER_CHAINING_WIDTH 1
15917#define MC_CMD_GET_CAPABILITIES_V6_OUT_PM_AND_RXDP_COUNTERS_OFST 0
15918#define MC_CMD_GET_CAPABILITIES_V6_OUT_PM_AND_RXDP_COUNTERS_LBN 27
15919#define MC_CMD_GET_CAPABILITIES_V6_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
15920#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_DISABLE_SCATTER_OFST 0
15921#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_DISABLE_SCATTER_LBN 28
15922#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_DISABLE_SCATTER_WIDTH 1
15923#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
15924#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29
15925#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
15926#define MC_CMD_GET_CAPABILITIES_V6_OUT_EVB_OFST 0
15927#define MC_CMD_GET_CAPABILITIES_V6_OUT_EVB_LBN 30
15928#define MC_CMD_GET_CAPABILITIES_V6_OUT_EVB_WIDTH 1
15929#define MC_CMD_GET_CAPABILITIES_V6_OUT_VXLAN_NVGRE_OFST 0
15930#define MC_CMD_GET_CAPABILITIES_V6_OUT_VXLAN_NVGRE_LBN 31
15931#define MC_CMD_GET_CAPABILITIES_V6_OUT_VXLAN_NVGRE_WIDTH 1
15932/* RxDPCPU firmware id. */
15933#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_DPCPU_FW_ID_OFST 4
15934#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_DPCPU_FW_ID_LEN 2
15935/* enum: Standard RXDP firmware */
15936#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP 0x0
15937/* enum: Low latency RXDP firmware */
15938#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_LOW_LATENCY 0x1
15939/* enum: Packed stream RXDP firmware */
15940#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_PACKED_STREAM 0x2
15941/* enum: Rules engine RXDP firmware */
15942#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_RULES_ENGINE 0x5
15943/* enum: DPDK RXDP firmware */
15944#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_DPDK 0x6
15945/* enum: BIST RXDP firmware */
15946#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_BIST 0x10a
15947/* enum: RXDP Test firmware image 1 */
15948#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
15949/* enum: RXDP Test firmware image 2 */
15950#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
15951/* enum: RXDP Test firmware image 3 */
15952#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
15953/* enum: RXDP Test firmware image 4 */
15954#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
15955/* enum: RXDP Test firmware image 5 */
15956#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_BACKPRESSURE 0x105
15957/* enum: RXDP Test firmware image 6 */
15958#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
15959/* enum: RXDP Test firmware image 7 */
15960#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
15961/* enum: RXDP Test firmware image 8 */
15962#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
15963/* enum: RXDP Test firmware image 9 */
15964#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
15965/* enum: RXDP Test firmware image 10 */
15966#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_SLOW 0x10c
15967/* TxDPCPU firmware id. */
15968#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_DPCPU_FW_ID_OFST 6
15969#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_DPCPU_FW_ID_LEN 2
15970/* enum: Standard TXDP firmware */
15971#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP 0x0
15972/* enum: Low latency TXDP firmware */
15973#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_LOW_LATENCY 0x1
15974/* enum: High packet rate TXDP firmware */
15975#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_HIGH_PACKET_RATE 0x3
15976/* enum: Rules engine TXDP firmware */
15977#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_RULES_ENGINE 0x5
15978/* enum: DPDK TXDP firmware */
15979#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_DPDK 0x6
15980/* enum: BIST TXDP firmware */
15981#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_BIST 0x12d
15982/* enum: TXDP Test firmware image 1 */
15983#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
15984/* enum: TXDP Test firmware image 2 */
15985#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
15986/* enum: TXDP CSR bus test firmware */
15987#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_TEST_FW_CSR 0x103
15988#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_OFST 8
15989#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_LEN 2
15990#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_REV_OFST 8
15991#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_REV_LBN 0
15992#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_REV_WIDTH 12
15993#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_TYPE_OFST 8
15994#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_TYPE_LBN 12
15995#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
15996/* enum: reserved value - do not use (may indicate alternative interpretation
15997 * of REV field in future)
15998 */
15999#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_RESERVED 0x0
16000/* enum: Trivial RX PD firmware for early Huntington development (Huntington
16001 * development only)
16002 */
16003#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
16004/* enum: RX PD firmware for telemetry prototyping (Medford2 development only)
16005 */
16006#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
16007/* enum: RX PD firmware with approximately Siena-compatible behaviour
16008 * (Huntington development only)
16009 */
16010#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
16011/* enum: Full featured RX PD production firmware */
16012#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
16013/* enum: (deprecated original name for the FULL_FEATURED variant) */
16014#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_VSWITCH 0x3
16015/* enum: siena_compat variant RX PD firmware using PM rather than MAC
16016 * (Huntington development only)
16017 */
16018#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
16019/* enum: Low latency RX PD production firmware */
16020#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
16021/* enum: Packed stream RX PD production firmware */
16022#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
16023/* enum: RX PD firmware handling layer 2 only for high packet rate performance
16024 * tests (Medford development only)
16025 */
16026#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
16027/* enum: Rules engine RX PD production firmware */
16028#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
16029/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
16030#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_L3XUDP 0x9
16031/* enum: DPDK RX PD production firmware */
16032#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_DPDK 0xa
16033/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
16034#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
16035/* enum: RX PD firmware parsing but not filtering network overlay tunnel
16036 * encapsulations (Medford development only)
16037 */
16038#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
16039#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_OFST 10
16040#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_LEN 2
16041#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_REV_OFST 10
16042#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_REV_LBN 0
16043#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_REV_WIDTH 12
16044#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_TYPE_OFST 10
16045#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_TYPE_LBN 12
16046#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
16047/* enum: reserved value - do not use (may indicate alternative interpretation
16048 * of REV field in future)
16049 */
16050#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_RESERVED 0x0
16051/* enum: Trivial TX PD firmware for early Huntington development (Huntington
16052 * development only)
16053 */
16054#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
16055/* enum: TX PD firmware for telemetry prototyping (Medford2 development only)
16056 */
16057#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
16058/* enum: TX PD firmware with approximately Siena-compatible behaviour
16059 * (Huntington development only)
16060 */
16061#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
16062/* enum: Full featured TX PD production firmware */
16063#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
16064/* enum: (deprecated original name for the FULL_FEATURED variant) */
16065#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_VSWITCH 0x3
16066/* enum: siena_compat variant TX PD firmware using PM rather than MAC
16067 * (Huntington development only)
16068 */
16069#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
16070#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
16071/* enum: TX PD firmware handling layer 2 only for high packet rate performance
16072 * tests (Medford development only)
16073 */
16074#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
16075/* enum: Rules engine TX PD production firmware */
16076#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
16077/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
16078#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_L3XUDP 0x9
16079/* enum: DPDK TX PD production firmware */
16080#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_DPDK 0xa
16081/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
16082#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
16083/* Hardware capabilities of NIC */
16084#define MC_CMD_GET_CAPABILITIES_V6_OUT_HW_CAPABILITIES_OFST 12
16085#define MC_CMD_GET_CAPABILITIES_V6_OUT_HW_CAPABILITIES_LEN 4
16086/* Licensed capabilities */
16087#define MC_CMD_GET_CAPABILITIES_V6_OUT_LICENSE_CAPABILITIES_OFST 16
16088#define MC_CMD_GET_CAPABILITIES_V6_OUT_LICENSE_CAPABILITIES_LEN 4
16089/* Second word of flags. Not present on older firmware (check the length). */
16090#define MC_CMD_GET_CAPABILITIES_V6_OUT_FLAGS2_OFST 20
16091#define MC_CMD_GET_CAPABILITIES_V6_OUT_FLAGS2_LEN 4
16092#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_OFST 20
16093#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_LBN 0
16094#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_WIDTH 1
16095#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_ENCAP_OFST 20
16096#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_ENCAP_LBN 1
16097#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_ENCAP_WIDTH 1
16098#define MC_CMD_GET_CAPABILITIES_V6_OUT_EVQ_TIMER_CTRL_OFST 20
16099#define MC_CMD_GET_CAPABILITIES_V6_OUT_EVQ_TIMER_CTRL_LBN 2
16100#define MC_CMD_GET_CAPABILITIES_V6_OUT_EVQ_TIMER_CTRL_WIDTH 1
16101#define MC_CMD_GET_CAPABILITIES_V6_OUT_EVENT_CUT_THROUGH_OFST 20
16102#define MC_CMD_GET_CAPABILITIES_V6_OUT_EVENT_CUT_THROUGH_LBN 3
16103#define MC_CMD_GET_CAPABILITIES_V6_OUT_EVENT_CUT_THROUGH_WIDTH 1
16104#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_CUT_THROUGH_OFST 20
16105#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_CUT_THROUGH_LBN 4
16106#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_CUT_THROUGH_WIDTH 1
16107#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_VFIFO_ULL_MODE_OFST 20
16108#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_VFIFO_ULL_MODE_LBN 5
16109#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_VFIFO_ULL_MODE_WIDTH 1
16110#define MC_CMD_GET_CAPABILITIES_V6_OUT_MAC_STATS_40G_TX_SIZE_BINS_OFST 20
16111#define MC_CMD_GET_CAPABILITIES_V6_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6
16112#define MC_CMD_GET_CAPABILITIES_V6_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1
16113#define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_EVQ_TYPE_SUPPORTED_OFST 20
16114#define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_EVQ_TYPE_SUPPORTED_LBN 7
16115#define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 1
16116#define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_EVQ_V2_OFST 20
16117#define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_EVQ_V2_LBN 7
16118#define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_EVQ_V2_WIDTH 1
16119#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MAC_TIMESTAMPING_OFST 20
16120#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MAC_TIMESTAMPING_LBN 8
16121#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MAC_TIMESTAMPING_WIDTH 1
16122#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TIMESTAMP_OFST 20
16123#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TIMESTAMP_LBN 9
16124#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TIMESTAMP_WIDTH 1
16125#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_SNIFF_OFST 20
16126#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_SNIFF_LBN 10
16127#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_SNIFF_WIDTH 1
16128#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_SNIFF_OFST 20
16129#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_SNIFF_LBN 11
16130#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_SNIFF_WIDTH 1
16131#define MC_CMD_GET_CAPABILITIES_V6_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_OFST 20
16132#define MC_CMD_GET_CAPABILITIES_V6_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12
16133#define MC_CMD_GET_CAPABILITIES_V6_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1
16134#define MC_CMD_GET_CAPABILITIES_V6_OUT_MCDI_BACKGROUND_OFST 20
16135#define MC_CMD_GET_CAPABILITIES_V6_OUT_MCDI_BACKGROUND_LBN 13
16136#define MC_CMD_GET_CAPABILITIES_V6_OUT_MCDI_BACKGROUND_WIDTH 1
16137#define MC_CMD_GET_CAPABILITIES_V6_OUT_MCDI_DB_RETURN_OFST 20
16138#define MC_CMD_GET_CAPABILITIES_V6_OUT_MCDI_DB_RETURN_LBN 14
16139#define MC_CMD_GET_CAPABILITIES_V6_OUT_MCDI_DB_RETURN_WIDTH 1
16140#define MC_CMD_GET_CAPABILITIES_V6_OUT_CTPIO_OFST 20
16141#define MC_CMD_GET_CAPABILITIES_V6_OUT_CTPIO_LBN 15
16142#define MC_CMD_GET_CAPABILITIES_V6_OUT_CTPIO_WIDTH 1
16143#define MC_CMD_GET_CAPABILITIES_V6_OUT_TSA_SUPPORT_OFST 20
16144#define MC_CMD_GET_CAPABILITIES_V6_OUT_TSA_SUPPORT_LBN 16
16145#define MC_CMD_GET_CAPABILITIES_V6_OUT_TSA_SUPPORT_WIDTH 1
16146#define MC_CMD_GET_CAPABILITIES_V6_OUT_TSA_BOUND_OFST 20
16147#define MC_CMD_GET_CAPABILITIES_V6_OUT_TSA_BOUND_LBN 17
16148#define MC_CMD_GET_CAPABILITIES_V6_OUT_TSA_BOUND_WIDTH 1
16149#define MC_CMD_GET_CAPABILITIES_V6_OUT_SF_ADAPTER_AUTHENTICATION_OFST 20
16150#define MC_CMD_GET_CAPABILITIES_V6_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18
16151#define MC_CMD_GET_CAPABILITIES_V6_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1
16152#define MC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_FLAG_OFST 20
16153#define MC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_FLAG_LBN 19
16154#define MC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_FLAG_WIDTH 1
16155#define MC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_MARK_OFST 20
16156#define MC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_MARK_LBN 20
16157#define MC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_MARK_WIDTH 1
16158#define MC_CMD_GET_CAPABILITIES_V6_OUT_EQUAL_STRIDE_SUPER_BUFFER_OFST 20
16159#define MC_CMD_GET_CAPABILITIES_V6_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 21
16160#define MC_CMD_GET_CAPABILITIES_V6_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1
16161#define MC_CMD_GET_CAPABILITIES_V6_OUT_EQUAL_STRIDE_PACKED_STREAM_OFST 20
16162#define MC_CMD_GET_CAPABILITIES_V6_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21
16163#define MC_CMD_GET_CAPABILITIES_V6_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1
16164#define MC_CMD_GET_CAPABILITIES_V6_OUT_L3XUDP_SUPPORT_OFST 20
16165#define MC_CMD_GET_CAPABILITIES_V6_OUT_L3XUDP_SUPPORT_LBN 22
16166#define MC_CMD_GET_CAPABILITIES_V6_OUT_L3XUDP_SUPPORT_WIDTH 1
16167#define MC_CMD_GET_CAPABILITIES_V6_OUT_FW_SUBVARIANT_NO_TX_CSUM_OFST 20
16168#define MC_CMD_GET_CAPABILITIES_V6_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23
16169#define MC_CMD_GET_CAPABILITIES_V6_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1
16170#define MC_CMD_GET_CAPABILITIES_V6_OUT_VI_SPREADING_OFST 20
16171#define MC_CMD_GET_CAPABILITIES_V6_OUT_VI_SPREADING_LBN 24
16172#define MC_CMD_GET_CAPABILITIES_V6_OUT_VI_SPREADING_WIDTH 1
16173#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_HLB_IDLE_OFST 20
16174#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_HLB_IDLE_LBN 25
16175#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_HLB_IDLE_WIDTH 1
16176#define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_RXQ_NO_CONT_EV_OFST 20
16177#define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_RXQ_NO_CONT_EV_LBN 26
16178#define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1
16179#define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_RXQ_WITH_BUFFER_SIZE_OFST 20
16180#define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 27
16181#define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1
16182#define MC_CMD_GET_CAPABILITIES_V6_OUT_BUNDLE_UPDATE_OFST 20
16183#define MC_CMD_GET_CAPABILITIES_V6_OUT_BUNDLE_UPDATE_LBN 28
16184#define MC_CMD_GET_CAPABILITIES_V6_OUT_BUNDLE_UPDATE_WIDTH 1
16185#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V3_OFST 20
16186#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V3_LBN 29
16187#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V3_WIDTH 1
16188#define MC_CMD_GET_CAPABILITIES_V6_OUT_DYNAMIC_SENSORS_OFST 20
16189#define MC_CMD_GET_CAPABILITIES_V6_OUT_DYNAMIC_SENSORS_LBN 30
16190#define MC_CMD_GET_CAPABILITIES_V6_OUT_DYNAMIC_SENSORS_WIDTH 1
16191#define MC_CMD_GET_CAPABILITIES_V6_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_OFST 20
16192#define MC_CMD_GET_CAPABILITIES_V6_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 31
16193#define MC_CMD_GET_CAPABILITIES_V6_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1
16194/* Number of FATSOv2 contexts per datapath supported by this NIC (when
16195 * TX_TSO_V2 == 1). Not present on older firmware (check the length).
16196 */
16197#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24
16198#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2
16199/* One byte per PF containing the number of the external port assigned to this
16200 * PF, indexed by PF number. Special values indicate that a PF is either not
16201 * present or not assigned.
16202 */
16203#define MC_CMD_GET_CAPABILITIES_V6_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26
16204#define MC_CMD_GET_CAPABILITIES_V6_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1
16205#define MC_CMD_GET_CAPABILITIES_V6_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16
16206/* enum: The caller is not permitted to access information on this PF. */
16207#define MC_CMD_GET_CAPABILITIES_V6_OUT_ACCESS_NOT_PERMITTED 0xff
16208/* enum: PF does not exist. */
16209#define MC_CMD_GET_CAPABILITIES_V6_OUT_PF_NOT_PRESENT 0xfe
16210/* enum: PF does exist but is not assigned to any external port. */
16211#define MC_CMD_GET_CAPABILITIES_V6_OUT_PF_NOT_ASSIGNED 0xfd
16212/* enum: This value indicates that PF is assigned, but it cannot be expressed
16213 * in this field. It is intended for a possible future situation where a more
16214 * complex scheme of PFs to ports mapping is being used. The future driver
16215 * should look for a new field supporting the new scheme. The current/old
16216 * driver should treat this value as PF_NOT_ASSIGNED.
16217 */
16218#define MC_CMD_GET_CAPABILITIES_V6_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
16219/* One byte per PF containing the number of its VFs, indexed by PF number. A
16220 * special value indicates that a PF is not present.
16221 */
16222#define MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_VFS_PER_PF_OFST 42
16223#define MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_VFS_PER_PF_LEN 1
16224#define MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_VFS_PER_PF_NUM 16
16225/* enum: The caller is not permitted to access information on this PF. */
16226/* MC_CMD_GET_CAPABILITIES_V6_OUT_ACCESS_NOT_PERMITTED 0xff */
16227/* enum: PF does not exist. */
16228/* MC_CMD_GET_CAPABILITIES_V6_OUT_PF_NOT_PRESENT 0xfe */
16229/* Number of VIs available for each external port */
16230#define MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_VIS_PER_PORT_OFST 58
16231#define MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_VIS_PER_PORT_LEN 2
16232#define MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_VIS_PER_PORT_NUM 4
16233/* Size of RX descriptor cache expressed as binary logarithm The actual size
16234 * equals (2 ^ RX_DESC_CACHE_SIZE)
16235 */
16236#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_DESC_CACHE_SIZE_OFST 66
16237#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_DESC_CACHE_SIZE_LEN 1
16238/* Size of TX descriptor cache expressed as binary logarithm The actual size
16239 * equals (2 ^ TX_DESC_CACHE_SIZE)
16240 */
16241#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_DESC_CACHE_SIZE_OFST 67
16242#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_DESC_CACHE_SIZE_LEN 1
16243/* Total number of available PIO buffers */
16244#define MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_PIO_BUFFS_OFST 68
16245#define MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_PIO_BUFFS_LEN 2
16246/* Size of a single PIO buffer */
16247#define MC_CMD_GET_CAPABILITIES_V6_OUT_SIZE_PIO_BUFF_OFST 70
16248#define MC_CMD_GET_CAPABILITIES_V6_OUT_SIZE_PIO_BUFF_LEN 2
16249/* On chips later than Medford the amount of address space assigned to each VI
16250 * is configurable. This is a global setting that the driver must query to
16251 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
16252 * with 8k VI windows.
16253 */
16254#define MC_CMD_GET_CAPABILITIES_V6_OUT_VI_WINDOW_MODE_OFST 72
16255#define MC_CMD_GET_CAPABILITIES_V6_OUT_VI_WINDOW_MODE_LEN 1
16256/* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
16257 * CTPIO is not mapped.
16258 */
16259#define MC_CMD_GET_CAPABILITIES_V6_OUT_VI_WINDOW_MODE_8K 0x0
16260/* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
16261#define MC_CMD_GET_CAPABILITIES_V6_OUT_VI_WINDOW_MODE_16K 0x1
16262/* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
16263#define MC_CMD_GET_CAPABILITIES_V6_OUT_VI_WINDOW_MODE_64K 0x2
16264/* Number of vFIFOs per adapter that can be used for VFIFO Stuffing
16265 * (SF-115995-SW) in the present configuration of firmware and port mode.
16266 */
16267#define MC_CMD_GET_CAPABILITIES_V6_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 73
16268#define MC_CMD_GET_CAPABILITIES_V6_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1
16269/* Number of buffers per adapter that can be used for VFIFO Stuffing
16270 * (SF-115995-SW) in the present configuration of firmware and port mode.
16271 */
16272#define MC_CMD_GET_CAPABILITIES_V6_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 74
16273#define MC_CMD_GET_CAPABILITIES_V6_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 2
16274/* Entry count in the MAC stats array, including the final GENERATION_END
16275 * entry. For MAC stats DMA, drivers should allocate a buffer large enough to
16276 * hold at least this many 64-bit stats values, if they wish to receive all
16277 * available stats. If the buffer is shorter than MAC_STATS_NUM_STATS * 8, the
16278 * stats array returned will be truncated.
16279 */
16280#define MC_CMD_GET_CAPABILITIES_V6_OUT_MAC_STATS_NUM_STATS_OFST 76
16281#define MC_CMD_GET_CAPABILITIES_V6_OUT_MAC_STATS_NUM_STATS_LEN 2
16282/* Maximum supported value for MC_CMD_FILTER_OP_V3/MATCH_MARK_VALUE. This field
16283 * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set.
16284 */
16285#define MC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_MARK_MAX_OFST 80
16286#define MC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_MARK_MAX_LEN 4
16287/* On devices where the INIT_RXQ_WITH_BUFFER_SIZE flag (in
16288 * GET_CAPABILITIES_OUT_V2) is set, drivers have to specify a buffer size when
16289 * they create an RX queue. Due to hardware limitations, only a small number of
16290 * different buffer sizes may be available concurrently. Nonzero entries in
16291 * this array are the sizes of buffers which the system guarantees will be
16292 * available for use. If the list is empty, there are no limitations on
16293 * concurrent buffer sizes.
16294 */
16295#define MC_CMD_GET_CAPABILITIES_V6_OUT_GUARANTEED_RX_BUFFER_SIZES_OFST 84
16296#define MC_CMD_GET_CAPABILITIES_V6_OUT_GUARANTEED_RX_BUFFER_SIZES_LEN 4
16297#define MC_CMD_GET_CAPABILITIES_V6_OUT_GUARANTEED_RX_BUFFER_SIZES_NUM 16
16298
16299/* MC_CMD_GET_CAPABILITIES_V7_OUT msgresponse */
16300#define MC_CMD_GET_CAPABILITIES_V7_OUT_LEN 152
16301/* First word of flags. */
16302#define MC_CMD_GET_CAPABILITIES_V7_OUT_FLAGS1_OFST 0
16303#define MC_CMD_GET_CAPABILITIES_V7_OUT_FLAGS1_LEN 4
16304#define MC_CMD_GET_CAPABILITIES_V7_OUT_VPORT_RECONFIGURE_OFST 0
16305#define MC_CMD_GET_CAPABILITIES_V7_OUT_VPORT_RECONFIGURE_LBN 3
16306#define MC_CMD_GET_CAPABILITIES_V7_OUT_VPORT_RECONFIGURE_WIDTH 1
16307#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_STRIPING_OFST 0
16308#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_STRIPING_LBN 4
16309#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_STRIPING_WIDTH 1
16310#define MC_CMD_GET_CAPABILITIES_V7_OUT_VADAPTOR_QUERY_OFST 0
16311#define MC_CMD_GET_CAPABILITIES_V7_OUT_VADAPTOR_QUERY_LBN 5
16312#define MC_CMD_GET_CAPABILITIES_V7_OUT_VADAPTOR_QUERY_WIDTH 1
16313#define MC_CMD_GET_CAPABILITIES_V7_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
16314#define MC_CMD_GET_CAPABILITIES_V7_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6
16315#define MC_CMD_GET_CAPABILITIES_V7_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
16316#define MC_CMD_GET_CAPABILITIES_V7_OUT_DRV_ATTACH_PREBOOT_OFST 0
16317#define MC_CMD_GET_CAPABILITIES_V7_OUT_DRV_ATTACH_PREBOOT_LBN 7
16318#define MC_CMD_GET_CAPABILITIES_V7_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
16319#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_FORCE_EVENT_MERGING_OFST 0
16320#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_FORCE_EVENT_MERGING_LBN 8
16321#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
16322#define MC_CMD_GET_CAPABILITIES_V7_OUT_SET_MAC_ENHANCED_OFST 0
16323#define MC_CMD_GET_CAPABILITIES_V7_OUT_SET_MAC_ENHANCED_LBN 9
16324#define MC_CMD_GET_CAPABILITIES_V7_OUT_SET_MAC_ENHANCED_WIDTH 1
16325#define MC_CMD_GET_CAPABILITIES_V7_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
16326#define MC_CMD_GET_CAPABILITIES_V7_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10
16327#define MC_CMD_GET_CAPABILITIES_V7_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
16328#define MC_CMD_GET_CAPABILITIES_V7_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
16329#define MC_CMD_GET_CAPABILITIES_V7_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11
16330#define MC_CMD_GET_CAPABILITIES_V7_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
16331#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
16332#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MAC_SECURITY_FILTERING_LBN 12
16333#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
16334#define MC_CMD_GET_CAPABILITIES_V7_OUT_ADDITIONAL_RSS_MODES_OFST 0
16335#define MC_CMD_GET_CAPABILITIES_V7_OUT_ADDITIONAL_RSS_MODES_LBN 13
16336#define MC_CMD_GET_CAPABILITIES_V7_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
16337#define MC_CMD_GET_CAPABILITIES_V7_OUT_QBB_OFST 0
16338#define MC_CMD_GET_CAPABILITIES_V7_OUT_QBB_LBN 14
16339#define MC_CMD_GET_CAPABILITIES_V7_OUT_QBB_WIDTH 1
16340#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
16341#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15
16342#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
16343#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_RSS_LIMITED_OFST 0
16344#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_RSS_LIMITED_LBN 16
16345#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_RSS_LIMITED_WIDTH 1
16346#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PACKED_STREAM_OFST 0
16347#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PACKED_STREAM_LBN 17
16348#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PACKED_STREAM_WIDTH 1
16349#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_INCLUDE_FCS_OFST 0
16350#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_INCLUDE_FCS_LBN 18
16351#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_INCLUDE_FCS_WIDTH 1
16352#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_VLAN_INSERTION_OFST 0
16353#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_VLAN_INSERTION_LBN 19
16354#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_VLAN_INSERTION_WIDTH 1
16355#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_VLAN_STRIPPING_OFST 0
16356#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_VLAN_STRIPPING_LBN 20
16357#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_VLAN_STRIPPING_WIDTH 1
16358#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_OFST 0
16359#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_LBN 21
16360#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_WIDTH 1
16361#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PREFIX_LEN_0_OFST 0
16362#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PREFIX_LEN_0_LBN 22
16363#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PREFIX_LEN_0_WIDTH 1
16364#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PREFIX_LEN_14_OFST 0
16365#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PREFIX_LEN_14_LBN 23
16366#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PREFIX_LEN_14_WIDTH 1
16367#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_TIMESTAMP_OFST 0
16368#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_TIMESTAMP_LBN 24
16369#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_TIMESTAMP_WIDTH 1
16370#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_BATCHING_OFST 0
16371#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_BATCHING_LBN 25
16372#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_BATCHING_WIDTH 1
16373#define MC_CMD_GET_CAPABILITIES_V7_OUT_MCAST_FILTER_CHAINING_OFST 0
16374#define MC_CMD_GET_CAPABILITIES_V7_OUT_MCAST_FILTER_CHAINING_LBN 26
16375#define MC_CMD_GET_CAPABILITIES_V7_OUT_MCAST_FILTER_CHAINING_WIDTH 1
16376#define MC_CMD_GET_CAPABILITIES_V7_OUT_PM_AND_RXDP_COUNTERS_OFST 0
16377#define MC_CMD_GET_CAPABILITIES_V7_OUT_PM_AND_RXDP_COUNTERS_LBN 27
16378#define MC_CMD_GET_CAPABILITIES_V7_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
16379#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_DISABLE_SCATTER_OFST 0
16380#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_DISABLE_SCATTER_LBN 28
16381#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_DISABLE_SCATTER_WIDTH 1
16382#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
16383#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29
16384#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
16385#define MC_CMD_GET_CAPABILITIES_V7_OUT_EVB_OFST 0
16386#define MC_CMD_GET_CAPABILITIES_V7_OUT_EVB_LBN 30
16387#define MC_CMD_GET_CAPABILITIES_V7_OUT_EVB_WIDTH 1
16388#define MC_CMD_GET_CAPABILITIES_V7_OUT_VXLAN_NVGRE_OFST 0
16389#define MC_CMD_GET_CAPABILITIES_V7_OUT_VXLAN_NVGRE_LBN 31
16390#define MC_CMD_GET_CAPABILITIES_V7_OUT_VXLAN_NVGRE_WIDTH 1
16391/* RxDPCPU firmware id. */
16392#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_DPCPU_FW_ID_OFST 4
16393#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_DPCPU_FW_ID_LEN 2
16394/* enum: Standard RXDP firmware */
16395#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP 0x0
16396/* enum: Low latency RXDP firmware */
16397#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_LOW_LATENCY 0x1
16398/* enum: Packed stream RXDP firmware */
16399#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_PACKED_STREAM 0x2
16400/* enum: Rules engine RXDP firmware */
16401#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_RULES_ENGINE 0x5
16402/* enum: DPDK RXDP firmware */
16403#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_DPDK 0x6
16404/* enum: BIST RXDP firmware */
16405#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_BIST 0x10a
16406/* enum: RXDP Test firmware image 1 */
16407#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
16408/* enum: RXDP Test firmware image 2 */
16409#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
16410/* enum: RXDP Test firmware image 3 */
16411#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
16412/* enum: RXDP Test firmware image 4 */
16413#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
16414/* enum: RXDP Test firmware image 5 */
16415#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_BACKPRESSURE 0x105
16416/* enum: RXDP Test firmware image 6 */
16417#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
16418/* enum: RXDP Test firmware image 7 */
16419#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
16420/* enum: RXDP Test firmware image 8 */
16421#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
16422/* enum: RXDP Test firmware image 9 */
16423#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
16424/* enum: RXDP Test firmware image 10 */
16425#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_SLOW 0x10c
16426/* TxDPCPU firmware id. */
16427#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_DPCPU_FW_ID_OFST 6
16428#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_DPCPU_FW_ID_LEN 2
16429/* enum: Standard TXDP firmware */
16430#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP 0x0
16431/* enum: Low latency TXDP firmware */
16432#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_LOW_LATENCY 0x1
16433/* enum: High packet rate TXDP firmware */
16434#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_HIGH_PACKET_RATE 0x3
16435/* enum: Rules engine TXDP firmware */
16436#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_RULES_ENGINE 0x5
16437/* enum: DPDK TXDP firmware */
16438#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_DPDK 0x6
16439/* enum: BIST TXDP firmware */
16440#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_BIST 0x12d
16441/* enum: TXDP Test firmware image 1 */
16442#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
16443/* enum: TXDP Test firmware image 2 */
16444#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
16445/* enum: TXDP CSR bus test firmware */
16446#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_TEST_FW_CSR 0x103
16447#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_VERSION_OFST 8
16448#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_VERSION_LEN 2
16449#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_VERSION_REV_OFST 8
16450#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_VERSION_REV_LBN 0
16451#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_VERSION_REV_WIDTH 12
16452#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_VERSION_TYPE_OFST 8
16453#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_VERSION_TYPE_LBN 12
16454#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
16455/* enum: reserved value - do not use (may indicate alternative interpretation
16456 * of REV field in future)
16457 */
16458#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_RESERVED 0x0
16459/* enum: Trivial RX PD firmware for early Huntington development (Huntington
16460 * development only)
16461 */
16462#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
16463/* enum: RX PD firmware for telemetry prototyping (Medford2 development only)
16464 */
16465#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
16466/* enum: RX PD firmware with approximately Siena-compatible behaviour
16467 * (Huntington development only)
16468 */
16469#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
16470/* enum: Full featured RX PD production firmware */
16471#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
16472/* enum: (deprecated original name for the FULL_FEATURED variant) */
16473#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_VSWITCH 0x3
16474/* enum: siena_compat variant RX PD firmware using PM rather than MAC
16475 * (Huntington development only)
16476 */
16477#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
16478/* enum: Low latency RX PD production firmware */
16479#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
16480/* enum: Packed stream RX PD production firmware */
16481#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
16482/* enum: RX PD firmware handling layer 2 only for high packet rate performance
16483 * tests (Medford development only)
16484 */
16485#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
16486/* enum: Rules engine RX PD production firmware */
16487#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
16488/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
16489#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_L3XUDP 0x9
16490/* enum: DPDK RX PD production firmware */
16491#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_DPDK 0xa
16492/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
16493#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
16494/* enum: RX PD firmware parsing but not filtering network overlay tunnel
16495 * encapsulations (Medford development only)
16496 */
16497#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
16498#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_VERSION_OFST 10
16499#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_VERSION_LEN 2
16500#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_VERSION_REV_OFST 10
16501#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_VERSION_REV_LBN 0
16502#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_VERSION_REV_WIDTH 12
16503#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_VERSION_TYPE_OFST 10
16504#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_VERSION_TYPE_LBN 12
16505#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
16506/* enum: reserved value - do not use (may indicate alternative interpretation
16507 * of REV field in future)
16508 */
16509#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_RESERVED 0x0
16510/* enum: Trivial TX PD firmware for early Huntington development (Huntington
16511 * development only)
16512 */
16513#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
16514/* enum: TX PD firmware for telemetry prototyping (Medford2 development only)
16515 */
16516#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
16517/* enum: TX PD firmware with approximately Siena-compatible behaviour
16518 * (Huntington development only)
16519 */
16520#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
16521/* enum: Full featured TX PD production firmware */
16522#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
16523/* enum: (deprecated original name for the FULL_FEATURED variant) */
16524#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_VSWITCH 0x3
16525/* enum: siena_compat variant TX PD firmware using PM rather than MAC
16526 * (Huntington development only)
16527 */
16528#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
16529#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
16530/* enum: TX PD firmware handling layer 2 only for high packet rate performance
16531 * tests (Medford development only)
16532 */
16533#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
16534/* enum: Rules engine TX PD production firmware */
16535#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
16536/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
16537#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_L3XUDP 0x9
16538/* enum: DPDK TX PD production firmware */
16539#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_DPDK 0xa
16540/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
16541#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
16542/* Hardware capabilities of NIC */
16543#define MC_CMD_GET_CAPABILITIES_V7_OUT_HW_CAPABILITIES_OFST 12
16544#define MC_CMD_GET_CAPABILITIES_V7_OUT_HW_CAPABILITIES_LEN 4
16545/* Licensed capabilities */
16546#define MC_CMD_GET_CAPABILITIES_V7_OUT_LICENSE_CAPABILITIES_OFST 16
16547#define MC_CMD_GET_CAPABILITIES_V7_OUT_LICENSE_CAPABILITIES_LEN 4
16548/* Second word of flags. Not present on older firmware (check the length). */
16549#define MC_CMD_GET_CAPABILITIES_V7_OUT_FLAGS2_OFST 20
16550#define MC_CMD_GET_CAPABILITIES_V7_OUT_FLAGS2_LEN 4
16551#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V2_OFST 20
16552#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V2_LBN 0
16553#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V2_WIDTH 1
16554#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V2_ENCAP_OFST 20
16555#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V2_ENCAP_LBN 1
16556#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V2_ENCAP_WIDTH 1
16557#define MC_CMD_GET_CAPABILITIES_V7_OUT_EVQ_TIMER_CTRL_OFST 20
16558#define MC_CMD_GET_CAPABILITIES_V7_OUT_EVQ_TIMER_CTRL_LBN 2
16559#define MC_CMD_GET_CAPABILITIES_V7_OUT_EVQ_TIMER_CTRL_WIDTH 1
16560#define MC_CMD_GET_CAPABILITIES_V7_OUT_EVENT_CUT_THROUGH_OFST 20
16561#define MC_CMD_GET_CAPABILITIES_V7_OUT_EVENT_CUT_THROUGH_LBN 3
16562#define MC_CMD_GET_CAPABILITIES_V7_OUT_EVENT_CUT_THROUGH_WIDTH 1
16563#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_CUT_THROUGH_OFST 20
16564#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_CUT_THROUGH_LBN 4
16565#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_CUT_THROUGH_WIDTH 1
16566#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_VFIFO_ULL_MODE_OFST 20
16567#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_VFIFO_ULL_MODE_LBN 5
16568#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_VFIFO_ULL_MODE_WIDTH 1
16569#define MC_CMD_GET_CAPABILITIES_V7_OUT_MAC_STATS_40G_TX_SIZE_BINS_OFST 20
16570#define MC_CMD_GET_CAPABILITIES_V7_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6
16571#define MC_CMD_GET_CAPABILITIES_V7_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1
16572#define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_EVQ_TYPE_SUPPORTED_OFST 20
16573#define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_EVQ_TYPE_SUPPORTED_LBN 7
16574#define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 1
16575#define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_EVQ_V2_OFST 20
16576#define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_EVQ_V2_LBN 7
16577#define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_EVQ_V2_WIDTH 1
16578#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MAC_TIMESTAMPING_OFST 20
16579#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MAC_TIMESTAMPING_LBN 8
16580#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MAC_TIMESTAMPING_WIDTH 1
16581#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TIMESTAMP_OFST 20
16582#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TIMESTAMP_LBN 9
16583#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TIMESTAMP_WIDTH 1
16584#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_SNIFF_OFST 20
16585#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_SNIFF_LBN 10
16586#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_SNIFF_WIDTH 1
16587#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_SNIFF_OFST 20
16588#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_SNIFF_LBN 11
16589#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_SNIFF_WIDTH 1
16590#define MC_CMD_GET_CAPABILITIES_V7_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_OFST 20
16591#define MC_CMD_GET_CAPABILITIES_V7_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12
16592#define MC_CMD_GET_CAPABILITIES_V7_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1
16593#define MC_CMD_GET_CAPABILITIES_V7_OUT_MCDI_BACKGROUND_OFST 20
16594#define MC_CMD_GET_CAPABILITIES_V7_OUT_MCDI_BACKGROUND_LBN 13
16595#define MC_CMD_GET_CAPABILITIES_V7_OUT_MCDI_BACKGROUND_WIDTH 1
16596#define MC_CMD_GET_CAPABILITIES_V7_OUT_MCDI_DB_RETURN_OFST 20
16597#define MC_CMD_GET_CAPABILITIES_V7_OUT_MCDI_DB_RETURN_LBN 14
16598#define MC_CMD_GET_CAPABILITIES_V7_OUT_MCDI_DB_RETURN_WIDTH 1
16599#define MC_CMD_GET_CAPABILITIES_V7_OUT_CTPIO_OFST 20
16600#define MC_CMD_GET_CAPABILITIES_V7_OUT_CTPIO_LBN 15
16601#define MC_CMD_GET_CAPABILITIES_V7_OUT_CTPIO_WIDTH 1
16602#define MC_CMD_GET_CAPABILITIES_V7_OUT_TSA_SUPPORT_OFST 20
16603#define MC_CMD_GET_CAPABILITIES_V7_OUT_TSA_SUPPORT_LBN 16
16604#define MC_CMD_GET_CAPABILITIES_V7_OUT_TSA_SUPPORT_WIDTH 1
16605#define MC_CMD_GET_CAPABILITIES_V7_OUT_TSA_BOUND_OFST 20
16606#define MC_CMD_GET_CAPABILITIES_V7_OUT_TSA_BOUND_LBN 17
16607#define MC_CMD_GET_CAPABILITIES_V7_OUT_TSA_BOUND_WIDTH 1
16608#define MC_CMD_GET_CAPABILITIES_V7_OUT_SF_ADAPTER_AUTHENTICATION_OFST 20
16609#define MC_CMD_GET_CAPABILITIES_V7_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18
16610#define MC_CMD_GET_CAPABILITIES_V7_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1
16611#define MC_CMD_GET_CAPABILITIES_V7_OUT_FILTER_ACTION_FLAG_OFST 20
16612#define MC_CMD_GET_CAPABILITIES_V7_OUT_FILTER_ACTION_FLAG_LBN 19
16613#define MC_CMD_GET_CAPABILITIES_V7_OUT_FILTER_ACTION_FLAG_WIDTH 1
16614#define MC_CMD_GET_CAPABILITIES_V7_OUT_FILTER_ACTION_MARK_OFST 20
16615#define MC_CMD_GET_CAPABILITIES_V7_OUT_FILTER_ACTION_MARK_LBN 20
16616#define MC_CMD_GET_CAPABILITIES_V7_OUT_FILTER_ACTION_MARK_WIDTH 1
16617#define MC_CMD_GET_CAPABILITIES_V7_OUT_EQUAL_STRIDE_SUPER_BUFFER_OFST 20
16618#define MC_CMD_GET_CAPABILITIES_V7_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 21
16619#define MC_CMD_GET_CAPABILITIES_V7_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1
16620#define MC_CMD_GET_CAPABILITIES_V7_OUT_EQUAL_STRIDE_PACKED_STREAM_OFST 20
16621#define MC_CMD_GET_CAPABILITIES_V7_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21
16622#define MC_CMD_GET_CAPABILITIES_V7_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1
16623#define MC_CMD_GET_CAPABILITIES_V7_OUT_L3XUDP_SUPPORT_OFST 20
16624#define MC_CMD_GET_CAPABILITIES_V7_OUT_L3XUDP_SUPPORT_LBN 22
16625#define MC_CMD_GET_CAPABILITIES_V7_OUT_L3XUDP_SUPPORT_WIDTH 1
16626#define MC_CMD_GET_CAPABILITIES_V7_OUT_FW_SUBVARIANT_NO_TX_CSUM_OFST 20
16627#define MC_CMD_GET_CAPABILITIES_V7_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23
16628#define MC_CMD_GET_CAPABILITIES_V7_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1
16629#define MC_CMD_GET_CAPABILITIES_V7_OUT_VI_SPREADING_OFST 20
16630#define MC_CMD_GET_CAPABILITIES_V7_OUT_VI_SPREADING_LBN 24
16631#define MC_CMD_GET_CAPABILITIES_V7_OUT_VI_SPREADING_WIDTH 1
16632#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_HLB_IDLE_OFST 20
16633#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_HLB_IDLE_LBN 25
16634#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_HLB_IDLE_WIDTH 1
16635#define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_RXQ_NO_CONT_EV_OFST 20
16636#define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_RXQ_NO_CONT_EV_LBN 26
16637#define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1
16638#define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_RXQ_WITH_BUFFER_SIZE_OFST 20
16639#define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 27
16640#define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1
16641#define MC_CMD_GET_CAPABILITIES_V7_OUT_BUNDLE_UPDATE_OFST 20
16642#define MC_CMD_GET_CAPABILITIES_V7_OUT_BUNDLE_UPDATE_LBN 28
16643#define MC_CMD_GET_CAPABILITIES_V7_OUT_BUNDLE_UPDATE_WIDTH 1
16644#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V3_OFST 20
16645#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V3_LBN 29
16646#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V3_WIDTH 1
16647#define MC_CMD_GET_CAPABILITIES_V7_OUT_DYNAMIC_SENSORS_OFST 20
16648#define MC_CMD_GET_CAPABILITIES_V7_OUT_DYNAMIC_SENSORS_LBN 30
16649#define MC_CMD_GET_CAPABILITIES_V7_OUT_DYNAMIC_SENSORS_WIDTH 1
16650#define MC_CMD_GET_CAPABILITIES_V7_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_OFST 20
16651#define MC_CMD_GET_CAPABILITIES_V7_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 31
16652#define MC_CMD_GET_CAPABILITIES_V7_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1
16653/* Number of FATSOv2 contexts per datapath supported by this NIC (when
16654 * TX_TSO_V2 == 1). Not present on older firmware (check the length).
16655 */
16656#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24
16657#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2
16658/* One byte per PF containing the number of the external port assigned to this
16659 * PF, indexed by PF number. Special values indicate that a PF is either not
16660 * present or not assigned.
16661 */
16662#define MC_CMD_GET_CAPABILITIES_V7_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26
16663#define MC_CMD_GET_CAPABILITIES_V7_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1
16664#define MC_CMD_GET_CAPABILITIES_V7_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16
16665/* enum: The caller is not permitted to access information on this PF. */
16666#define MC_CMD_GET_CAPABILITIES_V7_OUT_ACCESS_NOT_PERMITTED 0xff
16667/* enum: PF does not exist. */
16668#define MC_CMD_GET_CAPABILITIES_V7_OUT_PF_NOT_PRESENT 0xfe
16669/* enum: PF does exist but is not assigned to any external port. */
16670#define MC_CMD_GET_CAPABILITIES_V7_OUT_PF_NOT_ASSIGNED 0xfd
16671/* enum: This value indicates that PF is assigned, but it cannot be expressed
16672 * in this field. It is intended for a possible future situation where a more
16673 * complex scheme of PFs to ports mapping is being used. The future driver
16674 * should look for a new field supporting the new scheme. The current/old
16675 * driver should treat this value as PF_NOT_ASSIGNED.
16676 */
16677#define MC_CMD_GET_CAPABILITIES_V7_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
16678/* One byte per PF containing the number of its VFs, indexed by PF number. A
16679 * special value indicates that a PF is not present.
16680 */
16681#define MC_CMD_GET_CAPABILITIES_V7_OUT_NUM_VFS_PER_PF_OFST 42
16682#define MC_CMD_GET_CAPABILITIES_V7_OUT_NUM_VFS_PER_PF_LEN 1
16683#define MC_CMD_GET_CAPABILITIES_V7_OUT_NUM_VFS_PER_PF_NUM 16
16684/* enum: The caller is not permitted to access information on this PF. */
16685/* MC_CMD_GET_CAPABILITIES_V7_OUT_ACCESS_NOT_PERMITTED 0xff */
16686/* enum: PF does not exist. */
16687/* MC_CMD_GET_CAPABILITIES_V7_OUT_PF_NOT_PRESENT 0xfe */
16688/* Number of VIs available for each external port */
16689#define MC_CMD_GET_CAPABILITIES_V7_OUT_NUM_VIS_PER_PORT_OFST 58
16690#define MC_CMD_GET_CAPABILITIES_V7_OUT_NUM_VIS_PER_PORT_LEN 2
16691#define MC_CMD_GET_CAPABILITIES_V7_OUT_NUM_VIS_PER_PORT_NUM 4
16692/* Size of RX descriptor cache expressed as binary logarithm The actual size
16693 * equals (2 ^ RX_DESC_CACHE_SIZE)
16694 */
16695#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_DESC_CACHE_SIZE_OFST 66
16696#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_DESC_CACHE_SIZE_LEN 1
16697/* Size of TX descriptor cache expressed as binary logarithm The actual size
16698 * equals (2 ^ TX_DESC_CACHE_SIZE)
16699 */
16700#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_DESC_CACHE_SIZE_OFST 67
16701#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_DESC_CACHE_SIZE_LEN 1
16702/* Total number of available PIO buffers */
16703#define MC_CMD_GET_CAPABILITIES_V7_OUT_NUM_PIO_BUFFS_OFST 68
16704#define MC_CMD_GET_CAPABILITIES_V7_OUT_NUM_PIO_BUFFS_LEN 2
16705/* Size of a single PIO buffer */
16706#define MC_CMD_GET_CAPABILITIES_V7_OUT_SIZE_PIO_BUFF_OFST 70
16707#define MC_CMD_GET_CAPABILITIES_V7_OUT_SIZE_PIO_BUFF_LEN 2
16708/* On chips later than Medford the amount of address space assigned to each VI
16709 * is configurable. This is a global setting that the driver must query to
16710 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
16711 * with 8k VI windows.
16712 */
16713#define MC_CMD_GET_CAPABILITIES_V7_OUT_VI_WINDOW_MODE_OFST 72
16714#define MC_CMD_GET_CAPABILITIES_V7_OUT_VI_WINDOW_MODE_LEN 1
16715/* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
16716 * CTPIO is not mapped.
16717 */
16718#define MC_CMD_GET_CAPABILITIES_V7_OUT_VI_WINDOW_MODE_8K 0x0
16719/* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
16720#define MC_CMD_GET_CAPABILITIES_V7_OUT_VI_WINDOW_MODE_16K 0x1
16721/* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
16722#define MC_CMD_GET_CAPABILITIES_V7_OUT_VI_WINDOW_MODE_64K 0x2
16723/* Number of vFIFOs per adapter that can be used for VFIFO Stuffing
16724 * (SF-115995-SW) in the present configuration of firmware and port mode.
16725 */
16726#define MC_CMD_GET_CAPABILITIES_V7_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 73
16727#define MC_CMD_GET_CAPABILITIES_V7_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1
16728/* Number of buffers per adapter that can be used for VFIFO Stuffing
16729 * (SF-115995-SW) in the present configuration of firmware and port mode.
16730 */
16731#define MC_CMD_GET_CAPABILITIES_V7_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 74
16732#define MC_CMD_GET_CAPABILITIES_V7_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 2
16733/* Entry count in the MAC stats array, including the final GENERATION_END
16734 * entry. For MAC stats DMA, drivers should allocate a buffer large enough to
16735 * hold at least this many 64-bit stats values, if they wish to receive all
16736 * available stats. If the buffer is shorter than MAC_STATS_NUM_STATS * 8, the
16737 * stats array returned will be truncated.
16738 */
16739#define MC_CMD_GET_CAPABILITIES_V7_OUT_MAC_STATS_NUM_STATS_OFST 76
16740#define MC_CMD_GET_CAPABILITIES_V7_OUT_MAC_STATS_NUM_STATS_LEN 2
16741/* Maximum supported value for MC_CMD_FILTER_OP_V3/MATCH_MARK_VALUE. This field
16742 * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set.
16743 */
16744#define MC_CMD_GET_CAPABILITIES_V7_OUT_FILTER_ACTION_MARK_MAX_OFST 80
16745#define MC_CMD_GET_CAPABILITIES_V7_OUT_FILTER_ACTION_MARK_MAX_LEN 4
16746/* On devices where the INIT_RXQ_WITH_BUFFER_SIZE flag (in
16747 * GET_CAPABILITIES_OUT_V2) is set, drivers have to specify a buffer size when
16748 * they create an RX queue. Due to hardware limitations, only a small number of
16749 * different buffer sizes may be available concurrently. Nonzero entries in
16750 * this array are the sizes of buffers which the system guarantees will be
16751 * available for use. If the list is empty, there are no limitations on
16752 * concurrent buffer sizes.
16753 */
16754#define MC_CMD_GET_CAPABILITIES_V7_OUT_GUARANTEED_RX_BUFFER_SIZES_OFST 84
16755#define MC_CMD_GET_CAPABILITIES_V7_OUT_GUARANTEED_RX_BUFFER_SIZES_LEN 4
16756#define MC_CMD_GET_CAPABILITIES_V7_OUT_GUARANTEED_RX_BUFFER_SIZES_NUM 16
16757/* Third word of flags. Not present on older firmware (check the length). */
16758#define MC_CMD_GET_CAPABILITIES_V7_OUT_FLAGS3_OFST 148
16759#define MC_CMD_GET_CAPABILITIES_V7_OUT_FLAGS3_LEN 4
16760#define MC_CMD_GET_CAPABILITIES_V7_OUT_WOL_ETHERWAKE_OFST 148
16761#define MC_CMD_GET_CAPABILITIES_V7_OUT_WOL_ETHERWAKE_LBN 0
16762#define MC_CMD_GET_CAPABILITIES_V7_OUT_WOL_ETHERWAKE_WIDTH 1
16763#define MC_CMD_GET_CAPABILITIES_V7_OUT_RSS_EVEN_SPREADING_OFST 148
16764#define MC_CMD_GET_CAPABILITIES_V7_OUT_RSS_EVEN_SPREADING_LBN 1
16765#define MC_CMD_GET_CAPABILITIES_V7_OUT_RSS_EVEN_SPREADING_WIDTH 1
16766#define MC_CMD_GET_CAPABILITIES_V7_OUT_RSS_SELECTABLE_TABLE_SIZE_OFST 148
16767#define MC_CMD_GET_CAPABILITIES_V7_OUT_RSS_SELECTABLE_TABLE_SIZE_LBN 2
16768#define MC_CMD_GET_CAPABILITIES_V7_OUT_RSS_SELECTABLE_TABLE_SIZE_WIDTH 1
16769#define MC_CMD_GET_CAPABILITIES_V7_OUT_MAE_SUPPORTED_OFST 148
16770#define MC_CMD_GET_CAPABILITIES_V7_OUT_MAE_SUPPORTED_LBN 3
16771#define MC_CMD_GET_CAPABILITIES_V7_OUT_MAE_SUPPORTED_WIDTH 1
16772#define MC_CMD_GET_CAPABILITIES_V7_OUT_VDPA_SUPPORTED_OFST 148
16773#define MC_CMD_GET_CAPABILITIES_V7_OUT_VDPA_SUPPORTED_LBN 4
16774#define MC_CMD_GET_CAPABILITIES_V7_OUT_VDPA_SUPPORTED_WIDTH 1
16775#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_OFST 148
16776#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_LBN 5
16777#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_WIDTH 1
16778#define MC_CMD_GET_CAPABILITIES_V7_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_OFST 148
16779#define MC_CMD_GET_CAPABILITIES_V7_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_LBN 6
16780#define MC_CMD_GET_CAPABILITIES_V7_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_WIDTH 1
16781#define MC_CMD_GET_CAPABILITIES_V7_OUT_UNSOL_EV_CREDIT_SUPPORTED_OFST 148
16782#define MC_CMD_GET_CAPABILITIES_V7_OUT_UNSOL_EV_CREDIT_SUPPORTED_LBN 7
16783#define MC_CMD_GET_CAPABILITIES_V7_OUT_UNSOL_EV_CREDIT_SUPPORTED_WIDTH 1
16784#define MC_CMD_GET_CAPABILITIES_V7_OUT_ENCAPSULATED_MCDI_SUPPORTED_OFST 148
16785#define MC_CMD_GET_CAPABILITIES_V7_OUT_ENCAPSULATED_MCDI_SUPPORTED_LBN 8
16786#define MC_CMD_GET_CAPABILITIES_V7_OUT_ENCAPSULATED_MCDI_SUPPORTED_WIDTH 1
16787#define MC_CMD_GET_CAPABILITIES_V7_OUT_EXTERNAL_MAE_SUPPORTED_OFST 148
16788#define MC_CMD_GET_CAPABILITIES_V7_OUT_EXTERNAL_MAE_SUPPORTED_LBN 9
16789#define MC_CMD_GET_CAPABILITIES_V7_OUT_EXTERNAL_MAE_SUPPORTED_WIDTH 1
16790#define MC_CMD_GET_CAPABILITIES_V7_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_OFST 148
16791#define MC_CMD_GET_CAPABILITIES_V7_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_LBN 10
16792#define MC_CMD_GET_CAPABILITIES_V7_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_WIDTH 1
16793#define MC_CMD_GET_CAPABILITIES_V7_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_OFST 148
16794#define MC_CMD_GET_CAPABILITIES_V7_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_LBN 11
16795#define MC_CMD_GET_CAPABILITIES_V7_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_WIDTH 1
16796#define MC_CMD_GET_CAPABILITIES_V7_OUT_RSS_STEER_ON_OUTER_SUPPORTED_OFST 148
16797#define MC_CMD_GET_CAPABILITIES_V7_OUT_RSS_STEER_ON_OUTER_SUPPORTED_LBN 12
16798#define MC_CMD_GET_CAPABILITIES_V7_OUT_RSS_STEER_ON_OUTER_SUPPORTED_WIDTH 1
16799#define MC_CMD_GET_CAPABILITIES_V7_OUT_DYNAMIC_MPORT_JOURNAL_OFST 148
16800#define MC_CMD_GET_CAPABILITIES_V7_OUT_DYNAMIC_MPORT_JOURNAL_LBN 14
16801#define MC_CMD_GET_CAPABILITIES_V7_OUT_DYNAMIC_MPORT_JOURNAL_WIDTH 1
16802
16803/* MC_CMD_GET_CAPABILITIES_V8_OUT msgresponse */
16804#define MC_CMD_GET_CAPABILITIES_V8_OUT_LEN 160
16805/* First word of flags. */
16806#define MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS1_OFST 0
16807#define MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS1_LEN 4
16808#define MC_CMD_GET_CAPABILITIES_V8_OUT_VPORT_RECONFIGURE_OFST 0
16809#define MC_CMD_GET_CAPABILITIES_V8_OUT_VPORT_RECONFIGURE_LBN 3
16810#define MC_CMD_GET_CAPABILITIES_V8_OUT_VPORT_RECONFIGURE_WIDTH 1
16811#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_STRIPING_OFST 0
16812#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_STRIPING_LBN 4
16813#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_STRIPING_WIDTH 1
16814#define MC_CMD_GET_CAPABILITIES_V8_OUT_VADAPTOR_QUERY_OFST 0
16815#define MC_CMD_GET_CAPABILITIES_V8_OUT_VADAPTOR_QUERY_LBN 5
16816#define MC_CMD_GET_CAPABILITIES_V8_OUT_VADAPTOR_QUERY_WIDTH 1
16817#define MC_CMD_GET_CAPABILITIES_V8_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
16818#define MC_CMD_GET_CAPABILITIES_V8_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6
16819#define MC_CMD_GET_CAPABILITIES_V8_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
16820#define MC_CMD_GET_CAPABILITIES_V8_OUT_DRV_ATTACH_PREBOOT_OFST 0
16821#define MC_CMD_GET_CAPABILITIES_V8_OUT_DRV_ATTACH_PREBOOT_LBN 7
16822#define MC_CMD_GET_CAPABILITIES_V8_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
16823#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_FORCE_EVENT_MERGING_OFST 0
16824#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_FORCE_EVENT_MERGING_LBN 8
16825#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
16826#define MC_CMD_GET_CAPABILITIES_V8_OUT_SET_MAC_ENHANCED_OFST 0
16827#define MC_CMD_GET_CAPABILITIES_V8_OUT_SET_MAC_ENHANCED_LBN 9
16828#define MC_CMD_GET_CAPABILITIES_V8_OUT_SET_MAC_ENHANCED_WIDTH 1
16829#define MC_CMD_GET_CAPABILITIES_V8_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
16830#define MC_CMD_GET_CAPABILITIES_V8_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10
16831#define MC_CMD_GET_CAPABILITIES_V8_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
16832#define MC_CMD_GET_CAPABILITIES_V8_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
16833#define MC_CMD_GET_CAPABILITIES_V8_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11
16834#define MC_CMD_GET_CAPABILITIES_V8_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
16835#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
16836#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MAC_SECURITY_FILTERING_LBN 12
16837#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
16838#define MC_CMD_GET_CAPABILITIES_V8_OUT_ADDITIONAL_RSS_MODES_OFST 0
16839#define MC_CMD_GET_CAPABILITIES_V8_OUT_ADDITIONAL_RSS_MODES_LBN 13
16840#define MC_CMD_GET_CAPABILITIES_V8_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
16841#define MC_CMD_GET_CAPABILITIES_V8_OUT_QBB_OFST 0
16842#define MC_CMD_GET_CAPABILITIES_V8_OUT_QBB_LBN 14
16843#define MC_CMD_GET_CAPABILITIES_V8_OUT_QBB_WIDTH 1
16844#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
16845#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15
16846#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
16847#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_RSS_LIMITED_OFST 0
16848#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_RSS_LIMITED_LBN 16
16849#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_RSS_LIMITED_WIDTH 1
16850#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PACKED_STREAM_OFST 0
16851#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PACKED_STREAM_LBN 17
16852#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PACKED_STREAM_WIDTH 1
16853#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_INCLUDE_FCS_OFST 0
16854#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_INCLUDE_FCS_LBN 18
16855#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_INCLUDE_FCS_WIDTH 1
16856#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_VLAN_INSERTION_OFST 0
16857#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_VLAN_INSERTION_LBN 19
16858#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_VLAN_INSERTION_WIDTH 1
16859#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_VLAN_STRIPPING_OFST 0
16860#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_VLAN_STRIPPING_LBN 20
16861#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_VLAN_STRIPPING_WIDTH 1
16862#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_OFST 0
16863#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_LBN 21
16864#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_WIDTH 1
16865#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PREFIX_LEN_0_OFST 0
16866#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PREFIX_LEN_0_LBN 22
16867#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PREFIX_LEN_0_WIDTH 1
16868#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PREFIX_LEN_14_OFST 0
16869#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PREFIX_LEN_14_LBN 23
16870#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PREFIX_LEN_14_WIDTH 1
16871#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_TIMESTAMP_OFST 0
16872#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_TIMESTAMP_LBN 24
16873#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_TIMESTAMP_WIDTH 1
16874#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_BATCHING_OFST 0
16875#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_BATCHING_LBN 25
16876#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_BATCHING_WIDTH 1
16877#define MC_CMD_GET_CAPABILITIES_V8_OUT_MCAST_FILTER_CHAINING_OFST 0
16878#define MC_CMD_GET_CAPABILITIES_V8_OUT_MCAST_FILTER_CHAINING_LBN 26
16879#define MC_CMD_GET_CAPABILITIES_V8_OUT_MCAST_FILTER_CHAINING_WIDTH 1
16880#define MC_CMD_GET_CAPABILITIES_V8_OUT_PM_AND_RXDP_COUNTERS_OFST 0
16881#define MC_CMD_GET_CAPABILITIES_V8_OUT_PM_AND_RXDP_COUNTERS_LBN 27
16882#define MC_CMD_GET_CAPABILITIES_V8_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
16883#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_DISABLE_SCATTER_OFST 0
16884#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_DISABLE_SCATTER_LBN 28
16885#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_DISABLE_SCATTER_WIDTH 1
16886#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
16887#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29
16888#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
16889#define MC_CMD_GET_CAPABILITIES_V8_OUT_EVB_OFST 0
16890#define MC_CMD_GET_CAPABILITIES_V8_OUT_EVB_LBN 30
16891#define MC_CMD_GET_CAPABILITIES_V8_OUT_EVB_WIDTH 1
16892#define MC_CMD_GET_CAPABILITIES_V8_OUT_VXLAN_NVGRE_OFST 0
16893#define MC_CMD_GET_CAPABILITIES_V8_OUT_VXLAN_NVGRE_LBN 31
16894#define MC_CMD_GET_CAPABILITIES_V8_OUT_VXLAN_NVGRE_WIDTH 1
16895/* RxDPCPU firmware id. */
16896#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_DPCPU_FW_ID_OFST 4
16897#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_DPCPU_FW_ID_LEN 2
16898/* enum: Standard RXDP firmware */
16899#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP 0x0
16900/* enum: Low latency RXDP firmware */
16901#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_LOW_LATENCY 0x1
16902/* enum: Packed stream RXDP firmware */
16903#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_PACKED_STREAM 0x2
16904/* enum: Rules engine RXDP firmware */
16905#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_RULES_ENGINE 0x5
16906/* enum: DPDK RXDP firmware */
16907#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_DPDK 0x6
16908/* enum: BIST RXDP firmware */
16909#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_BIST 0x10a
16910/* enum: RXDP Test firmware image 1 */
16911#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
16912/* enum: RXDP Test firmware image 2 */
16913#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
16914/* enum: RXDP Test firmware image 3 */
16915#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
16916/* enum: RXDP Test firmware image 4 */
16917#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
16918/* enum: RXDP Test firmware image 5 */
16919#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_BACKPRESSURE 0x105
16920/* enum: RXDP Test firmware image 6 */
16921#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
16922/* enum: RXDP Test firmware image 7 */
16923#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
16924/* enum: RXDP Test firmware image 8 */
16925#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
16926/* enum: RXDP Test firmware image 9 */
16927#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
16928/* enum: RXDP Test firmware image 10 */
16929#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_SLOW 0x10c
16930/* TxDPCPU firmware id. */
16931#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_DPCPU_FW_ID_OFST 6
16932#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_DPCPU_FW_ID_LEN 2
16933/* enum: Standard TXDP firmware */
16934#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP 0x0
16935/* enum: Low latency TXDP firmware */
16936#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_LOW_LATENCY 0x1
16937/* enum: High packet rate TXDP firmware */
16938#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_HIGH_PACKET_RATE 0x3
16939/* enum: Rules engine TXDP firmware */
16940#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_RULES_ENGINE 0x5
16941/* enum: DPDK TXDP firmware */
16942#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_DPDK 0x6
16943/* enum: BIST TXDP firmware */
16944#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_BIST 0x12d
16945/* enum: TXDP Test firmware image 1 */
16946#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
16947/* enum: TXDP Test firmware image 2 */
16948#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
16949/* enum: TXDP CSR bus test firmware */
16950#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_TEST_FW_CSR 0x103
16951#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_VERSION_OFST 8
16952#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_VERSION_LEN 2
16953#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_VERSION_REV_OFST 8
16954#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_VERSION_REV_LBN 0
16955#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_VERSION_REV_WIDTH 12
16956#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_VERSION_TYPE_OFST 8
16957#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_VERSION_TYPE_LBN 12
16958#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
16959/* enum: reserved value - do not use (may indicate alternative interpretation
16960 * of REV field in future)
16961 */
16962#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_RESERVED 0x0
16963/* enum: Trivial RX PD firmware for early Huntington development (Huntington
16964 * development only)
16965 */
16966#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
16967/* enum: RX PD firmware for telemetry prototyping (Medford2 development only)
16968 */
16969#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
16970/* enum: RX PD firmware with approximately Siena-compatible behaviour
16971 * (Huntington development only)
16972 */
16973#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
16974/* enum: Full featured RX PD production firmware */
16975#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
16976/* enum: (deprecated original name for the FULL_FEATURED variant) */
16977#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_VSWITCH 0x3
16978/* enum: siena_compat variant RX PD firmware using PM rather than MAC
16979 * (Huntington development only)
16980 */
16981#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
16982/* enum: Low latency RX PD production firmware */
16983#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
16984/* enum: Packed stream RX PD production firmware */
16985#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
16986/* enum: RX PD firmware handling layer 2 only for high packet rate performance
16987 * tests (Medford development only)
16988 */
16989#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
16990/* enum: Rules engine RX PD production firmware */
16991#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
16992/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
16993#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_L3XUDP 0x9
16994/* enum: DPDK RX PD production firmware */
16995#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_DPDK 0xa
16996/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
16997#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
16998/* enum: RX PD firmware parsing but not filtering network overlay tunnel
16999 * encapsulations (Medford development only)
17000 */
17001#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
17002#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_VERSION_OFST 10
17003#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_VERSION_LEN 2
17004#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_VERSION_REV_OFST 10
17005#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_VERSION_REV_LBN 0
17006#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_VERSION_REV_WIDTH 12
17007#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_VERSION_TYPE_OFST 10
17008#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_VERSION_TYPE_LBN 12
17009#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
17010/* enum: reserved value - do not use (may indicate alternative interpretation
17011 * of REV field in future)
17012 */
17013#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_RESERVED 0x0
17014/* enum: Trivial TX PD firmware for early Huntington development (Huntington
17015 * development only)
17016 */
17017#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
17018/* enum: TX PD firmware for telemetry prototyping (Medford2 development only)
17019 */
17020#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
17021/* enum: TX PD firmware with approximately Siena-compatible behaviour
17022 * (Huntington development only)
17023 */
17024#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
17025/* enum: Full featured TX PD production firmware */
17026#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
17027/* enum: (deprecated original name for the FULL_FEATURED variant) */
17028#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_VSWITCH 0x3
17029/* enum: siena_compat variant TX PD firmware using PM rather than MAC
17030 * (Huntington development only)
17031 */
17032#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
17033#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
17034/* enum: TX PD firmware handling layer 2 only for high packet rate performance
17035 * tests (Medford development only)
17036 */
17037#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
17038/* enum: Rules engine TX PD production firmware */
17039#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
17040/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
17041#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_L3XUDP 0x9
17042/* enum: DPDK TX PD production firmware */
17043#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_DPDK 0xa
17044/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
17045#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
17046/* Hardware capabilities of NIC */
17047#define MC_CMD_GET_CAPABILITIES_V8_OUT_HW_CAPABILITIES_OFST 12
17048#define MC_CMD_GET_CAPABILITIES_V8_OUT_HW_CAPABILITIES_LEN 4
17049/* Licensed capabilities */
17050#define MC_CMD_GET_CAPABILITIES_V8_OUT_LICENSE_CAPABILITIES_OFST 16
17051#define MC_CMD_GET_CAPABILITIES_V8_OUT_LICENSE_CAPABILITIES_LEN 4
17052/* Second word of flags. Not present on older firmware (check the length). */
17053#define MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS2_OFST 20
17054#define MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS2_LEN 4
17055#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V2_OFST 20
17056#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V2_LBN 0
17057#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V2_WIDTH 1
17058#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V2_ENCAP_OFST 20
17059#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V2_ENCAP_LBN 1
17060#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V2_ENCAP_WIDTH 1
17061#define MC_CMD_GET_CAPABILITIES_V8_OUT_EVQ_TIMER_CTRL_OFST 20
17062#define MC_CMD_GET_CAPABILITIES_V8_OUT_EVQ_TIMER_CTRL_LBN 2
17063#define MC_CMD_GET_CAPABILITIES_V8_OUT_EVQ_TIMER_CTRL_WIDTH 1
17064#define MC_CMD_GET_CAPABILITIES_V8_OUT_EVENT_CUT_THROUGH_OFST 20
17065#define MC_CMD_GET_CAPABILITIES_V8_OUT_EVENT_CUT_THROUGH_LBN 3
17066#define MC_CMD_GET_CAPABILITIES_V8_OUT_EVENT_CUT_THROUGH_WIDTH 1
17067#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_CUT_THROUGH_OFST 20
17068#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_CUT_THROUGH_LBN 4
17069#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_CUT_THROUGH_WIDTH 1
17070#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_VFIFO_ULL_MODE_OFST 20
17071#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_VFIFO_ULL_MODE_LBN 5
17072#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_VFIFO_ULL_MODE_WIDTH 1
17073#define MC_CMD_GET_CAPABILITIES_V8_OUT_MAC_STATS_40G_TX_SIZE_BINS_OFST 20
17074#define MC_CMD_GET_CAPABILITIES_V8_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6
17075#define MC_CMD_GET_CAPABILITIES_V8_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1
17076#define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_EVQ_TYPE_SUPPORTED_OFST 20
17077#define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_EVQ_TYPE_SUPPORTED_LBN 7
17078#define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 1
17079#define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_EVQ_V2_OFST 20
17080#define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_EVQ_V2_LBN 7
17081#define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_EVQ_V2_WIDTH 1
17082#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MAC_TIMESTAMPING_OFST 20
17083#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MAC_TIMESTAMPING_LBN 8
17084#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MAC_TIMESTAMPING_WIDTH 1
17085#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TIMESTAMP_OFST 20
17086#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TIMESTAMP_LBN 9
17087#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TIMESTAMP_WIDTH 1
17088#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_SNIFF_OFST 20
17089#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_SNIFF_LBN 10
17090#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_SNIFF_WIDTH 1
17091#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_SNIFF_OFST 20
17092#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_SNIFF_LBN 11
17093#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_SNIFF_WIDTH 1
17094#define MC_CMD_GET_CAPABILITIES_V8_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_OFST 20
17095#define MC_CMD_GET_CAPABILITIES_V8_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12
17096#define MC_CMD_GET_CAPABILITIES_V8_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1
17097#define MC_CMD_GET_CAPABILITIES_V8_OUT_MCDI_BACKGROUND_OFST 20
17098#define MC_CMD_GET_CAPABILITIES_V8_OUT_MCDI_BACKGROUND_LBN 13
17099#define MC_CMD_GET_CAPABILITIES_V8_OUT_MCDI_BACKGROUND_WIDTH 1
17100#define MC_CMD_GET_CAPABILITIES_V8_OUT_MCDI_DB_RETURN_OFST 20
17101#define MC_CMD_GET_CAPABILITIES_V8_OUT_MCDI_DB_RETURN_LBN 14
17102#define MC_CMD_GET_CAPABILITIES_V8_OUT_MCDI_DB_RETURN_WIDTH 1
17103#define MC_CMD_GET_CAPABILITIES_V8_OUT_CTPIO_OFST 20
17104#define MC_CMD_GET_CAPABILITIES_V8_OUT_CTPIO_LBN 15
17105#define MC_CMD_GET_CAPABILITIES_V8_OUT_CTPIO_WIDTH 1
17106#define MC_CMD_GET_CAPABILITIES_V8_OUT_TSA_SUPPORT_OFST 20
17107#define MC_CMD_GET_CAPABILITIES_V8_OUT_TSA_SUPPORT_LBN 16
17108#define MC_CMD_GET_CAPABILITIES_V8_OUT_TSA_SUPPORT_WIDTH 1
17109#define MC_CMD_GET_CAPABILITIES_V8_OUT_TSA_BOUND_OFST 20
17110#define MC_CMD_GET_CAPABILITIES_V8_OUT_TSA_BOUND_LBN 17
17111#define MC_CMD_GET_CAPABILITIES_V8_OUT_TSA_BOUND_WIDTH 1
17112#define MC_CMD_GET_CAPABILITIES_V8_OUT_SF_ADAPTER_AUTHENTICATION_OFST 20
17113#define MC_CMD_GET_CAPABILITIES_V8_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18
17114#define MC_CMD_GET_CAPABILITIES_V8_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1
17115#define MC_CMD_GET_CAPABILITIES_V8_OUT_FILTER_ACTION_FLAG_OFST 20
17116#define MC_CMD_GET_CAPABILITIES_V8_OUT_FILTER_ACTION_FLAG_LBN 19
17117#define MC_CMD_GET_CAPABILITIES_V8_OUT_FILTER_ACTION_FLAG_WIDTH 1
17118#define MC_CMD_GET_CAPABILITIES_V8_OUT_FILTER_ACTION_MARK_OFST 20
17119#define MC_CMD_GET_CAPABILITIES_V8_OUT_FILTER_ACTION_MARK_LBN 20
17120#define MC_CMD_GET_CAPABILITIES_V8_OUT_FILTER_ACTION_MARK_WIDTH 1
17121#define MC_CMD_GET_CAPABILITIES_V8_OUT_EQUAL_STRIDE_SUPER_BUFFER_OFST 20
17122#define MC_CMD_GET_CAPABILITIES_V8_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 21
17123#define MC_CMD_GET_CAPABILITIES_V8_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1
17124#define MC_CMD_GET_CAPABILITIES_V8_OUT_EQUAL_STRIDE_PACKED_STREAM_OFST 20
17125#define MC_CMD_GET_CAPABILITIES_V8_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21
17126#define MC_CMD_GET_CAPABILITIES_V8_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1
17127#define MC_CMD_GET_CAPABILITIES_V8_OUT_L3XUDP_SUPPORT_OFST 20
17128#define MC_CMD_GET_CAPABILITIES_V8_OUT_L3XUDP_SUPPORT_LBN 22
17129#define MC_CMD_GET_CAPABILITIES_V8_OUT_L3XUDP_SUPPORT_WIDTH 1
17130#define MC_CMD_GET_CAPABILITIES_V8_OUT_FW_SUBVARIANT_NO_TX_CSUM_OFST 20
17131#define MC_CMD_GET_CAPABILITIES_V8_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23
17132#define MC_CMD_GET_CAPABILITIES_V8_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1
17133#define MC_CMD_GET_CAPABILITIES_V8_OUT_VI_SPREADING_OFST 20
17134#define MC_CMD_GET_CAPABILITIES_V8_OUT_VI_SPREADING_LBN 24
17135#define MC_CMD_GET_CAPABILITIES_V8_OUT_VI_SPREADING_WIDTH 1
17136#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_HLB_IDLE_OFST 20
17137#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_HLB_IDLE_LBN 25
17138#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_HLB_IDLE_WIDTH 1
17139#define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_RXQ_NO_CONT_EV_OFST 20
17140#define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_RXQ_NO_CONT_EV_LBN 26
17141#define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1
17142#define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_RXQ_WITH_BUFFER_SIZE_OFST 20
17143#define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 27
17144#define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1
17145#define MC_CMD_GET_CAPABILITIES_V8_OUT_BUNDLE_UPDATE_OFST 20
17146#define MC_CMD_GET_CAPABILITIES_V8_OUT_BUNDLE_UPDATE_LBN 28
17147#define MC_CMD_GET_CAPABILITIES_V8_OUT_BUNDLE_UPDATE_WIDTH 1
17148#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V3_OFST 20
17149#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V3_LBN 29
17150#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V3_WIDTH 1
17151#define MC_CMD_GET_CAPABILITIES_V8_OUT_DYNAMIC_SENSORS_OFST 20
17152#define MC_CMD_GET_CAPABILITIES_V8_OUT_DYNAMIC_SENSORS_LBN 30
17153#define MC_CMD_GET_CAPABILITIES_V8_OUT_DYNAMIC_SENSORS_WIDTH 1
17154#define MC_CMD_GET_CAPABILITIES_V8_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_OFST 20
17155#define MC_CMD_GET_CAPABILITIES_V8_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 31
17156#define MC_CMD_GET_CAPABILITIES_V8_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1
17157/* Number of FATSOv2 contexts per datapath supported by this NIC (when
17158 * TX_TSO_V2 == 1). Not present on older firmware (check the length).
17159 */
17160#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24
17161#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2
17162/* One byte per PF containing the number of the external port assigned to this
17163 * PF, indexed by PF number. Special values indicate that a PF is either not
17164 * present or not assigned.
17165 */
17166#define MC_CMD_GET_CAPABILITIES_V8_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26
17167#define MC_CMD_GET_CAPABILITIES_V8_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1
17168#define MC_CMD_GET_CAPABILITIES_V8_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16
17169/* enum: The caller is not permitted to access information on this PF. */
17170#define MC_CMD_GET_CAPABILITIES_V8_OUT_ACCESS_NOT_PERMITTED 0xff
17171/* enum: PF does not exist. */
17172#define MC_CMD_GET_CAPABILITIES_V8_OUT_PF_NOT_PRESENT 0xfe
17173/* enum: PF does exist but is not assigned to any external port. */
17174#define MC_CMD_GET_CAPABILITIES_V8_OUT_PF_NOT_ASSIGNED 0xfd
17175/* enum: This value indicates that PF is assigned, but it cannot be expressed
17176 * in this field. It is intended for a possible future situation where a more
17177 * complex scheme of PFs to ports mapping is being used. The future driver
17178 * should look for a new field supporting the new scheme. The current/old
17179 * driver should treat this value as PF_NOT_ASSIGNED.
17180 */
17181#define MC_CMD_GET_CAPABILITIES_V8_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
17182/* One byte per PF containing the number of its VFs, indexed by PF number. A
17183 * special value indicates that a PF is not present.
17184 */
17185#define MC_CMD_GET_CAPABILITIES_V8_OUT_NUM_VFS_PER_PF_OFST 42
17186#define MC_CMD_GET_CAPABILITIES_V8_OUT_NUM_VFS_PER_PF_LEN 1
17187#define MC_CMD_GET_CAPABILITIES_V8_OUT_NUM_VFS_PER_PF_NUM 16
17188/* enum: The caller is not permitted to access information on this PF. */
17189/* MC_CMD_GET_CAPABILITIES_V8_OUT_ACCESS_NOT_PERMITTED 0xff */
17190/* enum: PF does not exist. */
17191/* MC_CMD_GET_CAPABILITIES_V8_OUT_PF_NOT_PRESENT 0xfe */
17192/* Number of VIs available for each external port */
17193#define MC_CMD_GET_CAPABILITIES_V8_OUT_NUM_VIS_PER_PORT_OFST 58
17194#define MC_CMD_GET_CAPABILITIES_V8_OUT_NUM_VIS_PER_PORT_LEN 2
17195#define MC_CMD_GET_CAPABILITIES_V8_OUT_NUM_VIS_PER_PORT_NUM 4
17196/* Size of RX descriptor cache expressed as binary logarithm The actual size
17197 * equals (2 ^ RX_DESC_CACHE_SIZE)
17198 */
17199#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_DESC_CACHE_SIZE_OFST 66
17200#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_DESC_CACHE_SIZE_LEN 1
17201/* Size of TX descriptor cache expressed as binary logarithm The actual size
17202 * equals (2 ^ TX_DESC_CACHE_SIZE)
17203 */
17204#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_DESC_CACHE_SIZE_OFST 67
17205#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_DESC_CACHE_SIZE_LEN 1
17206/* Total number of available PIO buffers */
17207#define MC_CMD_GET_CAPABILITIES_V8_OUT_NUM_PIO_BUFFS_OFST 68
17208#define MC_CMD_GET_CAPABILITIES_V8_OUT_NUM_PIO_BUFFS_LEN 2
17209/* Size of a single PIO buffer */
17210#define MC_CMD_GET_CAPABILITIES_V8_OUT_SIZE_PIO_BUFF_OFST 70
17211#define MC_CMD_GET_CAPABILITIES_V8_OUT_SIZE_PIO_BUFF_LEN 2
17212/* On chips later than Medford the amount of address space assigned to each VI
17213 * is configurable. This is a global setting that the driver must query to
17214 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
17215 * with 8k VI windows.
17216 */
17217#define MC_CMD_GET_CAPABILITIES_V8_OUT_VI_WINDOW_MODE_OFST 72
17218#define MC_CMD_GET_CAPABILITIES_V8_OUT_VI_WINDOW_MODE_LEN 1
17219/* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
17220 * CTPIO is not mapped.
17221 */
17222#define MC_CMD_GET_CAPABILITIES_V8_OUT_VI_WINDOW_MODE_8K 0x0
17223/* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
17224#define MC_CMD_GET_CAPABILITIES_V8_OUT_VI_WINDOW_MODE_16K 0x1
17225/* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
17226#define MC_CMD_GET_CAPABILITIES_V8_OUT_VI_WINDOW_MODE_64K 0x2
17227/* Number of vFIFOs per adapter that can be used for VFIFO Stuffing
17228 * (SF-115995-SW) in the present configuration of firmware and port mode.
17229 */
17230#define MC_CMD_GET_CAPABILITIES_V8_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 73
17231#define MC_CMD_GET_CAPABILITIES_V8_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1
17232/* Number of buffers per adapter that can be used for VFIFO Stuffing
17233 * (SF-115995-SW) in the present configuration of firmware and port mode.
17234 */
17235#define MC_CMD_GET_CAPABILITIES_V8_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 74
17236#define MC_CMD_GET_CAPABILITIES_V8_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 2
17237/* Entry count in the MAC stats array, including the final GENERATION_END
17238 * entry. For MAC stats DMA, drivers should allocate a buffer large enough to
17239 * hold at least this many 64-bit stats values, if they wish to receive all
17240 * available stats. If the buffer is shorter than MAC_STATS_NUM_STATS * 8, the
17241 * stats array returned will be truncated.
17242 */
17243#define MC_CMD_GET_CAPABILITIES_V8_OUT_MAC_STATS_NUM_STATS_OFST 76
17244#define MC_CMD_GET_CAPABILITIES_V8_OUT_MAC_STATS_NUM_STATS_LEN 2
17245/* Maximum supported value for MC_CMD_FILTER_OP_V3/MATCH_MARK_VALUE. This field
17246 * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set.
17247 */
17248#define MC_CMD_GET_CAPABILITIES_V8_OUT_FILTER_ACTION_MARK_MAX_OFST 80
17249#define MC_CMD_GET_CAPABILITIES_V8_OUT_FILTER_ACTION_MARK_MAX_LEN 4
17250/* On devices where the INIT_RXQ_WITH_BUFFER_SIZE flag (in
17251 * GET_CAPABILITIES_OUT_V2) is set, drivers have to specify a buffer size when
17252 * they create an RX queue. Due to hardware limitations, only a small number of
17253 * different buffer sizes may be available concurrently. Nonzero entries in
17254 * this array are the sizes of buffers which the system guarantees will be
17255 * available for use. If the list is empty, there are no limitations on
17256 * concurrent buffer sizes.
17257 */
17258#define MC_CMD_GET_CAPABILITIES_V8_OUT_GUARANTEED_RX_BUFFER_SIZES_OFST 84
17259#define MC_CMD_GET_CAPABILITIES_V8_OUT_GUARANTEED_RX_BUFFER_SIZES_LEN 4
17260#define MC_CMD_GET_CAPABILITIES_V8_OUT_GUARANTEED_RX_BUFFER_SIZES_NUM 16
17261/* Third word of flags. Not present on older firmware (check the length). */
17262#define MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS3_OFST 148
17263#define MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS3_LEN 4
17264#define MC_CMD_GET_CAPABILITIES_V8_OUT_WOL_ETHERWAKE_OFST 148
17265#define MC_CMD_GET_CAPABILITIES_V8_OUT_WOL_ETHERWAKE_LBN 0
17266#define MC_CMD_GET_CAPABILITIES_V8_OUT_WOL_ETHERWAKE_WIDTH 1
17267#define MC_CMD_GET_CAPABILITIES_V8_OUT_RSS_EVEN_SPREADING_OFST 148
17268#define MC_CMD_GET_CAPABILITIES_V8_OUT_RSS_EVEN_SPREADING_LBN 1
17269#define MC_CMD_GET_CAPABILITIES_V8_OUT_RSS_EVEN_SPREADING_WIDTH 1
17270#define MC_CMD_GET_CAPABILITIES_V8_OUT_RSS_SELECTABLE_TABLE_SIZE_OFST 148
17271#define MC_CMD_GET_CAPABILITIES_V8_OUT_RSS_SELECTABLE_TABLE_SIZE_LBN 2
17272#define MC_CMD_GET_CAPABILITIES_V8_OUT_RSS_SELECTABLE_TABLE_SIZE_WIDTH 1
17273#define MC_CMD_GET_CAPABILITIES_V8_OUT_MAE_SUPPORTED_OFST 148
17274#define MC_CMD_GET_CAPABILITIES_V8_OUT_MAE_SUPPORTED_LBN 3
17275#define MC_CMD_GET_CAPABILITIES_V8_OUT_MAE_SUPPORTED_WIDTH 1
17276#define MC_CMD_GET_CAPABILITIES_V8_OUT_VDPA_SUPPORTED_OFST 148
17277#define MC_CMD_GET_CAPABILITIES_V8_OUT_VDPA_SUPPORTED_LBN 4
17278#define MC_CMD_GET_CAPABILITIES_V8_OUT_VDPA_SUPPORTED_WIDTH 1
17279#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_OFST 148
17280#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_LBN 5
17281#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_WIDTH 1
17282#define MC_CMD_GET_CAPABILITIES_V8_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_OFST 148
17283#define MC_CMD_GET_CAPABILITIES_V8_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_LBN 6
17284#define MC_CMD_GET_CAPABILITIES_V8_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_WIDTH 1
17285#define MC_CMD_GET_CAPABILITIES_V8_OUT_UNSOL_EV_CREDIT_SUPPORTED_OFST 148
17286#define MC_CMD_GET_CAPABILITIES_V8_OUT_UNSOL_EV_CREDIT_SUPPORTED_LBN 7
17287#define MC_CMD_GET_CAPABILITIES_V8_OUT_UNSOL_EV_CREDIT_SUPPORTED_WIDTH 1
17288#define MC_CMD_GET_CAPABILITIES_V8_OUT_ENCAPSULATED_MCDI_SUPPORTED_OFST 148
17289#define MC_CMD_GET_CAPABILITIES_V8_OUT_ENCAPSULATED_MCDI_SUPPORTED_LBN 8
17290#define MC_CMD_GET_CAPABILITIES_V8_OUT_ENCAPSULATED_MCDI_SUPPORTED_WIDTH 1
17291#define MC_CMD_GET_CAPABILITIES_V8_OUT_EXTERNAL_MAE_SUPPORTED_OFST 148
17292#define MC_CMD_GET_CAPABILITIES_V8_OUT_EXTERNAL_MAE_SUPPORTED_LBN 9
17293#define MC_CMD_GET_CAPABILITIES_V8_OUT_EXTERNAL_MAE_SUPPORTED_WIDTH 1
17294#define MC_CMD_GET_CAPABILITIES_V8_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_OFST 148
17295#define MC_CMD_GET_CAPABILITIES_V8_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_LBN 10
17296#define MC_CMD_GET_CAPABILITIES_V8_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_WIDTH 1
17297#define MC_CMD_GET_CAPABILITIES_V8_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_OFST 148
17298#define MC_CMD_GET_CAPABILITIES_V8_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_LBN 11
17299#define MC_CMD_GET_CAPABILITIES_V8_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_WIDTH 1
17300#define MC_CMD_GET_CAPABILITIES_V8_OUT_RSS_STEER_ON_OUTER_SUPPORTED_OFST 148
17301#define MC_CMD_GET_CAPABILITIES_V8_OUT_RSS_STEER_ON_OUTER_SUPPORTED_LBN 12
17302#define MC_CMD_GET_CAPABILITIES_V8_OUT_RSS_STEER_ON_OUTER_SUPPORTED_WIDTH 1
17303#define MC_CMD_GET_CAPABILITIES_V8_OUT_DYNAMIC_MPORT_JOURNAL_OFST 148
17304#define MC_CMD_GET_CAPABILITIES_V8_OUT_DYNAMIC_MPORT_JOURNAL_LBN 14
17305#define MC_CMD_GET_CAPABILITIES_V8_OUT_DYNAMIC_MPORT_JOURNAL_WIDTH 1
17306/* These bits are reserved for communicating test-specific capabilities to
17307 * host-side test software. All production drivers should treat this field as
17308 * opaque.
17309 */
17310#define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_OFST 152
17311#define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_LEN 8
17312#define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_LO_OFST 152
17313#define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_LO_LEN 4
17314#define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_LO_LBN 1216
17315#define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_LO_WIDTH 32
17316#define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_HI_OFST 156
17317#define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_HI_LEN 4
17318#define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_HI_LBN 1248
17319#define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_HI_WIDTH 32
17320
17321/* MC_CMD_GET_CAPABILITIES_V9_OUT msgresponse */
17322#define MC_CMD_GET_CAPABILITIES_V9_OUT_LEN 184
17323/* First word of flags. */
17324#define MC_CMD_GET_CAPABILITIES_V9_OUT_FLAGS1_OFST 0
17325#define MC_CMD_GET_CAPABILITIES_V9_OUT_FLAGS1_LEN 4
17326#define MC_CMD_GET_CAPABILITIES_V9_OUT_VPORT_RECONFIGURE_OFST 0
17327#define MC_CMD_GET_CAPABILITIES_V9_OUT_VPORT_RECONFIGURE_LBN 3
17328#define MC_CMD_GET_CAPABILITIES_V9_OUT_VPORT_RECONFIGURE_WIDTH 1
17329#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_STRIPING_OFST 0
17330#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_STRIPING_LBN 4
17331#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_STRIPING_WIDTH 1
17332#define MC_CMD_GET_CAPABILITIES_V9_OUT_VADAPTOR_QUERY_OFST 0
17333#define MC_CMD_GET_CAPABILITIES_V9_OUT_VADAPTOR_QUERY_LBN 5
17334#define MC_CMD_GET_CAPABILITIES_V9_OUT_VADAPTOR_QUERY_WIDTH 1
17335#define MC_CMD_GET_CAPABILITIES_V9_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
17336#define MC_CMD_GET_CAPABILITIES_V9_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6
17337#define MC_CMD_GET_CAPABILITIES_V9_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
17338#define MC_CMD_GET_CAPABILITIES_V9_OUT_DRV_ATTACH_PREBOOT_OFST 0
17339#define MC_CMD_GET_CAPABILITIES_V9_OUT_DRV_ATTACH_PREBOOT_LBN 7
17340#define MC_CMD_GET_CAPABILITIES_V9_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
17341#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_FORCE_EVENT_MERGING_OFST 0
17342#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_FORCE_EVENT_MERGING_LBN 8
17343#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
17344#define MC_CMD_GET_CAPABILITIES_V9_OUT_SET_MAC_ENHANCED_OFST 0
17345#define MC_CMD_GET_CAPABILITIES_V9_OUT_SET_MAC_ENHANCED_LBN 9
17346#define MC_CMD_GET_CAPABILITIES_V9_OUT_SET_MAC_ENHANCED_WIDTH 1
17347#define MC_CMD_GET_CAPABILITIES_V9_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
17348#define MC_CMD_GET_CAPABILITIES_V9_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10
17349#define MC_CMD_GET_CAPABILITIES_V9_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
17350#define MC_CMD_GET_CAPABILITIES_V9_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
17351#define MC_CMD_GET_CAPABILITIES_V9_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11
17352#define MC_CMD_GET_CAPABILITIES_V9_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
17353#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
17354#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MAC_SECURITY_FILTERING_LBN 12
17355#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
17356#define MC_CMD_GET_CAPABILITIES_V9_OUT_ADDITIONAL_RSS_MODES_OFST 0
17357#define MC_CMD_GET_CAPABILITIES_V9_OUT_ADDITIONAL_RSS_MODES_LBN 13
17358#define MC_CMD_GET_CAPABILITIES_V9_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
17359#define MC_CMD_GET_CAPABILITIES_V9_OUT_QBB_OFST 0
17360#define MC_CMD_GET_CAPABILITIES_V9_OUT_QBB_LBN 14
17361#define MC_CMD_GET_CAPABILITIES_V9_OUT_QBB_WIDTH 1
17362#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
17363#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15
17364#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
17365#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_RSS_LIMITED_OFST 0
17366#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_RSS_LIMITED_LBN 16
17367#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_RSS_LIMITED_WIDTH 1
17368#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PACKED_STREAM_OFST 0
17369#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PACKED_STREAM_LBN 17
17370#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PACKED_STREAM_WIDTH 1
17371#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_INCLUDE_FCS_OFST 0
17372#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_INCLUDE_FCS_LBN 18
17373#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_INCLUDE_FCS_WIDTH 1
17374#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_VLAN_INSERTION_OFST 0
17375#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_VLAN_INSERTION_LBN 19
17376#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_VLAN_INSERTION_WIDTH 1
17377#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_VLAN_STRIPPING_OFST 0
17378#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_VLAN_STRIPPING_LBN 20
17379#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_VLAN_STRIPPING_WIDTH 1
17380#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_OFST 0
17381#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_LBN 21
17382#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_WIDTH 1
17383#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PREFIX_LEN_0_OFST 0
17384#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PREFIX_LEN_0_LBN 22
17385#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PREFIX_LEN_0_WIDTH 1
17386#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PREFIX_LEN_14_OFST 0
17387#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PREFIX_LEN_14_LBN 23
17388#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PREFIX_LEN_14_WIDTH 1
17389#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_TIMESTAMP_OFST 0
17390#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_TIMESTAMP_LBN 24
17391#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_TIMESTAMP_WIDTH 1
17392#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_BATCHING_OFST 0
17393#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_BATCHING_LBN 25
17394#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_BATCHING_WIDTH 1
17395#define MC_CMD_GET_CAPABILITIES_V9_OUT_MCAST_FILTER_CHAINING_OFST 0
17396#define MC_CMD_GET_CAPABILITIES_V9_OUT_MCAST_FILTER_CHAINING_LBN 26
17397#define MC_CMD_GET_CAPABILITIES_V9_OUT_MCAST_FILTER_CHAINING_WIDTH 1
17398#define MC_CMD_GET_CAPABILITIES_V9_OUT_PM_AND_RXDP_COUNTERS_OFST 0
17399#define MC_CMD_GET_CAPABILITIES_V9_OUT_PM_AND_RXDP_COUNTERS_LBN 27
17400#define MC_CMD_GET_CAPABILITIES_V9_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
17401#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_DISABLE_SCATTER_OFST 0
17402#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_DISABLE_SCATTER_LBN 28
17403#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_DISABLE_SCATTER_WIDTH 1
17404#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
17405#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29
17406#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
17407#define MC_CMD_GET_CAPABILITIES_V9_OUT_EVB_OFST 0
17408#define MC_CMD_GET_CAPABILITIES_V9_OUT_EVB_LBN 30
17409#define MC_CMD_GET_CAPABILITIES_V9_OUT_EVB_WIDTH 1
17410#define MC_CMD_GET_CAPABILITIES_V9_OUT_VXLAN_NVGRE_OFST 0
17411#define MC_CMD_GET_CAPABILITIES_V9_OUT_VXLAN_NVGRE_LBN 31
17412#define MC_CMD_GET_CAPABILITIES_V9_OUT_VXLAN_NVGRE_WIDTH 1
17413/* RxDPCPU firmware id. */
17414#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_DPCPU_FW_ID_OFST 4
17415#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_DPCPU_FW_ID_LEN 2
17416/* enum: Standard RXDP firmware */
17417#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP 0x0
17418/* enum: Low latency RXDP firmware */
17419#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_LOW_LATENCY 0x1
17420/* enum: Packed stream RXDP firmware */
17421#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_PACKED_STREAM 0x2
17422/* enum: Rules engine RXDP firmware */
17423#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_RULES_ENGINE 0x5
17424/* enum: DPDK RXDP firmware */
17425#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_DPDK 0x6
17426/* enum: BIST RXDP firmware */
17427#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_BIST 0x10a
17428/* enum: RXDP Test firmware image 1 */
17429#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
17430/* enum: RXDP Test firmware image 2 */
17431#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
17432/* enum: RXDP Test firmware image 3 */
17433#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
17434/* enum: RXDP Test firmware image 4 */
17435#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
17436/* enum: RXDP Test firmware image 5 */
17437#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_BACKPRESSURE 0x105
17438/* enum: RXDP Test firmware image 6 */
17439#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
17440/* enum: RXDP Test firmware image 7 */
17441#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
17442/* enum: RXDP Test firmware image 8 */
17443#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
17444/* enum: RXDP Test firmware image 9 */
17445#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
17446/* enum: RXDP Test firmware image 10 */
17447#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_SLOW 0x10c
17448/* TxDPCPU firmware id. */
17449#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_DPCPU_FW_ID_OFST 6
17450#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_DPCPU_FW_ID_LEN 2
17451/* enum: Standard TXDP firmware */
17452#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP 0x0
17453/* enum: Low latency TXDP firmware */
17454#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_LOW_LATENCY 0x1
17455/* enum: High packet rate TXDP firmware */
17456#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_HIGH_PACKET_RATE 0x3
17457/* enum: Rules engine TXDP firmware */
17458#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_RULES_ENGINE 0x5
17459/* enum: DPDK TXDP firmware */
17460#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_DPDK 0x6
17461/* enum: BIST TXDP firmware */
17462#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_BIST 0x12d
17463/* enum: TXDP Test firmware image 1 */
17464#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
17465/* enum: TXDP Test firmware image 2 */
17466#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
17467/* enum: TXDP CSR bus test firmware */
17468#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_TEST_FW_CSR 0x103
17469#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_VERSION_OFST 8
17470#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_VERSION_LEN 2
17471#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_VERSION_REV_OFST 8
17472#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_VERSION_REV_LBN 0
17473#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_VERSION_REV_WIDTH 12
17474#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_VERSION_TYPE_OFST 8
17475#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_VERSION_TYPE_LBN 12
17476#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
17477/* enum: reserved value - do not use (may indicate alternative interpretation
17478 * of REV field in future)
17479 */
17480#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_RESERVED 0x0
17481/* enum: Trivial RX PD firmware for early Huntington development (Huntington
17482 * development only)
17483 */
17484#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
17485/* enum: RX PD firmware for telemetry prototyping (Medford2 development only)
17486 */
17487#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
17488/* enum: RX PD firmware with approximately Siena-compatible behaviour
17489 * (Huntington development only)
17490 */
17491#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
17492/* enum: Full featured RX PD production firmware */
17493#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
17494/* enum: (deprecated original name for the FULL_FEATURED variant) */
17495#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_VSWITCH 0x3
17496/* enum: siena_compat variant RX PD firmware using PM rather than MAC
17497 * (Huntington development only)
17498 */
17499#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
17500/* enum: Low latency RX PD production firmware */
17501#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
17502/* enum: Packed stream RX PD production firmware */
17503#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
17504/* enum: RX PD firmware handling layer 2 only for high packet rate performance
17505 * tests (Medford development only)
17506 */
17507#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
17508/* enum: Rules engine RX PD production firmware */
17509#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
17510/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
17511#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_L3XUDP 0x9
17512/* enum: DPDK RX PD production firmware */
17513#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_DPDK 0xa
17514/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
17515#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
17516/* enum: RX PD firmware parsing but not filtering network overlay tunnel
17517 * encapsulations (Medford development only)
17518 */
17519#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
17520#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_VERSION_OFST 10
17521#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_VERSION_LEN 2
17522#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_VERSION_REV_OFST 10
17523#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_VERSION_REV_LBN 0
17524#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_VERSION_REV_WIDTH 12
17525#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_VERSION_TYPE_OFST 10
17526#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_VERSION_TYPE_LBN 12
17527#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
17528/* enum: reserved value - do not use (may indicate alternative interpretation
17529 * of REV field in future)
17530 */
17531#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_RESERVED 0x0
17532/* enum: Trivial TX PD firmware for early Huntington development (Huntington
17533 * development only)
17534 */
17535#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
17536/* enum: TX PD firmware for telemetry prototyping (Medford2 development only)
17537 */
17538#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
17539/* enum: TX PD firmware with approximately Siena-compatible behaviour
17540 * (Huntington development only)
17541 */
17542#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
17543/* enum: Full featured TX PD production firmware */
17544#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
17545/* enum: (deprecated original name for the FULL_FEATURED variant) */
17546#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_VSWITCH 0x3
17547/* enum: siena_compat variant TX PD firmware using PM rather than MAC
17548 * (Huntington development only)
17549 */
17550#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
17551#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
17552/* enum: TX PD firmware handling layer 2 only for high packet rate performance
17553 * tests (Medford development only)
17554 */
17555#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
17556/* enum: Rules engine TX PD production firmware */
17557#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
17558/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
17559#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_L3XUDP 0x9
17560/* enum: DPDK TX PD production firmware */
17561#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_DPDK 0xa
17562/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
17563#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
17564/* Hardware capabilities of NIC */
17565#define MC_CMD_GET_CAPABILITIES_V9_OUT_HW_CAPABILITIES_OFST 12
17566#define MC_CMD_GET_CAPABILITIES_V9_OUT_HW_CAPABILITIES_LEN 4
17567/* Licensed capabilities */
17568#define MC_CMD_GET_CAPABILITIES_V9_OUT_LICENSE_CAPABILITIES_OFST 16
17569#define MC_CMD_GET_CAPABILITIES_V9_OUT_LICENSE_CAPABILITIES_LEN 4
17570/* Second word of flags. Not present on older firmware (check the length). */
17571#define MC_CMD_GET_CAPABILITIES_V9_OUT_FLAGS2_OFST 20
17572#define MC_CMD_GET_CAPABILITIES_V9_OUT_FLAGS2_LEN 4
17573#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V2_OFST 20
17574#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V2_LBN 0
17575#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V2_WIDTH 1
17576#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V2_ENCAP_OFST 20
17577#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V2_ENCAP_LBN 1
17578#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V2_ENCAP_WIDTH 1
17579#define MC_CMD_GET_CAPABILITIES_V9_OUT_EVQ_TIMER_CTRL_OFST 20
17580#define MC_CMD_GET_CAPABILITIES_V9_OUT_EVQ_TIMER_CTRL_LBN 2
17581#define MC_CMD_GET_CAPABILITIES_V9_OUT_EVQ_TIMER_CTRL_WIDTH 1
17582#define MC_CMD_GET_CAPABILITIES_V9_OUT_EVENT_CUT_THROUGH_OFST 20
17583#define MC_CMD_GET_CAPABILITIES_V9_OUT_EVENT_CUT_THROUGH_LBN 3
17584#define MC_CMD_GET_CAPABILITIES_V9_OUT_EVENT_CUT_THROUGH_WIDTH 1
17585#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_CUT_THROUGH_OFST 20
17586#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_CUT_THROUGH_LBN 4
17587#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_CUT_THROUGH_WIDTH 1
17588#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_VFIFO_ULL_MODE_OFST 20
17589#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_VFIFO_ULL_MODE_LBN 5
17590#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_VFIFO_ULL_MODE_WIDTH 1
17591#define MC_CMD_GET_CAPABILITIES_V9_OUT_MAC_STATS_40G_TX_SIZE_BINS_OFST 20
17592#define MC_CMD_GET_CAPABILITIES_V9_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6
17593#define MC_CMD_GET_CAPABILITIES_V9_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1
17594#define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_EVQ_TYPE_SUPPORTED_OFST 20
17595#define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_EVQ_TYPE_SUPPORTED_LBN 7
17596#define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 1
17597#define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_EVQ_V2_OFST 20
17598#define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_EVQ_V2_LBN 7
17599#define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_EVQ_V2_WIDTH 1
17600#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MAC_TIMESTAMPING_OFST 20
17601#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MAC_TIMESTAMPING_LBN 8
17602#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MAC_TIMESTAMPING_WIDTH 1
17603#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TIMESTAMP_OFST 20
17604#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TIMESTAMP_LBN 9
17605#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TIMESTAMP_WIDTH 1
17606#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_SNIFF_OFST 20
17607#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_SNIFF_LBN 10
17608#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_SNIFF_WIDTH 1
17609#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_SNIFF_OFST 20
17610#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_SNIFF_LBN 11
17611#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_SNIFF_WIDTH 1
17612#define MC_CMD_GET_CAPABILITIES_V9_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_OFST 20
17613#define MC_CMD_GET_CAPABILITIES_V9_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12
17614#define MC_CMD_GET_CAPABILITIES_V9_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1
17615#define MC_CMD_GET_CAPABILITIES_V9_OUT_MCDI_BACKGROUND_OFST 20
17616#define MC_CMD_GET_CAPABILITIES_V9_OUT_MCDI_BACKGROUND_LBN 13
17617#define MC_CMD_GET_CAPABILITIES_V9_OUT_MCDI_BACKGROUND_WIDTH 1
17618#define MC_CMD_GET_CAPABILITIES_V9_OUT_MCDI_DB_RETURN_OFST 20
17619#define MC_CMD_GET_CAPABILITIES_V9_OUT_MCDI_DB_RETURN_LBN 14
17620#define MC_CMD_GET_CAPABILITIES_V9_OUT_MCDI_DB_RETURN_WIDTH 1
17621#define MC_CMD_GET_CAPABILITIES_V9_OUT_CTPIO_OFST 20
17622#define MC_CMD_GET_CAPABILITIES_V9_OUT_CTPIO_LBN 15
17623#define MC_CMD_GET_CAPABILITIES_V9_OUT_CTPIO_WIDTH 1
17624#define MC_CMD_GET_CAPABILITIES_V9_OUT_TSA_SUPPORT_OFST 20
17625#define MC_CMD_GET_CAPABILITIES_V9_OUT_TSA_SUPPORT_LBN 16
17626#define MC_CMD_GET_CAPABILITIES_V9_OUT_TSA_SUPPORT_WIDTH 1
17627#define MC_CMD_GET_CAPABILITIES_V9_OUT_TSA_BOUND_OFST 20
17628#define MC_CMD_GET_CAPABILITIES_V9_OUT_TSA_BOUND_LBN 17
17629#define MC_CMD_GET_CAPABILITIES_V9_OUT_TSA_BOUND_WIDTH 1
17630#define MC_CMD_GET_CAPABILITIES_V9_OUT_SF_ADAPTER_AUTHENTICATION_OFST 20
17631#define MC_CMD_GET_CAPABILITIES_V9_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18
17632#define MC_CMD_GET_CAPABILITIES_V9_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1
17633#define MC_CMD_GET_CAPABILITIES_V9_OUT_FILTER_ACTION_FLAG_OFST 20
17634#define MC_CMD_GET_CAPABILITIES_V9_OUT_FILTER_ACTION_FLAG_LBN 19
17635#define MC_CMD_GET_CAPABILITIES_V9_OUT_FILTER_ACTION_FLAG_WIDTH 1
17636#define MC_CMD_GET_CAPABILITIES_V9_OUT_FILTER_ACTION_MARK_OFST 20
17637#define MC_CMD_GET_CAPABILITIES_V9_OUT_FILTER_ACTION_MARK_LBN 20
17638#define MC_CMD_GET_CAPABILITIES_V9_OUT_FILTER_ACTION_MARK_WIDTH 1
17639#define MC_CMD_GET_CAPABILITIES_V9_OUT_EQUAL_STRIDE_SUPER_BUFFER_OFST 20
17640#define MC_CMD_GET_CAPABILITIES_V9_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 21
17641#define MC_CMD_GET_CAPABILITIES_V9_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1
17642#define MC_CMD_GET_CAPABILITIES_V9_OUT_EQUAL_STRIDE_PACKED_STREAM_OFST 20
17643#define MC_CMD_GET_CAPABILITIES_V9_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21
17644#define MC_CMD_GET_CAPABILITIES_V9_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1
17645#define MC_CMD_GET_CAPABILITIES_V9_OUT_L3XUDP_SUPPORT_OFST 20
17646#define MC_CMD_GET_CAPABILITIES_V9_OUT_L3XUDP_SUPPORT_LBN 22
17647#define MC_CMD_GET_CAPABILITIES_V9_OUT_L3XUDP_SUPPORT_WIDTH 1
17648#define MC_CMD_GET_CAPABILITIES_V9_OUT_FW_SUBVARIANT_NO_TX_CSUM_OFST 20
17649#define MC_CMD_GET_CAPABILITIES_V9_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23
17650#define MC_CMD_GET_CAPABILITIES_V9_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1
17651#define MC_CMD_GET_CAPABILITIES_V9_OUT_VI_SPREADING_OFST 20
17652#define MC_CMD_GET_CAPABILITIES_V9_OUT_VI_SPREADING_LBN 24
17653#define MC_CMD_GET_CAPABILITIES_V9_OUT_VI_SPREADING_WIDTH 1
17654#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_HLB_IDLE_OFST 20
17655#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_HLB_IDLE_LBN 25
17656#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_HLB_IDLE_WIDTH 1
17657#define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_RXQ_NO_CONT_EV_OFST 20
17658#define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_RXQ_NO_CONT_EV_LBN 26
17659#define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1
17660#define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_RXQ_WITH_BUFFER_SIZE_OFST 20
17661#define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 27
17662#define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1
17663#define MC_CMD_GET_CAPABILITIES_V9_OUT_BUNDLE_UPDATE_OFST 20
17664#define MC_CMD_GET_CAPABILITIES_V9_OUT_BUNDLE_UPDATE_LBN 28
17665#define MC_CMD_GET_CAPABILITIES_V9_OUT_BUNDLE_UPDATE_WIDTH 1
17666#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V3_OFST 20
17667#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V3_LBN 29
17668#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V3_WIDTH 1
17669#define MC_CMD_GET_CAPABILITIES_V9_OUT_DYNAMIC_SENSORS_OFST 20
17670#define MC_CMD_GET_CAPABILITIES_V9_OUT_DYNAMIC_SENSORS_LBN 30
17671#define MC_CMD_GET_CAPABILITIES_V9_OUT_DYNAMIC_SENSORS_WIDTH 1
17672#define MC_CMD_GET_CAPABILITIES_V9_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_OFST 20
17673#define MC_CMD_GET_CAPABILITIES_V9_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 31
17674#define MC_CMD_GET_CAPABILITIES_V9_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1
17675/* Number of FATSOv2 contexts per datapath supported by this NIC (when
17676 * TX_TSO_V2 == 1). Not present on older firmware (check the length).
17677 */
17678#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24
17679#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2
17680/* One byte per PF containing the number of the external port assigned to this
17681 * PF, indexed by PF number. Special values indicate that a PF is either not
17682 * present or not assigned.
17683 */
17684#define MC_CMD_GET_CAPABILITIES_V9_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26
17685#define MC_CMD_GET_CAPABILITIES_V9_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1
17686#define MC_CMD_GET_CAPABILITIES_V9_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16
17687/* enum: The caller is not permitted to access information on this PF. */
17688#define MC_CMD_GET_CAPABILITIES_V9_OUT_ACCESS_NOT_PERMITTED 0xff
17689/* enum: PF does not exist. */
17690#define MC_CMD_GET_CAPABILITIES_V9_OUT_PF_NOT_PRESENT 0xfe
17691/* enum: PF does exist but is not assigned to any external port. */
17692#define MC_CMD_GET_CAPABILITIES_V9_OUT_PF_NOT_ASSIGNED 0xfd
17693/* enum: This value indicates that PF is assigned, but it cannot be expressed
17694 * in this field. It is intended for a possible future situation where a more
17695 * complex scheme of PFs to ports mapping is being used. The future driver
17696 * should look for a new field supporting the new scheme. The current/old
17697 * driver should treat this value as PF_NOT_ASSIGNED.
17698 */
17699#define MC_CMD_GET_CAPABILITIES_V9_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
17700/* One byte per PF containing the number of its VFs, indexed by PF number. A
17701 * special value indicates that a PF is not present.
17702 */
17703#define MC_CMD_GET_CAPABILITIES_V9_OUT_NUM_VFS_PER_PF_OFST 42
17704#define MC_CMD_GET_CAPABILITIES_V9_OUT_NUM_VFS_PER_PF_LEN 1
17705#define MC_CMD_GET_CAPABILITIES_V9_OUT_NUM_VFS_PER_PF_NUM 16
17706/* enum: The caller is not permitted to access information on this PF. */
17707/* MC_CMD_GET_CAPABILITIES_V9_OUT_ACCESS_NOT_PERMITTED 0xff */
17708/* enum: PF does not exist. */
17709/* MC_CMD_GET_CAPABILITIES_V9_OUT_PF_NOT_PRESENT 0xfe */
17710/* Number of VIs available for each external port */
17711#define MC_CMD_GET_CAPABILITIES_V9_OUT_NUM_VIS_PER_PORT_OFST 58
17712#define MC_CMD_GET_CAPABILITIES_V9_OUT_NUM_VIS_PER_PORT_LEN 2
17713#define MC_CMD_GET_CAPABILITIES_V9_OUT_NUM_VIS_PER_PORT_NUM 4
17714/* Size of RX descriptor cache expressed as binary logarithm The actual size
17715 * equals (2 ^ RX_DESC_CACHE_SIZE)
17716 */
17717#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_DESC_CACHE_SIZE_OFST 66
17718#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_DESC_CACHE_SIZE_LEN 1
17719/* Size of TX descriptor cache expressed as binary logarithm The actual size
17720 * equals (2 ^ TX_DESC_CACHE_SIZE)
17721 */
17722#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_DESC_CACHE_SIZE_OFST 67
17723#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_DESC_CACHE_SIZE_LEN 1
17724/* Total number of available PIO buffers */
17725#define MC_CMD_GET_CAPABILITIES_V9_OUT_NUM_PIO_BUFFS_OFST 68
17726#define MC_CMD_GET_CAPABILITIES_V9_OUT_NUM_PIO_BUFFS_LEN 2
17727/* Size of a single PIO buffer */
17728#define MC_CMD_GET_CAPABILITIES_V9_OUT_SIZE_PIO_BUFF_OFST 70
17729#define MC_CMD_GET_CAPABILITIES_V9_OUT_SIZE_PIO_BUFF_LEN 2
17730/* On chips later than Medford the amount of address space assigned to each VI
17731 * is configurable. This is a global setting that the driver must query to
17732 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
17733 * with 8k VI windows.
17734 */
17735#define MC_CMD_GET_CAPABILITIES_V9_OUT_VI_WINDOW_MODE_OFST 72
17736#define MC_CMD_GET_CAPABILITIES_V9_OUT_VI_WINDOW_MODE_LEN 1
17737/* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
17738 * CTPIO is not mapped.
17739 */
17740#define MC_CMD_GET_CAPABILITIES_V9_OUT_VI_WINDOW_MODE_8K 0x0
17741/* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
17742#define MC_CMD_GET_CAPABILITIES_V9_OUT_VI_WINDOW_MODE_16K 0x1
17743/* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
17744#define MC_CMD_GET_CAPABILITIES_V9_OUT_VI_WINDOW_MODE_64K 0x2
17745/* Number of vFIFOs per adapter that can be used for VFIFO Stuffing
17746 * (SF-115995-SW) in the present configuration of firmware and port mode.
17747 */
17748#define MC_CMD_GET_CAPABILITIES_V9_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 73
17749#define MC_CMD_GET_CAPABILITIES_V9_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1
17750/* Number of buffers per adapter that can be used for VFIFO Stuffing
17751 * (SF-115995-SW) in the present configuration of firmware and port mode.
17752 */
17753#define MC_CMD_GET_CAPABILITIES_V9_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 74
17754#define MC_CMD_GET_CAPABILITIES_V9_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 2
17755/* Entry count in the MAC stats array, including the final GENERATION_END
17756 * entry. For MAC stats DMA, drivers should allocate a buffer large enough to
17757 * hold at least this many 64-bit stats values, if they wish to receive all
17758 * available stats. If the buffer is shorter than MAC_STATS_NUM_STATS * 8, the
17759 * stats array returned will be truncated.
17760 */
17761#define MC_CMD_GET_CAPABILITIES_V9_OUT_MAC_STATS_NUM_STATS_OFST 76
17762#define MC_CMD_GET_CAPABILITIES_V9_OUT_MAC_STATS_NUM_STATS_LEN 2
17763/* Maximum supported value for MC_CMD_FILTER_OP_V3/MATCH_MARK_VALUE. This field
17764 * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set.
17765 */
17766#define MC_CMD_GET_CAPABILITIES_V9_OUT_FILTER_ACTION_MARK_MAX_OFST 80
17767#define MC_CMD_GET_CAPABILITIES_V9_OUT_FILTER_ACTION_MARK_MAX_LEN 4
17768/* On devices where the INIT_RXQ_WITH_BUFFER_SIZE flag (in
17769 * GET_CAPABILITIES_OUT_V2) is set, drivers have to specify a buffer size when
17770 * they create an RX queue. Due to hardware limitations, only a small number of
17771 * different buffer sizes may be available concurrently. Nonzero entries in
17772 * this array are the sizes of buffers which the system guarantees will be
17773 * available for use. If the list is empty, there are no limitations on
17774 * concurrent buffer sizes.
17775 */
17776#define MC_CMD_GET_CAPABILITIES_V9_OUT_GUARANTEED_RX_BUFFER_SIZES_OFST 84
17777#define MC_CMD_GET_CAPABILITIES_V9_OUT_GUARANTEED_RX_BUFFER_SIZES_LEN 4
17778#define MC_CMD_GET_CAPABILITIES_V9_OUT_GUARANTEED_RX_BUFFER_SIZES_NUM 16
17779/* Third word of flags. Not present on older firmware (check the length). */
17780#define MC_CMD_GET_CAPABILITIES_V9_OUT_FLAGS3_OFST 148
17781#define MC_CMD_GET_CAPABILITIES_V9_OUT_FLAGS3_LEN 4
17782#define MC_CMD_GET_CAPABILITIES_V9_OUT_WOL_ETHERWAKE_OFST 148
17783#define MC_CMD_GET_CAPABILITIES_V9_OUT_WOL_ETHERWAKE_LBN 0
17784#define MC_CMD_GET_CAPABILITIES_V9_OUT_WOL_ETHERWAKE_WIDTH 1
17785#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_EVEN_SPREADING_OFST 148
17786#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_EVEN_SPREADING_LBN 1
17787#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_EVEN_SPREADING_WIDTH 1
17788#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_SELECTABLE_TABLE_SIZE_OFST 148
17789#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_SELECTABLE_TABLE_SIZE_LBN 2
17790#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_SELECTABLE_TABLE_SIZE_WIDTH 1
17791#define MC_CMD_GET_CAPABILITIES_V9_OUT_MAE_SUPPORTED_OFST 148
17792#define MC_CMD_GET_CAPABILITIES_V9_OUT_MAE_SUPPORTED_LBN 3
17793#define MC_CMD_GET_CAPABILITIES_V9_OUT_MAE_SUPPORTED_WIDTH 1
17794#define MC_CMD_GET_CAPABILITIES_V9_OUT_VDPA_SUPPORTED_OFST 148
17795#define MC_CMD_GET_CAPABILITIES_V9_OUT_VDPA_SUPPORTED_LBN 4
17796#define MC_CMD_GET_CAPABILITIES_V9_OUT_VDPA_SUPPORTED_WIDTH 1
17797#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_OFST 148
17798#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_LBN 5
17799#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_WIDTH 1
17800#define MC_CMD_GET_CAPABILITIES_V9_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_OFST 148
17801#define MC_CMD_GET_CAPABILITIES_V9_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_LBN 6
17802#define MC_CMD_GET_CAPABILITIES_V9_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_WIDTH 1
17803#define MC_CMD_GET_CAPABILITIES_V9_OUT_UNSOL_EV_CREDIT_SUPPORTED_OFST 148
17804#define MC_CMD_GET_CAPABILITIES_V9_OUT_UNSOL_EV_CREDIT_SUPPORTED_LBN 7
17805#define MC_CMD_GET_CAPABILITIES_V9_OUT_UNSOL_EV_CREDIT_SUPPORTED_WIDTH 1
17806#define MC_CMD_GET_CAPABILITIES_V9_OUT_ENCAPSULATED_MCDI_SUPPORTED_OFST 148
17807#define MC_CMD_GET_CAPABILITIES_V9_OUT_ENCAPSULATED_MCDI_SUPPORTED_LBN 8
17808#define MC_CMD_GET_CAPABILITIES_V9_OUT_ENCAPSULATED_MCDI_SUPPORTED_WIDTH 1
17809#define MC_CMD_GET_CAPABILITIES_V9_OUT_EXTERNAL_MAE_SUPPORTED_OFST 148
17810#define MC_CMD_GET_CAPABILITIES_V9_OUT_EXTERNAL_MAE_SUPPORTED_LBN 9
17811#define MC_CMD_GET_CAPABILITIES_V9_OUT_EXTERNAL_MAE_SUPPORTED_WIDTH 1
17812#define MC_CMD_GET_CAPABILITIES_V9_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_OFST 148
17813#define MC_CMD_GET_CAPABILITIES_V9_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_LBN 10
17814#define MC_CMD_GET_CAPABILITIES_V9_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_WIDTH 1
17815#define MC_CMD_GET_CAPABILITIES_V9_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_OFST 148
17816#define MC_CMD_GET_CAPABILITIES_V9_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_LBN 11
17817#define MC_CMD_GET_CAPABILITIES_V9_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_WIDTH 1
17818#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_STEER_ON_OUTER_SUPPORTED_OFST 148
17819#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_STEER_ON_OUTER_SUPPORTED_LBN 12
17820#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_STEER_ON_OUTER_SUPPORTED_WIDTH 1
17821#define MC_CMD_GET_CAPABILITIES_V9_OUT_DYNAMIC_MPORT_JOURNAL_OFST 148
17822#define MC_CMD_GET_CAPABILITIES_V9_OUT_DYNAMIC_MPORT_JOURNAL_LBN 14
17823#define MC_CMD_GET_CAPABILITIES_V9_OUT_DYNAMIC_MPORT_JOURNAL_WIDTH 1
17824/* These bits are reserved for communicating test-specific capabilities to
17825 * host-side test software. All production drivers should treat this field as
17826 * opaque.
17827 */
17828#define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_OFST 152
17829#define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_LEN 8
17830#define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_LO_OFST 152
17831#define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_LO_LEN 4
17832#define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_LO_LBN 1216
17833#define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_LO_WIDTH 32
17834#define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_HI_OFST 156
17835#define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_HI_LEN 4
17836#define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_HI_LBN 1248
17837#define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_HI_WIDTH 32
17838/* The minimum size (in table entries) of indirection table to be allocated
17839 * from the pool for an RSS context. Note that the table size used must be a
17840 * power of 2.
17841 */
17842#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MIN_INDIRECTION_TABLE_SIZE_OFST 160
17843#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MIN_INDIRECTION_TABLE_SIZE_LEN 4
17844/* The maximum size (in table entries) of indirection table to be allocated
17845 * from the pool for an RSS context. Note that the table size used must be a
17846 * power of 2.
17847 */
17848#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MAX_INDIRECTION_TABLE_SIZE_OFST 164
17849#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MAX_INDIRECTION_TABLE_SIZE_LEN 4
17850/* The maximum number of queues that can be used by an RSS context in exclusive
17851 * mode. In exclusive mode the context has a configurable indirection table and
17852 * a configurable RSS key.
17853 */
17854#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MAX_INDIRECTION_QUEUES_OFST 168
17855#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MAX_INDIRECTION_QUEUES_LEN 4
17856/* The maximum number of queues that can be used by an RSS context in even-
17857 * spreading mode. In even-spreading mode the context has no indirection table
17858 * but it does have a configurable RSS key.
17859 */
17860#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MAX_EVEN_SPREADING_QUEUES_OFST 172
17861#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MAX_EVEN_SPREADING_QUEUES_LEN 4
17862/* The total number of RSS contexts supported. Note that the number of
17863 * available contexts using indirection tables is also limited by the
17864 * availability of indirection table space allocated from a common pool.
17865 */
17866#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_NUM_CONTEXTS_OFST 176
17867#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_NUM_CONTEXTS_LEN 4
17868/* The total amount of indirection table space that can be shared between RSS
17869 * contexts.
17870 */
17871#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_TABLE_POOL_SIZE_OFST 180
17872#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_TABLE_POOL_SIZE_LEN 4
17873
17874/* MC_CMD_GET_CAPABILITIES_V10_OUT msgresponse */
17875#define MC_CMD_GET_CAPABILITIES_V10_OUT_LEN 192
17876/* First word of flags. */
17877#define MC_CMD_GET_CAPABILITIES_V10_OUT_FLAGS1_OFST 0
17878#define MC_CMD_GET_CAPABILITIES_V10_OUT_FLAGS1_LEN 4
17879#define MC_CMD_GET_CAPABILITIES_V10_OUT_VPORT_RECONFIGURE_OFST 0
17880#define MC_CMD_GET_CAPABILITIES_V10_OUT_VPORT_RECONFIGURE_LBN 3
17881#define MC_CMD_GET_CAPABILITIES_V10_OUT_VPORT_RECONFIGURE_WIDTH 1
17882#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_STRIPING_OFST 0
17883#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_STRIPING_LBN 4
17884#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_STRIPING_WIDTH 1
17885#define MC_CMD_GET_CAPABILITIES_V10_OUT_VADAPTOR_QUERY_OFST 0
17886#define MC_CMD_GET_CAPABILITIES_V10_OUT_VADAPTOR_QUERY_LBN 5
17887#define MC_CMD_GET_CAPABILITIES_V10_OUT_VADAPTOR_QUERY_WIDTH 1
17888#define MC_CMD_GET_CAPABILITIES_V10_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
17889#define MC_CMD_GET_CAPABILITIES_V10_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6
17890#define MC_CMD_GET_CAPABILITIES_V10_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
17891#define MC_CMD_GET_CAPABILITIES_V10_OUT_DRV_ATTACH_PREBOOT_OFST 0
17892#define MC_CMD_GET_CAPABILITIES_V10_OUT_DRV_ATTACH_PREBOOT_LBN 7
17893#define MC_CMD_GET_CAPABILITIES_V10_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
17894#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_FORCE_EVENT_MERGING_OFST 0
17895#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_FORCE_EVENT_MERGING_LBN 8
17896#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
17897#define MC_CMD_GET_CAPABILITIES_V10_OUT_SET_MAC_ENHANCED_OFST 0
17898#define MC_CMD_GET_CAPABILITIES_V10_OUT_SET_MAC_ENHANCED_LBN 9
17899#define MC_CMD_GET_CAPABILITIES_V10_OUT_SET_MAC_ENHANCED_WIDTH 1
17900#define MC_CMD_GET_CAPABILITIES_V10_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
17901#define MC_CMD_GET_CAPABILITIES_V10_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10
17902#define MC_CMD_GET_CAPABILITIES_V10_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
17903#define MC_CMD_GET_CAPABILITIES_V10_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
17904#define MC_CMD_GET_CAPABILITIES_V10_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11
17905#define MC_CMD_GET_CAPABILITIES_V10_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
17906#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
17907#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_MAC_SECURITY_FILTERING_LBN 12
17908#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
17909#define MC_CMD_GET_CAPABILITIES_V10_OUT_ADDITIONAL_RSS_MODES_OFST 0
17910#define MC_CMD_GET_CAPABILITIES_V10_OUT_ADDITIONAL_RSS_MODES_LBN 13
17911#define MC_CMD_GET_CAPABILITIES_V10_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
17912#define MC_CMD_GET_CAPABILITIES_V10_OUT_QBB_OFST 0
17913#define MC_CMD_GET_CAPABILITIES_V10_OUT_QBB_LBN 14
17914#define MC_CMD_GET_CAPABILITIES_V10_OUT_QBB_WIDTH 1
17915#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
17916#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15
17917#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
17918#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_RSS_LIMITED_OFST 0
17919#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_RSS_LIMITED_LBN 16
17920#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_RSS_LIMITED_WIDTH 1
17921#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_PACKED_STREAM_OFST 0
17922#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_PACKED_STREAM_LBN 17
17923#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_PACKED_STREAM_WIDTH 1
17924#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_INCLUDE_FCS_OFST 0
17925#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_INCLUDE_FCS_LBN 18
17926#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_INCLUDE_FCS_WIDTH 1
17927#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_VLAN_INSERTION_OFST 0
17928#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_VLAN_INSERTION_LBN 19
17929#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_VLAN_INSERTION_WIDTH 1
17930#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_VLAN_STRIPPING_OFST 0
17931#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_VLAN_STRIPPING_LBN 20
17932#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_VLAN_STRIPPING_WIDTH 1
17933#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_TSO_OFST 0
17934#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_TSO_LBN 21
17935#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_TSO_WIDTH 1
17936#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_PREFIX_LEN_0_OFST 0
17937#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_PREFIX_LEN_0_LBN 22
17938#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_PREFIX_LEN_0_WIDTH 1
17939#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_PREFIX_LEN_14_OFST 0
17940#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_PREFIX_LEN_14_LBN 23
17941#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_PREFIX_LEN_14_WIDTH 1
17942#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_TIMESTAMP_OFST 0
17943#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_TIMESTAMP_LBN 24
17944#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_TIMESTAMP_WIDTH 1
17945#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_BATCHING_OFST 0
17946#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_BATCHING_LBN 25
17947#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_BATCHING_WIDTH 1
17948#define MC_CMD_GET_CAPABILITIES_V10_OUT_MCAST_FILTER_CHAINING_OFST 0
17949#define MC_CMD_GET_CAPABILITIES_V10_OUT_MCAST_FILTER_CHAINING_LBN 26
17950#define MC_CMD_GET_CAPABILITIES_V10_OUT_MCAST_FILTER_CHAINING_WIDTH 1
17951#define MC_CMD_GET_CAPABILITIES_V10_OUT_PM_AND_RXDP_COUNTERS_OFST 0
17952#define MC_CMD_GET_CAPABILITIES_V10_OUT_PM_AND_RXDP_COUNTERS_LBN 27
17953#define MC_CMD_GET_CAPABILITIES_V10_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
17954#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_DISABLE_SCATTER_OFST 0
17955#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_DISABLE_SCATTER_LBN 28
17956#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_DISABLE_SCATTER_WIDTH 1
17957#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
17958#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29
17959#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
17960#define MC_CMD_GET_CAPABILITIES_V10_OUT_EVB_OFST 0
17961#define MC_CMD_GET_CAPABILITIES_V10_OUT_EVB_LBN 30
17962#define MC_CMD_GET_CAPABILITIES_V10_OUT_EVB_WIDTH 1
17963#define MC_CMD_GET_CAPABILITIES_V10_OUT_VXLAN_NVGRE_OFST 0
17964#define MC_CMD_GET_CAPABILITIES_V10_OUT_VXLAN_NVGRE_LBN 31
17965#define MC_CMD_GET_CAPABILITIES_V10_OUT_VXLAN_NVGRE_WIDTH 1
17966/* RxDPCPU firmware id. */
17967#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_DPCPU_FW_ID_OFST 4
17968#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_DPCPU_FW_ID_LEN 2
17969/* enum: Standard RXDP firmware */
17970#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP 0x0
17971/* enum: Low latency RXDP firmware */
17972#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_LOW_LATENCY 0x1
17973/* enum: Packed stream RXDP firmware */
17974#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_PACKED_STREAM 0x2
17975/* enum: Rules engine RXDP firmware */
17976#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_RULES_ENGINE 0x5
17977/* enum: DPDK RXDP firmware */
17978#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_DPDK 0x6
17979/* enum: BIST RXDP firmware */
17980#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_BIST 0x10a
17981/* enum: RXDP Test firmware image 1 */
17982#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
17983/* enum: RXDP Test firmware image 2 */
17984#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
17985/* enum: RXDP Test firmware image 3 */
17986#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
17987/* enum: RXDP Test firmware image 4 */
17988#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
17989/* enum: RXDP Test firmware image 5 */
17990#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_TEST_BACKPRESSURE 0x105
17991/* enum: RXDP Test firmware image 6 */
17992#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
17993/* enum: RXDP Test firmware image 7 */
17994#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
17995/* enum: RXDP Test firmware image 8 */
17996#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
17997/* enum: RXDP Test firmware image 9 */
17998#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
17999/* enum: RXDP Test firmware image 10 */
18000#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_TEST_FW_SLOW 0x10c
18001/* TxDPCPU firmware id. */
18002#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_DPCPU_FW_ID_OFST 6
18003#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_DPCPU_FW_ID_LEN 2
18004/* enum: Standard TXDP firmware */
18005#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXDP 0x0
18006/* enum: Low latency TXDP firmware */
18007#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXDP_LOW_LATENCY 0x1
18008/* enum: High packet rate TXDP firmware */
18009#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXDP_HIGH_PACKET_RATE 0x3
18010/* enum: Rules engine TXDP firmware */
18011#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXDP_RULES_ENGINE 0x5
18012/* enum: DPDK TXDP firmware */
18013#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXDP_DPDK 0x6
18014/* enum: BIST TXDP firmware */
18015#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXDP_BIST 0x12d
18016/* enum: TXDP Test firmware image 1 */
18017#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
18018/* enum: TXDP Test firmware image 2 */
18019#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
18020/* enum: TXDP CSR bus test firmware */
18021#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXDP_TEST_FW_CSR 0x103
18022#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_VERSION_OFST 8
18023#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_VERSION_LEN 2
18024#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_VERSION_REV_OFST 8
18025#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_VERSION_REV_LBN 0
18026#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_VERSION_REV_WIDTH 12
18027#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_VERSION_TYPE_OFST 8
18028#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_VERSION_TYPE_LBN 12
18029#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
18030/* enum: reserved value - do not use (may indicate alternative interpretation
18031 * of REV field in future)
18032 */
18033#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_RESERVED 0x0
18034/* enum: Trivial RX PD firmware for early Huntington development (Huntington
18035 * development only)
18036 */
18037#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
18038/* enum: RX PD firmware for telemetry prototyping (Medford2 development only)
18039 */
18040#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
18041/* enum: RX PD firmware with approximately Siena-compatible behaviour
18042 * (Huntington development only)
18043 */
18044#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
18045/* enum: Full featured RX PD production firmware */
18046#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
18047/* enum: (deprecated original name for the FULL_FEATURED variant) */
18048#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_VSWITCH 0x3
18049/* enum: siena_compat variant RX PD firmware using PM rather than MAC
18050 * (Huntington development only)
18051 */
18052#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
18053/* enum: Low latency RX PD production firmware */
18054#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
18055/* enum: Packed stream RX PD production firmware */
18056#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
18057/* enum: RX PD firmware handling layer 2 only for high packet rate performance
18058 * tests (Medford development only)
18059 */
18060#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
18061/* enum: Rules engine RX PD production firmware */
18062#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
18063/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
18064#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_L3XUDP 0x9
18065/* enum: DPDK RX PD production firmware */
18066#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_DPDK 0xa
18067/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
18068#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
18069/* enum: RX PD firmware parsing but not filtering network overlay tunnel
18070 * encapsulations (Medford development only)
18071 */
18072#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
18073#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_VERSION_OFST 10
18074#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_VERSION_LEN 2
18075#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_VERSION_REV_OFST 10
18076#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_VERSION_REV_LBN 0
18077#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_VERSION_REV_WIDTH 12
18078#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_VERSION_TYPE_OFST 10
18079#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_VERSION_TYPE_LBN 12
18080#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
18081/* enum: reserved value - do not use (may indicate alternative interpretation
18082 * of REV field in future)
18083 */
18084#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_RESERVED 0x0
18085/* enum: Trivial TX PD firmware for early Huntington development (Huntington
18086 * development only)
18087 */
18088#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
18089/* enum: TX PD firmware for telemetry prototyping (Medford2 development only)
18090 */
18091#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
18092/* enum: TX PD firmware with approximately Siena-compatible behaviour
18093 * (Huntington development only)
18094 */
18095#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
18096/* enum: Full featured TX PD production firmware */
18097#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
18098/* enum: (deprecated original name for the FULL_FEATURED variant) */
18099#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_VSWITCH 0x3
18100/* enum: siena_compat variant TX PD firmware using PM rather than MAC
18101 * (Huntington development only)
18102 */
18103#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
18104#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
18105/* enum: TX PD firmware handling layer 2 only for high packet rate performance
18106 * tests (Medford development only)
18107 */
18108#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
18109/* enum: Rules engine TX PD production firmware */
18110#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
18111/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
18112#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_L3XUDP 0x9
18113/* enum: DPDK TX PD production firmware */
18114#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_DPDK 0xa
18115/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
18116#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
18117/* Hardware capabilities of NIC */
18118#define MC_CMD_GET_CAPABILITIES_V10_OUT_HW_CAPABILITIES_OFST 12
18119#define MC_CMD_GET_CAPABILITIES_V10_OUT_HW_CAPABILITIES_LEN 4
18120/* Licensed capabilities */
18121#define MC_CMD_GET_CAPABILITIES_V10_OUT_LICENSE_CAPABILITIES_OFST 16
18122#define MC_CMD_GET_CAPABILITIES_V10_OUT_LICENSE_CAPABILITIES_LEN 4
18123/* Second word of flags. Not present on older firmware (check the length). */
18124#define MC_CMD_GET_CAPABILITIES_V10_OUT_FLAGS2_OFST 20
18125#define MC_CMD_GET_CAPABILITIES_V10_OUT_FLAGS2_LEN 4
18126#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_TSO_V2_OFST 20
18127#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_TSO_V2_LBN 0
18128#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_TSO_V2_WIDTH 1
18129#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_TSO_V2_ENCAP_OFST 20
18130#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_TSO_V2_ENCAP_LBN 1
18131#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_TSO_V2_ENCAP_WIDTH 1
18132#define MC_CMD_GET_CAPABILITIES_V10_OUT_EVQ_TIMER_CTRL_OFST 20
18133#define MC_CMD_GET_CAPABILITIES_V10_OUT_EVQ_TIMER_CTRL_LBN 2
18134#define MC_CMD_GET_CAPABILITIES_V10_OUT_EVQ_TIMER_CTRL_WIDTH 1
18135#define MC_CMD_GET_CAPABILITIES_V10_OUT_EVENT_CUT_THROUGH_OFST 20
18136#define MC_CMD_GET_CAPABILITIES_V10_OUT_EVENT_CUT_THROUGH_LBN 3
18137#define MC_CMD_GET_CAPABILITIES_V10_OUT_EVENT_CUT_THROUGH_WIDTH 1
18138#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_CUT_THROUGH_OFST 20
18139#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_CUT_THROUGH_LBN 4
18140#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_CUT_THROUGH_WIDTH 1
18141#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_VFIFO_ULL_MODE_OFST 20
18142#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_VFIFO_ULL_MODE_LBN 5
18143#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_VFIFO_ULL_MODE_WIDTH 1
18144#define MC_CMD_GET_CAPABILITIES_V10_OUT_MAC_STATS_40G_TX_SIZE_BINS_OFST 20
18145#define MC_CMD_GET_CAPABILITIES_V10_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6
18146#define MC_CMD_GET_CAPABILITIES_V10_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1
18147#define MC_CMD_GET_CAPABILITIES_V10_OUT_INIT_EVQ_TYPE_SUPPORTED_OFST 20
18148#define MC_CMD_GET_CAPABILITIES_V10_OUT_INIT_EVQ_TYPE_SUPPORTED_LBN 7
18149#define MC_CMD_GET_CAPABILITIES_V10_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 1
18150#define MC_CMD_GET_CAPABILITIES_V10_OUT_INIT_EVQ_V2_OFST 20
18151#define MC_CMD_GET_CAPABILITIES_V10_OUT_INIT_EVQ_V2_LBN 7
18152#define MC_CMD_GET_CAPABILITIES_V10_OUT_INIT_EVQ_V2_WIDTH 1
18153#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_MAC_TIMESTAMPING_OFST 20
18154#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_MAC_TIMESTAMPING_LBN 8
18155#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_MAC_TIMESTAMPING_WIDTH 1
18156#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_TIMESTAMP_OFST 20
18157#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_TIMESTAMP_LBN 9
18158#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_TIMESTAMP_WIDTH 1
18159#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_SNIFF_OFST 20
18160#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_SNIFF_LBN 10
18161#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_SNIFF_WIDTH 1
18162#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_SNIFF_OFST 20
18163#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_SNIFF_LBN 11
18164#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_SNIFF_WIDTH 1
18165#define MC_CMD_GET_CAPABILITIES_V10_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_OFST 20
18166#define MC_CMD_GET_CAPABILITIES_V10_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12
18167#define MC_CMD_GET_CAPABILITIES_V10_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1
18168#define MC_CMD_GET_CAPABILITIES_V10_OUT_MCDI_BACKGROUND_OFST 20
18169#define MC_CMD_GET_CAPABILITIES_V10_OUT_MCDI_BACKGROUND_LBN 13
18170#define MC_CMD_GET_CAPABILITIES_V10_OUT_MCDI_BACKGROUND_WIDTH 1
18171#define MC_CMD_GET_CAPABILITIES_V10_OUT_MCDI_DB_RETURN_OFST 20
18172#define MC_CMD_GET_CAPABILITIES_V10_OUT_MCDI_DB_RETURN_LBN 14
18173#define MC_CMD_GET_CAPABILITIES_V10_OUT_MCDI_DB_RETURN_WIDTH 1
18174#define MC_CMD_GET_CAPABILITIES_V10_OUT_CTPIO_OFST 20
18175#define MC_CMD_GET_CAPABILITIES_V10_OUT_CTPIO_LBN 15
18176#define MC_CMD_GET_CAPABILITIES_V10_OUT_CTPIO_WIDTH 1
18177#define MC_CMD_GET_CAPABILITIES_V10_OUT_TSA_SUPPORT_OFST 20
18178#define MC_CMD_GET_CAPABILITIES_V10_OUT_TSA_SUPPORT_LBN 16
18179#define MC_CMD_GET_CAPABILITIES_V10_OUT_TSA_SUPPORT_WIDTH 1
18180#define MC_CMD_GET_CAPABILITIES_V10_OUT_TSA_BOUND_OFST 20
18181#define MC_CMD_GET_CAPABILITIES_V10_OUT_TSA_BOUND_LBN 17
18182#define MC_CMD_GET_CAPABILITIES_V10_OUT_TSA_BOUND_WIDTH 1
18183#define MC_CMD_GET_CAPABILITIES_V10_OUT_SF_ADAPTER_AUTHENTICATION_OFST 20
18184#define MC_CMD_GET_CAPABILITIES_V10_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18
18185#define MC_CMD_GET_CAPABILITIES_V10_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1
18186#define MC_CMD_GET_CAPABILITIES_V10_OUT_FILTER_ACTION_FLAG_OFST 20
18187#define MC_CMD_GET_CAPABILITIES_V10_OUT_FILTER_ACTION_FLAG_LBN 19
18188#define MC_CMD_GET_CAPABILITIES_V10_OUT_FILTER_ACTION_FLAG_WIDTH 1
18189#define MC_CMD_GET_CAPABILITIES_V10_OUT_FILTER_ACTION_MARK_OFST 20
18190#define MC_CMD_GET_CAPABILITIES_V10_OUT_FILTER_ACTION_MARK_LBN 20
18191#define MC_CMD_GET_CAPABILITIES_V10_OUT_FILTER_ACTION_MARK_WIDTH 1
18192#define MC_CMD_GET_CAPABILITIES_V10_OUT_EQUAL_STRIDE_SUPER_BUFFER_OFST 20
18193#define MC_CMD_GET_CAPABILITIES_V10_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 21
18194#define MC_CMD_GET_CAPABILITIES_V10_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1
18195#define MC_CMD_GET_CAPABILITIES_V10_OUT_EQUAL_STRIDE_PACKED_STREAM_OFST 20
18196#define MC_CMD_GET_CAPABILITIES_V10_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21
18197#define MC_CMD_GET_CAPABILITIES_V10_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1
18198#define MC_CMD_GET_CAPABILITIES_V10_OUT_L3XUDP_SUPPORT_OFST 20
18199#define MC_CMD_GET_CAPABILITIES_V10_OUT_L3XUDP_SUPPORT_LBN 22
18200#define MC_CMD_GET_CAPABILITIES_V10_OUT_L3XUDP_SUPPORT_WIDTH 1
18201#define MC_CMD_GET_CAPABILITIES_V10_OUT_FW_SUBVARIANT_NO_TX_CSUM_OFST 20
18202#define MC_CMD_GET_CAPABILITIES_V10_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23
18203#define MC_CMD_GET_CAPABILITIES_V10_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1
18204#define MC_CMD_GET_CAPABILITIES_V10_OUT_VI_SPREADING_OFST 20
18205#define MC_CMD_GET_CAPABILITIES_V10_OUT_VI_SPREADING_LBN 24
18206#define MC_CMD_GET_CAPABILITIES_V10_OUT_VI_SPREADING_WIDTH 1
18207#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_HLB_IDLE_OFST 20
18208#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_HLB_IDLE_LBN 25
18209#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_HLB_IDLE_WIDTH 1
18210#define MC_CMD_GET_CAPABILITIES_V10_OUT_INIT_RXQ_NO_CONT_EV_OFST 20
18211#define MC_CMD_GET_CAPABILITIES_V10_OUT_INIT_RXQ_NO_CONT_EV_LBN 26
18212#define MC_CMD_GET_CAPABILITIES_V10_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1
18213#define MC_CMD_GET_CAPABILITIES_V10_OUT_INIT_RXQ_WITH_BUFFER_SIZE_OFST 20
18214#define MC_CMD_GET_CAPABILITIES_V10_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 27
18215#define MC_CMD_GET_CAPABILITIES_V10_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1
18216#define MC_CMD_GET_CAPABILITIES_V10_OUT_BUNDLE_UPDATE_OFST 20
18217#define MC_CMD_GET_CAPABILITIES_V10_OUT_BUNDLE_UPDATE_LBN 28
18218#define MC_CMD_GET_CAPABILITIES_V10_OUT_BUNDLE_UPDATE_WIDTH 1
18219#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_TSO_V3_OFST 20
18220#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_TSO_V3_LBN 29
18221#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_TSO_V3_WIDTH 1
18222#define MC_CMD_GET_CAPABILITIES_V10_OUT_DYNAMIC_SENSORS_OFST 20
18223#define MC_CMD_GET_CAPABILITIES_V10_OUT_DYNAMIC_SENSORS_LBN 30
18224#define MC_CMD_GET_CAPABILITIES_V10_OUT_DYNAMIC_SENSORS_WIDTH 1
18225#define MC_CMD_GET_CAPABILITIES_V10_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_OFST 20
18226#define MC_CMD_GET_CAPABILITIES_V10_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 31
18227#define MC_CMD_GET_CAPABILITIES_V10_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1
18228/* Number of FATSOv2 contexts per datapath supported by this NIC (when
18229 * TX_TSO_V2 == 1). Not present on older firmware (check the length).
18230 */
18231#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24
18232#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2
18233/* One byte per PF containing the number of the external port assigned to this
18234 * PF, indexed by PF number. Special values indicate that a PF is either not
18235 * present or not assigned.
18236 */
18237#define MC_CMD_GET_CAPABILITIES_V10_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26
18238#define MC_CMD_GET_CAPABILITIES_V10_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1
18239#define MC_CMD_GET_CAPABILITIES_V10_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16
18240/* enum: The caller is not permitted to access information on this PF. */
18241#define MC_CMD_GET_CAPABILITIES_V10_OUT_ACCESS_NOT_PERMITTED 0xff
18242/* enum: PF does not exist. */
18243#define MC_CMD_GET_CAPABILITIES_V10_OUT_PF_NOT_PRESENT 0xfe
18244/* enum: PF does exist but is not assigned to any external port. */
18245#define MC_CMD_GET_CAPABILITIES_V10_OUT_PF_NOT_ASSIGNED 0xfd
18246/* enum: This value indicates that PF is assigned, but it cannot be expressed
18247 * in this field. It is intended for a possible future situation where a more
18248 * complex scheme of PFs to ports mapping is being used. The future driver
18249 * should look for a new field supporting the new scheme. The current/old
18250 * driver should treat this value as PF_NOT_ASSIGNED.
18251 */
18252#define MC_CMD_GET_CAPABILITIES_V10_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
18253/* One byte per PF containing the number of its VFs, indexed by PF number. A
18254 * special value indicates that a PF is not present.
18255 */
18256#define MC_CMD_GET_CAPABILITIES_V10_OUT_NUM_VFS_PER_PF_OFST 42
18257#define MC_CMD_GET_CAPABILITIES_V10_OUT_NUM_VFS_PER_PF_LEN 1
18258#define MC_CMD_GET_CAPABILITIES_V10_OUT_NUM_VFS_PER_PF_NUM 16
18259/* enum: The caller is not permitted to access information on this PF. */
18260/* MC_CMD_GET_CAPABILITIES_V10_OUT_ACCESS_NOT_PERMITTED 0xff */
18261/* enum: PF does not exist. */
18262/* MC_CMD_GET_CAPABILITIES_V10_OUT_PF_NOT_PRESENT 0xfe */
18263/* Number of VIs available for each external port */
18264#define MC_CMD_GET_CAPABILITIES_V10_OUT_NUM_VIS_PER_PORT_OFST 58
18265#define MC_CMD_GET_CAPABILITIES_V10_OUT_NUM_VIS_PER_PORT_LEN 2
18266#define MC_CMD_GET_CAPABILITIES_V10_OUT_NUM_VIS_PER_PORT_NUM 4
18267/* Size of RX descriptor cache expressed as binary logarithm The actual size
18268 * equals (2 ^ RX_DESC_CACHE_SIZE)
18269 */
18270#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_DESC_CACHE_SIZE_OFST 66
18271#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_DESC_CACHE_SIZE_LEN 1
18272/* Size of TX descriptor cache expressed as binary logarithm The actual size
18273 * equals (2 ^ TX_DESC_CACHE_SIZE)
18274 */
18275#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_DESC_CACHE_SIZE_OFST 67
18276#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_DESC_CACHE_SIZE_LEN 1
18277/* Total number of available PIO buffers */
18278#define MC_CMD_GET_CAPABILITIES_V10_OUT_NUM_PIO_BUFFS_OFST 68
18279#define MC_CMD_GET_CAPABILITIES_V10_OUT_NUM_PIO_BUFFS_LEN 2
18280/* Size of a single PIO buffer */
18281#define MC_CMD_GET_CAPABILITIES_V10_OUT_SIZE_PIO_BUFF_OFST 70
18282#define MC_CMD_GET_CAPABILITIES_V10_OUT_SIZE_PIO_BUFF_LEN 2
18283/* On chips later than Medford the amount of address space assigned to each VI
18284 * is configurable. This is a global setting that the driver must query to
18285 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
18286 * with 8k VI windows.
18287 */
18288#define MC_CMD_GET_CAPABILITIES_V10_OUT_VI_WINDOW_MODE_OFST 72
18289#define MC_CMD_GET_CAPABILITIES_V10_OUT_VI_WINDOW_MODE_LEN 1
18290/* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
18291 * CTPIO is not mapped.
18292 */
18293#define MC_CMD_GET_CAPABILITIES_V10_OUT_VI_WINDOW_MODE_8K 0x0
18294/* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
18295#define MC_CMD_GET_CAPABILITIES_V10_OUT_VI_WINDOW_MODE_16K 0x1
18296/* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
18297#define MC_CMD_GET_CAPABILITIES_V10_OUT_VI_WINDOW_MODE_64K 0x2
18298/* Number of vFIFOs per adapter that can be used for VFIFO Stuffing
18299 * (SF-115995-SW) in the present configuration of firmware and port mode.
18300 */
18301#define MC_CMD_GET_CAPABILITIES_V10_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 73
18302#define MC_CMD_GET_CAPABILITIES_V10_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1
18303/* Number of buffers per adapter that can be used for VFIFO Stuffing
18304 * (SF-115995-SW) in the present configuration of firmware and port mode.
18305 */
18306#define MC_CMD_GET_CAPABILITIES_V10_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 74
18307#define MC_CMD_GET_CAPABILITIES_V10_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 2
18308/* Entry count in the MAC stats array, including the final GENERATION_END
18309 * entry. For MAC stats DMA, drivers should allocate a buffer large enough to
18310 * hold at least this many 64-bit stats values, if they wish to receive all
18311 * available stats. If the buffer is shorter than MAC_STATS_NUM_STATS * 8, the
18312 * stats array returned will be truncated.
18313 */
18314#define MC_CMD_GET_CAPABILITIES_V10_OUT_MAC_STATS_NUM_STATS_OFST 76
18315#define MC_CMD_GET_CAPABILITIES_V10_OUT_MAC_STATS_NUM_STATS_LEN 2
18316/* Maximum supported value for MC_CMD_FILTER_OP_V3/MATCH_MARK_VALUE. This field
18317 * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set.
18318 */
18319#define MC_CMD_GET_CAPABILITIES_V10_OUT_FILTER_ACTION_MARK_MAX_OFST 80
18320#define MC_CMD_GET_CAPABILITIES_V10_OUT_FILTER_ACTION_MARK_MAX_LEN 4
18321/* On devices where the INIT_RXQ_WITH_BUFFER_SIZE flag (in
18322 * GET_CAPABILITIES_OUT_V2) is set, drivers have to specify a buffer size when
18323 * they create an RX queue. Due to hardware limitations, only a small number of
18324 * different buffer sizes may be available concurrently. Nonzero entries in
18325 * this array are the sizes of buffers which the system guarantees will be
18326 * available for use. If the list is empty, there are no limitations on
18327 * concurrent buffer sizes.
18328 */
18329#define MC_CMD_GET_CAPABILITIES_V10_OUT_GUARANTEED_RX_BUFFER_SIZES_OFST 84
18330#define MC_CMD_GET_CAPABILITIES_V10_OUT_GUARANTEED_RX_BUFFER_SIZES_LEN 4
18331#define MC_CMD_GET_CAPABILITIES_V10_OUT_GUARANTEED_RX_BUFFER_SIZES_NUM 16
18332/* Third word of flags. Not present on older firmware (check the length). */
18333#define MC_CMD_GET_CAPABILITIES_V10_OUT_FLAGS3_OFST 148
18334#define MC_CMD_GET_CAPABILITIES_V10_OUT_FLAGS3_LEN 4
18335#define MC_CMD_GET_CAPABILITIES_V10_OUT_WOL_ETHERWAKE_OFST 148
18336#define MC_CMD_GET_CAPABILITIES_V10_OUT_WOL_ETHERWAKE_LBN 0
18337#define MC_CMD_GET_CAPABILITIES_V10_OUT_WOL_ETHERWAKE_WIDTH 1
18338#define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_EVEN_SPREADING_OFST 148
18339#define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_EVEN_SPREADING_LBN 1
18340#define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_EVEN_SPREADING_WIDTH 1
18341#define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_SELECTABLE_TABLE_SIZE_OFST 148
18342#define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_SELECTABLE_TABLE_SIZE_LBN 2
18343#define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_SELECTABLE_TABLE_SIZE_WIDTH 1
18344#define MC_CMD_GET_CAPABILITIES_V10_OUT_MAE_SUPPORTED_OFST 148
18345#define MC_CMD_GET_CAPABILITIES_V10_OUT_MAE_SUPPORTED_LBN 3
18346#define MC_CMD_GET_CAPABILITIES_V10_OUT_MAE_SUPPORTED_WIDTH 1
18347#define MC_CMD_GET_CAPABILITIES_V10_OUT_VDPA_SUPPORTED_OFST 148
18348#define MC_CMD_GET_CAPABILITIES_V10_OUT_VDPA_SUPPORTED_LBN 4
18349#define MC_CMD_GET_CAPABILITIES_V10_OUT_VDPA_SUPPORTED_WIDTH 1
18350#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_OFST 148
18351#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_LBN 5
18352#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_WIDTH 1
18353#define MC_CMD_GET_CAPABILITIES_V10_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_OFST 148
18354#define MC_CMD_GET_CAPABILITIES_V10_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_LBN 6
18355#define MC_CMD_GET_CAPABILITIES_V10_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_WIDTH 1
18356#define MC_CMD_GET_CAPABILITIES_V10_OUT_UNSOL_EV_CREDIT_SUPPORTED_OFST 148
18357#define MC_CMD_GET_CAPABILITIES_V10_OUT_UNSOL_EV_CREDIT_SUPPORTED_LBN 7
18358#define MC_CMD_GET_CAPABILITIES_V10_OUT_UNSOL_EV_CREDIT_SUPPORTED_WIDTH 1
18359#define MC_CMD_GET_CAPABILITIES_V10_OUT_ENCAPSULATED_MCDI_SUPPORTED_OFST 148
18360#define MC_CMD_GET_CAPABILITIES_V10_OUT_ENCAPSULATED_MCDI_SUPPORTED_LBN 8
18361#define MC_CMD_GET_CAPABILITIES_V10_OUT_ENCAPSULATED_MCDI_SUPPORTED_WIDTH 1
18362#define MC_CMD_GET_CAPABILITIES_V10_OUT_EXTERNAL_MAE_SUPPORTED_OFST 148
18363#define MC_CMD_GET_CAPABILITIES_V10_OUT_EXTERNAL_MAE_SUPPORTED_LBN 9
18364#define MC_CMD_GET_CAPABILITIES_V10_OUT_EXTERNAL_MAE_SUPPORTED_WIDTH 1
18365#define MC_CMD_GET_CAPABILITIES_V10_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_OFST 148
18366#define MC_CMD_GET_CAPABILITIES_V10_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_LBN 10
18367#define MC_CMD_GET_CAPABILITIES_V10_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_WIDTH 1
18368#define MC_CMD_GET_CAPABILITIES_V10_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_OFST 148
18369#define MC_CMD_GET_CAPABILITIES_V10_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_LBN 11
18370#define MC_CMD_GET_CAPABILITIES_V10_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_WIDTH 1
18371#define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_STEER_ON_OUTER_SUPPORTED_OFST 148
18372#define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_STEER_ON_OUTER_SUPPORTED_LBN 12
18373#define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_STEER_ON_OUTER_SUPPORTED_WIDTH 1
18374#define MC_CMD_GET_CAPABILITIES_V10_OUT_DYNAMIC_MPORT_JOURNAL_OFST 148
18375#define MC_CMD_GET_CAPABILITIES_V10_OUT_DYNAMIC_MPORT_JOURNAL_LBN 14
18376#define MC_CMD_GET_CAPABILITIES_V10_OUT_DYNAMIC_MPORT_JOURNAL_WIDTH 1
18377/* These bits are reserved for communicating test-specific capabilities to
18378 * host-side test software. All production drivers should treat this field as
18379 * opaque.
18380 */
18381#define MC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_OFST 152
18382#define MC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_LEN 8
18383#define MC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_LO_OFST 152
18384#define MC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_LO_LEN 4
18385#define MC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_LO_LBN 1216
18386#define MC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_LO_WIDTH 32
18387#define MC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_HI_OFST 156
18388#define MC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_HI_LEN 4
18389#define MC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_HI_LBN 1248
18390#define MC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_HI_WIDTH 32
18391/* The minimum size (in table entries) of indirection table to be allocated
18392 * from the pool for an RSS context. Note that the table size used must be a
18393 * power of 2.
18394 */
18395#define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_MIN_INDIRECTION_TABLE_SIZE_OFST 160
18396#define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_MIN_INDIRECTION_TABLE_SIZE_LEN 4
18397/* The maximum size (in table entries) of indirection table to be allocated
18398 * from the pool for an RSS context. Note that the table size used must be a
18399 * power of 2.
18400 */
18401#define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_MAX_INDIRECTION_TABLE_SIZE_OFST 164
18402#define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_MAX_INDIRECTION_TABLE_SIZE_LEN 4
18403/* The maximum number of queues that can be used by an RSS context in exclusive
18404 * mode. In exclusive mode the context has a configurable indirection table and
18405 * a configurable RSS key.
18406 */
18407#define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_MAX_INDIRECTION_QUEUES_OFST 168
18408#define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_MAX_INDIRECTION_QUEUES_LEN 4
18409/* The maximum number of queues that can be used by an RSS context in even-
18410 * spreading mode. In even-spreading mode the context has no indirection table
18411 * but it does have a configurable RSS key.
18412 */
18413#define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_MAX_EVEN_SPREADING_QUEUES_OFST 172
18414#define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_MAX_EVEN_SPREADING_QUEUES_LEN 4
18415/* The total number of RSS contexts supported. Note that the number of
18416 * available contexts using indirection tables is also limited by the
18417 * availability of indirection table space allocated from a common pool.
18418 */
18419#define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_NUM_CONTEXTS_OFST 176
18420#define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_NUM_CONTEXTS_LEN 4
18421/* The total amount of indirection table space that can be shared between RSS
18422 * contexts.
18423 */
18424#define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_TABLE_POOL_SIZE_OFST 180
18425#define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_TABLE_POOL_SIZE_LEN 4
18426/* A bitmap of the queue sizes the device can provide, where bit N being set
18427 * indicates that 2**N is a valid size. The device may be limited in the number
18428 * of different queue sizes that can exist simultaneously, so a bit being set
18429 * here does not guarantee that an attempt to create a queue of that size will
18430 * succeed.
18431 */
18432#define MC_CMD_GET_CAPABILITIES_V10_OUT_SUPPORTED_QUEUE_SIZES_OFST 184
18433#define MC_CMD_GET_CAPABILITIES_V10_OUT_SUPPORTED_QUEUE_SIZES_LEN 4
18434/* A bitmap of queue sizes that are always available, in the same format as
18435 * SUPPORTED_QUEUE_SIZES. Attempting to create a queue with one of these sizes
18436 * will never fail due to unavailability of the requested size.
18437 */
18438#define MC_CMD_GET_CAPABILITIES_V10_OUT_GUARANTEED_QUEUE_SIZES_OFST 188
18439#define MC_CMD_GET_CAPABILITIES_V10_OUT_GUARANTEED_QUEUE_SIZES_LEN 4
18440
18441
18442/***********************************/
18443/* MC_CMD_V2_EXTN
18444 * Encapsulation for a v2 extended command
18445 */
18446#define MC_CMD_V2_EXTN 0x7f
18447
18448/* MC_CMD_V2_EXTN_IN msgrequest */
18449#define MC_CMD_V2_EXTN_IN_LEN 4
18450/* the extended command number */
18451#define MC_CMD_V2_EXTN_IN_EXTENDED_CMD_LBN 0
18452#define MC_CMD_V2_EXTN_IN_EXTENDED_CMD_WIDTH 15
18453#define MC_CMD_V2_EXTN_IN_UNUSED_LBN 15
18454#define MC_CMD_V2_EXTN_IN_UNUSED_WIDTH 1
18455/* the actual length of the encapsulated command (which is not in the v1
18456 * header)
18457 */
18458#define MC_CMD_V2_EXTN_IN_ACTUAL_LEN_LBN 16
18459#define MC_CMD_V2_EXTN_IN_ACTUAL_LEN_WIDTH 10
18460#define MC_CMD_V2_EXTN_IN_UNUSED2_LBN 26
18461#define MC_CMD_V2_EXTN_IN_UNUSED2_WIDTH 2
18462/* Type of command/response */
18463#define MC_CMD_V2_EXTN_IN_MESSAGE_TYPE_LBN 28
18464#define MC_CMD_V2_EXTN_IN_MESSAGE_TYPE_WIDTH 4
18465/* enum: MCDI command directed to or response originating from the MC. */
18466#define MC_CMD_V2_EXTN_IN_MCDI_MESSAGE_TYPE_MC 0x0
18467/* enum: MCDI command directed to a TSA controller. MCDI responses of this type
18468 * are not defined.
18469 */
18470#define MC_CMD_V2_EXTN_IN_MCDI_MESSAGE_TYPE_TSA 0x1
18471
18472
18473/***********************************/
18474/* MC_CMD_TCM_BUCKET_ALLOC
18475 * Allocate a pacer bucket (for qau rp or a snapper test)
18476 */
18477#define MC_CMD_TCM_BUCKET_ALLOC 0xb2
18478#undef MC_CMD_0xb2_PRIVILEGE_CTG
18479
18480#define MC_CMD_0xb2_PRIVILEGE_CTG SRIOV_CTG_GENERAL
18481
18482/* MC_CMD_TCM_BUCKET_ALLOC_IN msgrequest */
18483#define MC_CMD_TCM_BUCKET_ALLOC_IN_LEN 0
18484
18485/* MC_CMD_TCM_BUCKET_ALLOC_OUT msgresponse */
18486#define MC_CMD_TCM_BUCKET_ALLOC_OUT_LEN 4
18487/* the bucket id */
18488#define MC_CMD_TCM_BUCKET_ALLOC_OUT_BUCKET_OFST 0
18489#define MC_CMD_TCM_BUCKET_ALLOC_OUT_BUCKET_LEN 4
18490
18491
18492/***********************************/
18493/* MC_CMD_TCM_BUCKET_FREE
18494 * Free a pacer bucket
18495 */
18496#define MC_CMD_TCM_BUCKET_FREE 0xb3
18497#undef MC_CMD_0xb3_PRIVILEGE_CTG
18498
18499#define MC_CMD_0xb3_PRIVILEGE_CTG SRIOV_CTG_GENERAL
18500
18501/* MC_CMD_TCM_BUCKET_FREE_IN msgrequest */
18502#define MC_CMD_TCM_BUCKET_FREE_IN_LEN 4
18503/* the bucket id */
18504#define MC_CMD_TCM_BUCKET_FREE_IN_BUCKET_OFST 0
18505#define MC_CMD_TCM_BUCKET_FREE_IN_BUCKET_LEN 4
18506
18507/* MC_CMD_TCM_BUCKET_FREE_OUT msgresponse */
18508#define MC_CMD_TCM_BUCKET_FREE_OUT_LEN 0
18509
18510
18511/***********************************/
18512/* MC_CMD_TCM_BUCKET_INIT
18513 * Initialise pacer bucket with a given rate
18514 */
18515#define MC_CMD_TCM_BUCKET_INIT 0xb4
18516#undef MC_CMD_0xb4_PRIVILEGE_CTG
18517
18518#define MC_CMD_0xb4_PRIVILEGE_CTG SRIOV_CTG_GENERAL
18519
18520/* MC_CMD_TCM_BUCKET_INIT_IN msgrequest */
18521#define MC_CMD_TCM_BUCKET_INIT_IN_LEN 8
18522/* the bucket id */
18523#define MC_CMD_TCM_BUCKET_INIT_IN_BUCKET_OFST 0
18524#define MC_CMD_TCM_BUCKET_INIT_IN_BUCKET_LEN 4
18525/* the rate in mbps */
18526#define MC_CMD_TCM_BUCKET_INIT_IN_RATE_OFST 4
18527#define MC_CMD_TCM_BUCKET_INIT_IN_RATE_LEN 4
18528
18529/* MC_CMD_TCM_BUCKET_INIT_EXT_IN msgrequest */
18530#define MC_CMD_TCM_BUCKET_INIT_EXT_IN_LEN 12
18531/* the bucket id */
18532#define MC_CMD_TCM_BUCKET_INIT_EXT_IN_BUCKET_OFST 0
18533#define MC_CMD_TCM_BUCKET_INIT_EXT_IN_BUCKET_LEN 4
18534/* the rate in mbps */
18535#define MC_CMD_TCM_BUCKET_INIT_EXT_IN_RATE_OFST 4
18536#define MC_CMD_TCM_BUCKET_INIT_EXT_IN_RATE_LEN 4
18537/* the desired maximum fill level */
18538#define MC_CMD_TCM_BUCKET_INIT_EXT_IN_MAX_FILL_OFST 8
18539#define MC_CMD_TCM_BUCKET_INIT_EXT_IN_MAX_FILL_LEN 4
18540
18541/* MC_CMD_TCM_BUCKET_INIT_OUT msgresponse */
18542#define MC_CMD_TCM_BUCKET_INIT_OUT_LEN 0
18543
18544
18545/***********************************/
18546/* MC_CMD_TCM_TXQ_INIT
18547 * Initialise txq in pacer with given options or set options
18548 */
18549#define MC_CMD_TCM_TXQ_INIT 0xb5
18550#undef MC_CMD_0xb5_PRIVILEGE_CTG
18551
18552#define MC_CMD_0xb5_PRIVILEGE_CTG SRIOV_CTG_GENERAL
18553
18554/* MC_CMD_TCM_TXQ_INIT_IN msgrequest */
18555#define MC_CMD_TCM_TXQ_INIT_IN_LEN 28
18556/* the txq id */
18557#define MC_CMD_TCM_TXQ_INIT_IN_QID_OFST 0
18558#define MC_CMD_TCM_TXQ_INIT_IN_QID_LEN 4
18559/* the static priority associated with the txq */
18560#define MC_CMD_TCM_TXQ_INIT_IN_LABEL_OFST 4
18561#define MC_CMD_TCM_TXQ_INIT_IN_LABEL_LEN 4
18562/* bitmask of the priority queues this txq is inserted into when inserted. */
18563#define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAGS_OFST 8
18564#define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAGS_LEN 4
18565#define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_GUARANTEED_OFST 8
18566#define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_GUARANTEED_LBN 0
18567#define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_GUARANTEED_WIDTH 1
18568#define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_NORMAL_OFST 8
18569#define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_NORMAL_LBN 1
18570#define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_NORMAL_WIDTH 1
18571#define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_LOW_OFST 8
18572#define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_LOW_LBN 2
18573#define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_LOW_WIDTH 1
18574/* the reaction point (RP) bucket */
18575#define MC_CMD_TCM_TXQ_INIT_IN_RP_BKT_OFST 12
18576#define MC_CMD_TCM_TXQ_INIT_IN_RP_BKT_LEN 4
18577/* an already reserved bucket (typically set to bucket associated with outer
18578 * vswitch)
18579 */
18580#define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT1_OFST 16
18581#define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT1_LEN 4
18582/* an already reserved bucket (typically set to bucket associated with inner
18583 * vswitch)
18584 */
18585#define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT2_OFST 20
18586#define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT2_LEN 4
18587/* the min bucket (typically for ETS/minimum bandwidth) */
18588#define MC_CMD_TCM_TXQ_INIT_IN_MIN_BKT_OFST 24
18589#define MC_CMD_TCM_TXQ_INIT_IN_MIN_BKT_LEN 4
18590
18591/* MC_CMD_TCM_TXQ_INIT_EXT_IN msgrequest */
18592#define MC_CMD_TCM_TXQ_INIT_EXT_IN_LEN 32
18593/* the txq id */
18594#define MC_CMD_TCM_TXQ_INIT_EXT_IN_QID_OFST 0
18595#define MC_CMD_TCM_TXQ_INIT_EXT_IN_QID_LEN 4
18596/* the static priority associated with the txq */
18597#define MC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_NORMAL_OFST 4
18598#define MC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_NORMAL_LEN 4
18599/* bitmask of the priority queues this txq is inserted into when inserted. */
18600#define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAGS_OFST 8
18601#define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAGS_LEN 4
18602#define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_GUARANTEED_OFST 8
18603#define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_GUARANTEED_LBN 0
18604#define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_GUARANTEED_WIDTH 1
18605#define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_NORMAL_OFST 8
18606#define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_NORMAL_LBN 1
18607#define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_NORMAL_WIDTH 1
18608#define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_LOW_OFST 8
18609#define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_LOW_LBN 2
18610#define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_LOW_WIDTH 1
18611/* the reaction point (RP) bucket */
18612#define MC_CMD_TCM_TXQ_INIT_EXT_IN_RP_BKT_OFST 12
18613#define MC_CMD_TCM_TXQ_INIT_EXT_IN_RP_BKT_LEN 4
18614/* an already reserved bucket (typically set to bucket associated with outer
18615 * vswitch)
18616 */
18617#define MC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT1_OFST 16
18618#define MC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT1_LEN 4
18619/* an already reserved bucket (typically set to bucket associated with inner
18620 * vswitch)
18621 */
18622#define MC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT2_OFST 20
18623#define MC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT2_LEN 4
18624/* the min bucket (typically for ETS/minimum bandwidth) */
18625#define MC_CMD_TCM_TXQ_INIT_EXT_IN_MIN_BKT_OFST 24
18626#define MC_CMD_TCM_TXQ_INIT_EXT_IN_MIN_BKT_LEN 4
18627/* the static priority associated with the txq */
18628#define MC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_GUARANTEED_OFST 28
18629#define MC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_GUARANTEED_LEN 4
18630
18631/* MC_CMD_TCM_TXQ_INIT_OUT msgresponse */
18632#define MC_CMD_TCM_TXQ_INIT_OUT_LEN 0
18633
18634
18635/***********************************/
18636/* MC_CMD_LINK_PIOBUF
18637 * Link a push I/O buffer to a TxQ
18638 */
18639#define MC_CMD_LINK_PIOBUF 0x92
18640#undef MC_CMD_0x92_PRIVILEGE_CTG
18641
18642#define MC_CMD_0x92_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
18643
18644/* MC_CMD_LINK_PIOBUF_IN msgrequest */
18645#define MC_CMD_LINK_PIOBUF_IN_LEN 8
18646/* Handle for allocated push I/O buffer. */
18647#define MC_CMD_LINK_PIOBUF_IN_PIOBUF_HANDLE_OFST 0
18648#define MC_CMD_LINK_PIOBUF_IN_PIOBUF_HANDLE_LEN 4
18649/* Function Local Instance (VI) number which has a TxQ allocated to it. */
18650#define MC_CMD_LINK_PIOBUF_IN_TXQ_INSTANCE_OFST 4
18651#define MC_CMD_LINK_PIOBUF_IN_TXQ_INSTANCE_LEN 4
18652
18653/* MC_CMD_LINK_PIOBUF_OUT msgresponse */
18654#define MC_CMD_LINK_PIOBUF_OUT_LEN 0
18655
18656
18657/***********************************/
18658/* MC_CMD_UNLINK_PIOBUF
18659 * Unlink a push I/O buffer from a TxQ
18660 */
18661#define MC_CMD_UNLINK_PIOBUF 0x93
18662#undef MC_CMD_0x93_PRIVILEGE_CTG
18663
18664#define MC_CMD_0x93_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
18665
18666/* MC_CMD_UNLINK_PIOBUF_IN msgrequest */
18667#define MC_CMD_UNLINK_PIOBUF_IN_LEN 4
18668/* Function Local Instance (VI) number. */
18669#define MC_CMD_UNLINK_PIOBUF_IN_TXQ_INSTANCE_OFST 0
18670#define MC_CMD_UNLINK_PIOBUF_IN_TXQ_INSTANCE_LEN 4
18671
18672/* MC_CMD_UNLINK_PIOBUF_OUT msgresponse */
18673#define MC_CMD_UNLINK_PIOBUF_OUT_LEN 0
18674
18675
18676/***********************************/
18677/* MC_CMD_VSWITCH_ALLOC
18678 * allocate and initialise a v-switch.
18679 */
18680#define MC_CMD_VSWITCH_ALLOC 0x94
18681#undef MC_CMD_0x94_PRIVILEGE_CTG
18682
18683#define MC_CMD_0x94_PRIVILEGE_CTG SRIOV_CTG_GENERAL
18684
18685/* MC_CMD_VSWITCH_ALLOC_IN msgrequest */
18686#define MC_CMD_VSWITCH_ALLOC_IN_LEN 16
18687/* The port to connect to the v-switch's upstream port. */
18688#define MC_CMD_VSWITCH_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
18689#define MC_CMD_VSWITCH_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4
18690/* The type of v-switch to create. */
18691#define MC_CMD_VSWITCH_ALLOC_IN_TYPE_OFST 4
18692#define MC_CMD_VSWITCH_ALLOC_IN_TYPE_LEN 4
18693/* enum: VLAN */
18694#define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VLAN 0x1
18695/* enum: VEB */
18696#define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEB 0x2
18697/* enum: VEPA (obsolete) */
18698#define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEPA 0x3
18699/* enum: MUX */
18700#define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_MUX 0x4
18701/* enum: Snapper specific; semantics TBD */
18702#define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_TEST 0x5
18703/* Flags controlling v-port creation */
18704#define MC_CMD_VSWITCH_ALLOC_IN_FLAGS_OFST 8
18705#define MC_CMD_VSWITCH_ALLOC_IN_FLAGS_LEN 4
18706#define MC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_OFST 8
18707#define MC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_LBN 0
18708#define MC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_WIDTH 1
18709/* The number of VLAN tags to allow for attached v-ports. For VLAN aggregators,
18710 * this must be one or greated, and the attached v-ports must have exactly this
18711 * number of tags. For other v-switch types, this must be zero of greater, and
18712 * is an upper limit on the number of VLAN tags for attached v-ports. An error
18713 * will be returned if existing configuration means we can't support attached
18714 * v-ports with this number of tags.
18715 */
18716#define MC_CMD_VSWITCH_ALLOC_IN_NUM_VLAN_TAGS_OFST 12
18717#define MC_CMD_VSWITCH_ALLOC_IN_NUM_VLAN_TAGS_LEN 4
18718
18719/* MC_CMD_VSWITCH_ALLOC_OUT msgresponse */
18720#define MC_CMD_VSWITCH_ALLOC_OUT_LEN 0
18721
18722
18723/***********************************/
18724/* MC_CMD_VSWITCH_FREE
18725 * de-allocate a v-switch.
18726 */
18727#define MC_CMD_VSWITCH_FREE 0x95
18728#undef MC_CMD_0x95_PRIVILEGE_CTG
18729
18730#define MC_CMD_0x95_PRIVILEGE_CTG SRIOV_CTG_GENERAL
18731
18732/* MC_CMD_VSWITCH_FREE_IN msgrequest */
18733#define MC_CMD_VSWITCH_FREE_IN_LEN 4
18734/* The port to which the v-switch is connected. */
18735#define MC_CMD_VSWITCH_FREE_IN_UPSTREAM_PORT_ID_OFST 0
18736#define MC_CMD_VSWITCH_FREE_IN_UPSTREAM_PORT_ID_LEN 4
18737
18738/* MC_CMD_VSWITCH_FREE_OUT msgresponse */
18739#define MC_CMD_VSWITCH_FREE_OUT_LEN 0
18740
18741
18742/***********************************/
18743/* MC_CMD_VSWITCH_QUERY
18744 * read some config of v-switch. For now this command is an empty placeholder.
18745 * It may be used to check if a v-switch is connected to a given EVB port (if
18746 * not, then the command returns ENOENT).
18747 */
18748#define MC_CMD_VSWITCH_QUERY 0x63
18749#undef MC_CMD_0x63_PRIVILEGE_CTG
18750
18751#define MC_CMD_0x63_PRIVILEGE_CTG SRIOV_CTG_GENERAL
18752
18753/* MC_CMD_VSWITCH_QUERY_IN msgrequest */
18754#define MC_CMD_VSWITCH_QUERY_IN_LEN 4
18755/* The port to which the v-switch is connected. */
18756#define MC_CMD_VSWITCH_QUERY_IN_UPSTREAM_PORT_ID_OFST 0
18757#define MC_CMD_VSWITCH_QUERY_IN_UPSTREAM_PORT_ID_LEN 4
18758
18759/* MC_CMD_VSWITCH_QUERY_OUT msgresponse */
18760#define MC_CMD_VSWITCH_QUERY_OUT_LEN 0
18761
18762
18763/***********************************/
18764/* MC_CMD_VPORT_ALLOC
18765 * allocate a v-port.
18766 */
18767#define MC_CMD_VPORT_ALLOC 0x96
18768#undef MC_CMD_0x96_PRIVILEGE_CTG
18769
18770#define MC_CMD_0x96_PRIVILEGE_CTG SRIOV_CTG_GENERAL
18771
18772/* MC_CMD_VPORT_ALLOC_IN msgrequest */
18773#define MC_CMD_VPORT_ALLOC_IN_LEN 20
18774/* The port to which the v-switch is connected. */
18775#define MC_CMD_VPORT_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
18776#define MC_CMD_VPORT_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4
18777/* The type of the new v-port. */
18778#define MC_CMD_VPORT_ALLOC_IN_TYPE_OFST 4
18779#define MC_CMD_VPORT_ALLOC_IN_TYPE_LEN 4
18780/* enum: VLAN (obsolete) */
18781#define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VLAN 0x1
18782/* enum: VEB (obsolete) */
18783#define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VEB 0x2
18784/* enum: VEPA (obsolete) */
18785#define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VEPA 0x3
18786/* enum: A normal v-port receives packets which match a specified MAC and/or
18787 * VLAN.
18788 */
18789#define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_NORMAL 0x4
18790/* enum: An expansion v-port packets traffic which don't match any other
18791 * v-port.
18792 */
18793#define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_EXPANSION 0x5
18794/* enum: An test v-port receives packets which match any filters installed by
18795 * its downstream components.
18796 */
18797#define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_TEST 0x6
18798/* Flags controlling v-port creation */
18799#define MC_CMD_VPORT_ALLOC_IN_FLAGS_OFST 8
18800#define MC_CMD_VPORT_ALLOC_IN_FLAGS_LEN 4
18801#define MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_OFST 8
18802#define MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_LBN 0
18803#define MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_WIDTH 1
18804#define MC_CMD_VPORT_ALLOC_IN_FLAG_VLAN_RESTRICT_OFST 8
18805#define MC_CMD_VPORT_ALLOC_IN_FLAG_VLAN_RESTRICT_LBN 1
18806#define MC_CMD_VPORT_ALLOC_IN_FLAG_VLAN_RESTRICT_WIDTH 1
18807/* The number of VLAN tags to insert/remove. An error will be returned if
18808 * incompatible with the number of VLAN tags specified for the upstream
18809 * v-switch.
18810 */
18811#define MC_CMD_VPORT_ALLOC_IN_NUM_VLAN_TAGS_OFST 12
18812#define MC_CMD_VPORT_ALLOC_IN_NUM_VLAN_TAGS_LEN 4
18813/* The actual VLAN tags to insert/remove */
18814#define MC_CMD_VPORT_ALLOC_IN_VLAN_TAGS_OFST 16
18815#define MC_CMD_VPORT_ALLOC_IN_VLAN_TAGS_LEN 4
18816#define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_OFST 16
18817#define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_LBN 0
18818#define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_WIDTH 16
18819#define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_1_OFST 16
18820#define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_1_LBN 16
18821#define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_1_WIDTH 16
18822
18823/* MC_CMD_VPORT_ALLOC_OUT msgresponse */
18824#define MC_CMD_VPORT_ALLOC_OUT_LEN 4
18825/* The handle of the new v-port */
18826#define MC_CMD_VPORT_ALLOC_OUT_VPORT_ID_OFST 0
18827#define MC_CMD_VPORT_ALLOC_OUT_VPORT_ID_LEN 4
18828
18829
18830/***********************************/
18831/* MC_CMD_VPORT_FREE
18832 * de-allocate a v-port.
18833 */
18834#define MC_CMD_VPORT_FREE 0x97
18835#undef MC_CMD_0x97_PRIVILEGE_CTG
18836
18837#define MC_CMD_0x97_PRIVILEGE_CTG SRIOV_CTG_GENERAL
18838
18839/* MC_CMD_VPORT_FREE_IN msgrequest */
18840#define MC_CMD_VPORT_FREE_IN_LEN 4
18841/* The handle of the v-port */
18842#define MC_CMD_VPORT_FREE_IN_VPORT_ID_OFST 0
18843#define MC_CMD_VPORT_FREE_IN_VPORT_ID_LEN 4
18844
18845/* MC_CMD_VPORT_FREE_OUT msgresponse */
18846#define MC_CMD_VPORT_FREE_OUT_LEN 0
18847
18848
18849/***********************************/
18850/* MC_CMD_VADAPTOR_ALLOC
18851 * allocate a v-adaptor.
18852 */
18853#define MC_CMD_VADAPTOR_ALLOC 0x98
18854#undef MC_CMD_0x98_PRIVILEGE_CTG
18855
18856#define MC_CMD_0x98_PRIVILEGE_CTG SRIOV_CTG_GENERAL
18857
18858/* MC_CMD_VADAPTOR_ALLOC_IN msgrequest */
18859#define MC_CMD_VADAPTOR_ALLOC_IN_LEN 30
18860/* The port to connect to the v-adaptor's port. */
18861#define MC_CMD_VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
18862#define MC_CMD_VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4
18863/* Flags controlling v-adaptor creation */
18864#define MC_CMD_VADAPTOR_ALLOC_IN_FLAGS_OFST 8
18865#define MC_CMD_VADAPTOR_ALLOC_IN_FLAGS_LEN 4
18866#define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_OFST 8
18867#define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_LBN 0
18868#define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_WIDTH 1
18869#define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 8
18870#define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 1
18871#define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
18872/* The number of VLAN tags to strip on receive */
18873#define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLANS_OFST 12
18874#define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLANS_LEN 4
18875/* The number of VLAN tags to transparently insert/remove. */
18876#define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLAN_TAGS_OFST 16
18877#define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLAN_TAGS_LEN 4
18878/* The actual VLAN tags to insert/remove */
18879#define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAGS_OFST 20
18880#define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAGS_LEN 4
18881#define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_0_OFST 20
18882#define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_0_LBN 0
18883#define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_0_WIDTH 16
18884#define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_1_OFST 20
18885#define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_1_LBN 16
18886#define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_1_WIDTH 16
18887/* The MAC address to assign to this v-adaptor */
18888#define MC_CMD_VADAPTOR_ALLOC_IN_MACADDR_OFST 24
18889#define MC_CMD_VADAPTOR_ALLOC_IN_MACADDR_LEN 6
18890/* enum: Derive the MAC address from the upstream port */
18891#define MC_CMD_VADAPTOR_ALLOC_IN_AUTO_MAC 0x0
18892
18893/* MC_CMD_VADAPTOR_ALLOC_OUT msgresponse */
18894#define MC_CMD_VADAPTOR_ALLOC_OUT_LEN 0
18895
18896
18897/***********************************/
18898/* MC_CMD_VADAPTOR_FREE
18899 * de-allocate a v-adaptor.
18900 */
18901#define MC_CMD_VADAPTOR_FREE 0x99
18902#undef MC_CMD_0x99_PRIVILEGE_CTG
18903
18904#define MC_CMD_0x99_PRIVILEGE_CTG SRIOV_CTG_GENERAL
18905
18906/* MC_CMD_VADAPTOR_FREE_IN msgrequest */
18907#define MC_CMD_VADAPTOR_FREE_IN_LEN 4
18908/* The port to which the v-adaptor is connected. */
18909#define MC_CMD_VADAPTOR_FREE_IN_UPSTREAM_PORT_ID_OFST 0
18910#define MC_CMD_VADAPTOR_FREE_IN_UPSTREAM_PORT_ID_LEN 4
18911
18912/* MC_CMD_VADAPTOR_FREE_OUT msgresponse */
18913#define MC_CMD_VADAPTOR_FREE_OUT_LEN 0
18914
18915
18916/***********************************/
18917/* MC_CMD_VADAPTOR_SET_MAC
18918 * assign a new MAC address to a v-adaptor.
18919 */
18920#define MC_CMD_VADAPTOR_SET_MAC 0x5d
18921#undef MC_CMD_0x5d_PRIVILEGE_CTG
18922
18923#define MC_CMD_0x5d_PRIVILEGE_CTG SRIOV_CTG_GENERAL
18924
18925/* MC_CMD_VADAPTOR_SET_MAC_IN msgrequest */
18926#define MC_CMD_VADAPTOR_SET_MAC_IN_LEN 10
18927/* The port to which the v-adaptor is connected. */
18928#define MC_CMD_VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID_OFST 0
18929#define MC_CMD_VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID_LEN 4
18930/* The new MAC address to assign to this v-adaptor */
18931#define MC_CMD_VADAPTOR_SET_MAC_IN_MACADDR_OFST 4
18932#define MC_CMD_VADAPTOR_SET_MAC_IN_MACADDR_LEN 6
18933
18934/* MC_CMD_VADAPTOR_SET_MAC_OUT msgresponse */
18935#define MC_CMD_VADAPTOR_SET_MAC_OUT_LEN 0
18936
18937
18938/***********************************/
18939/* MC_CMD_VADAPTOR_GET_MAC
18940 * read the MAC address assigned to a v-adaptor.
18941 */
18942#define MC_CMD_VADAPTOR_GET_MAC 0x5e
18943#undef MC_CMD_0x5e_PRIVILEGE_CTG
18944
18945#define MC_CMD_0x5e_PRIVILEGE_CTG SRIOV_CTG_GENERAL
18946
18947/* MC_CMD_VADAPTOR_GET_MAC_IN msgrequest */
18948#define MC_CMD_VADAPTOR_GET_MAC_IN_LEN 4
18949/* The port to which the v-adaptor is connected. */
18950#define MC_CMD_VADAPTOR_GET_MAC_IN_UPSTREAM_PORT_ID_OFST 0
18951#define MC_CMD_VADAPTOR_GET_MAC_IN_UPSTREAM_PORT_ID_LEN 4
18952
18953/* MC_CMD_VADAPTOR_GET_MAC_OUT msgresponse */
18954#define MC_CMD_VADAPTOR_GET_MAC_OUT_LEN 6
18955/* The MAC address assigned to this v-adaptor */
18956#define MC_CMD_VADAPTOR_GET_MAC_OUT_MACADDR_OFST 0
18957#define MC_CMD_VADAPTOR_GET_MAC_OUT_MACADDR_LEN 6
18958
18959
18960/***********************************/
18961/* MC_CMD_VADAPTOR_QUERY
18962 * read some config of v-adaptor.
18963 */
18964#define MC_CMD_VADAPTOR_QUERY 0x61
18965#undef MC_CMD_0x61_PRIVILEGE_CTG
18966
18967#define MC_CMD_0x61_PRIVILEGE_CTG SRIOV_CTG_GENERAL
18968
18969/* MC_CMD_VADAPTOR_QUERY_IN msgrequest */
18970#define MC_CMD_VADAPTOR_QUERY_IN_LEN 4
18971/* The port to which the v-adaptor is connected. */
18972#define MC_CMD_VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID_OFST 0
18973#define MC_CMD_VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID_LEN 4
18974
18975/* MC_CMD_VADAPTOR_QUERY_OUT msgresponse */
18976#define MC_CMD_VADAPTOR_QUERY_OUT_LEN 12
18977/* The EVB port flags as defined at MC_CMD_VPORT_ALLOC. */
18978#define MC_CMD_VADAPTOR_QUERY_OUT_PORT_FLAGS_OFST 0
18979#define MC_CMD_VADAPTOR_QUERY_OUT_PORT_FLAGS_LEN 4
18980/* The v-adaptor flags as defined at MC_CMD_VADAPTOR_ALLOC. */
18981#define MC_CMD_VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS_OFST 4
18982#define MC_CMD_VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS_LEN 4
18983/* The number of VLAN tags that may still be added */
18984#define MC_CMD_VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_OFST 8
18985#define MC_CMD_VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_LEN 4
18986
18987
18988/***********************************/
18989/* MC_CMD_EVB_PORT_ASSIGN
18990 * assign a port to a PCI function.
18991 */
18992#define MC_CMD_EVB_PORT_ASSIGN 0x9a
18993#undef MC_CMD_0x9a_PRIVILEGE_CTG
18994
18995#define MC_CMD_0x9a_PRIVILEGE_CTG SRIOV_CTG_GENERAL
18996
18997/* MC_CMD_EVB_PORT_ASSIGN_IN msgrequest */
18998#define MC_CMD_EVB_PORT_ASSIGN_IN_LEN 8
18999/* The port to assign. */
19000#define MC_CMD_EVB_PORT_ASSIGN_IN_PORT_ID_OFST 0
19001#define MC_CMD_EVB_PORT_ASSIGN_IN_PORT_ID_LEN 4
19002/* The target function to modify. */
19003#define MC_CMD_EVB_PORT_ASSIGN_IN_FUNCTION_OFST 4
19004#define MC_CMD_EVB_PORT_ASSIGN_IN_FUNCTION_LEN 4
19005#define MC_CMD_EVB_PORT_ASSIGN_IN_PF_OFST 4
19006#define MC_CMD_EVB_PORT_ASSIGN_IN_PF_LBN 0
19007#define MC_CMD_EVB_PORT_ASSIGN_IN_PF_WIDTH 16
19008#define MC_CMD_EVB_PORT_ASSIGN_IN_VF_OFST 4
19009#define MC_CMD_EVB_PORT_ASSIGN_IN_VF_LBN 16
19010#define MC_CMD_EVB_PORT_ASSIGN_IN_VF_WIDTH 16
19011
19012/* MC_CMD_EVB_PORT_ASSIGN_OUT msgresponse */
19013#define MC_CMD_EVB_PORT_ASSIGN_OUT_LEN 0
19014
19015
19016/***********************************/
19017/* MC_CMD_RDWR_A64_REGIONS
19018 * Assign the 64 bit region addresses.
19019 */
19020#define MC_CMD_RDWR_A64_REGIONS 0x9b
19021#undef MC_CMD_0x9b_PRIVILEGE_CTG
19022
19023#define MC_CMD_0x9b_PRIVILEGE_CTG SRIOV_CTG_ADMIN
19024
19025/* MC_CMD_RDWR_A64_REGIONS_IN msgrequest */
19026#define MC_CMD_RDWR_A64_REGIONS_IN_LEN 17
19027#define MC_CMD_RDWR_A64_REGIONS_IN_REGION0_OFST 0
19028#define MC_CMD_RDWR_A64_REGIONS_IN_REGION0_LEN 4
19029#define MC_CMD_RDWR_A64_REGIONS_IN_REGION1_OFST 4
19030#define MC_CMD_RDWR_A64_REGIONS_IN_REGION1_LEN 4
19031#define MC_CMD_RDWR_A64_REGIONS_IN_REGION2_OFST 8
19032#define MC_CMD_RDWR_A64_REGIONS_IN_REGION2_LEN 4
19033#define MC_CMD_RDWR_A64_REGIONS_IN_REGION3_OFST 12
19034#define MC_CMD_RDWR_A64_REGIONS_IN_REGION3_LEN 4
19035/* Write enable bits 0-3, set to write, clear to read. */
19036#define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_LBN 128
19037#define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_WIDTH 4
19038#define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_BYTE_OFST 16
19039#define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_BYTE_LEN 1
19040
19041/* MC_CMD_RDWR_A64_REGIONS_OUT msgresponse: This data always included
19042 * regardless of state of write bits in the request.
19043 */
19044#define MC_CMD_RDWR_A64_REGIONS_OUT_LEN 16
19045#define MC_CMD_RDWR_A64_REGIONS_OUT_REGION0_OFST 0
19046#define MC_CMD_RDWR_A64_REGIONS_OUT_REGION0_LEN 4
19047#define MC_CMD_RDWR_A64_REGIONS_OUT_REGION1_OFST 4
19048#define MC_CMD_RDWR_A64_REGIONS_OUT_REGION1_LEN 4
19049#define MC_CMD_RDWR_A64_REGIONS_OUT_REGION2_OFST 8
19050#define MC_CMD_RDWR_A64_REGIONS_OUT_REGION2_LEN 4
19051#define MC_CMD_RDWR_A64_REGIONS_OUT_REGION3_OFST 12
19052#define MC_CMD_RDWR_A64_REGIONS_OUT_REGION3_LEN 4
19053
19054
19055/***********************************/
19056/* MC_CMD_ONLOAD_STACK_ALLOC
19057 * Allocate an Onload stack ID.
19058 */
19059#define MC_CMD_ONLOAD_STACK_ALLOC 0x9c
19060#undef MC_CMD_0x9c_PRIVILEGE_CTG
19061
19062#define MC_CMD_0x9c_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
19063
19064/* MC_CMD_ONLOAD_STACK_ALLOC_IN msgrequest */
19065#define MC_CMD_ONLOAD_STACK_ALLOC_IN_LEN 4
19066/* The handle of the owning upstream port */
19067#define MC_CMD_ONLOAD_STACK_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
19068#define MC_CMD_ONLOAD_STACK_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4
19069
19070/* MC_CMD_ONLOAD_STACK_ALLOC_OUT msgresponse */
19071#define MC_CMD_ONLOAD_STACK_ALLOC_OUT_LEN 4
19072/* The handle of the new Onload stack */
19073#define MC_CMD_ONLOAD_STACK_ALLOC_OUT_ONLOAD_STACK_ID_OFST 0
19074#define MC_CMD_ONLOAD_STACK_ALLOC_OUT_ONLOAD_STACK_ID_LEN 4
19075
19076
19077/***********************************/
19078/* MC_CMD_ONLOAD_STACK_FREE
19079 * Free an Onload stack ID.
19080 */
19081#define MC_CMD_ONLOAD_STACK_FREE 0x9d
19082#undef MC_CMD_0x9d_PRIVILEGE_CTG
19083
19084#define MC_CMD_0x9d_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
19085
19086/* MC_CMD_ONLOAD_STACK_FREE_IN msgrequest */
19087#define MC_CMD_ONLOAD_STACK_FREE_IN_LEN 4
19088/* The handle of the Onload stack */
19089#define MC_CMD_ONLOAD_STACK_FREE_IN_ONLOAD_STACK_ID_OFST 0
19090#define MC_CMD_ONLOAD_STACK_FREE_IN_ONLOAD_STACK_ID_LEN 4
19091
19092/* MC_CMD_ONLOAD_STACK_FREE_OUT msgresponse */
19093#define MC_CMD_ONLOAD_STACK_FREE_OUT_LEN 0
19094
19095
19096/***********************************/
19097/* MC_CMD_RSS_CONTEXT_ALLOC
19098 * Allocate an RSS context.
19099 */
19100#define MC_CMD_RSS_CONTEXT_ALLOC 0x9e
19101#undef MC_CMD_0x9e_PRIVILEGE_CTG
19102
19103#define MC_CMD_0x9e_PRIVILEGE_CTG SRIOV_CTG_GENERAL
19104
19105/* MC_CMD_RSS_CONTEXT_ALLOC_IN msgrequest */
19106#define MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN 12
19107/* The handle of the owning upstream port */
19108#define MC_CMD_RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
19109#define MC_CMD_RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4
19110/* The type of context to allocate */
19111#define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_OFST 4
19112#define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_LEN 4
19113/* enum: Allocate a context for exclusive use. The key and indirection table
19114 * must be explicitly configured.
19115 */
19116#define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE 0x0
19117/* enum: Allocate a context for shared use; this will spread across a range of
19118 * queues, but the key and indirection table are pre-configured and may not be
19119 * changed. For this mode, NUM_QUEUES must 2, 4, 8, 16, 32 or 64.
19120 */
19121#define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED 0x1
19122/* enum: Allocate a context to spread evenly across an arbitrary number of
19123 * queues. No indirection table space is allocated for this context. (EF100 and
19124 * later)
19125 */
19126#define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EVEN_SPREADING 0x2
19127/* Number of queues spanned by this context. For exclusive contexts this must
19128 * be in the range 1 to RSS_MAX_INDIRECTION_QUEUES, where
19129 * RSS_MAX_INDIRECTION_QUEUES is queried from MC_CMD_GET_CAPABILITIES_V9 or if
19130 * V9 is not supported then RSS_MAX_INDIRECTION_QUEUES is 64. Valid entries in
19131 * the indirection table will be in the range 0 to NUM_QUEUES-1. For even-
19132 * spreading contexts this must be in the range 1 to
19133 * RSS_MAX_EVEN_SPREADING_QUEUES as queried from MC_CMD_GET_CAPABILITIES. Note
19134 * that specifying NUM_QUEUES = 1 will not perform any spreading but may still
19135 * be useful as a way of obtaining the Toeplitz hash.
19136 */
19137#define MC_CMD_RSS_CONTEXT_ALLOC_IN_NUM_QUEUES_OFST 8
19138#define MC_CMD_RSS_CONTEXT_ALLOC_IN_NUM_QUEUES_LEN 4
19139
19140/* MC_CMD_RSS_CONTEXT_ALLOC_V2_IN msgrequest */
19141#define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_LEN 16
19142/* The handle of the owning upstream port */
19143#define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_UPSTREAM_PORT_ID_OFST 0
19144#define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_UPSTREAM_PORT_ID_LEN 4
19145/* The type of context to allocate */
19146#define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_TYPE_OFST 4
19147#define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_TYPE_LEN 4
19148/* enum: Allocate a context for exclusive use. The key and indirection table
19149 * must be explicitly configured.
19150 */
19151#define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_TYPE_EXCLUSIVE 0x0
19152/* enum: Allocate a context for shared use; this will spread across a range of
19153 * queues, but the key and indirection table are pre-configured and may not be
19154 * changed. For this mode, NUM_QUEUES must 2, 4, 8, 16, 32 or 64.
19155 */
19156#define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_TYPE_SHARED 0x1
19157/* enum: Allocate a context to spread evenly across an arbitrary number of
19158 * queues. No indirection table space is allocated for this context. (EF100 and
19159 * later)
19160 */
19161#define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_TYPE_EVEN_SPREADING 0x2
19162/* Number of queues spanned by this context. For exclusive contexts this must
19163 * be in the range 1 to RSS_MAX_INDIRECTION_QUEUES, where
19164 * RSS_MAX_INDIRECTION_QUEUES is queried from MC_CMD_GET_CAPABILITIES_V9 or if
19165 * V9 is not supported then RSS_MAX_INDIRECTION_QUEUES is 64. Valid entries in
19166 * the indirection table will be in the range 0 to NUM_QUEUES-1. For even-
19167 * spreading contexts this must be in the range 1 to
19168 * RSS_MAX_EVEN_SPREADING_QUEUES as queried from MC_CMD_GET_CAPABILITIES. Note
19169 * that specifying NUM_QUEUES = 1 will not perform any spreading but may still
19170 * be useful as a way of obtaining the Toeplitz hash.
19171 */
19172#define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_NUM_QUEUES_OFST 8
19173#define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_NUM_QUEUES_LEN 4
19174/* Size of indirection table to be allocated to this context from the pool.
19175 * Must be a power of 2. The minimum and maximum table size can be queried
19176 * using MC_CMD_GET_CAPABILITIES_V9. If there is not enough space remaining in
19177 * the common pool to allocate the requested table size, due to allocating
19178 * table space to other RSS contexts, then the command will fail with
19179 * MC_CMD_ERR_ENOSPC.
19180 */
19181#define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_INDIRECTION_TABLE_SIZE_OFST 12
19182#define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_INDIRECTION_TABLE_SIZE_LEN 4
19183
19184/* MC_CMD_RSS_CONTEXT_ALLOC_OUT msgresponse */
19185#define MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN 4
19186/* The handle of the new RSS context. This should be considered opaque to the
19187 * host, although a value of 0xFFFFFFFF is guaranteed never to be a valid
19188 * handle.
19189 */
19190#define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_OFST 0
19191#define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_LEN 4
19192/* enum: guaranteed invalid RSS context handle value */
19193#define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_INVALID 0xffffffff
19194
19195
19196/***********************************/
19197/* MC_CMD_RSS_CONTEXT_FREE
19198 * Free an RSS context.
19199 */
19200#define MC_CMD_RSS_CONTEXT_FREE 0x9f
19201#undef MC_CMD_0x9f_PRIVILEGE_CTG
19202
19203#define MC_CMD_0x9f_PRIVILEGE_CTG SRIOV_CTG_GENERAL
19204
19205/* MC_CMD_RSS_CONTEXT_FREE_IN msgrequest */
19206#define MC_CMD_RSS_CONTEXT_FREE_IN_LEN 4
19207/* The handle of the RSS context */
19208#define MC_CMD_RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID_OFST 0
19209#define MC_CMD_RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID_LEN 4
19210
19211/* MC_CMD_RSS_CONTEXT_FREE_OUT msgresponse */
19212#define MC_CMD_RSS_CONTEXT_FREE_OUT_LEN 0
19213
19214
19215/***********************************/
19216/* MC_CMD_RSS_CONTEXT_SET_KEY
19217 * Set the Toeplitz hash key for an RSS context.
19218 */
19219#define MC_CMD_RSS_CONTEXT_SET_KEY 0xa0
19220#undef MC_CMD_0xa0_PRIVILEGE_CTG
19221
19222#define MC_CMD_0xa0_PRIVILEGE_CTG SRIOV_CTG_GENERAL
19223
19224/* MC_CMD_RSS_CONTEXT_SET_KEY_IN msgrequest */
19225#define MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN 44
19226/* The handle of the RSS context */
19227#define MC_CMD_RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID_OFST 0
19228#define MC_CMD_RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID_LEN 4
19229/* The 40-byte Toeplitz hash key (TBD endianness issues?) */
19230#define MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_OFST 4
19231#define MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN 40
19232
19233/* MC_CMD_RSS_CONTEXT_SET_KEY_OUT msgresponse */
19234#define MC_CMD_RSS_CONTEXT_SET_KEY_OUT_LEN 0
19235
19236
19237/***********************************/
19238/* MC_CMD_RSS_CONTEXT_GET_KEY
19239 * Get the Toeplitz hash key for an RSS context.
19240 */
19241#define MC_CMD_RSS_CONTEXT_GET_KEY 0xa1
19242#undef MC_CMD_0xa1_PRIVILEGE_CTG
19243
19244#define MC_CMD_0xa1_PRIVILEGE_CTG SRIOV_CTG_GENERAL
19245
19246/* MC_CMD_RSS_CONTEXT_GET_KEY_IN msgrequest */
19247#define MC_CMD_RSS_CONTEXT_GET_KEY_IN_LEN 4
19248/* The handle of the RSS context */
19249#define MC_CMD_RSS_CONTEXT_GET_KEY_IN_RSS_CONTEXT_ID_OFST 0
19250#define MC_CMD_RSS_CONTEXT_GET_KEY_IN_RSS_CONTEXT_ID_LEN 4
19251
19252/* MC_CMD_RSS_CONTEXT_GET_KEY_OUT msgresponse */
19253#define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_LEN 44
19254/* The 40-byte Toeplitz hash key (TBD endianness issues?) */
19255#define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY_OFST 4
19256#define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY_LEN 40
19257
19258
19259/***********************************/
19260/* MC_CMD_RSS_CONTEXT_SET_TABLE
19261 * Set the indirection table for an RSS context. This command should only be
19262 * used with indirection tables containing 128 entries, which is the default
19263 * when the RSS context is allocated without specifying a table size.
19264 */
19265#define MC_CMD_RSS_CONTEXT_SET_TABLE 0xa2
19266#undef MC_CMD_0xa2_PRIVILEGE_CTG
19267
19268#define MC_CMD_0xa2_PRIVILEGE_CTG SRIOV_CTG_GENERAL
19269
19270/* MC_CMD_RSS_CONTEXT_SET_TABLE_IN msgrequest */
19271#define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN 132
19272/* The handle of the RSS context */
19273#define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID_OFST 0
19274#define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID_LEN 4
19275/* The 128-byte indirection table (1 byte per entry) */
19276#define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_OFST 4
19277#define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN 128
19278
19279/* MC_CMD_RSS_CONTEXT_SET_TABLE_OUT msgresponse */
19280#define MC_CMD_RSS_CONTEXT_SET_TABLE_OUT_LEN 0
19281
19282
19283/***********************************/
19284/* MC_CMD_RSS_CONTEXT_GET_TABLE
19285 * Get the indirection table for an RSS context. This command should only be
19286 * used with indirection tables containing 128 entries, which is the default
19287 * when the RSS context is allocated without specifying a table size.
19288 */
19289#define MC_CMD_RSS_CONTEXT_GET_TABLE 0xa3
19290#undef MC_CMD_0xa3_PRIVILEGE_CTG
19291
19292#define MC_CMD_0xa3_PRIVILEGE_CTG SRIOV_CTG_GENERAL
19293
19294/* MC_CMD_RSS_CONTEXT_GET_TABLE_IN msgrequest */
19295#define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_LEN 4
19296/* The handle of the RSS context */
19297#define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_RSS_CONTEXT_ID_OFST 0
19298#define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_RSS_CONTEXT_ID_LEN 4
19299
19300/* MC_CMD_RSS_CONTEXT_GET_TABLE_OUT msgresponse */
19301#define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_LEN 132
19302/* The 128-byte indirection table (1 byte per entry) */
19303#define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_OFST 4
19304#define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_LEN 128
19305
19306
19307/***********************************/
19308/* MC_CMD_RSS_CONTEXT_WRITE_TABLE
19309 * Write a portion of a selectable-size indirection table for an RSS context.
19310 * This command must be used instead of MC_CMD_RSS_CONTEXT_SET_TABLE if the
19311 * RSS_SELECTABLE_TABLE_SIZE bit is set in MC_CMD_GET_CAPABILITIES.
19312 */
19313#define MC_CMD_RSS_CONTEXT_WRITE_TABLE 0x13e
19314#undef MC_CMD_0x13e_PRIVILEGE_CTG
19315
19316#define MC_CMD_0x13e_PRIVILEGE_CTG SRIOV_CTG_GENERAL
19317
19318/* MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN msgrequest */
19319#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_LENMIN 8
19320#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_LENMAX 252
19321#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_LENMAX_MCDI2 1020
19322#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_LEN(num) (4+4*(num))
19323#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_ENTRIES_NUM(len) (((len)-4)/4)
19324/* The handle of the RSS context */
19325#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_RSS_CONTEXT_ID_OFST 0
19326#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_RSS_CONTEXT_ID_LEN 4
19327/* An array of index-value pairs to be written to the table. Structure is
19328 * MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY.
19329 */
19330#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_ENTRIES_OFST 4
19331#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_ENTRIES_LEN 4
19332#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_ENTRIES_MINNUM 1
19333#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_ENTRIES_MAXNUM 62
19334#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_ENTRIES_MAXNUM_MCDI2 254
19335
19336/* MC_CMD_RSS_CONTEXT_WRITE_TABLE_OUT msgresponse */
19337#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_OUT_LEN 0
19338
19339/* MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY structuredef */
19340#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_LEN 4
19341/* The index of the table entry to be written. */
19342#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_INDEX_OFST 0
19343#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_INDEX_LEN 2
19344#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_INDEX_LBN 0
19345#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_INDEX_WIDTH 16
19346/* The value to write into the table entry. */
19347#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_VALUE_OFST 2
19348#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_VALUE_LEN 2
19349#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_VALUE_LBN 16
19350#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_VALUE_WIDTH 16
19351
19352
19353/***********************************/
19354/* MC_CMD_RSS_CONTEXT_READ_TABLE
19355 * Read a portion of a selectable-size indirection table for an RSS context.
19356 * This command must be used instead of MC_CMD_RSS_CONTEXT_GET_TABLE if the
19357 * RSS_SELECTABLE_TABLE_SIZE bit is set in MC_CMD_GET_CAPABILITIES.
19358 */
19359#define MC_CMD_RSS_CONTEXT_READ_TABLE 0x13f
19360#undef MC_CMD_0x13f_PRIVILEGE_CTG
19361
19362#define MC_CMD_0x13f_PRIVILEGE_CTG SRIOV_CTG_GENERAL
19363
19364/* MC_CMD_RSS_CONTEXT_READ_TABLE_IN msgrequest */
19365#define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_LENMIN 6
19366#define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_LENMAX 252
19367#define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_LENMAX_MCDI2 1020
19368#define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_LEN(num) (4+2*(num))
19369#define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_INDICES_NUM(len) (((len)-4)/2)
19370/* The handle of the RSS context */
19371#define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_RSS_CONTEXT_ID_OFST 0
19372#define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_RSS_CONTEXT_ID_LEN 4
19373/* An array containing the indices of the entries to be read. */
19374#define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_INDICES_OFST 4
19375#define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_INDICES_LEN 2
19376#define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_INDICES_MINNUM 1
19377#define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_INDICES_MAXNUM 124
19378#define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_INDICES_MAXNUM_MCDI2 508
19379
19380/* MC_CMD_RSS_CONTEXT_READ_TABLE_OUT msgresponse */
19381#define MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_LENMIN 2
19382#define MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_LENMAX 252
19383#define MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_LENMAX_MCDI2 1020
19384#define MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_LEN(num) (0+2*(num))
19385#define MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_DATA_NUM(len) (((len)-0)/2)
19386/* A buffer containing the requested entries read from the table. */
19387#define MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_DATA_OFST 0
19388#define MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_DATA_LEN 2
19389#define MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_DATA_MINNUM 1
19390#define MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_DATA_MAXNUM 126
19391#define MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_DATA_MAXNUM_MCDI2 510
19392
19393
19394/***********************************/
19395/* MC_CMD_RSS_CONTEXT_SET_FLAGS
19396 * Set various control flags for an RSS context.
19397 */
19398#define MC_CMD_RSS_CONTEXT_SET_FLAGS 0xe1
19399#undef MC_CMD_0xe1_PRIVILEGE_CTG
19400
19401#define MC_CMD_0xe1_PRIVILEGE_CTG SRIOV_CTG_GENERAL
19402
19403/* MC_CMD_RSS_CONTEXT_SET_FLAGS_IN msgrequest */
19404#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_LEN 8
19405/* The handle of the RSS context */
19406#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID_OFST 0
19407#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID_LEN 4
19408/* Hash control flags. The _EN bits are always supported, but new modes are
19409 * available when ADDITIONAL_RSS_MODES is reported by MC_CMD_GET_CAPABILITIES:
19410 * in this case, the MODE fields may be set to non-zero values, and will take
19411 * effect regardless of the settings of the _EN flags. See the RSS_MODE
19412 * structure for the meaning of the mode bits. Drivers must check the
19413 * capability before trying to set any _MODE fields, as older firmware will
19414 * reject any attempt to set the FLAGS field to a value > 0xff with EINVAL. In
19415 * the case where all the _MODE flags are zero, the _EN flags take effect,
19416 * providing backward compatibility for existing drivers. (Setting all _MODE
19417 * *and* all _EN flags to zero is valid, to disable RSS spreading for that
19418 * particular packet type.)
19419 */
19420#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_FLAGS_OFST 4
19421#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_FLAGS_LEN 4
19422#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_OFST 4
19423#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_LBN 0
19424#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_WIDTH 1
19425#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_OFST 4
19426#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_LBN 1
19427#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_WIDTH 1
19428#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_OFST 4
19429#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_LBN 2
19430#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_WIDTH 1
19431#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_OFST 4
19432#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_LBN 3
19433#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_WIDTH 1
19434#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_OFST 4
19435#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_LBN 4
19436#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_WIDTH 4
19437#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_OFST 4
19438#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_LBN 8
19439#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_WIDTH 4
19440#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE_OFST 4
19441#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE_LBN 12
19442#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE_WIDTH 4
19443#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_OFST 4
19444#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_LBN 16
19445#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_WIDTH 4
19446#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_OFST 4
19447#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_LBN 20
19448#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_WIDTH 4
19449#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE_OFST 4
19450#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE_LBN 24
19451#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE_WIDTH 4
19452#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_OFST 4
19453#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_LBN 28
19454#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_WIDTH 4
19455
19456/* MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT msgresponse */
19457#define MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT_LEN 0
19458
19459
19460/***********************************/
19461/* MC_CMD_RSS_CONTEXT_GET_FLAGS
19462 * Get various control flags for an RSS context.
19463 */
19464#define MC_CMD_RSS_CONTEXT_GET_FLAGS 0xe2
19465#undef MC_CMD_0xe2_PRIVILEGE_CTG
19466
19467#define MC_CMD_0xe2_PRIVILEGE_CTG SRIOV_CTG_GENERAL
19468
19469/* MC_CMD_RSS_CONTEXT_GET_FLAGS_IN msgrequest */
19470#define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_LEN 4
19471/* The handle of the RSS context */
19472#define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_RSS_CONTEXT_ID_OFST 0
19473#define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_RSS_CONTEXT_ID_LEN 4
19474
19475/* MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT msgresponse */
19476#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN 8
19477/* Hash control flags. If all _MODE bits are zero (which will always be true
19478 * for older firmware which does not report the ADDITIONAL_RSS_MODES
19479 * capability), the _EN bits report the state. If any _MODE bits are non-zero
19480 * (which will only be true when the firmware reports ADDITIONAL_RSS_MODES)
19481 * then the _EN bits should be disregarded, although the _MODE flags are
19482 * guaranteed to be consistent with the _EN flags for a freshly-allocated RSS
19483 * context and in the case where the _EN flags were used in the SET. This
19484 * provides backward compatibility: old drivers will not be attempting to
19485 * derive any meaning from the _MODE bits (and can never set them to any value
19486 * not representable by the _EN bits); new drivers can always determine the
19487 * mode by looking only at the _MODE bits; the value returned by a GET can
19488 * always be used for a SET regardless of old/new driver vs. old/new firmware.
19489 */
19490#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_OFST 4
19491#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_LEN 4
19492#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_OFST 4
19493#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_LBN 0
19494#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_WIDTH 1
19495#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_OFST 4
19496#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_LBN 1
19497#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_WIDTH 1
19498#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_OFST 4
19499#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_LBN 2
19500#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_WIDTH 1
19501#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_OFST 4
19502#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_LBN 3
19503#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_WIDTH 1
19504#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_RESERVED_OFST 4
19505#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_RESERVED_LBN 4
19506#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_RESERVED_WIDTH 4
19507#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_OFST 4
19508#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_LBN 8
19509#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_WIDTH 4
19510#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_OFST 4
19511#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_LBN 12
19512#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_WIDTH 4
19513#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_OFST 4
19514#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_LBN 16
19515#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_WIDTH 4
19516#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_OFST 4
19517#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_LBN 20
19518#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_WIDTH 4
19519#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_OFST 4
19520#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_LBN 24
19521#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_WIDTH 4
19522#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_OFST 4
19523#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_LBN 28
19524#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_WIDTH 4
19525
19526
19527/***********************************/
19528/* MC_CMD_DOT1P_MAPPING_ALLOC
19529 * Allocate a .1p mapping.
19530 */
19531#define MC_CMD_DOT1P_MAPPING_ALLOC 0xa4
19532#undef MC_CMD_0xa4_PRIVILEGE_CTG
19533
19534#define MC_CMD_0xa4_PRIVILEGE_CTG SRIOV_CTG_ADMIN
19535
19536/* MC_CMD_DOT1P_MAPPING_ALLOC_IN msgrequest */
19537#define MC_CMD_DOT1P_MAPPING_ALLOC_IN_LEN 8
19538/* The handle of the owning upstream port */
19539#define MC_CMD_DOT1P_MAPPING_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
19540#define MC_CMD_DOT1P_MAPPING_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4
19541/* Number of queues spanned by this mapping, in the range 1-64; valid fixed
19542 * offsets in the mapping table will be in the range 0 to NUM_QUEUES-1, and
19543 * referenced RSS contexts must span no more than this number.
19544 */
19545#define MC_CMD_DOT1P_MAPPING_ALLOC_IN_NUM_QUEUES_OFST 4
19546#define MC_CMD_DOT1P_MAPPING_ALLOC_IN_NUM_QUEUES_LEN 4
19547
19548/* MC_CMD_DOT1P_MAPPING_ALLOC_OUT msgresponse */
19549#define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_LEN 4
19550/* The handle of the new .1p mapping. This should be considered opaque to the
19551 * host, although a value of 0xFFFFFFFF is guaranteed never to be a valid
19552 * handle.
19553 */
19554#define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_OFST 0
19555#define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_LEN 4
19556/* enum: guaranteed invalid .1p mapping handle value */
19557#define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_INVALID 0xffffffff
19558
19559
19560/***********************************/
19561/* MC_CMD_DOT1P_MAPPING_FREE
19562 * Free a .1p mapping.
19563 */
19564#define MC_CMD_DOT1P_MAPPING_FREE 0xa5
19565#undef MC_CMD_0xa5_PRIVILEGE_CTG
19566
19567#define MC_CMD_0xa5_PRIVILEGE_CTG SRIOV_CTG_ADMIN
19568
19569/* MC_CMD_DOT1P_MAPPING_FREE_IN msgrequest */
19570#define MC_CMD_DOT1P_MAPPING_FREE_IN_LEN 4
19571/* The handle of the .1p mapping */
19572#define MC_CMD_DOT1P_MAPPING_FREE_IN_DOT1P_MAPPING_ID_OFST 0
19573#define MC_CMD_DOT1P_MAPPING_FREE_IN_DOT1P_MAPPING_ID_LEN 4
19574
19575/* MC_CMD_DOT1P_MAPPING_FREE_OUT msgresponse */
19576#define MC_CMD_DOT1P_MAPPING_FREE_OUT_LEN 0
19577
19578
19579/***********************************/
19580/* MC_CMD_DOT1P_MAPPING_SET_TABLE
19581 * Set the mapping table for a .1p mapping.
19582 */
19583#define MC_CMD_DOT1P_MAPPING_SET_TABLE 0xa6
19584#undef MC_CMD_0xa6_PRIVILEGE_CTG
19585
19586#define MC_CMD_0xa6_PRIVILEGE_CTG SRIOV_CTG_ADMIN
19587
19588/* MC_CMD_DOT1P_MAPPING_SET_TABLE_IN msgrequest */
19589#define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_LEN 36
19590/* The handle of the .1p mapping */
19591#define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_DOT1P_MAPPING_ID_OFST 0
19592#define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_DOT1P_MAPPING_ID_LEN 4
19593/* Per-priority mappings (1 32-bit word per entry - an offset or RSS context
19594 * handle)
19595 */
19596#define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_MAPPING_TABLE_OFST 4
19597#define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_MAPPING_TABLE_LEN 32
19598
19599/* MC_CMD_DOT1P_MAPPING_SET_TABLE_OUT msgresponse */
19600#define MC_CMD_DOT1P_MAPPING_SET_TABLE_OUT_LEN 0
19601
19602
19603/***********************************/
19604/* MC_CMD_DOT1P_MAPPING_GET_TABLE
19605 * Get the mapping table for a .1p mapping.
19606 */
19607#define MC_CMD_DOT1P_MAPPING_GET_TABLE 0xa7
19608#undef MC_CMD_0xa7_PRIVILEGE_CTG
19609
19610#define MC_CMD_0xa7_PRIVILEGE_CTG SRIOV_CTG_ADMIN
19611
19612/* MC_CMD_DOT1P_MAPPING_GET_TABLE_IN msgrequest */
19613#define MC_CMD_DOT1P_MAPPING_GET_TABLE_IN_LEN 4
19614/* The handle of the .1p mapping */
19615#define MC_CMD_DOT1P_MAPPING_GET_TABLE_IN_DOT1P_MAPPING_ID_OFST 0
19616#define MC_CMD_DOT1P_MAPPING_GET_TABLE_IN_DOT1P_MAPPING_ID_LEN 4
19617
19618/* MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT msgresponse */
19619#define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_LEN 36
19620/* Per-priority mappings (1 32-bit word per entry - an offset or RSS context
19621 * handle)
19622 */
19623#define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_MAPPING_TABLE_OFST 4
19624#define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_MAPPING_TABLE_LEN 32
19625
19626
19627/***********************************/
19628/* MC_CMD_GET_VECTOR_CFG
19629 * Get Interrupt Vector config for this PF.
19630 */
19631#define MC_CMD_GET_VECTOR_CFG 0xbf
19632#undef MC_CMD_0xbf_PRIVILEGE_CTG
19633
19634#define MC_CMD_0xbf_PRIVILEGE_CTG SRIOV_CTG_GENERAL
19635
19636/* MC_CMD_GET_VECTOR_CFG_IN msgrequest */
19637#define MC_CMD_GET_VECTOR_CFG_IN_LEN 0
19638
19639/* MC_CMD_GET_VECTOR_CFG_OUT msgresponse */
19640#define MC_CMD_GET_VECTOR_CFG_OUT_LEN 12
19641/* Base absolute interrupt vector number. */
19642#define MC_CMD_GET_VECTOR_CFG_OUT_VEC_BASE_OFST 0
19643#define MC_CMD_GET_VECTOR_CFG_OUT_VEC_BASE_LEN 4
19644/* Number of interrupt vectors allocate to this PF. */
19645#define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_PF_OFST 4
19646#define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_PF_LEN 4
19647/* Number of interrupt vectors to allocate per VF. */
19648#define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_VF_OFST 8
19649#define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_VF_LEN 4
19650
19651
19652/***********************************/
19653/* MC_CMD_SET_VECTOR_CFG
19654 * Set Interrupt Vector config for this PF.
19655 */
19656#define MC_CMD_SET_VECTOR_CFG 0xc0
19657#undef MC_CMD_0xc0_PRIVILEGE_CTG
19658
19659#define MC_CMD_0xc0_PRIVILEGE_CTG SRIOV_CTG_GENERAL
19660
19661/* MC_CMD_SET_VECTOR_CFG_IN msgrequest */
19662#define MC_CMD_SET_VECTOR_CFG_IN_LEN 12
19663/* Base absolute interrupt vector number, or MC_CMD_RESOURCE_INSTANCE_ANY to
19664 * let the system find a suitable base.
19665 */
19666#define MC_CMD_SET_VECTOR_CFG_IN_VEC_BASE_OFST 0
19667#define MC_CMD_SET_VECTOR_CFG_IN_VEC_BASE_LEN 4
19668/* Number of interrupt vectors allocate to this PF. */
19669#define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_PF_OFST 4
19670#define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_PF_LEN 4
19671/* Number of interrupt vectors to allocate per VF. */
19672#define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_VF_OFST 8
19673#define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_VF_LEN 4
19674
19675/* MC_CMD_SET_VECTOR_CFG_OUT msgresponse */
19676#define MC_CMD_SET_VECTOR_CFG_OUT_LEN 0
19677
19678
19679/***********************************/
19680/* MC_CMD_VPORT_ADD_MAC_ADDRESS
19681 * Add a MAC address to a v-port
19682 */
19683#define MC_CMD_VPORT_ADD_MAC_ADDRESS 0xa8
19684#undef MC_CMD_0xa8_PRIVILEGE_CTG
19685
19686#define MC_CMD_0xa8_PRIVILEGE_CTG SRIOV_CTG_GENERAL
19687
19688/* MC_CMD_VPORT_ADD_MAC_ADDRESS_IN msgrequest */
19689#define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN 10
19690/* The handle of the v-port */
19691#define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID_OFST 0
19692#define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID_LEN 4
19693/* MAC address to add */
19694#define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_MACADDR_OFST 4
19695#define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_MACADDR_LEN 6
19696
19697/* MC_CMD_VPORT_ADD_MAC_ADDRESS_OUT msgresponse */
19698#define MC_CMD_VPORT_ADD_MAC_ADDRESS_OUT_LEN 0
19699
19700
19701/***********************************/
19702/* MC_CMD_VPORT_DEL_MAC_ADDRESS
19703 * Delete a MAC address from a v-port
19704 */
19705#define MC_CMD_VPORT_DEL_MAC_ADDRESS 0xa9
19706#undef MC_CMD_0xa9_PRIVILEGE_CTG
19707
19708#define MC_CMD_0xa9_PRIVILEGE_CTG SRIOV_CTG_GENERAL
19709
19710/* MC_CMD_VPORT_DEL_MAC_ADDRESS_IN msgrequest */
19711#define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN 10
19712/* The handle of the v-port */
19713#define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID_OFST 0
19714#define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID_LEN 4
19715/* MAC address to add */
19716#define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_MACADDR_OFST 4
19717#define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_MACADDR_LEN 6
19718
19719/* MC_CMD_VPORT_DEL_MAC_ADDRESS_OUT msgresponse */
19720#define MC_CMD_VPORT_DEL_MAC_ADDRESS_OUT_LEN 0
19721
19722
19723/***********************************/
19724/* MC_CMD_VPORT_GET_MAC_ADDRESSES
19725 * Delete a MAC address from a v-port
19726 */
19727#define MC_CMD_VPORT_GET_MAC_ADDRESSES 0xaa
19728#undef MC_CMD_0xaa_PRIVILEGE_CTG
19729
19730#define MC_CMD_0xaa_PRIVILEGE_CTG SRIOV_CTG_GENERAL
19731
19732/* MC_CMD_VPORT_GET_MAC_ADDRESSES_IN msgrequest */
19733#define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN 4
19734/* The handle of the v-port */
19735#define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID_OFST 0
19736#define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID_LEN 4
19737
19738/* MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT msgresponse */
19739#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN 4
19740#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX 250
19741#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX_MCDI2 1018
19742#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LEN(num) (4+6*(num))
19743#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_NUM(len) (((len)-4)/6)
19744/* The number of MAC addresses returned */
19745#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT_OFST 0
19746#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT_LEN 4
19747/* Array of MAC addresses */
19748#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_OFST 4
19749#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_LEN 6
19750#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_MINNUM 0
19751#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_MAXNUM 41
19752#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_MAXNUM_MCDI2 169
19753
19754
19755/***********************************/
19756/* MC_CMD_VPORT_RECONFIGURE
19757 * Replace VLAN tags and/or MAC addresses of an existing v-port. If the v-port
19758 * has already been passed to another function (v-port's user), then that
19759 * function will be reset before applying the changes.
19760 */
19761#define MC_CMD_VPORT_RECONFIGURE 0xeb
19762#undef MC_CMD_0xeb_PRIVILEGE_CTG
19763
19764#define MC_CMD_0xeb_PRIVILEGE_CTG SRIOV_CTG_GENERAL
19765
19766/* MC_CMD_VPORT_RECONFIGURE_IN msgrequest */
19767#define MC_CMD_VPORT_RECONFIGURE_IN_LEN 44
19768/* The handle of the v-port */
19769#define MC_CMD_VPORT_RECONFIGURE_IN_VPORT_ID_OFST 0
19770#define MC_CMD_VPORT_RECONFIGURE_IN_VPORT_ID_LEN 4
19771/* Flags requesting what should be changed. */
19772#define MC_CMD_VPORT_RECONFIGURE_IN_FLAGS_OFST 4
19773#define MC_CMD_VPORT_RECONFIGURE_IN_FLAGS_LEN 4
19774#define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_VLAN_TAGS_OFST 4
19775#define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_VLAN_TAGS_LBN 0
19776#define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_VLAN_TAGS_WIDTH 1
19777#define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_MACADDRS_OFST 4
19778#define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_MACADDRS_LBN 1
19779#define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_MACADDRS_WIDTH 1
19780/* The number of VLAN tags to insert/remove. An error will be returned if
19781 * incompatible with the number of VLAN tags specified for the upstream
19782 * v-switch.
19783 */
19784#define MC_CMD_VPORT_RECONFIGURE_IN_NUM_VLAN_TAGS_OFST 8
19785#define MC_CMD_VPORT_RECONFIGURE_IN_NUM_VLAN_TAGS_LEN 4
19786/* The actual VLAN tags to insert/remove */
19787#define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAGS_OFST 12
19788#define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAGS_LEN 4
19789#define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_0_OFST 12
19790#define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_0_LBN 0
19791#define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_0_WIDTH 16
19792#define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_1_OFST 12
19793#define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_1_LBN 16
19794#define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_1_WIDTH 16
19795/* The number of MAC addresses to add */
19796#define MC_CMD_VPORT_RECONFIGURE_IN_NUM_MACADDRS_OFST 16
19797#define MC_CMD_VPORT_RECONFIGURE_IN_NUM_MACADDRS_LEN 4
19798/* MAC addresses to add */
19799#define MC_CMD_VPORT_RECONFIGURE_IN_MACADDRS_OFST 20
19800#define MC_CMD_VPORT_RECONFIGURE_IN_MACADDRS_LEN 6
19801#define MC_CMD_VPORT_RECONFIGURE_IN_MACADDRS_NUM 4
19802
19803/* MC_CMD_VPORT_RECONFIGURE_OUT msgresponse */
19804#define MC_CMD_VPORT_RECONFIGURE_OUT_LEN 4
19805#define MC_CMD_VPORT_RECONFIGURE_OUT_FLAGS_OFST 0
19806#define MC_CMD_VPORT_RECONFIGURE_OUT_FLAGS_LEN 4
19807#define MC_CMD_VPORT_RECONFIGURE_OUT_RESET_DONE_OFST 0
19808#define MC_CMD_VPORT_RECONFIGURE_OUT_RESET_DONE_LBN 0
19809#define MC_CMD_VPORT_RECONFIGURE_OUT_RESET_DONE_WIDTH 1
19810
19811
19812/***********************************/
19813/* MC_CMD_EVB_PORT_QUERY
19814 * read some config of v-port.
19815 */
19816#define MC_CMD_EVB_PORT_QUERY 0x62
19817#undef MC_CMD_0x62_PRIVILEGE_CTG
19818
19819#define MC_CMD_0x62_PRIVILEGE_CTG SRIOV_CTG_GENERAL
19820
19821/* MC_CMD_EVB_PORT_QUERY_IN msgrequest */
19822#define MC_CMD_EVB_PORT_QUERY_IN_LEN 4
19823/* The handle of the v-port */
19824#define MC_CMD_EVB_PORT_QUERY_IN_PORT_ID_OFST 0
19825#define MC_CMD_EVB_PORT_QUERY_IN_PORT_ID_LEN 4
19826
19827/* MC_CMD_EVB_PORT_QUERY_OUT msgresponse */
19828#define MC_CMD_EVB_PORT_QUERY_OUT_LEN 8
19829/* The EVB port flags as defined at MC_CMD_VPORT_ALLOC. */
19830#define MC_CMD_EVB_PORT_QUERY_OUT_PORT_FLAGS_OFST 0
19831#define MC_CMD_EVB_PORT_QUERY_OUT_PORT_FLAGS_LEN 4
19832/* The number of VLAN tags that may be used on a v-adaptor connected to this
19833 * EVB port.
19834 */
19835#define MC_CMD_EVB_PORT_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_OFST 4
19836#define MC_CMD_EVB_PORT_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_LEN 4
19837
19838
19839/***********************************/
19840/* MC_CMD_DUMP_BUFTBL_ENTRIES
19841 * Dump buffer table entries, mainly for command client debug use. Dumps
19842 * absolute entries, and does not use chunk handles. All entries must be in
19843 * range, and used for q page mapping, Although the latter restriction may be
19844 * lifted in future.
19845 */
19846#define MC_CMD_DUMP_BUFTBL_ENTRIES 0xab
19847#undef MC_CMD_0xab_PRIVILEGE_CTG
19848
19849#define MC_CMD_0xab_PRIVILEGE_CTG SRIOV_CTG_INSECURE
19850
19851/* MC_CMD_DUMP_BUFTBL_ENTRIES_IN msgrequest */
19852#define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_LEN 8
19853/* Index of the first buffer table entry. */
19854#define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_FIRSTID_OFST 0
19855#define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_FIRSTID_LEN 4
19856/* Number of buffer table entries to dump. */
19857#define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_NUMENTRIES_OFST 4
19858#define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_NUMENTRIES_LEN 4
19859
19860/* MC_CMD_DUMP_BUFTBL_ENTRIES_OUT msgresponse */
19861#define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LENMIN 12
19862#define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LENMAX 252
19863#define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LENMAX_MCDI2 1020
19864#define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LEN(num) (0+12*(num))
19865#define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_NUM(len) (((len)-0)/12)
19866/* Raw buffer table entries, layed out as BUFTBL_ENTRY. */
19867#define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_OFST 0
19868#define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_LEN 12
19869#define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_MINNUM 1
19870#define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_MAXNUM 21
19871#define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_MAXNUM_MCDI2 85
19872
19873
19874/***********************************/
19875/* MC_CMD_SET_RXDP_CONFIG
19876 * Set global RXDP configuration settings
19877 */
19878#define MC_CMD_SET_RXDP_CONFIG 0xc1
19879#undef MC_CMD_0xc1_PRIVILEGE_CTG
19880
19881#define MC_CMD_0xc1_PRIVILEGE_CTG SRIOV_CTG_ADMIN
19882
19883/* MC_CMD_SET_RXDP_CONFIG_IN msgrequest */
19884#define MC_CMD_SET_RXDP_CONFIG_IN_LEN 4
19885#define MC_CMD_SET_RXDP_CONFIG_IN_DATA_OFST 0
19886#define MC_CMD_SET_RXDP_CONFIG_IN_DATA_LEN 4
19887#define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_DMA_OFST 0
19888#define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_DMA_LBN 0
19889#define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_DMA_WIDTH 1
19890#define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_LEN_OFST 0
19891#define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_LEN_LBN 1
19892#define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_LEN_WIDTH 2
19893/* enum: pad to 64 bytes */
19894#define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_64 0x0
19895/* enum: pad to 128 bytes (Medford only) */
19896#define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_128 0x1
19897/* enum: pad to 256 bytes (Medford only) */
19898#define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_256 0x2
19899
19900/* MC_CMD_SET_RXDP_CONFIG_OUT msgresponse */
19901#define MC_CMD_SET_RXDP_CONFIG_OUT_LEN 0
19902
19903
19904/***********************************/
19905/* MC_CMD_GET_RXDP_CONFIG
19906 * Get global RXDP configuration settings
19907 */
19908#define MC_CMD_GET_RXDP_CONFIG 0xc2
19909#undef MC_CMD_0xc2_PRIVILEGE_CTG
19910
19911#define MC_CMD_0xc2_PRIVILEGE_CTG SRIOV_CTG_GENERAL
19912
19913/* MC_CMD_GET_RXDP_CONFIG_IN msgrequest */
19914#define MC_CMD_GET_RXDP_CONFIG_IN_LEN 0
19915
19916/* MC_CMD_GET_RXDP_CONFIG_OUT msgresponse */
19917#define MC_CMD_GET_RXDP_CONFIG_OUT_LEN 4
19918#define MC_CMD_GET_RXDP_CONFIG_OUT_DATA_OFST 0
19919#define MC_CMD_GET_RXDP_CONFIG_OUT_DATA_LEN 4
19920#define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_DMA_OFST 0
19921#define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_DMA_LBN 0
19922#define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_DMA_WIDTH 1
19923#define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_LEN_OFST 0
19924#define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_LEN_LBN 1
19925#define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_LEN_WIDTH 2
19926/* Enum values, see field(s): */
19927/* MC_CMD_SET_RXDP_CONFIG/MC_CMD_SET_RXDP_CONFIG_IN/PAD_HOST_LEN */
19928
19929
19930/***********************************/
19931/* MC_CMD_GET_CLOCK
19932 * Return the system and PDCPU clock frequencies.
19933 */
19934#define MC_CMD_GET_CLOCK 0xac
19935#undef MC_CMD_0xac_PRIVILEGE_CTG
19936
19937#define MC_CMD_0xac_PRIVILEGE_CTG SRIOV_CTG_GENERAL
19938
19939/* MC_CMD_GET_CLOCK_IN msgrequest */
19940#define MC_CMD_GET_CLOCK_IN_LEN 0
19941
19942/* MC_CMD_GET_CLOCK_OUT msgresponse */
19943#define MC_CMD_GET_CLOCK_OUT_LEN 8
19944/* System frequency, MHz */
19945#define MC_CMD_GET_CLOCK_OUT_SYS_FREQ_OFST 0
19946#define MC_CMD_GET_CLOCK_OUT_SYS_FREQ_LEN 4
19947/* DPCPU frequency, MHz */
19948#define MC_CMD_GET_CLOCK_OUT_DPCPU_FREQ_OFST 4
19949#define MC_CMD_GET_CLOCK_OUT_DPCPU_FREQ_LEN 4
19950
19951
19952/***********************************/
19953/* MC_CMD_SET_CLOCK
19954 * Control the system and DPCPU clock frequencies. Changes are lost reboot.
19955 */
19956#define MC_CMD_SET_CLOCK 0xad
19957#undef MC_CMD_0xad_PRIVILEGE_CTG
19958
19959#define MC_CMD_0xad_PRIVILEGE_CTG SRIOV_CTG_INSECURE
19960
19961/* MC_CMD_SET_CLOCK_IN msgrequest */
19962#define MC_CMD_SET_CLOCK_IN_LEN 28
19963/* Requested frequency in MHz for system clock domain */
19964#define MC_CMD_SET_CLOCK_IN_SYS_FREQ_OFST 0
19965#define MC_CMD_SET_CLOCK_IN_SYS_FREQ_LEN 4
19966/* enum: Leave the system clock domain frequency unchanged */
19967#define MC_CMD_SET_CLOCK_IN_SYS_DOMAIN_DONT_CHANGE 0x0
19968/* Requested frequency in MHz for inter-core clock domain */
19969#define MC_CMD_SET_CLOCK_IN_ICORE_FREQ_OFST 4
19970#define MC_CMD_SET_CLOCK_IN_ICORE_FREQ_LEN 4
19971/* enum: Leave the inter-core clock domain frequency unchanged */
19972#define MC_CMD_SET_CLOCK_IN_ICORE_DOMAIN_DONT_CHANGE 0x0
19973/* Requested frequency in MHz for DPCPU clock domain */
19974#define MC_CMD_SET_CLOCK_IN_DPCPU_FREQ_OFST 8
19975#define MC_CMD_SET_CLOCK_IN_DPCPU_FREQ_LEN 4
19976/* enum: Leave the DPCPU clock domain frequency unchanged */
19977#define MC_CMD_SET_CLOCK_IN_DPCPU_DOMAIN_DONT_CHANGE 0x0
19978/* Requested frequency in MHz for PCS clock domain */
19979#define MC_CMD_SET_CLOCK_IN_PCS_FREQ_OFST 12
19980#define MC_CMD_SET_CLOCK_IN_PCS_FREQ_LEN 4
19981/* enum: Leave the PCS clock domain frequency unchanged */
19982#define MC_CMD_SET_CLOCK_IN_PCS_DOMAIN_DONT_CHANGE 0x0
19983/* Requested frequency in MHz for MC clock domain */
19984#define MC_CMD_SET_CLOCK_IN_MC_FREQ_OFST 16
19985#define MC_CMD_SET_CLOCK_IN_MC_FREQ_LEN 4
19986/* enum: Leave the MC clock domain frequency unchanged */
19987#define MC_CMD_SET_CLOCK_IN_MC_DOMAIN_DONT_CHANGE 0x0
19988/* Requested frequency in MHz for rmon clock domain */
19989#define MC_CMD_SET_CLOCK_IN_RMON_FREQ_OFST 20
19990#define MC_CMD_SET_CLOCK_IN_RMON_FREQ_LEN 4
19991/* enum: Leave the rmon clock domain frequency unchanged */
19992#define MC_CMD_SET_CLOCK_IN_RMON_DOMAIN_DONT_CHANGE 0x0
19993/* Requested frequency in MHz for vswitch clock domain */
19994#define MC_CMD_SET_CLOCK_IN_VSWITCH_FREQ_OFST 24
19995#define MC_CMD_SET_CLOCK_IN_VSWITCH_FREQ_LEN 4
19996/* enum: Leave the vswitch clock domain frequency unchanged */
19997#define MC_CMD_SET_CLOCK_IN_VSWITCH_DOMAIN_DONT_CHANGE 0x0
19998
19999/* MC_CMD_SET_CLOCK_OUT msgresponse */
20000#define MC_CMD_SET_CLOCK_OUT_LEN 28
20001/* Resulting system frequency in MHz */
20002#define MC_CMD_SET_CLOCK_OUT_SYS_FREQ_OFST 0
20003#define MC_CMD_SET_CLOCK_OUT_SYS_FREQ_LEN 4
20004/* enum: The system clock domain doesn't exist */
20005#define MC_CMD_SET_CLOCK_OUT_SYS_DOMAIN_UNSUPPORTED 0x0
20006/* Resulting inter-core frequency in MHz */
20007#define MC_CMD_SET_CLOCK_OUT_ICORE_FREQ_OFST 4
20008#define MC_CMD_SET_CLOCK_OUT_ICORE_FREQ_LEN 4
20009/* enum: The inter-core clock domain doesn't exist / isn't used */
20010#define MC_CMD_SET_CLOCK_OUT_ICORE_DOMAIN_UNSUPPORTED 0x0
20011/* Resulting DPCPU frequency in MHz */
20012#define MC_CMD_SET_CLOCK_OUT_DPCPU_FREQ_OFST 8
20013#define MC_CMD_SET_CLOCK_OUT_DPCPU_FREQ_LEN 4
20014/* enum: The dpcpu clock domain doesn't exist */
20015#define MC_CMD_SET_CLOCK_OUT_DPCPU_DOMAIN_UNSUPPORTED 0x0
20016/* Resulting PCS frequency in MHz */
20017#define MC_CMD_SET_CLOCK_OUT_PCS_FREQ_OFST 12
20018#define MC_CMD_SET_CLOCK_OUT_PCS_FREQ_LEN 4
20019/* enum: The PCS clock domain doesn't exist / isn't controlled */
20020#define MC_CMD_SET_CLOCK_OUT_PCS_DOMAIN_UNSUPPORTED 0x0
20021/* Resulting MC frequency in MHz */
20022#define MC_CMD_SET_CLOCK_OUT_MC_FREQ_OFST 16
20023#define MC_CMD_SET_CLOCK_OUT_MC_FREQ_LEN 4
20024/* enum: The MC clock domain doesn't exist / isn't controlled */
20025#define MC_CMD_SET_CLOCK_OUT_MC_DOMAIN_UNSUPPORTED 0x0
20026/* Resulting rmon frequency in MHz */
20027#define MC_CMD_SET_CLOCK_OUT_RMON_FREQ_OFST 20
20028#define MC_CMD_SET_CLOCK_OUT_RMON_FREQ_LEN 4
20029/* enum: The rmon clock domain doesn't exist / isn't controlled */
20030#define MC_CMD_SET_CLOCK_OUT_RMON_DOMAIN_UNSUPPORTED 0x0
20031/* Resulting vswitch frequency in MHz */
20032#define MC_CMD_SET_CLOCK_OUT_VSWITCH_FREQ_OFST 24
20033#define MC_CMD_SET_CLOCK_OUT_VSWITCH_FREQ_LEN 4
20034/* enum: The vswitch clock domain doesn't exist / isn't controlled */
20035#define MC_CMD_SET_CLOCK_OUT_VSWITCH_DOMAIN_UNSUPPORTED 0x0
20036
20037
20038/***********************************/
20039/* MC_CMD_DPCPU_RPC
20040 * Send an arbitrary DPCPU message.
20041 */
20042#define MC_CMD_DPCPU_RPC 0xae
20043#undef MC_CMD_0xae_PRIVILEGE_CTG
20044
20045#define MC_CMD_0xae_PRIVILEGE_CTG SRIOV_CTG_INSECURE
20046
20047/* MC_CMD_DPCPU_RPC_IN msgrequest */
20048#define MC_CMD_DPCPU_RPC_IN_LEN 36
20049#define MC_CMD_DPCPU_RPC_IN_CPU_OFST 0
20050#define MC_CMD_DPCPU_RPC_IN_CPU_LEN 4
20051/* enum: RxDPCPU0 */
20052#define MC_CMD_DPCPU_RPC_IN_DPCPU_RX0 0x0
20053/* enum: TxDPCPU0 */
20054#define MC_CMD_DPCPU_RPC_IN_DPCPU_TX0 0x1
20055/* enum: TxDPCPU1 */
20056#define MC_CMD_DPCPU_RPC_IN_DPCPU_TX1 0x2
20057/* enum: RxDPCPU1 (Medford only) */
20058#define MC_CMD_DPCPU_RPC_IN_DPCPU_RX1 0x3
20059/* enum: RxDPCPU (will be for the calling function; for now, just an alias of
20060 * DPCPU_RX0)
20061 */
20062#define MC_CMD_DPCPU_RPC_IN_DPCPU_RX 0x80
20063/* enum: TxDPCPU (will be for the calling function; for now, just an alias of
20064 * DPCPU_TX0)
20065 */
20066#define MC_CMD_DPCPU_RPC_IN_DPCPU_TX 0x81
20067/* First 8 bits [39:32] of DATA are consumed by MC-DPCPU protocol and must be
20068 * initialised to zero
20069 */
20070#define MC_CMD_DPCPU_RPC_IN_DATA_OFST 4
20071#define MC_CMD_DPCPU_RPC_IN_DATA_LEN 32
20072#define MC_CMD_DPCPU_RPC_IN_HDR_CMD_CMDNUM_OFST 4
20073#define MC_CMD_DPCPU_RPC_IN_HDR_CMD_CMDNUM_LBN 8
20074#define MC_CMD_DPCPU_RPC_IN_HDR_CMD_CMDNUM_WIDTH 8
20075#define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_READ 0x6 /* enum */
20076#define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_WRITE 0x7 /* enum */
20077#define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_SELF_TEST 0xc /* enum */
20078#define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_CSR_ACCESS 0xe /* enum */
20079#define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_READ 0x46 /* enum */
20080#define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_WRITE 0x47 /* enum */
20081#define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_SELF_TEST 0x4a /* enum */
20082#define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_CSR_ACCESS 0x4c /* enum */
20083#define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_SET_MC_REPLAY_CNTXT 0x4d /* enum */
20084#define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_OBJID_OFST 4
20085#define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_OBJID_LBN 16
20086#define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_OBJID_WIDTH 16
20087#define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_ADDR_OFST 4
20088#define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_ADDR_LBN 16
20089#define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_ADDR_WIDTH 16
20090#define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_COUNT_OFST 4
20091#define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_COUNT_LBN 48
20092#define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_COUNT_WIDTH 16
20093#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_INFO_OFST 4
20094#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_INFO_LBN 16
20095#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_INFO_WIDTH 240
20096#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_OFST 4
20097#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_LBN 16
20098#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_WIDTH 16
20099#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_STOP_RETURN_RESULT 0x0 /* enum */
20100#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_READ 0x1 /* enum */
20101#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_WRITE 0x2 /* enum */
20102#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_WRITE_READ 0x3 /* enum */
20103#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_PIPELINED_READ 0x4 /* enum */
20104#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_START_DELAY_OFST 4
20105#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_START_DELAY_LBN 48
20106#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_START_DELAY_WIDTH 16
20107#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_RPT_COUNT_OFST 4
20108#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_RPT_COUNT_LBN 64
20109#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_RPT_COUNT_WIDTH 16
20110#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_GAP_DELAY_OFST 4
20111#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_GAP_DELAY_LBN 80
20112#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_GAP_DELAY_WIDTH 16
20113#define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_OFST 4
20114#define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_LBN 16
20115#define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_WIDTH 16
20116#define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_CUT_THROUGH 0x1 /* enum */
20117#define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_STORE_FORWARD 0x2 /* enum */
20118#define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_STORE_FORWARD_FIRST 0x3 /* enum */
20119#define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_CNTXT_OFST 4
20120#define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_CNTXT_LBN 64
20121#define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_CNTXT_WIDTH 16
20122#define MC_CMD_DPCPU_RPC_IN_WDATA_OFST 12
20123#define MC_CMD_DPCPU_RPC_IN_WDATA_LEN 24
20124/* Register data to write. Only valid in write/write-read. */
20125#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_DATA_OFST 16
20126#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_DATA_LEN 4
20127/* Register address. */
20128#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_ADDRESS_OFST 20
20129#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_ADDRESS_LEN 4
20130
20131/* MC_CMD_DPCPU_RPC_OUT msgresponse */
20132#define MC_CMD_DPCPU_RPC_OUT_LEN 36
20133#define MC_CMD_DPCPU_RPC_OUT_RC_OFST 0
20134#define MC_CMD_DPCPU_RPC_OUT_RC_LEN 4
20135/* DATA */
20136#define MC_CMD_DPCPU_RPC_OUT_DATA_OFST 4
20137#define MC_CMD_DPCPU_RPC_OUT_DATA_LEN 32
20138#define MC_CMD_DPCPU_RPC_OUT_HDR_CMD_RESP_ERRCODE_OFST 4
20139#define MC_CMD_DPCPU_RPC_OUT_HDR_CMD_RESP_ERRCODE_LBN 32
20140#define MC_CMD_DPCPU_RPC_OUT_HDR_CMD_RESP_ERRCODE_WIDTH 16
20141#define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_COUNT_OFST 4
20142#define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_COUNT_LBN 48
20143#define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_COUNT_WIDTH 16
20144#define MC_CMD_DPCPU_RPC_OUT_RDATA_OFST 12
20145#define MC_CMD_DPCPU_RPC_OUT_RDATA_LEN 24
20146#define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_1_OFST 12
20147#define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_1_LEN 4
20148#define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_2_OFST 16
20149#define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_2_LEN 4
20150#define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_3_OFST 20
20151#define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_3_LEN 4
20152#define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_4_OFST 24
20153#define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_4_LEN 4
20154
20155
20156/***********************************/
20157/* MC_CMD_TRIGGER_INTERRUPT
20158 * Trigger an interrupt by prodding the BIU.
20159 */
20160#define MC_CMD_TRIGGER_INTERRUPT 0xe3
20161#undef MC_CMD_0xe3_PRIVILEGE_CTG
20162
20163#define MC_CMD_0xe3_PRIVILEGE_CTG SRIOV_CTG_GENERAL
20164
20165/* MC_CMD_TRIGGER_INTERRUPT_IN msgrequest */
20166#define MC_CMD_TRIGGER_INTERRUPT_IN_LEN 4
20167/* Interrupt level relative to base for function. */
20168#define MC_CMD_TRIGGER_INTERRUPT_IN_INTR_LEVEL_OFST 0
20169#define MC_CMD_TRIGGER_INTERRUPT_IN_INTR_LEVEL_LEN 4
20170
20171/* MC_CMD_TRIGGER_INTERRUPT_OUT msgresponse */
20172#define MC_CMD_TRIGGER_INTERRUPT_OUT_LEN 0
20173
20174
20175/***********************************/
20176/* MC_CMD_SHMBOOT_OP
20177 * Special operations to support (for now) shmboot.
20178 */
20179#define MC_CMD_SHMBOOT_OP 0xe6
20180#undef MC_CMD_0xe6_PRIVILEGE_CTG
20181
20182#define MC_CMD_0xe6_PRIVILEGE_CTG SRIOV_CTG_ADMIN
20183
20184/* MC_CMD_SHMBOOT_OP_IN msgrequest */
20185#define MC_CMD_SHMBOOT_OP_IN_LEN 4
20186/* Identifies the operation to perform */
20187#define MC_CMD_SHMBOOT_OP_IN_SHMBOOT_OP_OFST 0
20188#define MC_CMD_SHMBOOT_OP_IN_SHMBOOT_OP_LEN 4
20189/* enum: Copy slave_data section to the slave core. (Greenport only) */
20190#define MC_CMD_SHMBOOT_OP_IN_PUSH_SLAVE_DATA 0x0
20191
20192/* MC_CMD_SHMBOOT_OP_OUT msgresponse */
20193#define MC_CMD_SHMBOOT_OP_OUT_LEN 0
20194
20195
20196/***********************************/
20197/* MC_CMD_CAP_BLK_READ
20198 * Read multiple 64bit words from capture block memory
20199 */
20200#define MC_CMD_CAP_BLK_READ 0xe7
20201#undef MC_CMD_0xe7_PRIVILEGE_CTG
20202
20203#define MC_CMD_0xe7_PRIVILEGE_CTG SRIOV_CTG_INSECURE
20204
20205/* MC_CMD_CAP_BLK_READ_IN msgrequest */
20206#define MC_CMD_CAP_BLK_READ_IN_LEN 12
20207#define MC_CMD_CAP_BLK_READ_IN_CAP_REG_OFST 0
20208#define MC_CMD_CAP_BLK_READ_IN_CAP_REG_LEN 4
20209#define MC_CMD_CAP_BLK_READ_IN_ADDR_OFST 4
20210#define MC_CMD_CAP_BLK_READ_IN_ADDR_LEN 4
20211#define MC_CMD_CAP_BLK_READ_IN_COUNT_OFST 8
20212#define MC_CMD_CAP_BLK_READ_IN_COUNT_LEN 4
20213
20214/* MC_CMD_CAP_BLK_READ_OUT msgresponse */
20215#define MC_CMD_CAP_BLK_READ_OUT_LENMIN 8
20216#define MC_CMD_CAP_BLK_READ_OUT_LENMAX 248
20217#define MC_CMD_CAP_BLK_READ_OUT_LENMAX_MCDI2 1016
20218#define MC_CMD_CAP_BLK_READ_OUT_LEN(num) (0+8*(num))
20219#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_NUM(len) (((len)-0)/8)
20220#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_OFST 0
20221#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_LEN 8
20222#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_LO_OFST 0
20223#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_LO_LEN 4
20224#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_LO_LBN 0
20225#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_LO_WIDTH 32
20226#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_HI_OFST 4
20227#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_HI_LEN 4
20228#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_HI_LBN 32
20229#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_HI_WIDTH 32
20230#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_MINNUM 1
20231#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_MAXNUM 31
20232#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_MAXNUM_MCDI2 127
20233
20234
20235/***********************************/
20236/* MC_CMD_DUMP_DO
20237 * Take a dump of the DUT state
20238 */
20239#define MC_CMD_DUMP_DO 0xe8
20240#undef MC_CMD_0xe8_PRIVILEGE_CTG
20241
20242#define MC_CMD_0xe8_PRIVILEGE_CTG SRIOV_CTG_INSECURE
20243
20244/* MC_CMD_DUMP_DO_IN msgrequest */
20245#define MC_CMD_DUMP_DO_IN_LEN 52
20246#define MC_CMD_DUMP_DO_IN_PADDING_OFST 0
20247#define MC_CMD_DUMP_DO_IN_PADDING_LEN 4
20248#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_OFST 4
20249#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_LEN 4
20250#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM 0x0 /* enum */
20251#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_DEFAULT 0x1 /* enum */
20252#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_TYPE_OFST 8
20253#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_TYPE_LEN 4
20254#define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_NVRAM 0x1 /* enum */
20255#define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_HOST_MEMORY 0x2 /* enum */
20256#define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_HOST_MEMORY_MLI 0x3 /* enum */
20257#define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_UART 0x4 /* enum */
20258#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 12
20259#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_LEN 4
20260#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_OFST 16
20261#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_LEN 4
20262#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 12
20263#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_LEN 4
20264#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 16
20265#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_LEN 4
20266#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 12
20267#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_LEN 4
20268#define MC_CMD_DUMP_DO_IN_HOST_MEMORY_MLI_PAGE_SIZE 0x1000 /* enum */
20269#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 16
20270#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_LEN 4
20271#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 20
20272#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_LEN 4
20273#define MC_CMD_DUMP_DO_IN_HOST_MEMORY_MLI_MAX_DEPTH 0x2 /* enum */
20274#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_OFST 12
20275#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_LEN 4
20276/* enum: The uart port this command was received over (if using a uart
20277 * transport)
20278 */
20279#define MC_CMD_DUMP_DO_IN_UART_PORT_SRC 0xff
20280#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_SIZE_OFST 24
20281#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_SIZE_LEN 4
20282#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_OFST 28
20283#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_LEN 4
20284#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM 0x0 /* enum */
20285#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_NVRAM_DUMP_PARTITION 0x1 /* enum */
20286#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_TYPE_OFST 32
20287#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_TYPE_LEN 4
20288/* Enum values, see field(s): */
20289/* MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */
20290#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 36
20291#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_LEN 4
20292#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_OFST 40
20293#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_LEN 4
20294#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 36
20295#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_LEN 4
20296#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 40
20297#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_LEN 4
20298#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 36
20299#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_LEN 4
20300#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 40
20301#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_LEN 4
20302#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 44
20303#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_LEN 4
20304#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_UART_PORT_OFST 36
20305#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_UART_PORT_LEN 4
20306#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_SIZE_OFST 48
20307#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_SIZE_LEN 4
20308
20309/* MC_CMD_DUMP_DO_OUT msgresponse */
20310#define MC_CMD_DUMP_DO_OUT_LEN 4
20311#define MC_CMD_DUMP_DO_OUT_DUMPFILE_SIZE_OFST 0
20312#define MC_CMD_DUMP_DO_OUT_DUMPFILE_SIZE_LEN 4
20313
20314
20315/***********************************/
20316/* MC_CMD_DUMP_CONFIGURE_UNSOLICITED
20317 * Configure unsolicited dumps
20318 */
20319#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED 0xe9
20320#undef MC_CMD_0xe9_PRIVILEGE_CTG
20321
20322#define MC_CMD_0xe9_PRIVILEGE_CTG SRIOV_CTG_INSECURE
20323
20324/* MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN msgrequest */
20325#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_LEN 52
20326#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_ENABLE_OFST 0
20327#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_ENABLE_LEN 4
20328#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_OFST 4
20329#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_LEN 4
20330/* Enum values, see field(s): */
20331/* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC */
20332#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_TYPE_OFST 8
20333#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_TYPE_LEN 4
20334/* Enum values, see field(s): */
20335/* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */
20336#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 12
20337#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_LEN 4
20338#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_OFST 16
20339#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_LEN 4
20340#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 12
20341#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_LEN 4
20342#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 16
20343#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_LEN 4
20344#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 12
20345#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_LEN 4
20346#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 16
20347#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_LEN 4
20348#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 20
20349#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_LEN 4
20350#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_OFST 12
20351#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_LEN 4
20352#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_SIZE_OFST 24
20353#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_SIZE_LEN 4
20354#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_OFST 28
20355#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_LEN 4
20356/* Enum values, see field(s): */
20357/* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPFILE_DST */
20358#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_TYPE_OFST 32
20359#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_TYPE_LEN 4
20360/* Enum values, see field(s): */
20361/* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */
20362#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 36
20363#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_LEN 4
20364#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_OFST 40
20365#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_LEN 4
20366#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 36
20367#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_LEN 4
20368#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 40
20369#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_LEN 4
20370#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 36
20371#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_LEN 4
20372#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 40
20373#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_LEN 4
20374#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 44
20375#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_LEN 4
20376#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_UART_PORT_OFST 36
20377#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_UART_PORT_LEN 4
20378#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_SIZE_OFST 48
20379#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_SIZE_LEN 4
20380
20381
20382/***********************************/
20383/* MC_CMD_SET_PSU
20384 * Adjusts power supply parameters. This is a warranty-voiding operation.
20385 * Returns: ENOENT if the parameter or rail specified does not exist, EINVAL if
20386 * the parameter is out of range.
20387 */
20388#define MC_CMD_SET_PSU 0xea
20389#undef MC_CMD_0xea_PRIVILEGE_CTG
20390
20391#define MC_CMD_0xea_PRIVILEGE_CTG SRIOV_CTG_INSECURE
20392
20393/* MC_CMD_SET_PSU_IN msgrequest */
20394#define MC_CMD_SET_PSU_IN_LEN 12
20395#define MC_CMD_SET_PSU_IN_PARAM_OFST 0
20396#define MC_CMD_SET_PSU_IN_PARAM_LEN 4
20397#define MC_CMD_SET_PSU_IN_PARAM_SUPPLY_VOLTAGE 0x0 /* enum */
20398#define MC_CMD_SET_PSU_IN_RAIL_OFST 4
20399#define MC_CMD_SET_PSU_IN_RAIL_LEN 4
20400#define MC_CMD_SET_PSU_IN_RAIL_0V9 0x0 /* enum */
20401#define MC_CMD_SET_PSU_IN_RAIL_1V2 0x1 /* enum */
20402/* desired value, eg voltage in mV */
20403#define MC_CMD_SET_PSU_IN_VALUE_OFST 8
20404#define MC_CMD_SET_PSU_IN_VALUE_LEN 4
20405
20406/* MC_CMD_SET_PSU_OUT msgresponse */
20407#define MC_CMD_SET_PSU_OUT_LEN 0
20408
20409
20410/***********************************/
20411/* MC_CMD_GET_FUNCTION_INFO
20412 * Get function information. PF and VF number.
20413 */
20414#define MC_CMD_GET_FUNCTION_INFO 0xec
20415#undef MC_CMD_0xec_PRIVILEGE_CTG
20416
20417#define MC_CMD_0xec_PRIVILEGE_CTG SRIOV_CTG_GENERAL
20418
20419/* MC_CMD_GET_FUNCTION_INFO_IN msgrequest */
20420#define MC_CMD_GET_FUNCTION_INFO_IN_LEN 0
20421
20422/* MC_CMD_GET_FUNCTION_INFO_OUT msgresponse */
20423#define MC_CMD_GET_FUNCTION_INFO_OUT_LEN 8
20424#define MC_CMD_GET_FUNCTION_INFO_OUT_PF_OFST 0
20425#define MC_CMD_GET_FUNCTION_INFO_OUT_PF_LEN 4
20426#define MC_CMD_GET_FUNCTION_INFO_OUT_VF_OFST 4
20427#define MC_CMD_GET_FUNCTION_INFO_OUT_VF_LEN 4
20428
20429/* MC_CMD_GET_FUNCTION_INFO_OUT_V2 msgresponse */
20430#define MC_CMD_GET_FUNCTION_INFO_OUT_V2_LEN 12
20431#define MC_CMD_GET_FUNCTION_INFO_OUT_V2_PF_OFST 0
20432#define MC_CMD_GET_FUNCTION_INFO_OUT_V2_PF_LEN 4
20433#define MC_CMD_GET_FUNCTION_INFO_OUT_V2_VF_OFST 4
20434#define MC_CMD_GET_FUNCTION_INFO_OUT_V2_VF_LEN 4
20435/* Values from PCIE_INTERFACE enumeration. For NICs with a single interface, or
20436 * in the case of a V1 response, this should be HOST_PRIMARY.
20437 */
20438#define MC_CMD_GET_FUNCTION_INFO_OUT_V2_INTF_OFST 8
20439#define MC_CMD_GET_FUNCTION_INFO_OUT_V2_INTF_LEN 4
20440
20441
20442/***********************************/
20443/* MC_CMD_ENABLE_OFFLINE_BIST
20444 * Enters offline BIST mode. All queues are torn down, chip enters quiescent
20445 * mode, calling function gets exclusive MCDI ownership. The only way out is
20446 * reboot.
20447 */
20448#define MC_CMD_ENABLE_OFFLINE_BIST 0xed
20449#undef MC_CMD_0xed_PRIVILEGE_CTG
20450
20451#define MC_CMD_0xed_PRIVILEGE_CTG SRIOV_CTG_ADMIN
20452
20453/* MC_CMD_ENABLE_OFFLINE_BIST_IN msgrequest */
20454#define MC_CMD_ENABLE_OFFLINE_BIST_IN_LEN 0
20455
20456/* MC_CMD_ENABLE_OFFLINE_BIST_OUT msgresponse */
20457#define MC_CMD_ENABLE_OFFLINE_BIST_OUT_LEN 0
20458
20459
20460/***********************************/
20461/* MC_CMD_UART_SEND_DATA
20462 * Send checksummed[sic] block of data over the uart. Response is a placeholder
20463 * should we wish to make this reliable; currently requests are fire-and-
20464 * forget.
20465 */
20466#define MC_CMD_UART_SEND_DATA 0xee
20467#undef MC_CMD_0xee_PRIVILEGE_CTG
20468
20469#define MC_CMD_0xee_PRIVILEGE_CTG SRIOV_CTG_GENERAL
20470
20471/* MC_CMD_UART_SEND_DATA_OUT msgrequest */
20472#define MC_CMD_UART_SEND_DATA_OUT_LENMIN 16
20473#define MC_CMD_UART_SEND_DATA_OUT_LENMAX 252
20474#define MC_CMD_UART_SEND_DATA_OUT_LENMAX_MCDI2 1020
20475#define MC_CMD_UART_SEND_DATA_OUT_LEN(num) (16+1*(num))
20476#define MC_CMD_UART_SEND_DATA_OUT_DATA_NUM(len) (((len)-16)/1)
20477/* CRC32 over OFFSET, LENGTH, RESERVED, DATA */
20478#define MC_CMD_UART_SEND_DATA_OUT_CHECKSUM_OFST 0
20479#define MC_CMD_UART_SEND_DATA_OUT_CHECKSUM_LEN 4
20480/* Offset at which to write the data */
20481#define MC_CMD_UART_SEND_DATA_OUT_OFFSET_OFST 4
20482#define MC_CMD_UART_SEND_DATA_OUT_OFFSET_LEN 4
20483/* Length of data */
20484#define MC_CMD_UART_SEND_DATA_OUT_LENGTH_OFST 8
20485#define MC_CMD_UART_SEND_DATA_OUT_LENGTH_LEN 4
20486/* Reserved for future use */
20487#define MC_CMD_UART_SEND_DATA_OUT_RESERVED_OFST 12
20488#define MC_CMD_UART_SEND_DATA_OUT_RESERVED_LEN 4
20489#define MC_CMD_UART_SEND_DATA_OUT_DATA_OFST 16
20490#define MC_CMD_UART_SEND_DATA_OUT_DATA_LEN 1
20491#define MC_CMD_UART_SEND_DATA_OUT_DATA_MINNUM 0
20492#define MC_CMD_UART_SEND_DATA_OUT_DATA_MAXNUM 236
20493#define MC_CMD_UART_SEND_DATA_OUT_DATA_MAXNUM_MCDI2 1004
20494
20495/* MC_CMD_UART_SEND_DATA_IN msgresponse */
20496#define MC_CMD_UART_SEND_DATA_IN_LEN 0
20497
20498
20499/***********************************/
20500/* MC_CMD_UART_RECV_DATA
20501 * Request checksummed[sic] block of data over the uart. Only a placeholder,
20502 * subject to change and not currently implemented.
20503 */
20504#define MC_CMD_UART_RECV_DATA 0xef
20505#undef MC_CMD_0xef_PRIVILEGE_CTG
20506
20507#define MC_CMD_0xef_PRIVILEGE_CTG SRIOV_CTG_GENERAL
20508
20509/* MC_CMD_UART_RECV_DATA_OUT msgrequest */
20510#define MC_CMD_UART_RECV_DATA_OUT_LEN 16
20511/* CRC32 over OFFSET, LENGTH, RESERVED */
20512#define MC_CMD_UART_RECV_DATA_OUT_CHECKSUM_OFST 0
20513#define MC_CMD_UART_RECV_DATA_OUT_CHECKSUM_LEN 4
20514/* Offset from which to read the data */
20515#define MC_CMD_UART_RECV_DATA_OUT_OFFSET_OFST 4
20516#define MC_CMD_UART_RECV_DATA_OUT_OFFSET_LEN 4
20517/* Length of data */
20518#define MC_CMD_UART_RECV_DATA_OUT_LENGTH_OFST 8
20519#define MC_CMD_UART_RECV_DATA_OUT_LENGTH_LEN 4
20520/* Reserved for future use */
20521#define MC_CMD_UART_RECV_DATA_OUT_RESERVED_OFST 12
20522#define MC_CMD_UART_RECV_DATA_OUT_RESERVED_LEN 4
20523
20524/* MC_CMD_UART_RECV_DATA_IN msgresponse */
20525#define MC_CMD_UART_RECV_DATA_IN_LENMIN 16
20526#define MC_CMD_UART_RECV_DATA_IN_LENMAX 252
20527#define MC_CMD_UART_RECV_DATA_IN_LENMAX_MCDI2 1020
20528#define MC_CMD_UART_RECV_DATA_IN_LEN(num) (16+1*(num))
20529#define MC_CMD_UART_RECV_DATA_IN_DATA_NUM(len) (((len)-16)/1)
20530/* CRC32 over RESERVED1, RESERVED2, RESERVED3, DATA */
20531#define MC_CMD_UART_RECV_DATA_IN_CHECKSUM_OFST 0
20532#define MC_CMD_UART_RECV_DATA_IN_CHECKSUM_LEN 4
20533/* Offset at which to write the data */
20534#define MC_CMD_UART_RECV_DATA_IN_RESERVED1_OFST 4
20535#define MC_CMD_UART_RECV_DATA_IN_RESERVED1_LEN 4
20536/* Length of data */
20537#define MC_CMD_UART_RECV_DATA_IN_RESERVED2_OFST 8
20538#define MC_CMD_UART_RECV_DATA_IN_RESERVED2_LEN 4
20539/* Reserved for future use */
20540#define MC_CMD_UART_RECV_DATA_IN_RESERVED3_OFST 12
20541#define MC_CMD_UART_RECV_DATA_IN_RESERVED3_LEN 4
20542#define MC_CMD_UART_RECV_DATA_IN_DATA_OFST 16
20543#define MC_CMD_UART_RECV_DATA_IN_DATA_LEN 1
20544#define MC_CMD_UART_RECV_DATA_IN_DATA_MINNUM 0
20545#define MC_CMD_UART_RECV_DATA_IN_DATA_MAXNUM 236
20546#define MC_CMD_UART_RECV_DATA_IN_DATA_MAXNUM_MCDI2 1004
20547
20548
20549/***********************************/
20550/* MC_CMD_READ_FUSES
20551 * Read data programmed into the device One-Time-Programmable (OTP) Fuses
20552 */
20553#define MC_CMD_READ_FUSES 0xf0
20554#undef MC_CMD_0xf0_PRIVILEGE_CTG
20555
20556#define MC_CMD_0xf0_PRIVILEGE_CTG SRIOV_CTG_INSECURE
20557
20558/* MC_CMD_READ_FUSES_IN msgrequest */
20559#define MC_CMD_READ_FUSES_IN_LEN 8
20560/* Offset in OTP to read */
20561#define MC_CMD_READ_FUSES_IN_OFFSET_OFST 0
20562#define MC_CMD_READ_FUSES_IN_OFFSET_LEN 4
20563/* Length of data to read in bytes */
20564#define MC_CMD_READ_FUSES_IN_LENGTH_OFST 4
20565#define MC_CMD_READ_FUSES_IN_LENGTH_LEN 4
20566
20567/* MC_CMD_READ_FUSES_OUT msgresponse */
20568#define MC_CMD_READ_FUSES_OUT_LENMIN 4
20569#define MC_CMD_READ_FUSES_OUT_LENMAX 252
20570#define MC_CMD_READ_FUSES_OUT_LENMAX_MCDI2 1020
20571#define MC_CMD_READ_FUSES_OUT_LEN(num) (4+1*(num))
20572#define MC_CMD_READ_FUSES_OUT_DATA_NUM(len) (((len)-4)/1)
20573/* Length of returned OTP data in bytes */
20574#define MC_CMD_READ_FUSES_OUT_LENGTH_OFST 0
20575#define MC_CMD_READ_FUSES_OUT_LENGTH_LEN 4
20576/* Returned data */
20577#define MC_CMD_READ_FUSES_OUT_DATA_OFST 4
20578#define MC_CMD_READ_FUSES_OUT_DATA_LEN 1
20579#define MC_CMD_READ_FUSES_OUT_DATA_MINNUM 0
20580#define MC_CMD_READ_FUSES_OUT_DATA_MAXNUM 248
20581#define MC_CMD_READ_FUSES_OUT_DATA_MAXNUM_MCDI2 1016
20582
20583
20584/***********************************/
20585/* MC_CMD_KR_TUNE
20586 * Get or set KR Serdes RXEQ and TX Driver settings
20587 */
20588#define MC_CMD_KR_TUNE 0xf1
20589#undef MC_CMD_0xf1_PRIVILEGE_CTG
20590
20591#define MC_CMD_0xf1_PRIVILEGE_CTG SRIOV_CTG_ADMIN
20592
20593/* MC_CMD_KR_TUNE_IN msgrequest */
20594#define MC_CMD_KR_TUNE_IN_LENMIN 4
20595#define MC_CMD_KR_TUNE_IN_LENMAX 252
20596#define MC_CMD_KR_TUNE_IN_LENMAX_MCDI2 1020
20597#define MC_CMD_KR_TUNE_IN_LEN(num) (4+4*(num))
20598#define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_NUM(len) (((len)-4)/4)
20599/* Requested operation */
20600#define MC_CMD_KR_TUNE_IN_KR_TUNE_OP_OFST 0
20601#define MC_CMD_KR_TUNE_IN_KR_TUNE_OP_LEN 1
20602/* enum: Get current RXEQ settings */
20603#define MC_CMD_KR_TUNE_IN_RXEQ_GET 0x0
20604/* enum: Override RXEQ settings */
20605#define MC_CMD_KR_TUNE_IN_RXEQ_SET 0x1
20606/* enum: Get current TX Driver settings */
20607#define MC_CMD_KR_TUNE_IN_TXEQ_GET 0x2
20608/* enum: Override TX Driver settings */
20609#define MC_CMD_KR_TUNE_IN_TXEQ_SET 0x3
20610/* enum: Force KR Serdes reset / recalibration */
20611#define MC_CMD_KR_TUNE_IN_RECAL 0x4
20612/* enum: Start KR Serdes Eye diagram plot on a given lane. Lane must have valid
20613 * signal.
20614 */
20615#define MC_CMD_KR_TUNE_IN_START_EYE_PLOT 0x5
20616/* enum: Poll KR Serdes Eye diagram plot. Returns one row of BER data. The
20617 * caller should call this command repeatedly after starting eye plot, until no
20618 * more data is returned.
20619 */
20620#define MC_CMD_KR_TUNE_IN_POLL_EYE_PLOT 0x6
20621/* enum: Read Figure Of Merit (eye quality, higher is better). */
20622#define MC_CMD_KR_TUNE_IN_READ_FOM 0x7
20623/* enum: Start/stop link training frames */
20624#define MC_CMD_KR_TUNE_IN_LINK_TRAIN_RUN 0x8
20625/* enum: Issue KR link training command (control training coefficients) */
20626#define MC_CMD_KR_TUNE_IN_LINK_TRAIN_CMD 0x9
20627/* Align the arguments to 32 bits */
20628#define MC_CMD_KR_TUNE_IN_KR_TUNE_RSVD_OFST 1
20629#define MC_CMD_KR_TUNE_IN_KR_TUNE_RSVD_LEN 3
20630/* Arguments specific to the operation */
20631#define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_OFST 4
20632#define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_LEN 4
20633#define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_MINNUM 0
20634#define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_MAXNUM 62
20635#define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_MAXNUM_MCDI2 254
20636
20637/* MC_CMD_KR_TUNE_OUT msgresponse */
20638#define MC_CMD_KR_TUNE_OUT_LEN 0
20639
20640/* MC_CMD_KR_TUNE_RXEQ_GET_IN msgrequest */
20641#define MC_CMD_KR_TUNE_RXEQ_GET_IN_LEN 4
20642/* Requested operation */
20643#define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_OP_OFST 0
20644#define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_OP_LEN 1
20645/* Align the arguments to 32 bits */
20646#define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_RSVD_OFST 1
20647#define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_RSVD_LEN 3
20648
20649/* MC_CMD_KR_TUNE_RXEQ_GET_OUT msgresponse */
20650#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LENMIN 4
20651#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LENMAX 252
20652#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LENMAX_MCDI2 1020
20653#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LEN(num) (0+4*(num))
20654#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_NUM(len) (((len)-0)/4)
20655/* RXEQ Parameter */
20656#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_OFST 0
20657#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LEN 4
20658#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_MINNUM 1
20659#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_MAXNUM 63
20660#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_MAXNUM_MCDI2 255
20661#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_OFST 0
20662#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_LBN 0
20663#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_WIDTH 8
20664/* enum: Attenuation (0-15, Huntington) */
20665#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_ATT 0x0
20666/* enum: CTLE Boost (0-15, Huntington) */
20667#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_BOOST 0x1
20668/* enum: Edge DFE Tap1 (Huntington - 0 - max negative, 64 - zero, 127 - max
20669 * positive, Medford - 0-31)
20670 */
20671#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP1 0x2
20672/* enum: Edge DFE Tap2 (Huntington - 0 - max negative, 32 - zero, 63 - max
20673 * positive, Medford - 0-31)
20674 */
20675#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP2 0x3
20676/* enum: Edge DFE Tap3 (Huntington - 0 - max negative, 32 - zero, 63 - max
20677 * positive, Medford - 0-16)
20678 */
20679#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP3 0x4
20680/* enum: Edge DFE Tap4 (Huntington - 0 - max negative, 32 - zero, 63 - max
20681 * positive, Medford - 0-16)
20682 */
20683#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP4 0x5
20684/* enum: Edge DFE Tap5 (Huntington - 0 - max negative, 32 - zero, 63 - max
20685 * positive, Medford - 0-16)
20686 */
20687#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP5 0x6
20688/* enum: Edge DFE DLEV (0-128 for Medford) */
20689#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_DLEV 0x7
20690/* enum: Variable Gain Amplifier (0-15, Medford) */
20691#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_VGA 0x8
20692/* enum: CTLE EQ Capacitor (0-15, Medford) */
20693#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_EQC 0x9
20694/* enum: CTLE EQ Resistor (0-7, Medford) */
20695#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_EQRES 0xa
20696/* enum: CTLE gain (0-31, Medford2) */
20697#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_GAIN 0xb
20698/* enum: CTLE pole (0-31, Medford2) */
20699#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_POLE 0xc
20700/* enum: CTLE peaking (0-31, Medford2) */
20701#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_PEAK 0xd
20702/* enum: DFE Tap1 - even path (Medford2 - 6 bit signed (-29 - +29)) */
20703#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP1_EVEN 0xe
20704/* enum: DFE Tap1 - odd path (Medford2 - 6 bit signed (-29 - +29)) */
20705#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP1_ODD 0xf
20706/* enum: DFE Tap2 (Medford2 - 6 bit signed (-20 - +20)) */
20707#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP2 0x10
20708/* enum: DFE Tap3 (Medford2 - 6 bit signed (-20 - +20)) */
20709#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP3 0x11
20710/* enum: DFE Tap4 (Medford2 - 6 bit signed (-20 - +20)) */
20711#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP4 0x12
20712/* enum: DFE Tap5 (Medford2 - 6 bit signed (-24 - +24)) */
20713#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP5 0x13
20714/* enum: DFE Tap6 (Medford2 - 6 bit signed (-24 - +24)) */
20715#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP6 0x14
20716/* enum: DFE Tap7 (Medford2 - 6 bit signed (-24 - +24)) */
20717#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP7 0x15
20718/* enum: DFE Tap8 (Medford2 - 6 bit signed (-24 - +24)) */
20719#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP8 0x16
20720/* enum: DFE Tap9 (Medford2 - 6 bit signed (-24 - +24)) */
20721#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP9 0x17
20722/* enum: DFE Tap10 (Medford2 - 6 bit signed (-24 - +24)) */
20723#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP10 0x18
20724/* enum: DFE Tap11 (Medford2 - 6 bit signed (-24 - +24)) */
20725#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP11 0x19
20726/* enum: DFE Tap12 (Medford2 - 6 bit signed (-24 - +24)) */
20727#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP12 0x1a
20728/* enum: I/Q clk offset (Medford2 - 4 bit signed (-5 - +5))) */
20729#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_IQ_OFF 0x1b
20730/* enum: Negative h1 polarity data sampler offset calibration code, even path
20731 * (Medford2 - 6 bit signed (-29 - +29)))
20732 */
20733#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_H1N_OFF_EVEN 0x1c
20734/* enum: Negative h1 polarity data sampler offset calibration code, odd path
20735 * (Medford2 - 6 bit signed (-29 - +29)))
20736 */
20737#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_H1N_OFF_ODD 0x1d
20738/* enum: Positive h1 polarity data sampler offset calibration code, even path
20739 * (Medford2 - 6 bit signed (-29 - +29)))
20740 */
20741#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_H1P_OFF_EVEN 0x1e
20742/* enum: Positive h1 polarity data sampler offset calibration code, odd path
20743 * (Medford2 - 6 bit signed (-29 - +29)))
20744 */
20745#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_H1P_OFF_ODD 0x1f
20746/* enum: CDR calibration loop code (Medford2) */
20747#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CDR_PVT 0x20
20748/* enum: CDR integral loop code (Medford2) */
20749#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CDR_INTEG 0x21
20750/* enum: CTLE Boost stages - retimer lineside (Medford2 with DS250x retimer - 4
20751 * stages, 2 bits per stage)
20752 */
20753#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_BOOST_RT_LS 0x22
20754/* enum: DFE Tap1 - retimer lineside (Medford2 with DS250x retimer (-31 - 31))
20755 */
20756#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP1_RT_LS 0x23
20757/* enum: DFE Tap2 - retimer lineside (Medford2 with DS250x retimer (-15 - 15))
20758 */
20759#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP2_RT_LS 0x24
20760/* enum: DFE Tap3 - retimer lineside (Medford2 with DS250x retimer (-15 - 15))
20761 */
20762#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP3_RT_LS 0x25
20763/* enum: DFE Tap4 - retimer lineside (Medford2 with DS250x retimer (-15 - 15))
20764 */
20765#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP4_RT_LS 0x26
20766/* enum: DFE Tap5 - retimer lineside (Medford2 with DS250x retimer (-15 - 15))
20767 */
20768#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP5_RT_LS 0x27
20769/* enum: CTLE Boost stages - retimer hostside (Medford2 with DS250x retimer - 4
20770 * stages, 2 bits per stage)
20771 */
20772#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_BOOST_RT_HS 0x28
20773/* enum: DFE Tap1 - retimer hostside (Medford2 with DS250x retimer (-31 - 31))
20774 */
20775#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP1_RT_HS 0x29
20776/* enum: DFE Tap2 - retimer hostside (Medford2 with DS250x retimer (-15 - 15))
20777 */
20778#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP2_RT_HS 0x2a
20779/* enum: DFE Tap3 - retimer hostside (Medford2 with DS250x retimer (-15 - 15))
20780 */
20781#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP3_RT_HS 0x2b
20782/* enum: DFE Tap4 - retimer hostside (Medford2 with DS250x retimer (-15 - 15))
20783 */
20784#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP4_RT_HS 0x2c
20785/* enum: DFE Tap5 - retimer hostside (Medford2 with DS250x retimer (-15 - 15))
20786 */
20787#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP5_RT_HS 0x2d
20788#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_OFST 0
20789#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_LBN 8
20790#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_WIDTH 3
20791#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_0 0x0 /* enum */
20792#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_1 0x1 /* enum */
20793#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_2 0x2 /* enum */
20794#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_3 0x3 /* enum */
20795#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_ALL 0x4 /* enum */
20796#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_OFST 0
20797#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_LBN 11
20798#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_WIDTH 1
20799#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_RESERVED_OFST 0
20800#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_RESERVED_LBN 12
20801#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_RESERVED_WIDTH 4
20802#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_INITIAL_OFST 0
20803#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_INITIAL_LBN 16
20804#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_INITIAL_WIDTH 8
20805#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_OFST 0
20806#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_LBN 24
20807#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8
20808
20809/* MC_CMD_KR_TUNE_RXEQ_SET_IN msgrequest */
20810#define MC_CMD_KR_TUNE_RXEQ_SET_IN_LENMIN 8
20811#define MC_CMD_KR_TUNE_RXEQ_SET_IN_LENMAX 252
20812#define MC_CMD_KR_TUNE_RXEQ_SET_IN_LENMAX_MCDI2 1020
20813#define MC_CMD_KR_TUNE_RXEQ_SET_IN_LEN(num) (4+4*(num))
20814#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_NUM(len) (((len)-4)/4)
20815/* Requested operation */
20816#define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_OP_OFST 0
20817#define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_OP_LEN 1
20818/* Align the arguments to 32 bits */
20819#define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_RSVD_OFST 1
20820#define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_RSVD_LEN 3
20821/* RXEQ Parameter */
20822#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_OFST 4
20823#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LEN 4
20824#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_MINNUM 1
20825#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_MAXNUM 62
20826#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_MAXNUM_MCDI2 254
20827#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_ID_OFST 4
20828#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_ID_LBN 0
20829#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_ID_WIDTH 8
20830/* Enum values, see field(s): */
20831/* MC_CMD_KR_TUNE_RXEQ_GET_OUT/PARAM_ID */
20832#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LANE_OFST 4
20833#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LANE_LBN 8
20834#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LANE_WIDTH 3
20835/* Enum values, see field(s): */
20836/* MC_CMD_KR_TUNE_RXEQ_GET_OUT/PARAM_LANE */
20837#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_OFST 4
20838#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_LBN 11
20839#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_WIDTH 1
20840#define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED_OFST 4
20841#define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED_LBN 12
20842#define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED_WIDTH 4
20843#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_INITIAL_OFST 4
20844#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_INITIAL_LBN 16
20845#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_INITIAL_WIDTH 8
20846#define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED2_OFST 4
20847#define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED2_LBN 24
20848#define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED2_WIDTH 8
20849
20850/* MC_CMD_KR_TUNE_RXEQ_SET_OUT msgresponse */
20851#define MC_CMD_KR_TUNE_RXEQ_SET_OUT_LEN 0
20852
20853/* MC_CMD_KR_TUNE_TXEQ_GET_IN msgrequest */
20854#define MC_CMD_KR_TUNE_TXEQ_GET_IN_LEN 4
20855/* Requested operation */
20856#define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_OP_OFST 0
20857#define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_OP_LEN 1
20858/* Align the arguments to 32 bits */
20859#define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_RSVD_OFST 1
20860#define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_RSVD_LEN 3
20861
20862/* MC_CMD_KR_TUNE_TXEQ_GET_OUT msgresponse */
20863#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LENMIN 4
20864#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LENMAX 252
20865#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LENMAX_MCDI2 1020
20866#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LEN(num) (0+4*(num))
20867#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_NUM(len) (((len)-0)/4)
20868/* TXEQ Parameter */
20869#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_OFST 0
20870#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LEN 4
20871#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_MINNUM 1
20872#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_MAXNUM 63
20873#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_MAXNUM_MCDI2 255
20874#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_ID_OFST 0
20875#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_ID_LBN 0
20876#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_ID_WIDTH 8
20877/* enum: TX Amplitude (Huntington, Medford, Medford2) */
20878#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV 0x0
20879/* enum: De-Emphasis Tap1 Magnitude (0-7) (Huntington) */
20880#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_MODE 0x1
20881/* enum: De-Emphasis Tap1 Fine */
20882#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_DTLEV 0x2
20883/* enum: De-Emphasis Tap2 Magnitude (0-6) (Huntington) */
20884#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_D2 0x3
20885/* enum: De-Emphasis Tap2 Fine (Huntington) */
20886#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_D2TLEV 0x4
20887/* enum: Pre-Emphasis Magnitude (Huntington) */
20888#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_E 0x5
20889/* enum: Pre-Emphasis Fine (Huntington) */
20890#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_ETLEV 0x6
20891/* enum: TX Slew Rate Coarse control (Huntington) */
20892#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_PREDRV_DLY 0x7
20893/* enum: TX Slew Rate Fine control (Huntington) */
20894#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_SR_SET 0x8
20895/* enum: TX Termination Impedance control (Huntington) */
20896#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_RT_SET 0x9
20897/* enum: TX Amplitude Fine control (Medford) */
20898#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV_FINE 0xa
20899/* enum: Pre-cursor Tap (Medford, Medford2) */
20900#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_ADV 0xb
20901/* enum: Post-cursor Tap (Medford, Medford2) */
20902#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_DLY 0xc
20903/* enum: TX Amplitude (Retimer Lineside) */
20904#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV_RT_LS 0xd
20905/* enum: Pre-cursor Tap (Retimer Lineside) */
20906#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_ADV_RT_LS 0xe
20907/* enum: Post-cursor Tap (Retimer Lineside) */
20908#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_DLY_RT_LS 0xf
20909/* enum: TX Amplitude (Retimer Hostside) */
20910#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV_RT_HS 0x10
20911/* enum: Pre-cursor Tap (Retimer Hostside) */
20912#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_ADV_RT_HS 0x11
20913/* enum: Post-cursor Tap (Retimer Hostside) */
20914#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_DLY_RT_HS 0x12
20915#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LANE_OFST 0
20916#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LANE_LBN 8
20917#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LANE_WIDTH 3
20918#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_0 0x0 /* enum */
20919#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_1 0x1 /* enum */
20920#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_2 0x2 /* enum */
20921#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_3 0x3 /* enum */
20922#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_ALL 0x4 /* enum */
20923#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED_OFST 0
20924#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED_LBN 11
20925#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED_WIDTH 5
20926#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_INITIAL_OFST 0
20927#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_INITIAL_LBN 16
20928#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_INITIAL_WIDTH 8
20929#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED2_OFST 0
20930#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED2_LBN 24
20931#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED2_WIDTH 8
20932
20933/* MC_CMD_KR_TUNE_TXEQ_SET_IN msgrequest */
20934#define MC_CMD_KR_TUNE_TXEQ_SET_IN_LENMIN 8
20935#define MC_CMD_KR_TUNE_TXEQ_SET_IN_LENMAX 252
20936#define MC_CMD_KR_TUNE_TXEQ_SET_IN_LENMAX_MCDI2 1020
20937#define MC_CMD_KR_TUNE_TXEQ_SET_IN_LEN(num) (4+4*(num))
20938#define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_NUM(len) (((len)-4)/4)
20939/* Requested operation */
20940#define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_OP_OFST 0
20941#define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_OP_LEN 1
20942/* Align the arguments to 32 bits */
20943#define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_RSVD_OFST 1
20944#define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_RSVD_LEN 3
20945/* TXEQ Parameter */
20946#define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_OFST 4
20947#define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LEN 4
20948#define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_MINNUM 1
20949#define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_MAXNUM 62
20950#define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_MAXNUM_MCDI2 254
20951#define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_ID_OFST 4
20952#define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_ID_LBN 0
20953#define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_ID_WIDTH 8
20954/* Enum values, see field(s): */
20955/* MC_CMD_KR_TUNE_TXEQ_GET_OUT/PARAM_ID */
20956#define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LANE_OFST 4
20957#define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LANE_LBN 8
20958#define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LANE_WIDTH 3
20959/* Enum values, see field(s): */
20960/* MC_CMD_KR_TUNE_TXEQ_GET_OUT/PARAM_LANE */
20961#define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED_OFST 4
20962#define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED_LBN 11
20963#define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED_WIDTH 5
20964#define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_INITIAL_OFST 4
20965#define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_INITIAL_LBN 16
20966#define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_INITIAL_WIDTH 8
20967#define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED2_OFST 4
20968#define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED2_LBN 24
20969#define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED2_WIDTH 8
20970
20971/* MC_CMD_KR_TUNE_TXEQ_SET_OUT msgresponse */
20972#define MC_CMD_KR_TUNE_TXEQ_SET_OUT_LEN 0
20973
20974/* MC_CMD_KR_TUNE_RECAL_IN msgrequest */
20975#define MC_CMD_KR_TUNE_RECAL_IN_LEN 4
20976/* Requested operation */
20977#define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_OP_OFST 0
20978#define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_OP_LEN 1
20979/* Align the arguments to 32 bits */
20980#define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_RSVD_OFST 1
20981#define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_RSVD_LEN 3
20982
20983/* MC_CMD_KR_TUNE_RECAL_OUT msgresponse */
20984#define MC_CMD_KR_TUNE_RECAL_OUT_LEN 0
20985
20986/* MC_CMD_KR_TUNE_START_EYE_PLOT_IN msgrequest */
20987#define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_LEN 8
20988/* Requested operation */
20989#define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_OP_OFST 0
20990#define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_OP_LEN 1
20991/* Align the arguments to 32 bits */
20992#define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_RSVD_OFST 1
20993#define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_RSVD_LEN 3
20994/* Port-relative lane to scan eye on */
20995#define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_LANE_OFST 4
20996#define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_LANE_LEN 4
20997
20998/* MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN msgrequest */
20999#define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LEN 12
21000/* Requested operation */
21001#define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_KR_TUNE_OP_OFST 0
21002#define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_KR_TUNE_OP_LEN 1
21003/* Align the arguments to 32 bits */
21004#define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_KR_TUNE_RSVD_OFST 1
21005#define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_KR_TUNE_RSVD_LEN 3
21006#define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_OFST 4
21007#define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_LEN 4
21008#define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_NUM_OFST 4
21009#define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_NUM_LBN 0
21010#define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_NUM_WIDTH 8
21011#define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_ABS_REL_OFST 4
21012#define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_ABS_REL_LBN 31
21013#define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_ABS_REL_WIDTH 1
21014/* Scan duration / cycle count */
21015#define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_BER_OFST 8
21016#define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_BER_LEN 4
21017
21018/* MC_CMD_KR_TUNE_START_EYE_PLOT_OUT msgresponse */
21019#define MC_CMD_KR_TUNE_START_EYE_PLOT_OUT_LEN 0
21020
21021/* MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN msgrequest */
21022#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_LEN 4
21023/* Requested operation */
21024#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_OP_OFST 0
21025#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_OP_LEN 1
21026/* Align the arguments to 32 bits */
21027#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_RSVD_OFST 1
21028#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_RSVD_LEN 3
21029
21030/* MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT msgresponse */
21031#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LENMIN 0
21032#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LENMAX 252
21033#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LENMAX_MCDI2 1020
21034#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LEN(num) (0+2*(num))
21035#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_NUM(len) (((len)-0)/2)
21036#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_OFST 0
21037#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_LEN 2
21038#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MINNUM 0
21039#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MAXNUM 126
21040#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MAXNUM_MCDI2 510
21041
21042/* MC_CMD_KR_TUNE_READ_FOM_IN msgrequest */
21043#define MC_CMD_KR_TUNE_READ_FOM_IN_LEN 8
21044/* Requested operation */
21045#define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_OP_OFST 0
21046#define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_OP_LEN 1
21047/* Align the arguments to 32 bits */
21048#define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_RSVD_OFST 1
21049#define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_RSVD_LEN 3
21050#define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_OFST 4
21051#define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_LEN 4
21052#define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_NUM_OFST 4
21053#define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_NUM_LBN 0
21054#define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_NUM_WIDTH 8
21055#define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_ABS_REL_OFST 4
21056#define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_ABS_REL_LBN 31
21057#define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_ABS_REL_WIDTH 1
21058
21059/* MC_CMD_KR_TUNE_READ_FOM_OUT msgresponse */
21060#define MC_CMD_KR_TUNE_READ_FOM_OUT_LEN 4
21061#define MC_CMD_KR_TUNE_READ_FOM_OUT_FOM_OFST 0
21062#define MC_CMD_KR_TUNE_READ_FOM_OUT_FOM_LEN 4
21063
21064/* MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN msgrequest */
21065#define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_LEN 8
21066/* Requested operation */
21067#define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_KR_TUNE_OP_OFST 0
21068#define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_KR_TUNE_OP_LEN 1
21069/* Align the arguments to 32 bits */
21070#define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_KR_TUNE_RSVD_OFST 1
21071#define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_KR_TUNE_RSVD_LEN 3
21072#define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_RUN_OFST 4
21073#define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_RUN_LEN 4
21074#define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_STOP 0x0 /* enum */
21075#define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_START 0x1 /* enum */
21076
21077/* MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN msgrequest */
21078#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_LEN 28
21079/* Requested operation */
21080#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_KR_TUNE_OP_OFST 0
21081#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_KR_TUNE_OP_LEN 1
21082/* Align the arguments to 32 bits */
21083#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_KR_TUNE_RSVD_OFST 1
21084#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_KR_TUNE_RSVD_LEN 3
21085#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_LANE_OFST 4
21086#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_LANE_LEN 4
21087/* Set INITIALIZE state */
21088#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_INITIALIZE_OFST 8
21089#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_INITIALIZE_LEN 4
21090/* Set PRESET state */
21091#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_PRESET_OFST 12
21092#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_PRESET_LEN 4
21093/* C(-1) request */
21094#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_CM1_OFST 16
21095#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_CM1_LEN 4
21096#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_REQ_HOLD 0x0 /* enum */
21097#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_REQ_INCREMENT 0x1 /* enum */
21098#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_REQ_DECREMENT 0x2 /* enum */
21099/* C(0) request */
21100#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_C0_OFST 20
21101#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_C0_LEN 4
21102/* Enum values, see field(s): */
21103/* MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN/CM1 */
21104/* C(+1) request */
21105#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_CP1_OFST 24
21106#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_CP1_LEN 4
21107/* Enum values, see field(s): */
21108/* MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN/CM1 */
21109
21110/* MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT msgresponse */
21111#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_LEN 24
21112/* C(-1) status */
21113#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CM1_STATUS_OFST 0
21114#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CM1_STATUS_LEN 4
21115#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_STATUS_NOT_UPDATED 0x0 /* enum */
21116#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_STATUS_UPDATED 0x1 /* enum */
21117#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_STATUS_MINIMUM 0x2 /* enum */
21118#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_STATUS_MAXIMUM 0x3 /* enum */
21119/* C(0) status */
21120#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_C0_STATUS_OFST 4
21121#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_C0_STATUS_LEN 4
21122/* Enum values, see field(s): */
21123/* MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN/CM1 */
21124/* C(+1) status */
21125#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CP1_STATUS_OFST 8
21126#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CP1_STATUS_LEN 4
21127/* Enum values, see field(s): */
21128/* MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN/CM1 */
21129/* C(-1) value */
21130#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CM1_VALUE_OFST 12
21131#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CM1_VALUE_LEN 4
21132/* C(0) value */
21133#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_C0_VALUE_OFST 16
21134#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_C0_VALUE_LEN 4
21135/* C(+1) status */
21136#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CP1_VALUE_OFST 20
21137#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CP1_VALUE_LEN 4
21138
21139
21140/***********************************/
21141/* MC_CMD_PCIE_TUNE
21142 * Get or set PCIE Serdes RXEQ and TX Driver settings
21143 */
21144#define MC_CMD_PCIE_TUNE 0xf2
21145#undef MC_CMD_0xf2_PRIVILEGE_CTG
21146
21147#define MC_CMD_0xf2_PRIVILEGE_CTG SRIOV_CTG_ADMIN
21148
21149/* MC_CMD_PCIE_TUNE_IN msgrequest */
21150#define MC_CMD_PCIE_TUNE_IN_LENMIN 4
21151#define MC_CMD_PCIE_TUNE_IN_LENMAX 252
21152#define MC_CMD_PCIE_TUNE_IN_LENMAX_MCDI2 1020
21153#define MC_CMD_PCIE_TUNE_IN_LEN(num) (4+4*(num))
21154#define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_NUM(len) (((len)-4)/4)
21155/* Requested operation */
21156#define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_OP_OFST 0
21157#define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_OP_LEN 1
21158/* enum: Get current RXEQ settings */
21159#define MC_CMD_PCIE_TUNE_IN_RXEQ_GET 0x0
21160/* enum: Override RXEQ settings */
21161#define MC_CMD_PCIE_TUNE_IN_RXEQ_SET 0x1
21162/* enum: Get current TX Driver settings */
21163#define MC_CMD_PCIE_TUNE_IN_TXEQ_GET 0x2
21164/* enum: Override TX Driver settings */
21165#define MC_CMD_PCIE_TUNE_IN_TXEQ_SET 0x3
21166/* enum: Start PCIe Serdes Eye diagram plot on a given lane. */
21167#define MC_CMD_PCIE_TUNE_IN_START_EYE_PLOT 0x5
21168/* enum: Poll PCIe Serdes Eye diagram plot. Returns one row of BER data. The
21169 * caller should call this command repeatedly after starting eye plot, until no
21170 * more data is returned.
21171 */
21172#define MC_CMD_PCIE_TUNE_IN_POLL_EYE_PLOT 0x6
21173/* enum: Enable the SERDES BIST and set it to generate a 200MHz square wave */
21174#define MC_CMD_PCIE_TUNE_IN_BIST_SQUARE_WAVE 0x7
21175/* Align the arguments to 32 bits */
21176#define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_RSVD_OFST 1
21177#define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_RSVD_LEN 3
21178/* Arguments specific to the operation */
21179#define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_OFST 4
21180#define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_LEN 4
21181#define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_MINNUM 0
21182#define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_MAXNUM 62
21183#define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_MAXNUM_MCDI2 254
21184
21185/* MC_CMD_PCIE_TUNE_OUT msgresponse */
21186#define MC_CMD_PCIE_TUNE_OUT_LEN 0
21187
21188/* MC_CMD_PCIE_TUNE_RXEQ_GET_IN msgrequest */
21189#define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_LEN 4
21190/* Requested operation */
21191#define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_OP_OFST 0
21192#define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_OP_LEN 1
21193/* Align the arguments to 32 bits */
21194#define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_RSVD_OFST 1
21195#define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_RSVD_LEN 3
21196
21197/* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT msgresponse */
21198#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LENMIN 4
21199#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LENMAX 252
21200#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LENMAX_MCDI2 1020
21201#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LEN(num) (0+4*(num))
21202#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_NUM(len) (((len)-0)/4)
21203/* RXEQ Parameter */
21204#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_OFST 0
21205#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LEN 4
21206#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_MINNUM 1
21207#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_MAXNUM 63
21208#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_MAXNUM_MCDI2 255
21209#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_ID_OFST 0
21210#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_ID_LBN 0
21211#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_ID_WIDTH 8
21212/* enum: Attenuation (0-15) */
21213#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_ATT 0x0
21214/* enum: CTLE Boost (0-15) */
21215#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_BOOST 0x1
21216/* enum: DFE Tap1 (0 - max negative, 64 - zero, 127 - max positive) */
21217#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP1 0x2
21218/* enum: DFE Tap2 (0 - max negative, 32 - zero, 63 - max positive) */
21219#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP2 0x3
21220/* enum: DFE Tap3 (0 - max negative, 32 - zero, 63 - max positive) */
21221#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP3 0x4
21222/* enum: DFE Tap4 (0 - max negative, 32 - zero, 63 - max positive) */
21223#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP4 0x5
21224/* enum: DFE Tap5 (0 - max negative, 32 - zero, 63 - max positive) */
21225#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP5 0x6
21226/* enum: DFE DLev */
21227#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_DLEV 0x7
21228/* enum: Figure of Merit */
21229#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_FOM 0x8
21230/* enum: CTLE EQ Capacitor (HF Gain) */
21231#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_CTLE_EQC 0x9
21232/* enum: CTLE EQ Resistor (DC Gain) */
21233#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_CTLE_EQRES 0xa
21234#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LANE_OFST 0
21235#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LANE_LBN 8
21236#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LANE_WIDTH 5
21237#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_0 0x0 /* enum */
21238#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_1 0x1 /* enum */
21239#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_2 0x2 /* enum */
21240#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_3 0x3 /* enum */
21241#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_4 0x4 /* enum */
21242#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_5 0x5 /* enum */
21243#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_6 0x6 /* enum */
21244#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_7 0x7 /* enum */
21245#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_8 0x8 /* enum */
21246#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_9 0x9 /* enum */
21247#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_10 0xa /* enum */
21248#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_11 0xb /* enum */
21249#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_12 0xc /* enum */
21250#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_13 0xd /* enum */
21251#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_14 0xe /* enum */
21252#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_15 0xf /* enum */
21253#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_ALL 0x10 /* enum */
21254#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_OFST 0
21255#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_LBN 13
21256#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_WIDTH 1
21257#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_RESERVED_OFST 0
21258#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_RESERVED_LBN 14
21259#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_RESERVED_WIDTH 10
21260#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_OFST 0
21261#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_LBN 24
21262#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8
21263
21264/* MC_CMD_PCIE_TUNE_RXEQ_SET_IN msgrequest */
21265#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_LENMIN 8
21266#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_LENMAX 252
21267#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_LENMAX_MCDI2 1020
21268#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_LEN(num) (4+4*(num))
21269#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_NUM(len) (((len)-4)/4)
21270/* Requested operation */
21271#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_OP_OFST 0
21272#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_OP_LEN 1
21273/* Align the arguments to 32 bits */
21274#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_RSVD_OFST 1
21275#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_RSVD_LEN 3
21276/* RXEQ Parameter */
21277#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_OFST 4
21278#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LEN 4
21279#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_MINNUM 1
21280#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_MAXNUM 62
21281#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_MAXNUM_MCDI2 254
21282#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_ID_OFST 4
21283#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_ID_LBN 0
21284#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_ID_WIDTH 8
21285/* Enum values, see field(s): */
21286/* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT/PARAM_ID */
21287#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LANE_OFST 4
21288#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LANE_LBN 8
21289#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LANE_WIDTH 5
21290/* Enum values, see field(s): */
21291/* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT/PARAM_LANE */
21292#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_OFST 4
21293#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_LBN 13
21294#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_WIDTH 1
21295#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED_OFST 4
21296#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED_LBN 14
21297#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED_WIDTH 2
21298#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_INITIAL_OFST 4
21299#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_INITIAL_LBN 16
21300#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_INITIAL_WIDTH 8
21301#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED2_OFST 4
21302#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED2_LBN 24
21303#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED2_WIDTH 8
21304
21305/* MC_CMD_PCIE_TUNE_RXEQ_SET_OUT msgresponse */
21306#define MC_CMD_PCIE_TUNE_RXEQ_SET_OUT_LEN 0
21307
21308/* MC_CMD_PCIE_TUNE_TXEQ_GET_IN msgrequest */
21309#define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_LEN 4
21310/* Requested operation */
21311#define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_OP_OFST 0
21312#define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_OP_LEN 1
21313/* Align the arguments to 32 bits */
21314#define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_RSVD_OFST 1
21315#define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_RSVD_LEN 3
21316
21317/* MC_CMD_PCIE_TUNE_TXEQ_GET_OUT msgresponse */
21318#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LENMIN 4
21319#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LENMAX 252
21320#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LENMAX_MCDI2 1020
21321#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LEN(num) (0+4*(num))
21322#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_NUM(len) (((len)-0)/4)
21323/* RXEQ Parameter */
21324#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_OFST 0
21325#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LEN 4
21326#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_MINNUM 1
21327#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_MAXNUM 63
21328#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_MAXNUM_MCDI2 255
21329#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_ID_OFST 0
21330#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_ID_LBN 0
21331#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_ID_WIDTH 8
21332/* enum: TxMargin (PIPE) */
21333#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_TXMARGIN 0x0
21334/* enum: TxSwing (PIPE) */
21335#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_TXSWING 0x1
21336/* enum: De-emphasis coefficient C(-1) (PIPE) */
21337#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_CM1 0x2
21338/* enum: De-emphasis coefficient C(0) (PIPE) */
21339#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_C0 0x3
21340/* enum: De-emphasis coefficient C(+1) (PIPE) */
21341#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_CP1 0x4
21342#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LANE_OFST 0
21343#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LANE_LBN 8
21344#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LANE_WIDTH 4
21345/* Enum values, see field(s): */
21346/* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT/PARAM_LANE */
21347#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_RESERVED_OFST 0
21348#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_RESERVED_LBN 12
21349#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_RESERVED_WIDTH 12
21350#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_CURRENT_OFST 0
21351#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_CURRENT_LBN 24
21352#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8
21353
21354/* MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN msgrequest */
21355#define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_LEN 8
21356/* Requested operation */
21357#define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_OP_OFST 0
21358#define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_OP_LEN 1
21359/* Align the arguments to 32 bits */
21360#define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_RSVD_OFST 1
21361#define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_RSVD_LEN 3
21362#define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_LANE_OFST 4
21363#define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_LANE_LEN 4
21364
21365/* MC_CMD_PCIE_TUNE_START_EYE_PLOT_OUT msgresponse */
21366#define MC_CMD_PCIE_TUNE_START_EYE_PLOT_OUT_LEN 0
21367
21368/* MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN msgrequest */
21369#define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_LEN 4
21370/* Requested operation */
21371#define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_OP_OFST 0
21372#define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_OP_LEN 1
21373/* Align the arguments to 32 bits */
21374#define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_RSVD_OFST 1
21375#define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_RSVD_LEN 3
21376
21377/* MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT msgresponse */
21378#define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LENMIN 0
21379#define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LENMAX 252
21380#define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LENMAX_MCDI2 1020
21381#define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LEN(num) (0+2*(num))
21382#define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_NUM(len) (((len)-0)/2)
21383#define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_OFST 0
21384#define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_LEN 2
21385#define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MINNUM 0
21386#define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MAXNUM 126
21387#define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MAXNUM_MCDI2 510
21388
21389/* MC_CMD_PCIE_TUNE_BIST_SQUARE_WAVE_IN msgrequest */
21390#define MC_CMD_PCIE_TUNE_BIST_SQUARE_WAVE_IN_LEN 0
21391
21392/* MC_CMD_PCIE_TUNE_BIST_SQUARE_WAVE_OUT msgrequest */
21393#define MC_CMD_PCIE_TUNE_BIST_SQUARE_WAVE_OUT_LEN 0
21394
21395
21396/***********************************/
21397/* MC_CMD_LICENSING
21398 * Operations on the NVRAM_PARTITION_TYPE_LICENSE application license partition
21399 * - not used for V3 licensing
21400 */
21401#define MC_CMD_LICENSING 0xf3
21402#undef MC_CMD_0xf3_PRIVILEGE_CTG
21403
21404#define MC_CMD_0xf3_PRIVILEGE_CTG SRIOV_CTG_GENERAL
21405
21406/* MC_CMD_LICENSING_IN msgrequest */
21407#define MC_CMD_LICENSING_IN_LEN 4
21408/* identifies the type of operation requested */
21409#define MC_CMD_LICENSING_IN_OP_OFST 0
21410#define MC_CMD_LICENSING_IN_OP_LEN 4
21411/* enum: re-read and apply licenses after a license key partition update; note
21412 * that this operation returns a zero-length response
21413 */
21414#define MC_CMD_LICENSING_IN_OP_UPDATE_LICENSE 0x0
21415/* enum: report counts of installed licenses */
21416#define MC_CMD_LICENSING_IN_OP_GET_KEY_STATS 0x1
21417
21418/* MC_CMD_LICENSING_OUT msgresponse */
21419#define MC_CMD_LICENSING_OUT_LEN 28
21420/* count of application keys which are valid */
21421#define MC_CMD_LICENSING_OUT_VALID_APP_KEYS_OFST 0
21422#define MC_CMD_LICENSING_OUT_VALID_APP_KEYS_LEN 4
21423/* sum of UNVERIFIABLE_APP_KEYS + WRONG_NODE_APP_KEYS (for compatibility with
21424 * MC_CMD_FC_OP_LICENSE)
21425 */
21426#define MC_CMD_LICENSING_OUT_INVALID_APP_KEYS_OFST 4
21427#define MC_CMD_LICENSING_OUT_INVALID_APP_KEYS_LEN 4
21428/* count of application keys which are invalid due to being blacklisted */
21429#define MC_CMD_LICENSING_OUT_BLACKLISTED_APP_KEYS_OFST 8
21430#define MC_CMD_LICENSING_OUT_BLACKLISTED_APP_KEYS_LEN 4
21431/* count of application keys which are invalid due to being unverifiable */
21432#define MC_CMD_LICENSING_OUT_UNVERIFIABLE_APP_KEYS_OFST 12
21433#define MC_CMD_LICENSING_OUT_UNVERIFIABLE_APP_KEYS_LEN 4
21434/* count of application keys which are invalid due to being for the wrong node
21435 */
21436#define MC_CMD_LICENSING_OUT_WRONG_NODE_APP_KEYS_OFST 16
21437#define MC_CMD_LICENSING_OUT_WRONG_NODE_APP_KEYS_LEN 4
21438/* licensing state (for diagnostics; the exact meaning of the bits in this
21439 * field are private to the firmware)
21440 */
21441#define MC_CMD_LICENSING_OUT_LICENSING_STATE_OFST 20
21442#define MC_CMD_LICENSING_OUT_LICENSING_STATE_LEN 4
21443/* licensing subsystem self-test report (for manftest) */
21444#define MC_CMD_LICENSING_OUT_LICENSING_SELF_TEST_OFST 24
21445#define MC_CMD_LICENSING_OUT_LICENSING_SELF_TEST_LEN 4
21446/* enum: licensing subsystem self-test failed */
21447#define MC_CMD_LICENSING_OUT_SELF_TEST_FAIL 0x0
21448/* enum: licensing subsystem self-test passed */
21449#define MC_CMD_LICENSING_OUT_SELF_TEST_PASS 0x1
21450
21451
21452/***********************************/
21453/* MC_CMD_LICENSING_V3
21454 * Operations on the NVRAM_PARTITION_TYPE_LICENSE application license partition
21455 * - V3 licensing (Medford)
21456 */
21457#define MC_CMD_LICENSING_V3 0xd0
21458#undef MC_CMD_0xd0_PRIVILEGE_CTG
21459
21460#define MC_CMD_0xd0_PRIVILEGE_CTG SRIOV_CTG_GENERAL
21461
21462/* MC_CMD_LICENSING_V3_IN msgrequest */
21463#define MC_CMD_LICENSING_V3_IN_LEN 4
21464/* identifies the type of operation requested */
21465#define MC_CMD_LICENSING_V3_IN_OP_OFST 0
21466#define MC_CMD_LICENSING_V3_IN_OP_LEN 4
21467/* enum: re-read and apply licenses after a license key partition update; note
21468 * that this operation returns a zero-length response
21469 */
21470#define MC_CMD_LICENSING_V3_IN_OP_UPDATE_LICENSE 0x0
21471/* enum: report counts of installed licenses Returns EAGAIN if license
21472 * processing (updating) has been started but not yet completed.
21473 */
21474#define MC_CMD_LICENSING_V3_IN_OP_REPORT_LICENSE 0x1
21475
21476/* MC_CMD_LICENSING_V3_OUT msgresponse */
21477#define MC_CMD_LICENSING_V3_OUT_LEN 88
21478/* count of keys which are valid */
21479#define MC_CMD_LICENSING_V3_OUT_VALID_KEYS_OFST 0
21480#define MC_CMD_LICENSING_V3_OUT_VALID_KEYS_LEN 4
21481/* sum of UNVERIFIABLE_KEYS + WRONG_NODE_KEYS (for compatibility with
21482 * MC_CMD_FC_OP_LICENSE)
21483 */
21484#define MC_CMD_LICENSING_V3_OUT_INVALID_KEYS_OFST 4
21485#define MC_CMD_LICENSING_V3_OUT_INVALID_KEYS_LEN 4
21486/* count of keys which are invalid due to being unverifiable */
21487#define MC_CMD_LICENSING_V3_OUT_UNVERIFIABLE_KEYS_OFST 8
21488#define MC_CMD_LICENSING_V3_OUT_UNVERIFIABLE_KEYS_LEN 4
21489/* count of keys which are invalid due to being for the wrong node */
21490#define MC_CMD_LICENSING_V3_OUT_WRONG_NODE_KEYS_OFST 12
21491#define MC_CMD_LICENSING_V3_OUT_WRONG_NODE_KEYS_LEN 4
21492/* licensing state (for diagnostics; the exact meaning of the bits in this
21493 * field are private to the firmware)
21494 */
21495#define MC_CMD_LICENSING_V3_OUT_LICENSING_STATE_OFST 16
21496#define MC_CMD_LICENSING_V3_OUT_LICENSING_STATE_LEN 4
21497/* licensing subsystem self-test report (for manftest) */
21498#define MC_CMD_LICENSING_V3_OUT_LICENSING_SELF_TEST_OFST 20
21499#define MC_CMD_LICENSING_V3_OUT_LICENSING_SELF_TEST_LEN 4
21500/* enum: licensing subsystem self-test failed */
21501#define MC_CMD_LICENSING_V3_OUT_SELF_TEST_FAIL 0x0
21502/* enum: licensing subsystem self-test passed */
21503#define MC_CMD_LICENSING_V3_OUT_SELF_TEST_PASS 0x1
21504/* bitmask of licensed applications */
21505#define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_OFST 24
21506#define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_LEN 8
21507#define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_LO_OFST 24
21508#define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_LO_LEN 4
21509#define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_LO_LBN 192
21510#define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_LO_WIDTH 32
21511#define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_HI_OFST 28
21512#define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_HI_LEN 4
21513#define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_HI_LBN 224
21514#define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_HI_WIDTH 32
21515/* reserved for future use */
21516#define MC_CMD_LICENSING_V3_OUT_RESERVED_0_OFST 32
21517#define MC_CMD_LICENSING_V3_OUT_RESERVED_0_LEN 24
21518/* bitmask of licensed features */
21519#define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_OFST 56
21520#define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_LEN 8
21521#define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_LO_OFST 56
21522#define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_LO_LEN 4
21523#define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_LO_LBN 448
21524#define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_LO_WIDTH 32
21525#define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_HI_OFST 60
21526#define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_HI_LEN 4
21527#define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_HI_LBN 480
21528#define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_HI_WIDTH 32
21529/* reserved for future use */
21530#define MC_CMD_LICENSING_V3_OUT_RESERVED_1_OFST 64
21531#define MC_CMD_LICENSING_V3_OUT_RESERVED_1_LEN 24
21532
21533
21534/***********************************/
21535/* MC_CMD_LICENSING_GET_ID_V3
21536 * Get ID and type from the NVRAM_PARTITION_TYPE_LICENSE application license
21537 * partition - V3 licensing (Medford)
21538 */
21539#define MC_CMD_LICENSING_GET_ID_V3 0xd1
21540#undef MC_CMD_0xd1_PRIVILEGE_CTG
21541
21542#define MC_CMD_0xd1_PRIVILEGE_CTG SRIOV_CTG_GENERAL
21543
21544/* MC_CMD_LICENSING_GET_ID_V3_IN msgrequest */
21545#define MC_CMD_LICENSING_GET_ID_V3_IN_LEN 0
21546
21547/* MC_CMD_LICENSING_GET_ID_V3_OUT msgresponse */
21548#define MC_CMD_LICENSING_GET_ID_V3_OUT_LENMIN 8
21549#define MC_CMD_LICENSING_GET_ID_V3_OUT_LENMAX 252
21550#define MC_CMD_LICENSING_GET_ID_V3_OUT_LENMAX_MCDI2 1020
21551#define MC_CMD_LICENSING_GET_ID_V3_OUT_LEN(num) (8+1*(num))
21552#define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_NUM(len) (((len)-8)/1)
21553/* type of license (eg 3) */
21554#define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_TYPE_OFST 0
21555#define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_TYPE_LEN 4
21556/* length of the license ID (in bytes) */
21557#define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_LENGTH_OFST 4
21558#define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_LENGTH_LEN 4
21559/* the unique license ID of the adapter */
21560#define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_OFST 8
21561#define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_LEN 1
21562#define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_MINNUM 0
21563#define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_MAXNUM 244
21564#define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_MAXNUM_MCDI2 1012
21565
21566
21567/***********************************/
21568/* MC_CMD_MC2MC_PROXY
21569 * Execute an arbitrary MCDI command on the slave MC of a dual-core device.
21570 * This will fail on a single-core system.
21571 */
21572#define MC_CMD_MC2MC_PROXY 0xf4
21573#undef MC_CMD_0xf4_PRIVILEGE_CTG
21574
21575#define MC_CMD_0xf4_PRIVILEGE_CTG SRIOV_CTG_GENERAL
21576
21577/* MC_CMD_MC2MC_PROXY_IN msgrequest */
21578#define MC_CMD_MC2MC_PROXY_IN_LEN 0
21579
21580/* MC_CMD_MC2MC_PROXY_OUT msgresponse */
21581#define MC_CMD_MC2MC_PROXY_OUT_LEN 0
21582
21583
21584/***********************************/
21585/* MC_CMD_GET_LICENSED_APP_STATE
21586 * Query the state of an individual licensed application. (Note that the actual
21587 * state may be invalidated by the MC_CMD_LICENSING OP_UPDATE_LICENSE operation
21588 * or a reboot of the MC.) Not used for V3 licensing
21589 */
21590#define MC_CMD_GET_LICENSED_APP_STATE 0xf5
21591#undef MC_CMD_0xf5_PRIVILEGE_CTG
21592
21593#define MC_CMD_0xf5_PRIVILEGE_CTG SRIOV_CTG_GENERAL
21594
21595/* MC_CMD_GET_LICENSED_APP_STATE_IN msgrequest */
21596#define MC_CMD_GET_LICENSED_APP_STATE_IN_LEN 4
21597/* application ID to query (LICENSED_APP_ID_xxx) */
21598#define MC_CMD_GET_LICENSED_APP_STATE_IN_APP_ID_OFST 0
21599#define MC_CMD_GET_LICENSED_APP_STATE_IN_APP_ID_LEN 4
21600
21601/* MC_CMD_GET_LICENSED_APP_STATE_OUT msgresponse */
21602#define MC_CMD_GET_LICENSED_APP_STATE_OUT_LEN 4
21603/* state of this application */
21604#define MC_CMD_GET_LICENSED_APP_STATE_OUT_STATE_OFST 0
21605#define MC_CMD_GET_LICENSED_APP_STATE_OUT_STATE_LEN 4
21606/* enum: no (or invalid) license is present for the application */
21607#define MC_CMD_GET_LICENSED_APP_STATE_OUT_NOT_LICENSED 0x0
21608/* enum: a valid license is present for the application */
21609#define MC_CMD_GET_LICENSED_APP_STATE_OUT_LICENSED 0x1
21610
21611
21612/***********************************/
21613/* MC_CMD_GET_LICENSED_V3_APP_STATE
21614 * Query the state of an individual licensed application. (Note that the actual
21615 * state may be invalidated by the MC_CMD_LICENSING_V3 OP_UPDATE_LICENSE
21616 * operation or a reboot of the MC.) Used for V3 licensing (Medford)
21617 */
21618#define MC_CMD_GET_LICENSED_V3_APP_STATE 0xd2
21619#undef MC_CMD_0xd2_PRIVILEGE_CTG
21620
21621#define MC_CMD_0xd2_PRIVILEGE_CTG SRIOV_CTG_GENERAL
21622
21623/* MC_CMD_GET_LICENSED_V3_APP_STATE_IN msgrequest */
21624#define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_LEN 8
21625/* application ID to query (LICENSED_V3_APPS_xxx) expressed as a single bit
21626 * mask
21627 */
21628#define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_OFST 0
21629#define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LEN 8
21630#define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LO_OFST 0
21631#define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LO_LEN 4
21632#define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LO_LBN 0
21633#define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LO_WIDTH 32
21634#define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_HI_OFST 4
21635#define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_HI_LEN 4
21636#define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_HI_LBN 32
21637#define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_HI_WIDTH 32
21638
21639/* MC_CMD_GET_LICENSED_V3_APP_STATE_OUT msgresponse */
21640#define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_LEN 4
21641/* state of this application */
21642#define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_STATE_OFST 0
21643#define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_STATE_LEN 4
21644/* enum: no (or invalid) license is present for the application */
21645#define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_NOT_LICENSED 0x0
21646/* enum: a valid license is present for the application */
21647#define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_LICENSED 0x1
21648
21649
21650/***********************************/
21651/* MC_CMD_GET_LICENSED_V3_FEATURE_STATES
21652 * Query the state of an one or more licensed features. (Note that the actual
21653 * state may be invalidated by the MC_CMD_LICENSING_V3 OP_UPDATE_LICENSE
21654 * operation or a reboot of the MC.) Used for V3 licensing (Medford)
21655 */
21656#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES 0xd3
21657#undef MC_CMD_0xd3_PRIVILEGE_CTG
21658
21659#define MC_CMD_0xd3_PRIVILEGE_CTG SRIOV_CTG_GENERAL
21660
21661/* MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN msgrequest */
21662#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_LEN 8
21663/* features to query (LICENSED_V3_FEATURES_xxx) expressed as a mask with one or
21664 * more bits set
21665 */
21666#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_OFST 0
21667#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LEN 8
21668#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LO_OFST 0
21669#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LO_LEN 4
21670#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LO_LBN 0
21671#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LO_WIDTH 32
21672#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_HI_OFST 4
21673#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_HI_LEN 4
21674#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_HI_LBN 32
21675#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_HI_WIDTH 32
21676
21677/* MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT msgresponse */
21678#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_LEN 8
21679/* states of these features - bit set for licensed, clear for not licensed */
21680#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_OFST 0
21681#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LEN 8
21682#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LO_OFST 0
21683#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LO_LEN 4
21684#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LO_LBN 0
21685#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LO_WIDTH 32
21686#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_HI_OFST 4
21687#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_HI_LEN 4
21688#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_HI_LBN 32
21689#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_HI_WIDTH 32
21690
21691
21692/***********************************/
21693/* MC_CMD_LICENSED_APP_OP
21694 * Perform an action for an individual licensed application - not used for V3
21695 * licensing.
21696 */
21697#define MC_CMD_LICENSED_APP_OP 0xf6
21698#undef MC_CMD_0xf6_PRIVILEGE_CTG
21699
21700#define MC_CMD_0xf6_PRIVILEGE_CTG SRIOV_CTG_GENERAL
21701
21702/* MC_CMD_LICENSED_APP_OP_IN msgrequest */
21703#define MC_CMD_LICENSED_APP_OP_IN_LENMIN 8
21704#define MC_CMD_LICENSED_APP_OP_IN_LENMAX 252
21705#define MC_CMD_LICENSED_APP_OP_IN_LENMAX_MCDI2 1020
21706#define MC_CMD_LICENSED_APP_OP_IN_LEN(num) (8+4*(num))
21707#define MC_CMD_LICENSED_APP_OP_IN_ARGS_NUM(len) (((len)-8)/4)
21708/* application ID */
21709#define MC_CMD_LICENSED_APP_OP_IN_APP_ID_OFST 0
21710#define MC_CMD_LICENSED_APP_OP_IN_APP_ID_LEN 4
21711/* the type of operation requested */
21712#define MC_CMD_LICENSED_APP_OP_IN_OP_OFST 4
21713#define MC_CMD_LICENSED_APP_OP_IN_OP_LEN 4
21714/* enum: validate application */
21715#define MC_CMD_LICENSED_APP_OP_IN_OP_VALIDATE 0x0
21716/* enum: mask application */
21717#define MC_CMD_LICENSED_APP_OP_IN_OP_MASK 0x1
21718/* arguments specific to this particular operation */
21719#define MC_CMD_LICENSED_APP_OP_IN_ARGS_OFST 8
21720#define MC_CMD_LICENSED_APP_OP_IN_ARGS_LEN 4
21721#define MC_CMD_LICENSED_APP_OP_IN_ARGS_MINNUM 0
21722#define MC_CMD_LICENSED_APP_OP_IN_ARGS_MAXNUM 61
21723#define MC_CMD_LICENSED_APP_OP_IN_ARGS_MAXNUM_MCDI2 253
21724
21725/* MC_CMD_LICENSED_APP_OP_OUT msgresponse */
21726#define MC_CMD_LICENSED_APP_OP_OUT_LENMIN 0
21727#define MC_CMD_LICENSED_APP_OP_OUT_LENMAX 252
21728#define MC_CMD_LICENSED_APP_OP_OUT_LENMAX_MCDI2 1020
21729#define MC_CMD_LICENSED_APP_OP_OUT_LEN(num) (0+4*(num))
21730#define MC_CMD_LICENSED_APP_OP_OUT_RESULT_NUM(len) (((len)-0)/4)
21731/* result specific to this particular operation */
21732#define MC_CMD_LICENSED_APP_OP_OUT_RESULT_OFST 0
21733#define MC_CMD_LICENSED_APP_OP_OUT_RESULT_LEN 4
21734#define MC_CMD_LICENSED_APP_OP_OUT_RESULT_MINNUM 0
21735#define MC_CMD_LICENSED_APP_OP_OUT_RESULT_MAXNUM 63
21736#define MC_CMD_LICENSED_APP_OP_OUT_RESULT_MAXNUM_MCDI2 255
21737
21738/* MC_CMD_LICENSED_APP_OP_VALIDATE_IN msgrequest */
21739#define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_LEN 72
21740/* application ID */
21741#define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_APP_ID_OFST 0
21742#define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_APP_ID_LEN 4
21743/* the type of operation requested */
21744#define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_OP_OFST 4
21745#define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_OP_LEN 4
21746/* validation challenge */
21747#define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_CHALLENGE_OFST 8
21748#define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_CHALLENGE_LEN 64
21749
21750/* MC_CMD_LICENSED_APP_OP_VALIDATE_OUT msgresponse */
21751#define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_LEN 68
21752/* feature expiry (time_t) */
21753#define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_EXPIRY_OFST 0
21754#define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_EXPIRY_LEN 4
21755/* validation response */
21756#define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_RESPONSE_OFST 4
21757#define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_RESPONSE_LEN 64
21758
21759/* MC_CMD_LICENSED_APP_OP_MASK_IN msgrequest */
21760#define MC_CMD_LICENSED_APP_OP_MASK_IN_LEN 12
21761/* application ID */
21762#define MC_CMD_LICENSED_APP_OP_MASK_IN_APP_ID_OFST 0
21763#define MC_CMD_LICENSED_APP_OP_MASK_IN_APP_ID_LEN 4
21764/* the type of operation requested */
21765#define MC_CMD_LICENSED_APP_OP_MASK_IN_OP_OFST 4
21766#define MC_CMD_LICENSED_APP_OP_MASK_IN_OP_LEN 4
21767/* flag */
21768#define MC_CMD_LICENSED_APP_OP_MASK_IN_FLAG_OFST 8
21769#define MC_CMD_LICENSED_APP_OP_MASK_IN_FLAG_LEN 4
21770
21771/* MC_CMD_LICENSED_APP_OP_MASK_OUT msgresponse */
21772#define MC_CMD_LICENSED_APP_OP_MASK_OUT_LEN 0
21773
21774
21775/***********************************/
21776/* MC_CMD_LICENSED_V3_VALIDATE_APP
21777 * Perform validation for an individual licensed application - V3 licensing
21778 * (Medford)
21779 */
21780#define MC_CMD_LICENSED_V3_VALIDATE_APP 0xd4
21781#undef MC_CMD_0xd4_PRIVILEGE_CTG
21782
21783#define MC_CMD_0xd4_PRIVILEGE_CTG SRIOV_CTG_GENERAL
21784
21785/* MC_CMD_LICENSED_V3_VALIDATE_APP_IN msgrequest */
21786#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_LEN 56
21787/* challenge for validation (384 bits) */
21788#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_CHALLENGE_OFST 0
21789#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_CHALLENGE_LEN 48
21790/* application ID expressed as a single bit mask */
21791#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_OFST 48
21792#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_LEN 8
21793#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_LO_OFST 48
21794#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_LO_LEN 4
21795#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_LO_LBN 384
21796#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_LO_WIDTH 32
21797#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_HI_OFST 52
21798#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_HI_LEN 4
21799#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_HI_LBN 416
21800#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_HI_WIDTH 32
21801
21802/* MC_CMD_LICENSED_V3_VALIDATE_APP_OUT msgresponse */
21803#define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_LEN 116
21804/* validation response to challenge in the form of ECDSA signature consisting
21805 * of two 384-bit integers, r and s, in big-endian order. The signature signs a
21806 * SHA-384 digest of a message constructed from the concatenation of the input
21807 * message and the remaining fields of this output message, e.g. challenge[48
21808 * bytes] ... expiry_time[4 bytes] ...
21809 */
21810#define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_RESPONSE_OFST 0
21811#define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_RESPONSE_LEN 96
21812/* application expiry time */
21813#define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_TIME_OFST 96
21814#define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_TIME_LEN 4
21815/* application expiry units */
21816#define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNITS_OFST 100
21817#define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNITS_LEN 4
21818/* enum: expiry units are accounting units */
21819#define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNIT_ACC 0x0
21820/* enum: expiry units are calendar days */
21821#define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNIT_DAYS 0x1
21822/* base MAC address of the NIC stored in NVRAM (note that this is a constant
21823 * value for a given NIC regardless which function is calling, effectively this
21824 * is PF0 base MAC address)
21825 */
21826#define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_BASE_MACADDR_OFST 104
21827#define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_BASE_MACADDR_LEN 6
21828/* MAC address of v-adaptor associated with the client. If no such v-adapator
21829 * exists, then the field is filled with 0xFF.
21830 */
21831#define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_VADAPTOR_MACADDR_OFST 110
21832#define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_VADAPTOR_MACADDR_LEN 6
21833
21834
21835/***********************************/
21836/* MC_CMD_LICENSED_V3_MASK_FEATURES
21837 * Mask features - V3 licensing (Medford)
21838 */
21839#define MC_CMD_LICENSED_V3_MASK_FEATURES 0xd5
21840#undef MC_CMD_0xd5_PRIVILEGE_CTG
21841
21842#define MC_CMD_0xd5_PRIVILEGE_CTG SRIOV_CTG_ADMIN
21843
21844/* MC_CMD_LICENSED_V3_MASK_FEATURES_IN msgrequest */
21845#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_LEN 12
21846/* mask to be applied to features to be changed */
21847#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_OFST 0
21848#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LEN 8
21849#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LO_OFST 0
21850#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LO_LEN 4
21851#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LO_LBN 0
21852#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LO_WIDTH 32
21853#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_HI_OFST 4
21854#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_HI_LEN 4
21855#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_HI_LBN 32
21856#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_HI_WIDTH 32
21857/* whether to turn on or turn off the masked features */
21858#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_FLAG_OFST 8
21859#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_FLAG_LEN 4
21860/* enum: turn the features off */
21861#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_OFF 0x0
21862/* enum: turn the features back on */
21863#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_ON 0x1
21864
21865/* MC_CMD_LICENSED_V3_MASK_FEATURES_OUT msgresponse */
21866#define MC_CMD_LICENSED_V3_MASK_FEATURES_OUT_LEN 0
21867
21868
21869/***********************************/
21870/* MC_CMD_LICENSING_V3_TEMPORARY
21871 * Perform operations to support installation of a single temporary license in
21872 * the adapter, in addition to those found in the licensing partition. See
21873 * SF-116124-SW for an overview of how this could be used. The license is
21874 * stored in MC persistent data and so will survive a MC reboot, but will be
21875 * erased when the adapter is power cycled
21876 */
21877#define MC_CMD_LICENSING_V3_TEMPORARY 0xd6
21878#undef MC_CMD_0xd6_PRIVILEGE_CTG
21879
21880#define MC_CMD_0xd6_PRIVILEGE_CTG SRIOV_CTG_ADMIN
21881
21882/* MC_CMD_LICENSING_V3_TEMPORARY_IN msgrequest */
21883#define MC_CMD_LICENSING_V3_TEMPORARY_IN_LEN 4
21884/* operation code */
21885#define MC_CMD_LICENSING_V3_TEMPORARY_IN_OP_OFST 0
21886#define MC_CMD_LICENSING_V3_TEMPORARY_IN_OP_LEN 4
21887/* enum: install a new license, overwriting any existing temporary license.
21888 * This is an asynchronous operation owing to the time taken to validate an
21889 * ECDSA license
21890 */
21891#define MC_CMD_LICENSING_V3_TEMPORARY_SET 0x0
21892/* enum: clear the license immediately rather than waiting for the next power
21893 * cycle
21894 */
21895#define MC_CMD_LICENSING_V3_TEMPORARY_CLEAR 0x1
21896/* enum: get the status of the asynchronous MC_CMD_LICENSING_V3_TEMPORARY_SET
21897 * operation
21898 */
21899#define MC_CMD_LICENSING_V3_TEMPORARY_STATUS 0x2
21900
21901/* MC_CMD_LICENSING_V3_TEMPORARY_IN_SET msgrequest */
21902#define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_LEN 164
21903#define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_OP_OFST 0
21904#define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_OP_LEN 4
21905/* ECDSA license and signature */
21906#define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_LICENSE_OFST 4
21907#define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_LICENSE_LEN 160
21908
21909/* MC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR msgrequest */
21910#define MC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR_LEN 4
21911#define MC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR_OP_OFST 0
21912#define MC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR_OP_LEN 4
21913
21914/* MC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS msgrequest */
21915#define MC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS_LEN 4
21916#define MC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS_OP_OFST 0
21917#define MC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS_OP_LEN 4
21918
21919/* MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS msgresponse */
21920#define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LEN 12
21921/* status code */
21922#define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_STATUS_OFST 0
21923#define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_STATUS_LEN 4
21924/* enum: finished validating and installing license */
21925#define MC_CMD_LICENSING_V3_TEMPORARY_STATUS_OK 0x0
21926/* enum: license validation and installation in progress */
21927#define MC_CMD_LICENSING_V3_TEMPORARY_STATUS_IN_PROGRESS 0x1
21928/* enum: licensing error. More specific error messages are not provided to
21929 * avoid exposing details of the licensing system to the client
21930 */
21931#define MC_CMD_LICENSING_V3_TEMPORARY_STATUS_ERROR 0x2
21932/* bitmask of licensed features */
21933#define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_OFST 4
21934#define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_LEN 8
21935#define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_LO_OFST 4
21936#define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_LO_LEN 4
21937#define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_LO_LBN 32
21938#define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_LO_WIDTH 32
21939#define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_HI_OFST 8
21940#define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_HI_LEN 4
21941#define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_HI_LBN 64
21942#define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_HI_WIDTH 32
21943
21944
21945/***********************************/
21946/* MC_CMD_SET_PORT_SNIFF_CONFIG
21947 * Configure RX port sniffing for the physical port associated with the calling
21948 * function. Only a privileged function may change the port sniffing
21949 * configuration. A copy of all traffic delivered to the host (non-promiscuous
21950 * mode) or all traffic arriving at the port (promiscuous mode) may be
21951 * delivered to a specific queue, or a set of queues with RSS.
21952 */
21953#define MC_CMD_SET_PORT_SNIFF_CONFIG 0xf7
21954#undef MC_CMD_0xf7_PRIVILEGE_CTG
21955
21956#define MC_CMD_0xf7_PRIVILEGE_CTG SRIOV_CTG_ADMIN
21957
21958/* MC_CMD_SET_PORT_SNIFF_CONFIG_IN msgrequest */
21959#define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_LEN 16
21960/* configuration flags */
21961#define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_FLAGS_OFST 0
21962#define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_FLAGS_LEN 4
21963#define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_ENABLE_OFST 0
21964#define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_ENABLE_LBN 0
21965#define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_ENABLE_WIDTH 1
21966#define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_PROMISCUOUS_OFST 0
21967#define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_PROMISCUOUS_LBN 1
21968#define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_PROMISCUOUS_WIDTH 1
21969/* receive queue handle (for RSS mode, this is the base queue) */
21970#define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_QUEUE_OFST 4
21971#define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_QUEUE_LEN 4
21972/* receive mode */
21973#define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_OFST 8
21974#define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_LEN 4
21975/* enum: receive to just the specified queue */
21976#define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_SIMPLE 0x0
21977/* enum: receive to multiple queues using RSS context */
21978#define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_RSS 0x1
21979/* RSS context (for RX_MODE_RSS) as returned by MC_CMD_RSS_CONTEXT_ALLOC. Note
21980 * that these handles should be considered opaque to the host, although a value
21981 * of 0xFFFFFFFF is guaranteed never to be a valid handle.
21982 */
21983#define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_OFST 12
21984#define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_LEN 4
21985
21986/* MC_CMD_SET_PORT_SNIFF_CONFIG_OUT msgresponse */
21987#define MC_CMD_SET_PORT_SNIFF_CONFIG_OUT_LEN 0
21988
21989
21990/***********************************/
21991/* MC_CMD_GET_PORT_SNIFF_CONFIG
21992 * Obtain the current RX port sniffing configuration for the physical port
21993 * associated with the calling function. Only a privileged function may read
21994 * the configuration.
21995 */
21996#define MC_CMD_GET_PORT_SNIFF_CONFIG 0xf8
21997#undef MC_CMD_0xf8_PRIVILEGE_CTG
21998
21999#define MC_CMD_0xf8_PRIVILEGE_CTG SRIOV_CTG_GENERAL
22000
22001/* MC_CMD_GET_PORT_SNIFF_CONFIG_IN msgrequest */
22002#define MC_CMD_GET_PORT_SNIFF_CONFIG_IN_LEN 0
22003
22004/* MC_CMD_GET_PORT_SNIFF_CONFIG_OUT msgresponse */
22005#define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_LEN 16
22006/* configuration flags */
22007#define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_FLAGS_OFST 0
22008#define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_FLAGS_LEN 4
22009#define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_ENABLE_OFST 0
22010#define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_ENABLE_LBN 0
22011#define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_ENABLE_WIDTH 1
22012#define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_PROMISCUOUS_OFST 0
22013#define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_PROMISCUOUS_LBN 1
22014#define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_PROMISCUOUS_WIDTH 1
22015/* receiving queue handle (for RSS mode, this is the base queue) */
22016#define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_OFST 4
22017#define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_LEN 4
22018/* receive mode */
22019#define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_OFST 8
22020#define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_LEN 4
22021/* enum: receiving to just the specified queue */
22022#define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_SIMPLE 0x0
22023/* enum: receiving to multiple queues using RSS context */
22024#define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_RSS 0x1
22025/* RSS context (for RX_MODE_RSS) */
22026#define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_OFST 12
22027#define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_LEN 4
22028
22029
22030/***********************************/
22031/* MC_CMD_SET_PARSER_DISP_CONFIG
22032 * Change configuration related to the parser-dispatcher subsystem.
22033 */
22034#define MC_CMD_SET_PARSER_DISP_CONFIG 0xf9
22035#undef MC_CMD_0xf9_PRIVILEGE_CTG
22036
22037#define MC_CMD_0xf9_PRIVILEGE_CTG SRIOV_CTG_GENERAL
22038
22039/* MC_CMD_SET_PARSER_DISP_CONFIG_IN msgrequest */
22040#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LENMIN 12
22041#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LENMAX 252
22042#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LENMAX_MCDI2 1020
22043#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LEN(num) (8+4*(num))
22044#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_NUM(len) (((len)-8)/4)
22045/* the type of configuration setting to change */
22046#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_TYPE_OFST 0
22047#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_TYPE_LEN 4
22048/* enum: Per-TXQ enable for multicast UDP destination lookup for possible
22049 * internal loopback. (ENTITY is a queue handle, VALUE is a single boolean.)
22050 */
22051#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_TXQ_MCAST_UDP_DST_LOOKUP_EN 0x0
22052/* enum: Per-v-adaptor enable for suppression of self-transmissions on the
22053 * internal loopback path. (ENTITY is an EVB_PORT_ID, VALUE is a single
22054 * boolean.)
22055 */
22056#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VADAPTOR_SUPPRESS_SELF_TX 0x1
22057/* handle for the entity to update: queue handle, EVB port ID, etc. depending
22058 * on the type of configuration setting being changed
22059 */
22060#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_ENTITY_OFST 4
22061#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_ENTITY_LEN 4
22062/* new value: the details depend on the type of configuration setting being
22063 * changed
22064 */
22065#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_OFST 8
22066#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_LEN 4
22067#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_MINNUM 1
22068#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_MAXNUM 61
22069#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_MAXNUM_MCDI2 253
22070
22071/* MC_CMD_SET_PARSER_DISP_CONFIG_OUT msgresponse */
22072#define MC_CMD_SET_PARSER_DISP_CONFIG_OUT_LEN 0
22073
22074
22075/***********************************/
22076/* MC_CMD_GET_PARSER_DISP_CONFIG
22077 * Read configuration related to the parser-dispatcher subsystem.
22078 */
22079#define MC_CMD_GET_PARSER_DISP_CONFIG 0xfa
22080#undef MC_CMD_0xfa_PRIVILEGE_CTG
22081
22082#define MC_CMD_0xfa_PRIVILEGE_CTG SRIOV_CTG_GENERAL
22083
22084/* MC_CMD_GET_PARSER_DISP_CONFIG_IN msgrequest */
22085#define MC_CMD_GET_PARSER_DISP_CONFIG_IN_LEN 8
22086/* the type of configuration setting to read */
22087#define MC_CMD_GET_PARSER_DISP_CONFIG_IN_TYPE_OFST 0
22088#define MC_CMD_GET_PARSER_DISP_CONFIG_IN_TYPE_LEN 4
22089/* Enum values, see field(s): */
22090/* MC_CMD_SET_PARSER_DISP_CONFIG/MC_CMD_SET_PARSER_DISP_CONFIG_IN/TYPE */
22091/* handle for the entity to query: queue handle, EVB port ID, etc. depending on
22092 * the type of configuration setting being read
22093 */
22094#define MC_CMD_GET_PARSER_DISP_CONFIG_IN_ENTITY_OFST 4
22095#define MC_CMD_GET_PARSER_DISP_CONFIG_IN_ENTITY_LEN 4
22096
22097/* MC_CMD_GET_PARSER_DISP_CONFIG_OUT msgresponse */
22098#define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LENMIN 4
22099#define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LENMAX 252
22100#define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LENMAX_MCDI2 1020
22101#define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LEN(num) (0+4*(num))
22102#define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_NUM(len) (((len)-0)/4)
22103/* current value: the details depend on the type of configuration setting being
22104 * read
22105 */
22106#define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_OFST 0
22107#define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_LEN 4
22108#define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_MINNUM 1
22109#define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_MAXNUM 63
22110#define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_MAXNUM_MCDI2 255
22111
22112
22113/***********************************/
22114/* MC_CMD_SET_TX_PORT_SNIFF_CONFIG
22115 * Configure TX port sniffing for the physical port associated with the calling
22116 * function. Only a privileged function may change the port sniffing
22117 * configuration. A copy of all traffic transmitted through the port may be
22118 * delivered to a specific queue, or a set of queues with RSS. Note that these
22119 * packets are delivered with transmit timestamps in the packet prefix, not
22120 * receive timestamps, so it is likely that the queue(s) will need to be
22121 * dedicated as TX sniff receivers.
22122 */
22123#define MC_CMD_SET_TX_PORT_SNIFF_CONFIG 0xfb
22124#undef MC_CMD_0xfb_PRIVILEGE_CTG
22125
22126#define MC_CMD_0xfb_PRIVILEGE_CTG SRIOV_CTG_ADMIN
22127
22128/* MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN msgrequest */
22129#define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_LEN 16
22130/* configuration flags */
22131#define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_FLAGS_OFST 0
22132#define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_FLAGS_LEN 4
22133#define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_ENABLE_OFST 0
22134#define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_ENABLE_LBN 0
22135#define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_ENABLE_WIDTH 1
22136/* receive queue handle (for RSS mode, this is the base queue) */
22137#define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_QUEUE_OFST 4
22138#define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_QUEUE_LEN 4
22139/* receive mode */
22140#define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_OFST 8
22141#define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_LEN 4
22142/* enum: receive to just the specified queue */
22143#define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_SIMPLE 0x0
22144/* enum: receive to multiple queues using RSS context */
22145#define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_RSS 0x1
22146/* RSS context (for RX_MODE_RSS) as returned by MC_CMD_RSS_CONTEXT_ALLOC. Note
22147 * that these handles should be considered opaque to the host, although a value
22148 * of 0xFFFFFFFF is guaranteed never to be a valid handle.
22149 */
22150#define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_OFST 12
22151#define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_LEN 4
22152
22153/* MC_CMD_SET_TX_PORT_SNIFF_CONFIG_OUT msgresponse */
22154#define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_OUT_LEN 0
22155
22156
22157/***********************************/
22158/* MC_CMD_GET_TX_PORT_SNIFF_CONFIG
22159 * Obtain the current TX port sniffing configuration for the physical port
22160 * associated with the calling function. Only a privileged function may read
22161 * the configuration.
22162 */
22163#define MC_CMD_GET_TX_PORT_SNIFF_CONFIG 0xfc
22164#undef MC_CMD_0xfc_PRIVILEGE_CTG
22165
22166#define MC_CMD_0xfc_PRIVILEGE_CTG SRIOV_CTG_GENERAL
22167
22168/* MC_CMD_GET_TX_PORT_SNIFF_CONFIG_IN msgrequest */
22169#define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_IN_LEN 0
22170
22171/* MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT msgresponse */
22172#define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_LEN 16
22173/* configuration flags */
22174#define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_FLAGS_OFST 0
22175#define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_FLAGS_LEN 4
22176#define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_ENABLE_OFST 0
22177#define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_ENABLE_LBN 0
22178#define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_ENABLE_WIDTH 1
22179/* receiving queue handle (for RSS mode, this is the base queue) */
22180#define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_OFST 4
22181#define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_LEN 4
22182/* receive mode */
22183#define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_OFST 8
22184#define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_LEN 4
22185/* enum: receiving to just the specified queue */
22186#define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_SIMPLE 0x0
22187/* enum: receiving to multiple queues using RSS context */
22188#define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_RSS 0x1
22189/* RSS context (for RX_MODE_RSS) */
22190#define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_OFST 12
22191#define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_LEN 4
22192
22193
22194/***********************************/
22195/* MC_CMD_RMON_STATS_RX_ERRORS
22196 * Per queue rx error stats.
22197 */
22198#define MC_CMD_RMON_STATS_RX_ERRORS 0xfe
22199#undef MC_CMD_0xfe_PRIVILEGE_CTG
22200
22201#define MC_CMD_0xfe_PRIVILEGE_CTG SRIOV_CTG_GENERAL
22202
22203/* MC_CMD_RMON_STATS_RX_ERRORS_IN msgrequest */
22204#define MC_CMD_RMON_STATS_RX_ERRORS_IN_LEN 8
22205/* The rx queue to get stats for. */
22206#define MC_CMD_RMON_STATS_RX_ERRORS_IN_RX_QUEUE_OFST 0
22207#define MC_CMD_RMON_STATS_RX_ERRORS_IN_RX_QUEUE_LEN 4
22208#define MC_CMD_RMON_STATS_RX_ERRORS_IN_FLAGS_OFST 4
22209#define MC_CMD_RMON_STATS_RX_ERRORS_IN_FLAGS_LEN 4
22210#define MC_CMD_RMON_STATS_RX_ERRORS_IN_RST_OFST 4
22211#define MC_CMD_RMON_STATS_RX_ERRORS_IN_RST_LBN 0
22212#define MC_CMD_RMON_STATS_RX_ERRORS_IN_RST_WIDTH 1
22213
22214/* MC_CMD_RMON_STATS_RX_ERRORS_OUT msgresponse */
22215#define MC_CMD_RMON_STATS_RX_ERRORS_OUT_LEN 16
22216#define MC_CMD_RMON_STATS_RX_ERRORS_OUT_CRC_ERRORS_OFST 0
22217#define MC_CMD_RMON_STATS_RX_ERRORS_OUT_CRC_ERRORS_LEN 4
22218#define MC_CMD_RMON_STATS_RX_ERRORS_OUT_TRUNC_ERRORS_OFST 4
22219#define MC_CMD_RMON_STATS_RX_ERRORS_OUT_TRUNC_ERRORS_LEN 4
22220#define MC_CMD_RMON_STATS_RX_ERRORS_OUT_RX_NO_DESC_DROPS_OFST 8
22221#define MC_CMD_RMON_STATS_RX_ERRORS_OUT_RX_NO_DESC_DROPS_LEN 4
22222#define MC_CMD_RMON_STATS_RX_ERRORS_OUT_RX_ABORT_OFST 12
22223#define MC_CMD_RMON_STATS_RX_ERRORS_OUT_RX_ABORT_LEN 4
22224
22225
22226/***********************************/
22227/* MC_CMD_GET_PCIE_RESOURCE_INFO
22228 * Find out about available PCIE resources
22229 */
22230#define MC_CMD_GET_PCIE_RESOURCE_INFO 0xfd
22231#undef MC_CMD_0xfd_PRIVILEGE_CTG
22232
22233#define MC_CMD_0xfd_PRIVILEGE_CTG SRIOV_CTG_GENERAL
22234
22235/* MC_CMD_GET_PCIE_RESOURCE_INFO_IN msgrequest */
22236#define MC_CMD_GET_PCIE_RESOURCE_INFO_IN_LEN 0
22237
22238/* MC_CMD_GET_PCIE_RESOURCE_INFO_OUT msgresponse */
22239#define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_LEN 28
22240/* The maximum number of PFs the device can expose */
22241#define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PFS_OFST 0
22242#define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PFS_LEN 4
22243/* The maximum number of VFs the device can expose in total */
22244#define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VFS_OFST 4
22245#define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VFS_LEN 4
22246/* The maximum number of MSI-X vectors the device can provide in total */
22247#define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VECTORS_OFST 8
22248#define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VECTORS_LEN 4
22249/* the number of MSI-X vectors the device will allocate by default to each PF
22250 */
22251#define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_DEFAULT_PF_VECTORS_OFST 12
22252#define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_DEFAULT_PF_VECTORS_LEN 4
22253/* the number of MSI-X vectors the device will allocate by default to each VF
22254 */
22255#define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_DEFAULT_VF_VECTORS_OFST 16
22256#define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_DEFAULT_VF_VECTORS_LEN 4
22257/* the maximum number of MSI-X vectors the device can allocate to any one PF */
22258#define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PF_VECTORS_OFST 20
22259#define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PF_VECTORS_LEN 4
22260/* the maximum number of MSI-X vectors the device can allocate to any one VF */
22261#define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VF_VECTORS_OFST 24
22262#define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VF_VECTORS_LEN 4
22263
22264
22265/***********************************/
22266/* MC_CMD_GET_PORT_MODES
22267 * Find out about available port modes
22268 */
22269#define MC_CMD_GET_PORT_MODES 0xff
22270#undef MC_CMD_0xff_PRIVILEGE_CTG
22271
22272#define MC_CMD_0xff_PRIVILEGE_CTG SRIOV_CTG_GENERAL
22273
22274/* MC_CMD_GET_PORT_MODES_IN msgrequest */
22275#define MC_CMD_GET_PORT_MODES_IN_LEN 0
22276
22277/* MC_CMD_GET_PORT_MODES_OUT msgresponse */
22278#define MC_CMD_GET_PORT_MODES_OUT_LEN 12
22279/* Bitmask of port modes available on the board (indexed by TLV_PORT_MODE_*)
22280 * that are supported for customer use in production firmware.
22281 */
22282#define MC_CMD_GET_PORT_MODES_OUT_MODES_OFST 0
22283#define MC_CMD_GET_PORT_MODES_OUT_MODES_LEN 4
22284/* Default (canonical) board mode */
22285#define MC_CMD_GET_PORT_MODES_OUT_DEFAULT_MODE_OFST 4
22286#define MC_CMD_GET_PORT_MODES_OUT_DEFAULT_MODE_LEN 4
22287/* Current board mode */
22288#define MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST 8
22289#define MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_LEN 4
22290
22291/* MC_CMD_GET_PORT_MODES_OUT_V2 msgresponse */
22292#define MC_CMD_GET_PORT_MODES_OUT_V2_LEN 16
22293/* Bitmask of port modes available on the board (indexed by TLV_PORT_MODE_*)
22294 * that are supported for customer use in production firmware.
22295 */
22296#define MC_CMD_GET_PORT_MODES_OUT_V2_MODES_OFST 0
22297#define MC_CMD_GET_PORT_MODES_OUT_V2_MODES_LEN 4
22298/* Default (canonical) board mode */
22299#define MC_CMD_GET_PORT_MODES_OUT_V2_DEFAULT_MODE_OFST 4
22300#define MC_CMD_GET_PORT_MODES_OUT_V2_DEFAULT_MODE_LEN 4
22301/* Current board mode */
22302#define MC_CMD_GET_PORT_MODES_OUT_V2_CURRENT_MODE_OFST 8
22303#define MC_CMD_GET_PORT_MODES_OUT_V2_CURRENT_MODE_LEN 4
22304/* Bitmask of engineering port modes available on the board (indexed by
22305 * TLV_PORT_MODE_*). A superset of MC_CMD_GET_PORT_MODES_OUT/MODES that
22306 * contains all modes implemented in firmware for a particular board. Modes
22307 * listed in MODES are considered production modes and should be exposed in
22308 * userland tools. Modes listed in ENGINEERING_MODES, but not in MODES
22309 * should be considered hidden (not to be exposed in userland tools) and for
22310 * engineering use only. There are no other semantic differences and any mode
22311 * listed in either MODES or ENGINEERING_MODES can be set on the board.
22312 */
22313#define MC_CMD_GET_PORT_MODES_OUT_V2_ENGINEERING_MODES_OFST 12
22314#define MC_CMD_GET_PORT_MODES_OUT_V2_ENGINEERING_MODES_LEN 4
22315
22316
22317/***********************************/
22318/* MC_CMD_OVERRIDE_PORT_MODE
22319 * Override flash config port mode for subsequent MC reboot(s). Override data
22320 * is stored in the presistent data section of DMEM and activated on next MC
22321 * warm reboot. A cold reboot resets the override. It is assumed that a
22322 * sufficient number of PFs are available and that port mapping is valid for
22323 * the new port mode, as the override does not affect PF configuration.
22324 */
22325#define MC_CMD_OVERRIDE_PORT_MODE 0x137
22326#undef MC_CMD_0x137_PRIVILEGE_CTG
22327
22328#define MC_CMD_0x137_PRIVILEGE_CTG SRIOV_CTG_ADMIN
22329
22330/* MC_CMD_OVERRIDE_PORT_MODE_IN msgrequest */
22331#define MC_CMD_OVERRIDE_PORT_MODE_IN_LEN 8
22332#define MC_CMD_OVERRIDE_PORT_MODE_IN_FLAGS_OFST 0
22333#define MC_CMD_OVERRIDE_PORT_MODE_IN_FLAGS_LEN 4
22334#define MC_CMD_OVERRIDE_PORT_MODE_IN_ENABLE_OFST 0
22335#define MC_CMD_OVERRIDE_PORT_MODE_IN_ENABLE_LBN 0
22336#define MC_CMD_OVERRIDE_PORT_MODE_IN_ENABLE_WIDTH 1
22337/* New mode (TLV_PORT_MODE_*) to set, if override enabled */
22338#define MC_CMD_OVERRIDE_PORT_MODE_IN_MODE_OFST 4
22339#define MC_CMD_OVERRIDE_PORT_MODE_IN_MODE_LEN 4
22340
22341/* MC_CMD_OVERRIDE_PORT_MODE_OUT msgresponse */
22342#define MC_CMD_OVERRIDE_PORT_MODE_OUT_LEN 0
22343
22344
22345/***********************************/
22346/* MC_CMD_READ_ATB
22347 * Sample voltages on the ATB
22348 */
22349#define MC_CMD_READ_ATB 0x100
22350#undef MC_CMD_0x100_PRIVILEGE_CTG
22351
22352#define MC_CMD_0x100_PRIVILEGE_CTG SRIOV_CTG_INSECURE
22353
22354/* MC_CMD_READ_ATB_IN msgrequest */
22355#define MC_CMD_READ_ATB_IN_LEN 16
22356#define MC_CMD_READ_ATB_IN_SIGNAL_BUS_OFST 0
22357#define MC_CMD_READ_ATB_IN_SIGNAL_BUS_LEN 4
22358#define MC_CMD_READ_ATB_IN_BUS_CCOM 0x0 /* enum */
22359#define MC_CMD_READ_ATB_IN_BUS_CKR 0x1 /* enum */
22360#define MC_CMD_READ_ATB_IN_BUS_CPCIE 0x8 /* enum */
22361#define MC_CMD_READ_ATB_IN_SIGNAL_EN_BITNO_OFST 4
22362#define MC_CMD_READ_ATB_IN_SIGNAL_EN_BITNO_LEN 4
22363#define MC_CMD_READ_ATB_IN_SIGNAL_SEL_OFST 8
22364#define MC_CMD_READ_ATB_IN_SIGNAL_SEL_LEN 4
22365#define MC_CMD_READ_ATB_IN_SETTLING_TIME_US_OFST 12
22366#define MC_CMD_READ_ATB_IN_SETTLING_TIME_US_LEN 4
22367
22368/* MC_CMD_READ_ATB_OUT msgresponse */
22369#define MC_CMD_READ_ATB_OUT_LEN 4
22370#define MC_CMD_READ_ATB_OUT_SAMPLE_MV_OFST 0
22371#define MC_CMD_READ_ATB_OUT_SAMPLE_MV_LEN 4
22372
22373
22374/***********************************/
22375/* MC_CMD_GET_WORKAROUNDS
22376 * Read the list of all implemented and all currently enabled workarounds. The
22377 * enums here must correspond with those in MC_CMD_WORKAROUND.
22378 */
22379#define MC_CMD_GET_WORKAROUNDS 0x59
22380#undef MC_CMD_0x59_PRIVILEGE_CTG
22381
22382#define MC_CMD_0x59_PRIVILEGE_CTG SRIOV_CTG_GENERAL
22383
22384/* MC_CMD_GET_WORKAROUNDS_OUT msgresponse */
22385#define MC_CMD_GET_WORKAROUNDS_OUT_LEN 8
22386/* Each workaround is represented by a single bit according to the enums below.
22387 */
22388#define MC_CMD_GET_WORKAROUNDS_OUT_IMPLEMENTED_OFST 0
22389#define MC_CMD_GET_WORKAROUNDS_OUT_IMPLEMENTED_LEN 4
22390#define MC_CMD_GET_WORKAROUNDS_OUT_ENABLED_OFST 4
22391#define MC_CMD_GET_WORKAROUNDS_OUT_ENABLED_LEN 4
22392/* enum: Bug 17230 work around. */
22393#define MC_CMD_GET_WORKAROUNDS_OUT_BUG17230 0x2
22394/* enum: Bug 35388 work around (unsafe EVQ writes). */
22395#define MC_CMD_GET_WORKAROUNDS_OUT_BUG35388 0x4
22396/* enum: Bug35017 workaround (A64 tables must be identity map) */
22397#define MC_CMD_GET_WORKAROUNDS_OUT_BUG35017 0x8
22398/* enum: Bug 41750 present (MC_CMD_TRIGGER_INTERRUPT won't work) */
22399#define MC_CMD_GET_WORKAROUNDS_OUT_BUG41750 0x10
22400/* enum: Bug 42008 present (Interrupts can overtake associated events). Caution
22401 * - before adding code that queries this workaround, remember that there's
22402 * released Monza firmware that doesn't understand MC_CMD_WORKAROUND_BUG42008,
22403 * and will hence (incorrectly) report that the bug doesn't exist.
22404 */
22405#define MC_CMD_GET_WORKAROUNDS_OUT_BUG42008 0x20
22406/* enum: Bug 26807 features present in firmware (multicast filter chaining) */
22407#define MC_CMD_GET_WORKAROUNDS_OUT_BUG26807 0x40
22408/* enum: Bug 61265 work around (broken EVQ TMR writes). */
22409#define MC_CMD_GET_WORKAROUNDS_OUT_BUG61265 0x80
22410
22411
22412/***********************************/
22413/* MC_CMD_PRIVILEGE_MASK
22414 * Read/set privileges of an arbitrary PCIe function
22415 */
22416#define MC_CMD_PRIVILEGE_MASK 0x5a
22417#undef MC_CMD_0x5a_PRIVILEGE_CTG
22418
22419#define MC_CMD_0x5a_PRIVILEGE_CTG SRIOV_CTG_GENERAL
22420
22421/* MC_CMD_PRIVILEGE_MASK_IN msgrequest */
22422#define MC_CMD_PRIVILEGE_MASK_IN_LEN 8
22423/* The target function to have its mask read or set e.g. PF 0 = 0xFFFF0000, VF
22424 * 1,3 = 0x00030001
22425 */
22426#define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_OFST 0
22427#define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_LEN 4
22428#define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_PF_OFST 0
22429#define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_PF_LBN 0
22430#define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_PF_WIDTH 16
22431#define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_VF_OFST 0
22432#define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_VF_LBN 16
22433#define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_VF_WIDTH 16
22434#define MC_CMD_PRIVILEGE_MASK_IN_VF_NULL 0xffff /* enum */
22435/* New privilege mask to be set. The mask will only be changed if the MSB is
22436 * set to 1.
22437 */
22438#define MC_CMD_PRIVILEGE_MASK_IN_NEW_MASK_OFST 4
22439#define MC_CMD_PRIVILEGE_MASK_IN_NEW_MASK_LEN 4
22440#define MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN 0x1 /* enum */
22441#define MC_CMD_PRIVILEGE_MASK_IN_GRP_LINK 0x2 /* enum */
22442#define MC_CMD_PRIVILEGE_MASK_IN_GRP_ONLOAD 0x4 /* enum */
22443#define MC_CMD_PRIVILEGE_MASK_IN_GRP_PTP 0x8 /* enum */
22444#define MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE_FILTERS 0x10 /* enum */
22445/* enum: Deprecated. Equivalent to MAC_SPOOFING_TX combined with CHANGE_MAC. */
22446#define MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING 0x20
22447#define MC_CMD_PRIVILEGE_MASK_IN_GRP_UNICAST 0x40 /* enum */
22448#define MC_CMD_PRIVILEGE_MASK_IN_GRP_MULTICAST 0x80 /* enum */
22449#define MC_CMD_PRIVILEGE_MASK_IN_GRP_BROADCAST 0x100 /* enum */
22450#define MC_CMD_PRIVILEGE_MASK_IN_GRP_ALL_MULTICAST 0x200 /* enum */
22451#define MC_CMD_PRIVILEGE_MASK_IN_GRP_PROMISCUOUS 0x400 /* enum */
22452/* enum: Allows to set the TX packets' source MAC address to any arbitrary MAC
22453 * adress.
22454 */
22455#define MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING_TX 0x800
22456/* enum: Privilege that allows a Function to change the MAC address configured
22457 * in its associated vAdapter/vPort.
22458 */
22459#define MC_CMD_PRIVILEGE_MASK_IN_GRP_CHANGE_MAC 0x1000
22460/* enum: Privilege that allows a Function to install filters that specify VLANs
22461 * that are not in the permit list for the associated vPort. This privilege is
22462 * primarily to support ESX where vPorts are created that restrict traffic to
22463 * only a set of permitted VLANs. See the vPort flag FLAG_VLAN_RESTRICT.
22464 */
22465#define MC_CMD_PRIVILEGE_MASK_IN_GRP_UNRESTRICTED_VLAN 0x2000
22466/* enum: Privilege for insecure commands. Commands that belong to this group
22467 * are not permitted on secure adapters regardless of the privilege mask.
22468 */
22469#define MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE 0x4000
22470/* enum: Trusted Server Adapter (TSA) / ServerLock. Privilege for
22471 * administrator-level operations that are not allowed from the local host once
22472 * an adapter has Bound to a remote ServerLock Controller (see doxbox
22473 * SF-117064-DG for background).
22474 */
22475#define MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN_TSA_UNBOUND 0x8000
22476/* enum: Control the Match-Action Engine if present. See mcdi_mae.yml. */
22477#define MC_CMD_PRIVILEGE_MASK_IN_GRP_MAE 0x10000
22478/* enum: This Function/client may call MC_CMD_CLIENT_ALLOC to create new
22479 * dynamic client children of itself.
22480 */
22481#define MC_CMD_PRIVILEGE_MASK_IN_GRP_ALLOC_CLIENT 0x20000
22482/* enum: A dynamic client with this privilege may perform all the same DMA
22483 * operations as the function client from which it is descended.
22484 */
22485#define MC_CMD_PRIVILEGE_MASK_IN_GRP_FUNC_DMA 0x40000
22486/* enum: A client with this privilege may perform DMA as any PCIe function on
22487 * the device and to on-device DDR. It allows clients to use TX-DESC2CMPT-DESC
22488 * descriptors, and to use TX-SEG-DESC and TX-MEM2MEM-DESC with an address
22489 * space override (i.e. with the ADDR_SPC_EN bit set).
22490 */
22491#define MC_CMD_PRIVILEGE_MASK_IN_GRP_ARBITRARY_DMA 0x80000
22492/* enum: Set this bit to indicate that a new privilege mask is to be set,
22493 * otherwise the command will only read the existing mask.
22494 */
22495#define MC_CMD_PRIVILEGE_MASK_IN_DO_CHANGE 0x80000000
22496
22497/* MC_CMD_PRIVILEGE_MASK_OUT msgresponse */
22498#define MC_CMD_PRIVILEGE_MASK_OUT_LEN 4
22499/* For an admin function, always all the privileges are reported. */
22500#define MC_CMD_PRIVILEGE_MASK_OUT_OLD_MASK_OFST 0
22501#define MC_CMD_PRIVILEGE_MASK_OUT_OLD_MASK_LEN 4
22502
22503
22504/***********************************/
22505/* MC_CMD_LINK_STATE_MODE
22506 * Read/set link state mode of a VF
22507 */
22508#define MC_CMD_LINK_STATE_MODE 0x5c
22509#undef MC_CMD_0x5c_PRIVILEGE_CTG
22510
22511#define MC_CMD_0x5c_PRIVILEGE_CTG SRIOV_CTG_GENERAL
22512
22513/* MC_CMD_LINK_STATE_MODE_IN msgrequest */
22514#define MC_CMD_LINK_STATE_MODE_IN_LEN 8
22515/* The target function to have its link state mode read or set, must be a VF
22516 * e.g. VF 1,3 = 0x00030001
22517 */
22518#define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_OFST 0
22519#define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_LEN 4
22520#define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_PF_OFST 0
22521#define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_PF_LBN 0
22522#define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_PF_WIDTH 16
22523#define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_VF_OFST 0
22524#define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_VF_LBN 16
22525#define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_VF_WIDTH 16
22526/* New link state mode to be set */
22527#define MC_CMD_LINK_STATE_MODE_IN_NEW_MODE_OFST 4
22528#define MC_CMD_LINK_STATE_MODE_IN_NEW_MODE_LEN 4
22529#define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_AUTO 0x0 /* enum */
22530#define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_UP 0x1 /* enum */
22531#define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_DOWN 0x2 /* enum */
22532/* enum: Use this value to just read the existing setting without modifying it.
22533 */
22534#define MC_CMD_LINK_STATE_MODE_IN_DO_NOT_CHANGE 0xffffffff
22535
22536/* MC_CMD_LINK_STATE_MODE_OUT msgresponse */
22537#define MC_CMD_LINK_STATE_MODE_OUT_LEN 4
22538#define MC_CMD_LINK_STATE_MODE_OUT_OLD_MODE_OFST 0
22539#define MC_CMD_LINK_STATE_MODE_OUT_OLD_MODE_LEN 4
22540
22541
22542/***********************************/
22543/* MC_CMD_GET_SNAPSHOT_LENGTH
22544 * Obtain the current range of allowable values for the SNAPSHOT_LENGTH
22545 * parameter to MC_CMD_INIT_RXQ.
22546 */
22547#define MC_CMD_GET_SNAPSHOT_LENGTH 0x101
22548#undef MC_CMD_0x101_PRIVILEGE_CTG
22549
22550#define MC_CMD_0x101_PRIVILEGE_CTG SRIOV_CTG_GENERAL
22551
22552/* MC_CMD_GET_SNAPSHOT_LENGTH_IN msgrequest */
22553#define MC_CMD_GET_SNAPSHOT_LENGTH_IN_LEN 0
22554
22555/* MC_CMD_GET_SNAPSHOT_LENGTH_OUT msgresponse */
22556#define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_LEN 8
22557/* Minimum acceptable snapshot length. */
22558#define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MIN_OFST 0
22559#define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MIN_LEN 4
22560/* Maximum acceptable snapshot length. */
22561#define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MAX_OFST 4
22562#define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MAX_LEN 4
22563
22564
22565/***********************************/
22566/* MC_CMD_FUSE_DIAGS
22567 * Additional fuse diagnostics
22568 */
22569#define MC_CMD_FUSE_DIAGS 0x102
22570#undef MC_CMD_0x102_PRIVILEGE_CTG
22571
22572#define MC_CMD_0x102_PRIVILEGE_CTG SRIOV_CTG_INSECURE
22573
22574/* MC_CMD_FUSE_DIAGS_IN msgrequest */
22575#define MC_CMD_FUSE_DIAGS_IN_LEN 0
22576
22577/* MC_CMD_FUSE_DIAGS_OUT msgresponse */
22578#define MC_CMD_FUSE_DIAGS_OUT_LEN 48
22579/* Total number of mismatched bits between pairs in area 0 */
22580#define MC_CMD_FUSE_DIAGS_OUT_AREA0_MISMATCH_BITS_OFST 0
22581#define MC_CMD_FUSE_DIAGS_OUT_AREA0_MISMATCH_BITS_LEN 4
22582/* Total number of unexpectedly clear (set in B but not A) bits in area 0 */
22583#define MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_A_BAD_BITS_OFST 4
22584#define MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_A_BAD_BITS_LEN 4
22585/* Total number of unexpectedly clear (set in A but not B) bits in area 0 */
22586#define MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_B_BAD_BITS_OFST 8
22587#define MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_B_BAD_BITS_LEN 4
22588/* Checksum of data after logical OR of pairs in area 0 */
22589#define MC_CMD_FUSE_DIAGS_OUT_AREA0_CHECKSUM_OFST 12
22590#define MC_CMD_FUSE_DIAGS_OUT_AREA0_CHECKSUM_LEN 4
22591/* Total number of mismatched bits between pairs in area 1 */
22592#define MC_CMD_FUSE_DIAGS_OUT_AREA1_MISMATCH_BITS_OFST 16
22593#define MC_CMD_FUSE_DIAGS_OUT_AREA1_MISMATCH_BITS_LEN 4
22594/* Total number of unexpectedly clear (set in B but not A) bits in area 1 */
22595#define MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_A_BAD_BITS_OFST 20
22596#define MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_A_BAD_BITS_LEN 4
22597/* Total number of unexpectedly clear (set in A but not B) bits in area 1 */
22598#define MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_B_BAD_BITS_OFST 24
22599#define MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_B_BAD_BITS_LEN 4
22600/* Checksum of data after logical OR of pairs in area 1 */
22601#define MC_CMD_FUSE_DIAGS_OUT_AREA1_CHECKSUM_OFST 28
22602#define MC_CMD_FUSE_DIAGS_OUT_AREA1_CHECKSUM_LEN 4
22603/* Total number of mismatched bits between pairs in area 2 */
22604#define MC_CMD_FUSE_DIAGS_OUT_AREA2_MISMATCH_BITS_OFST 32
22605#define MC_CMD_FUSE_DIAGS_OUT_AREA2_MISMATCH_BITS_LEN 4
22606/* Total number of unexpectedly clear (set in B but not A) bits in area 2 */
22607#define MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_A_BAD_BITS_OFST 36
22608#define MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_A_BAD_BITS_LEN 4
22609/* Total number of unexpectedly clear (set in A but not B) bits in area 2 */
22610#define MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_B_BAD_BITS_OFST 40
22611#define MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_B_BAD_BITS_LEN 4
22612/* Checksum of data after logical OR of pairs in area 2 */
22613#define MC_CMD_FUSE_DIAGS_OUT_AREA2_CHECKSUM_OFST 44
22614#define MC_CMD_FUSE_DIAGS_OUT_AREA2_CHECKSUM_LEN 4
22615
22616
22617/***********************************/
22618/* MC_CMD_PRIVILEGE_MODIFY
22619 * Modify the privileges of a set of PCIe functions. Note that this operation
22620 * only effects non-admin functions unless the admin privilege itself is
22621 * included in one of the masks provided.
22622 */
22623#define MC_CMD_PRIVILEGE_MODIFY 0x60
22624#undef MC_CMD_0x60_PRIVILEGE_CTG
22625
22626#define MC_CMD_0x60_PRIVILEGE_CTG SRIOV_CTG_ADMIN
22627
22628/* MC_CMD_PRIVILEGE_MODIFY_IN msgrequest */
22629#define MC_CMD_PRIVILEGE_MODIFY_IN_LEN 16
22630/* The groups of functions to have their privilege masks modified. */
22631#define MC_CMD_PRIVILEGE_MODIFY_IN_FN_GROUP_OFST 0
22632#define MC_CMD_PRIVILEGE_MODIFY_IN_FN_GROUP_LEN 4
22633#define MC_CMD_PRIVILEGE_MODIFY_IN_NONE 0x0 /* enum */
22634#define MC_CMD_PRIVILEGE_MODIFY_IN_ALL 0x1 /* enum */
22635#define MC_CMD_PRIVILEGE_MODIFY_IN_PFS_ONLY 0x2 /* enum */
22636#define MC_CMD_PRIVILEGE_MODIFY_IN_VFS_ONLY 0x3 /* enum */
22637#define MC_CMD_PRIVILEGE_MODIFY_IN_VFS_OF_PF 0x4 /* enum */
22638#define MC_CMD_PRIVILEGE_MODIFY_IN_ONE 0x5 /* enum */
22639/* For VFS_OF_PF specify the PF, for ONE specify the target function */
22640#define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_OFST 4
22641#define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_LEN 4
22642#define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_PF_OFST 4
22643#define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_PF_LBN 0
22644#define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_PF_WIDTH 16
22645#define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_VF_OFST 4
22646#define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_VF_LBN 16
22647#define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_VF_WIDTH 16
22648/* Privileges to be added to the target functions. For privilege definitions
22649 * refer to the command MC_CMD_PRIVILEGE_MASK
22650 */
22651#define MC_CMD_PRIVILEGE_MODIFY_IN_ADD_MASK_OFST 8
22652#define MC_CMD_PRIVILEGE_MODIFY_IN_ADD_MASK_LEN 4
22653/* Privileges to be removed from the target functions. For privilege
22654 * definitions refer to the command MC_CMD_PRIVILEGE_MASK
22655 */
22656#define MC_CMD_PRIVILEGE_MODIFY_IN_REMOVE_MASK_OFST 12
22657#define MC_CMD_PRIVILEGE_MODIFY_IN_REMOVE_MASK_LEN 4
22658
22659/* MC_CMD_PRIVILEGE_MODIFY_OUT msgresponse */
22660#define MC_CMD_PRIVILEGE_MODIFY_OUT_LEN 0
22661
22662
22663/***********************************/
22664/* MC_CMD_XPM_READ_BYTES
22665 * Read XPM memory
22666 */
22667#define MC_CMD_XPM_READ_BYTES 0x103
22668#undef MC_CMD_0x103_PRIVILEGE_CTG
22669
22670#define MC_CMD_0x103_PRIVILEGE_CTG SRIOV_CTG_ADMIN
22671
22672/* MC_CMD_XPM_READ_BYTES_IN msgrequest */
22673#define MC_CMD_XPM_READ_BYTES_IN_LEN 8
22674/* Start address (byte) */
22675#define MC_CMD_XPM_READ_BYTES_IN_ADDR_OFST 0
22676#define MC_CMD_XPM_READ_BYTES_IN_ADDR_LEN 4
22677/* Count (bytes) */
22678#define MC_CMD_XPM_READ_BYTES_IN_COUNT_OFST 4
22679#define MC_CMD_XPM_READ_BYTES_IN_COUNT_LEN 4
22680
22681/* MC_CMD_XPM_READ_BYTES_OUT msgresponse */
22682#define MC_CMD_XPM_READ_BYTES_OUT_LENMIN 0
22683#define MC_CMD_XPM_READ_BYTES_OUT_LENMAX 252
22684#define MC_CMD_XPM_READ_BYTES_OUT_LENMAX_MCDI2 1020
22685#define MC_CMD_XPM_READ_BYTES_OUT_LEN(num) (0+1*(num))
22686#define MC_CMD_XPM_READ_BYTES_OUT_DATA_NUM(len) (((len)-0)/1)
22687/* Data */
22688#define MC_CMD_XPM_READ_BYTES_OUT_DATA_OFST 0
22689#define MC_CMD_XPM_READ_BYTES_OUT_DATA_LEN 1
22690#define MC_CMD_XPM_READ_BYTES_OUT_DATA_MINNUM 0
22691#define MC_CMD_XPM_READ_BYTES_OUT_DATA_MAXNUM 252
22692#define MC_CMD_XPM_READ_BYTES_OUT_DATA_MAXNUM_MCDI2 1020
22693
22694
22695/***********************************/
22696/* MC_CMD_XPM_WRITE_BYTES
22697 * Write XPM memory
22698 */
22699#define MC_CMD_XPM_WRITE_BYTES 0x104
22700#undef MC_CMD_0x104_PRIVILEGE_CTG
22701
22702#define MC_CMD_0x104_PRIVILEGE_CTG SRIOV_CTG_INSECURE
22703
22704/* MC_CMD_XPM_WRITE_BYTES_IN msgrequest */
22705#define MC_CMD_XPM_WRITE_BYTES_IN_LENMIN 8
22706#define MC_CMD_XPM_WRITE_BYTES_IN_LENMAX 252
22707#define MC_CMD_XPM_WRITE_BYTES_IN_LENMAX_MCDI2 1020
22708#define MC_CMD_XPM_WRITE_BYTES_IN_LEN(num) (8+1*(num))
22709#define MC_CMD_XPM_WRITE_BYTES_IN_DATA_NUM(len) (((len)-8)/1)
22710/* Start address (byte) */
22711#define MC_CMD_XPM_WRITE_BYTES_IN_ADDR_OFST 0
22712#define MC_CMD_XPM_WRITE_BYTES_IN_ADDR_LEN 4
22713/* Count (bytes) */
22714#define MC_CMD_XPM_WRITE_BYTES_IN_COUNT_OFST 4
22715#define MC_CMD_XPM_WRITE_BYTES_IN_COUNT_LEN 4
22716/* Data */
22717#define MC_CMD_XPM_WRITE_BYTES_IN_DATA_OFST 8
22718#define MC_CMD_XPM_WRITE_BYTES_IN_DATA_LEN 1
22719#define MC_CMD_XPM_WRITE_BYTES_IN_DATA_MINNUM 0
22720#define MC_CMD_XPM_WRITE_BYTES_IN_DATA_MAXNUM 244
22721#define MC_CMD_XPM_WRITE_BYTES_IN_DATA_MAXNUM_MCDI2 1012
22722
22723/* MC_CMD_XPM_WRITE_BYTES_OUT msgresponse */
22724#define MC_CMD_XPM_WRITE_BYTES_OUT_LEN 0
22725
22726
22727/***********************************/
22728/* MC_CMD_XPM_READ_SECTOR
22729 * Read XPM sector
22730 */
22731#define MC_CMD_XPM_READ_SECTOR 0x105
22732#undef MC_CMD_0x105_PRIVILEGE_CTG
22733
22734#define MC_CMD_0x105_PRIVILEGE_CTG SRIOV_CTG_INSECURE
22735
22736/* MC_CMD_XPM_READ_SECTOR_IN msgrequest */
22737#define MC_CMD_XPM_READ_SECTOR_IN_LEN 8
22738/* Sector index */
22739#define MC_CMD_XPM_READ_SECTOR_IN_INDEX_OFST 0
22740#define MC_CMD_XPM_READ_SECTOR_IN_INDEX_LEN 4
22741/* Sector size */
22742#define MC_CMD_XPM_READ_SECTOR_IN_SIZE_OFST 4
22743#define MC_CMD_XPM_READ_SECTOR_IN_SIZE_LEN 4
22744
22745/* MC_CMD_XPM_READ_SECTOR_OUT msgresponse */
22746#define MC_CMD_XPM_READ_SECTOR_OUT_LENMIN 4
22747#define MC_CMD_XPM_READ_SECTOR_OUT_LENMAX 36
22748#define MC_CMD_XPM_READ_SECTOR_OUT_LENMAX_MCDI2 36
22749#define MC_CMD_XPM_READ_SECTOR_OUT_LEN(num) (4+1*(num))
22750#define MC_CMD_XPM_READ_SECTOR_OUT_DATA_NUM(len) (((len)-4)/1)
22751/* Sector type */
22752#define MC_CMD_XPM_READ_SECTOR_OUT_TYPE_OFST 0
22753#define MC_CMD_XPM_READ_SECTOR_OUT_TYPE_LEN 4
22754#define MC_CMD_XPM_READ_SECTOR_OUT_BLANK 0x0 /* enum */
22755#define MC_CMD_XPM_READ_SECTOR_OUT_CRYPTO_KEY_128 0x1 /* enum */
22756#define MC_CMD_XPM_READ_SECTOR_OUT_CRYPTO_KEY_256 0x2 /* enum */
22757#define MC_CMD_XPM_READ_SECTOR_OUT_CRYPTO_DATA 0x3 /* enum */
22758#define MC_CMD_XPM_READ_SECTOR_OUT_INVALID 0xff /* enum */
22759/* Sector data */
22760#define MC_CMD_XPM_READ_SECTOR_OUT_DATA_OFST 4
22761#define MC_CMD_XPM_READ_SECTOR_OUT_DATA_LEN 1
22762#define MC_CMD_XPM_READ_SECTOR_OUT_DATA_MINNUM 0
22763#define MC_CMD_XPM_READ_SECTOR_OUT_DATA_MAXNUM 32
22764#define MC_CMD_XPM_READ_SECTOR_OUT_DATA_MAXNUM_MCDI2 32
22765
22766
22767/***********************************/
22768/* MC_CMD_XPM_WRITE_SECTOR
22769 * Write XPM sector
22770 */
22771#define MC_CMD_XPM_WRITE_SECTOR 0x106
22772#undef MC_CMD_0x106_PRIVILEGE_CTG
22773
22774#define MC_CMD_0x106_PRIVILEGE_CTG SRIOV_CTG_INSECURE
22775
22776/* MC_CMD_XPM_WRITE_SECTOR_IN msgrequest */
22777#define MC_CMD_XPM_WRITE_SECTOR_IN_LENMIN 12
22778#define MC_CMD_XPM_WRITE_SECTOR_IN_LENMAX 44
22779#define MC_CMD_XPM_WRITE_SECTOR_IN_LENMAX_MCDI2 44
22780#define MC_CMD_XPM_WRITE_SECTOR_IN_LEN(num) (12+1*(num))
22781#define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_NUM(len) (((len)-12)/1)
22782/* If writing fails due to an uncorrectable error, try up to RETRIES following
22783 * sectors (or until no more space available). If 0, only one write attempt is
22784 * made. Note that uncorrectable errors are unlikely, thanks to XPM self-repair
22785 * mechanism.
22786 */
22787#define MC_CMD_XPM_WRITE_SECTOR_IN_RETRIES_OFST 0
22788#define MC_CMD_XPM_WRITE_SECTOR_IN_RETRIES_LEN 1
22789#define MC_CMD_XPM_WRITE_SECTOR_IN_RESERVED_OFST 1
22790#define MC_CMD_XPM_WRITE_SECTOR_IN_RESERVED_LEN 3
22791/* Sector type */
22792#define MC_CMD_XPM_WRITE_SECTOR_IN_TYPE_OFST 4
22793#define MC_CMD_XPM_WRITE_SECTOR_IN_TYPE_LEN 4
22794/* Enum values, see field(s): */
22795/* MC_CMD_XPM_READ_SECTOR/MC_CMD_XPM_READ_SECTOR_OUT/TYPE */
22796/* Sector size */
22797#define MC_CMD_XPM_WRITE_SECTOR_IN_SIZE_OFST 8
22798#define MC_CMD_XPM_WRITE_SECTOR_IN_SIZE_LEN 4
22799/* Sector data */
22800#define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_OFST 12
22801#define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_LEN 1
22802#define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_MINNUM 0
22803#define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_MAXNUM 32
22804#define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_MAXNUM_MCDI2 32
22805
22806/* MC_CMD_XPM_WRITE_SECTOR_OUT msgresponse */
22807#define MC_CMD_XPM_WRITE_SECTOR_OUT_LEN 4
22808/* New sector index */
22809#define MC_CMD_XPM_WRITE_SECTOR_OUT_INDEX_OFST 0
22810#define MC_CMD_XPM_WRITE_SECTOR_OUT_INDEX_LEN 4
22811
22812
22813/***********************************/
22814/* MC_CMD_XPM_INVALIDATE_SECTOR
22815 * Invalidate XPM sector
22816 */
22817#define MC_CMD_XPM_INVALIDATE_SECTOR 0x107
22818#undef MC_CMD_0x107_PRIVILEGE_CTG
22819
22820#define MC_CMD_0x107_PRIVILEGE_CTG SRIOV_CTG_INSECURE
22821
22822/* MC_CMD_XPM_INVALIDATE_SECTOR_IN msgrequest */
22823#define MC_CMD_XPM_INVALIDATE_SECTOR_IN_LEN 4
22824/* Sector index */
22825#define MC_CMD_XPM_INVALIDATE_SECTOR_IN_INDEX_OFST 0
22826#define MC_CMD_XPM_INVALIDATE_SECTOR_IN_INDEX_LEN 4
22827
22828/* MC_CMD_XPM_INVALIDATE_SECTOR_OUT msgresponse */
22829#define MC_CMD_XPM_INVALIDATE_SECTOR_OUT_LEN 0
22830
22831
22832/***********************************/
22833/* MC_CMD_XPM_BLANK_CHECK
22834 * Blank-check XPM memory and report bad locations
22835 */
22836#define MC_CMD_XPM_BLANK_CHECK 0x108
22837#undef MC_CMD_0x108_PRIVILEGE_CTG
22838
22839#define MC_CMD_0x108_PRIVILEGE_CTG SRIOV_CTG_INSECURE
22840
22841/* MC_CMD_XPM_BLANK_CHECK_IN msgrequest */
22842#define MC_CMD_XPM_BLANK_CHECK_IN_LEN 8
22843/* Start address (byte) */
22844#define MC_CMD_XPM_BLANK_CHECK_IN_ADDR_OFST 0
22845#define MC_CMD_XPM_BLANK_CHECK_IN_ADDR_LEN 4
22846/* Count (bytes) */
22847#define MC_CMD_XPM_BLANK_CHECK_IN_COUNT_OFST 4
22848#define MC_CMD_XPM_BLANK_CHECK_IN_COUNT_LEN 4
22849
22850/* MC_CMD_XPM_BLANK_CHECK_OUT msgresponse */
22851#define MC_CMD_XPM_BLANK_CHECK_OUT_LENMIN 4
22852#define MC_CMD_XPM_BLANK_CHECK_OUT_LENMAX 252
22853#define MC_CMD_XPM_BLANK_CHECK_OUT_LENMAX_MCDI2 1020
22854#define MC_CMD_XPM_BLANK_CHECK_OUT_LEN(num) (4+2*(num))
22855#define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_NUM(len) (((len)-4)/2)
22856/* Total number of bad (non-blank) locations */
22857#define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_COUNT_OFST 0
22858#define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_COUNT_LEN 4
22859/* Addresses of bad locations (may be less than BAD_COUNT, if all cannot fit
22860 * into MCDI response)
22861 */
22862#define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_OFST 4
22863#define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_LEN 2
22864#define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_MINNUM 0
22865#define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_MAXNUM 124
22866#define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_MAXNUM_MCDI2 508
22867
22868
22869/***********************************/
22870/* MC_CMD_XPM_REPAIR
22871 * Blank-check and repair XPM memory
22872 */
22873#define MC_CMD_XPM_REPAIR 0x109
22874#undef MC_CMD_0x109_PRIVILEGE_CTG
22875
22876#define MC_CMD_0x109_PRIVILEGE_CTG SRIOV_CTG_INSECURE
22877
22878/* MC_CMD_XPM_REPAIR_IN msgrequest */
22879#define MC_CMD_XPM_REPAIR_IN_LEN 8
22880/* Start address (byte) */
22881#define MC_CMD_XPM_REPAIR_IN_ADDR_OFST 0
22882#define MC_CMD_XPM_REPAIR_IN_ADDR_LEN 4
22883/* Count (bytes) */
22884#define MC_CMD_XPM_REPAIR_IN_COUNT_OFST 4
22885#define MC_CMD_XPM_REPAIR_IN_COUNT_LEN 4
22886
22887/* MC_CMD_XPM_REPAIR_OUT msgresponse */
22888#define MC_CMD_XPM_REPAIR_OUT_LEN 0
22889
22890
22891/***********************************/
22892/* MC_CMD_XPM_DECODER_TEST
22893 * Test XPM memory address decoders for gross manufacturing defects. Can only
22894 * be performed on an unprogrammed part.
22895 */
22896#define MC_CMD_XPM_DECODER_TEST 0x10a
22897#undef MC_CMD_0x10a_PRIVILEGE_CTG
22898
22899#define MC_CMD_0x10a_PRIVILEGE_CTG SRIOV_CTG_INSECURE
22900
22901/* MC_CMD_XPM_DECODER_TEST_IN msgrequest */
22902#define MC_CMD_XPM_DECODER_TEST_IN_LEN 0
22903
22904/* MC_CMD_XPM_DECODER_TEST_OUT msgresponse */
22905#define MC_CMD_XPM_DECODER_TEST_OUT_LEN 0
22906
22907
22908/***********************************/
22909/* MC_CMD_XPM_WRITE_TEST
22910 * XPM memory write test. Test XPM write logic for gross manufacturing defects
22911 * by writing to a dedicated test row. There are 16 locations in the test row
22912 * and the test can only be performed on locations that have not been
22913 * previously used (i.e. can be run at most 16 times). The test will pick the
22914 * first available location to use, or fail with ENOSPC if none left.
22915 */
22916#define MC_CMD_XPM_WRITE_TEST 0x10b
22917#undef MC_CMD_0x10b_PRIVILEGE_CTG
22918
22919#define MC_CMD_0x10b_PRIVILEGE_CTG SRIOV_CTG_INSECURE
22920
22921/* MC_CMD_XPM_WRITE_TEST_IN msgrequest */
22922#define MC_CMD_XPM_WRITE_TEST_IN_LEN 0
22923
22924/* MC_CMD_XPM_WRITE_TEST_OUT msgresponse */
22925#define MC_CMD_XPM_WRITE_TEST_OUT_LEN 0
22926
22927
22928/***********************************/
22929/* MC_CMD_EXEC_SIGNED
22930 * Check the CMAC of the contents of IMEM and DMEM against the value supplied
22931 * and if correct begin execution from the start of IMEM. The caller supplies a
22932 * key ID, the length of IMEM and DMEM to validate and the expected CMAC. CMAC
22933 * computation runs from the start of IMEM, and from the start of DMEM + 16k,
22934 * to match flash booting. The command will respond with EINVAL if the CMAC
22935 * does match, otherwise it will respond with success before it jumps to IMEM.
22936 */
22937#define MC_CMD_EXEC_SIGNED 0x10c
22938#undef MC_CMD_0x10c_PRIVILEGE_CTG
22939
22940#define MC_CMD_0x10c_PRIVILEGE_CTG SRIOV_CTG_ADMIN
22941
22942/* MC_CMD_EXEC_SIGNED_IN msgrequest */
22943#define MC_CMD_EXEC_SIGNED_IN_LEN 28
22944/* the length of code to include in the CMAC */
22945#define MC_CMD_EXEC_SIGNED_IN_CODELEN_OFST 0
22946#define MC_CMD_EXEC_SIGNED_IN_CODELEN_LEN 4
22947/* the length of date to include in the CMAC */
22948#define MC_CMD_EXEC_SIGNED_IN_DATALEN_OFST 4
22949#define MC_CMD_EXEC_SIGNED_IN_DATALEN_LEN 4
22950/* the XPM sector containing the key to use */
22951#define MC_CMD_EXEC_SIGNED_IN_KEYSECTOR_OFST 8
22952#define MC_CMD_EXEC_SIGNED_IN_KEYSECTOR_LEN 4
22953/* the expected CMAC value */
22954#define MC_CMD_EXEC_SIGNED_IN_CMAC_OFST 12
22955#define MC_CMD_EXEC_SIGNED_IN_CMAC_LEN 16
22956
22957/* MC_CMD_EXEC_SIGNED_OUT msgresponse */
22958#define MC_CMD_EXEC_SIGNED_OUT_LEN 0
22959
22960
22961/***********************************/
22962/* MC_CMD_PREPARE_SIGNED
22963 * Prepare to upload a signed image. This will scrub the specified length of
22964 * the data region, which must be at least as large as the DATALEN supplied to
22965 * MC_CMD_EXEC_SIGNED.
22966 */
22967#define MC_CMD_PREPARE_SIGNED 0x10d
22968#undef MC_CMD_0x10d_PRIVILEGE_CTG
22969
22970#define MC_CMD_0x10d_PRIVILEGE_CTG SRIOV_CTG_ADMIN
22971
22972/* MC_CMD_PREPARE_SIGNED_IN msgrequest */
22973#define MC_CMD_PREPARE_SIGNED_IN_LEN 4
22974/* the length of data area to clear */
22975#define MC_CMD_PREPARE_SIGNED_IN_DATALEN_OFST 0
22976#define MC_CMD_PREPARE_SIGNED_IN_DATALEN_LEN 4
22977
22978/* MC_CMD_PREPARE_SIGNED_OUT msgresponse */
22979#define MC_CMD_PREPARE_SIGNED_OUT_LEN 0
22980
22981
22982/* TUNNEL_ENCAP_UDP_PORT_ENTRY structuredef */
22983#define TUNNEL_ENCAP_UDP_PORT_ENTRY_LEN 4
22984/* UDP port (the standard ports are named below but any port may be used) */
22985#define TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_OFST 0
22986#define TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_LEN 2
22987/* enum: the IANA allocated UDP port for VXLAN */
22988#define TUNNEL_ENCAP_UDP_PORT_ENTRY_IANA_VXLAN_UDP_PORT 0x12b5
22989/* enum: the IANA allocated UDP port for Geneve */
22990#define TUNNEL_ENCAP_UDP_PORT_ENTRY_IANA_GENEVE_UDP_PORT 0x17c1
22991#define TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_LBN 0
22992#define TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_WIDTH 16
22993/* tunnel encapsulation protocol (only those named below are supported) */
22994#define TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_OFST 2
22995#define TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_LEN 2
22996/* enum: This port will be used for VXLAN on both IPv4 and IPv6 */
22997#define TUNNEL_ENCAP_UDP_PORT_ENTRY_VXLAN 0x0
22998/* enum: This port will be used for Geneve on both IPv4 and IPv6 */
22999#define TUNNEL_ENCAP_UDP_PORT_ENTRY_GENEVE 0x1
23000#define TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_LBN 16
23001#define TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_WIDTH 16
23002
23003
23004/***********************************/
23005/* MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS
23006 * Configure UDP ports for tunnel encapsulation hardware acceleration. The
23007 * parser-dispatcher will attempt to parse traffic on these ports as tunnel
23008 * encapsulation PDUs and filter them using the tunnel encapsulation filter
23009 * chain rather than the standard filter chain. Note that this command can
23010 * cause all functions to see a reset. (Available on Medford only.)
23011 */
23012#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS 0x117
23013#undef MC_CMD_0x117_PRIVILEGE_CTG
23014
23015#define MC_CMD_0x117_PRIVILEGE_CTG SRIOV_CTG_ADMIN
23016
23017/* MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN msgrequest */
23018#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMIN 4
23019#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMAX 68
23020#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMAX_MCDI2 68
23021#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LEN(num) (4+4*(num))
23022#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_NUM(len) (((len)-4)/4)
23023/* Flags */
23024#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS_OFST 0
23025#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS_LEN 2
23026#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING_OFST 0
23027#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING_LBN 0
23028#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING_WIDTH 1
23029/* The number of entries in the ENTRIES array */
23030#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_OFST 2
23031#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_LEN 2
23032/* Entries defining the UDP port to protocol mapping, each laid out as a
23033 * TUNNEL_ENCAP_UDP_PORT_ENTRY
23034 */
23035#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_OFST 4
23036#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_LEN 4
23037#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MINNUM 0
23038#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MAXNUM 16
23039#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MAXNUM_MCDI2 16
23040
23041/* MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT msgresponse */
23042#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_LEN 2
23043/* Flags */
23044#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_FLAGS_OFST 0
23045#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_FLAGS_LEN 2
23046#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_OFST 0
23047#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_LBN 0
23048#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_WIDTH 1
23049
23050
23051/***********************************/
23052/* MC_CMD_RX_BALANCING
23053 * Configure a port upconverter to distribute the packets on both RX engines.
23054 * Packets are distributed based on a table with the destination vFIFO. The
23055 * index of the table is a hash of source and destination of IPV4 and VLAN
23056 * priority.
23057 */
23058#define MC_CMD_RX_BALANCING 0x118
23059#undef MC_CMD_0x118_PRIVILEGE_CTG
23060
23061#define MC_CMD_0x118_PRIVILEGE_CTG SRIOV_CTG_ADMIN
23062
23063/* MC_CMD_RX_BALANCING_IN msgrequest */
23064#define MC_CMD_RX_BALANCING_IN_LEN 16
23065/* The RX port whose upconverter table will be modified */
23066#define MC_CMD_RX_BALANCING_IN_PORT_OFST 0
23067#define MC_CMD_RX_BALANCING_IN_PORT_LEN 4
23068/* The VLAN priority associated to the table index and vFIFO */
23069#define MC_CMD_RX_BALANCING_IN_PRIORITY_OFST 4
23070#define MC_CMD_RX_BALANCING_IN_PRIORITY_LEN 4
23071/* The resulting bit of SRC^DST for indexing the table */
23072#define MC_CMD_RX_BALANCING_IN_SRC_DST_OFST 8
23073#define MC_CMD_RX_BALANCING_IN_SRC_DST_LEN 4
23074/* The RX engine to which the vFIFO in the table entry will point to */
23075#define MC_CMD_RX_BALANCING_IN_ENG_OFST 12
23076#define MC_CMD_RX_BALANCING_IN_ENG_LEN 4
23077
23078/* MC_CMD_RX_BALANCING_OUT msgresponse */
23079#define MC_CMD_RX_BALANCING_OUT_LEN 0
23080
23081
23082/***********************************/
23083/* MC_CMD_NVRAM_PRIVATE_APPEND
23084 * Append a single TLV to the MC_USAGE_TLV partition. Returns MC_CMD_ERR_EEXIST
23085 * if the tag is already present.
23086 */
23087#define MC_CMD_NVRAM_PRIVATE_APPEND 0x11c
23088#undef MC_CMD_0x11c_PRIVILEGE_CTG
23089
23090#define MC_CMD_0x11c_PRIVILEGE_CTG SRIOV_CTG_ADMIN
23091
23092/* MC_CMD_NVRAM_PRIVATE_APPEND_IN msgrequest */
23093#define MC_CMD_NVRAM_PRIVATE_APPEND_IN_LENMIN 9
23094#define MC_CMD_NVRAM_PRIVATE_APPEND_IN_LENMAX 252
23095#define MC_CMD_NVRAM_PRIVATE_APPEND_IN_LENMAX_MCDI2 1020
23096#define MC_CMD_NVRAM_PRIVATE_APPEND_IN_LEN(num) (8+1*(num))
23097#define MC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_NUM(len) (((len)-8)/1)
23098/* The tag to be appended */
23099#define MC_CMD_NVRAM_PRIVATE_APPEND_IN_TAG_OFST 0
23100#define MC_CMD_NVRAM_PRIVATE_APPEND_IN_TAG_LEN 4
23101/* The length of the data */
23102#define MC_CMD_NVRAM_PRIVATE_APPEND_IN_LENGTH_OFST 4
23103#define MC_CMD_NVRAM_PRIVATE_APPEND_IN_LENGTH_LEN 4
23104/* The data to be contained in the TLV structure */
23105#define MC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_OFST 8
23106#define MC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_LEN 1
23107#define MC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_MINNUM 1
23108#define MC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_MAXNUM 244
23109#define MC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_MAXNUM_MCDI2 1012
23110
23111/* MC_CMD_NVRAM_PRIVATE_APPEND_OUT msgresponse */
23112#define MC_CMD_NVRAM_PRIVATE_APPEND_OUT_LEN 0
23113
23114
23115/***********************************/
23116/* MC_CMD_XPM_VERIFY_CONTENTS
23117 * Verify that the contents of the XPM memory is correct (Medford only). This
23118 * is used during manufacture to check that the XPM memory has been programmed
23119 * correctly at ATE.
23120 */
23121#define MC_CMD_XPM_VERIFY_CONTENTS 0x11b
23122#undef MC_CMD_0x11b_PRIVILEGE_CTG
23123
23124#define MC_CMD_0x11b_PRIVILEGE_CTG SRIOV_CTG_ADMIN
23125
23126/* MC_CMD_XPM_VERIFY_CONTENTS_IN msgrequest */
23127#define MC_CMD_XPM_VERIFY_CONTENTS_IN_LEN 4
23128/* Data type to be checked */
23129#define MC_CMD_XPM_VERIFY_CONTENTS_IN_DATA_TYPE_OFST 0
23130#define MC_CMD_XPM_VERIFY_CONTENTS_IN_DATA_TYPE_LEN 4
23131
23132/* MC_CMD_XPM_VERIFY_CONTENTS_OUT msgresponse */
23133#define MC_CMD_XPM_VERIFY_CONTENTS_OUT_LENMIN 12
23134#define MC_CMD_XPM_VERIFY_CONTENTS_OUT_LENMAX 252
23135#define MC_CMD_XPM_VERIFY_CONTENTS_OUT_LENMAX_MCDI2 1020
23136#define MC_CMD_XPM_VERIFY_CONTENTS_OUT_LEN(num) (12+1*(num))
23137#define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_NUM(len) (((len)-12)/1)
23138/* Number of sectors found (test builds only) */
23139#define MC_CMD_XPM_VERIFY_CONTENTS_OUT_NUM_SECTORS_OFST 0
23140#define MC_CMD_XPM_VERIFY_CONTENTS_OUT_NUM_SECTORS_LEN 4
23141/* Number of bytes found (test builds only) */
23142#define MC_CMD_XPM_VERIFY_CONTENTS_OUT_NUM_BYTES_OFST 4
23143#define MC_CMD_XPM_VERIFY_CONTENTS_OUT_NUM_BYTES_LEN 4
23144/* Length of signature */
23145#define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIG_LENGTH_OFST 8
23146#define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIG_LENGTH_LEN 4
23147/* Signature */
23148#define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_OFST 12
23149#define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_LEN 1
23150#define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_MINNUM 0
23151#define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_MAXNUM 240
23152#define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_MAXNUM_MCDI2 1008
23153
23154
23155/***********************************/
23156/* MC_CMD_SET_EVQ_TMR
23157 * Update the timer load, timer reload and timer mode values for a given EVQ.
23158 * The requested timer values (in TMR_LOAD_REQ_NS and TMR_RELOAD_REQ_NS) will
23159 * be rounded up to the granularity supported by the hardware, then truncated
23160 * to the range supported by the hardware. The resulting value after the
23161 * rounding and truncation will be returned to the caller (in TMR_LOAD_ACT_NS
23162 * and TMR_RELOAD_ACT_NS).
23163 */
23164#define MC_CMD_SET_EVQ_TMR 0x120
23165#undef MC_CMD_0x120_PRIVILEGE_CTG
23166
23167#define MC_CMD_0x120_PRIVILEGE_CTG SRIOV_CTG_GENERAL
23168
23169/* MC_CMD_SET_EVQ_TMR_IN msgrequest */
23170#define MC_CMD_SET_EVQ_TMR_IN_LEN 16
23171/* Function-relative queue instance */
23172#define MC_CMD_SET_EVQ_TMR_IN_INSTANCE_OFST 0
23173#define MC_CMD_SET_EVQ_TMR_IN_INSTANCE_LEN 4
23174/* Requested value for timer load (in nanoseconds) */
23175#define MC_CMD_SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS_OFST 4
23176#define MC_CMD_SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS_LEN 4
23177/* Requested value for timer reload (in nanoseconds) */
23178#define MC_CMD_SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS_OFST 8
23179#define MC_CMD_SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS_LEN 4
23180/* Timer mode. Meanings as per EVQ_TMR_REG.TC_TIMER_VAL */
23181#define MC_CMD_SET_EVQ_TMR_IN_TMR_MODE_OFST 12
23182#define MC_CMD_SET_EVQ_TMR_IN_TMR_MODE_LEN 4
23183#define MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_DIS 0x0 /* enum */
23184#define MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_IMMED_START 0x1 /* enum */
23185#define MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_TRIG_START 0x2 /* enum */
23186#define MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_INT_HLDOFF 0x3 /* enum */
23187
23188/* MC_CMD_SET_EVQ_TMR_OUT msgresponse */
23189#define MC_CMD_SET_EVQ_TMR_OUT_LEN 8
23190/* Actual value for timer load (in nanoseconds) */
23191#define MC_CMD_SET_EVQ_TMR_OUT_TMR_LOAD_ACT_NS_OFST 0
23192#define MC_CMD_SET_EVQ_TMR_OUT_TMR_LOAD_ACT_NS_LEN 4
23193/* Actual value for timer reload (in nanoseconds) */
23194#define MC_CMD_SET_EVQ_TMR_OUT_TMR_RELOAD_ACT_NS_OFST 4
23195#define MC_CMD_SET_EVQ_TMR_OUT_TMR_RELOAD_ACT_NS_LEN 4
23196
23197
23198/***********************************/
23199/* MC_CMD_GET_EVQ_TMR_PROPERTIES
23200 * Query properties about the event queue timers.
23201 */
23202#define MC_CMD_GET_EVQ_TMR_PROPERTIES 0x122
23203#undef MC_CMD_0x122_PRIVILEGE_CTG
23204
23205#define MC_CMD_0x122_PRIVILEGE_CTG SRIOV_CTG_GENERAL
23206
23207/* MC_CMD_GET_EVQ_TMR_PROPERTIES_IN msgrequest */
23208#define MC_CMD_GET_EVQ_TMR_PROPERTIES_IN_LEN 0
23209
23210/* MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT msgresponse */
23211#define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN 36
23212/* Reserved for future use. */
23213#define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_FLAGS_OFST 0
23214#define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_FLAGS_LEN 4
23215/* For timers updated via writes to EVQ_TMR_REG, this is the time interval (in
23216 * nanoseconds) for each increment of the timer load/reload count. The
23217 * requested duration of a timer is this value multiplied by the timer
23218 * load/reload count.
23219 */
23220#define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_NS_PER_COUNT_OFST 4
23221#define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_NS_PER_COUNT_LEN 4
23222/* For timers updated via writes to EVQ_TMR_REG, this is the maximum value
23223 * allowed for timer load/reload counts.
23224 */
23225#define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_MAX_COUNT_OFST 8
23226#define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_MAX_COUNT_LEN 4
23227/* For timers updated via writes to EVQ_TMR_REG, timer load/reload counts not a
23228 * multiple of this step size will be rounded in an implementation defined
23229 * manner.
23230 */
23231#define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_STEP_OFST 12
23232#define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_STEP_LEN 4
23233/* Maximum timer duration (in nanoseconds) for timers updated via MCDI. Only
23234 * meaningful if MC_CMD_SET_EVQ_TMR is implemented.
23235 */
23236#define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_MAX_NS_OFST 16
23237#define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_MAX_NS_LEN 4
23238/* Timer durations requested via MCDI that are not a multiple of this step size
23239 * will be rounded up. Only meaningful if MC_CMD_SET_EVQ_TMR is implemented.
23240 */
23241#define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_STEP_NS_OFST 20
23242#define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_STEP_NS_LEN 4
23243/* For timers updated using the bug35388 workaround, this is the time interval
23244 * (in nanoseconds) for each increment of the timer load/reload count. The
23245 * requested duration of a timer is this value multiplied by the timer
23246 * load/reload count. This field is only meaningful if the bug35388 workaround
23247 * is enabled.
23248 */
23249#define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_NS_PER_COUNT_OFST 24
23250#define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_NS_PER_COUNT_LEN 4
23251/* For timers updated using the bug35388 workaround, this is the maximum value
23252 * allowed for timer load/reload counts. This field is only meaningful if the
23253 * bug35388 workaround is enabled.
23254 */
23255#define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_MAX_COUNT_OFST 28
23256#define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_MAX_COUNT_LEN 4
23257/* For timers updated using the bug35388 workaround, timer load/reload counts
23258 * not a multiple of this step size will be rounded in an implementation
23259 * defined manner. This field is only meaningful if the bug35388 workaround is
23260 * enabled.
23261 */
23262#define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_STEP_OFST 32
23263#define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_STEP_LEN 4
23264
23265
23266/***********************************/
23267/* MC_CMD_ALLOCATE_TX_VFIFO_CP
23268 * When we use the TX_vFIFO_ULL mode, we can allocate common pools using the
23269 * non used switch buffers.
23270 */
23271#define MC_CMD_ALLOCATE_TX_VFIFO_CP 0x11d
23272#undef MC_CMD_0x11d_PRIVILEGE_CTG
23273
23274#define MC_CMD_0x11d_PRIVILEGE_CTG SRIOV_CTG_GENERAL
23275
23276/* MC_CMD_ALLOCATE_TX_VFIFO_CP_IN msgrequest */
23277#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_LEN 20
23278/* Desired instance. Must be set to a specific instance, which is a function
23279 * local queue index. The calling client must be the currently-assigned user of
23280 * this VI (see MC_CMD_SET_VI_USER).
23281 */
23282#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_INSTANCE_OFST 0
23283#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_INSTANCE_LEN 4
23284/* Will the common pool be used as TX_vFIFO_ULL (1) */
23285#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_MODE_OFST 4
23286#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_MODE_LEN 4
23287#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_ENABLED 0x1 /* enum */
23288/* enum: Using this interface without TX_vFIFO_ULL is not supported for now */
23289#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_DISABLED 0x0
23290/* Number of buffers to reserve for the common pool */
23291#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_SIZE_OFST 8
23292#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_SIZE_LEN 4
23293/* TX datapath to which the Common Pool is connected to. */
23294#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_INGRESS_OFST 12
23295#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_INGRESS_LEN 4
23296/* enum: Extracts information from function */
23297#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_USE_FUNCTION_VALUE -0x1
23298/* Network port or RX Engine to which the common pool connects. */
23299#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_EGRESS_OFST 16
23300#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_EGRESS_LEN 4
23301/* enum: Extracts information from function */
23302/* MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_USE_FUNCTION_VALUE -0x1 */
23303#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT0 0x0 /* enum */
23304#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT1 0x1 /* enum */
23305#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT2 0x2 /* enum */
23306#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT3 0x3 /* enum */
23307/* enum: To enable Switch loopback with Rx engine 0 */
23308#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_RX_ENGINE0 0x4
23309/* enum: To enable Switch loopback with Rx engine 1 */
23310#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_RX_ENGINE1 0x5
23311
23312/* MC_CMD_ALLOCATE_TX_VFIFO_CP_OUT msgresponse */
23313#define MC_CMD_ALLOCATE_TX_VFIFO_CP_OUT_LEN 4
23314/* ID of the common pool allocated */
23315#define MC_CMD_ALLOCATE_TX_VFIFO_CP_OUT_CP_ID_OFST 0
23316#define MC_CMD_ALLOCATE_TX_VFIFO_CP_OUT_CP_ID_LEN 4
23317
23318
23319/***********************************/
23320/* MC_CMD_ALLOCATE_TX_VFIFO_VFIFO
23321 * When we use the TX_vFIFO_ULL mode, we can allocate vFIFOs using the
23322 * previously allocated common pools.
23323 */
23324#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO 0x11e
23325#undef MC_CMD_0x11e_PRIVILEGE_CTG
23326
23327#define MC_CMD_0x11e_PRIVILEGE_CTG SRIOV_CTG_GENERAL
23328
23329/* MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN msgrequest */
23330#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_LEN 20
23331/* Common pool previously allocated to which the new vFIFO will be associated
23332 */
23333#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_CP_OFST 0
23334#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_CP_LEN 4
23335/* Port or RX engine to associate the vFIFO egress */
23336#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_EGRESS_OFST 4
23337#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_EGRESS_LEN 4
23338/* enum: Extracts information from common pool */
23339#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_USE_CP_VALUE -0x1
23340#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT0 0x0 /* enum */
23341#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT1 0x1 /* enum */
23342#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT2 0x2 /* enum */
23343#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT3 0x3 /* enum */
23344/* enum: To enable Switch loopback with Rx engine 0 */
23345#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_RX_ENGINE0 0x4
23346/* enum: To enable Switch loopback with Rx engine 1 */
23347#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_RX_ENGINE1 0x5
23348/* Minimum number of buffers that the pool must have */
23349#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_SIZE_OFST 8
23350#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_SIZE_LEN 4
23351/* enum: Do not check the space available */
23352#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_NO_MINIMUM 0x0
23353/* Will the vFIFO be used as TX_vFIFO_ULL */
23354#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_MODE_OFST 12
23355#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_MODE_LEN 4
23356/* Network priority of the vFIFO,if applicable */
23357#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PRIORITY_OFST 16
23358#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PRIORITY_LEN 4
23359/* enum: Search for the lowest unused priority */
23360#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_LOWEST_AVAILABLE -0x1
23361
23362/* MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT msgresponse */
23363#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_LEN 8
23364/* Short vFIFO ID */
23365#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_VID_OFST 0
23366#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_VID_LEN 4
23367/* Network priority of the vFIFO */
23368#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_PRIORITY_OFST 4
23369#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_PRIORITY_LEN 4
23370
23371
23372/***********************************/
23373/* MC_CMD_TEARDOWN_TX_VFIFO_VF
23374 * This interface clears the configuration of the given vFIFO and leaves it
23375 * ready to be re-used.
23376 */
23377#define MC_CMD_TEARDOWN_TX_VFIFO_VF 0x11f
23378#undef MC_CMD_0x11f_PRIVILEGE_CTG
23379
23380#define MC_CMD_0x11f_PRIVILEGE_CTG SRIOV_CTG_GENERAL
23381
23382/* MC_CMD_TEARDOWN_TX_VFIFO_VF_IN msgrequest */
23383#define MC_CMD_TEARDOWN_TX_VFIFO_VF_IN_LEN 4
23384/* Short vFIFO ID */
23385#define MC_CMD_TEARDOWN_TX_VFIFO_VF_IN_VFIFO_OFST 0
23386#define MC_CMD_TEARDOWN_TX_VFIFO_VF_IN_VFIFO_LEN 4
23387
23388/* MC_CMD_TEARDOWN_TX_VFIFO_VF_OUT msgresponse */
23389#define MC_CMD_TEARDOWN_TX_VFIFO_VF_OUT_LEN 0
23390
23391
23392/***********************************/
23393/* MC_CMD_DEALLOCATE_TX_VFIFO_CP
23394 * This interface clears the configuration of the given common pool and leaves
23395 * it ready to be re-used.
23396 */
23397#define MC_CMD_DEALLOCATE_TX_VFIFO_CP 0x121
23398#undef MC_CMD_0x121_PRIVILEGE_CTG
23399
23400#define MC_CMD_0x121_PRIVILEGE_CTG SRIOV_CTG_GENERAL
23401
23402/* MC_CMD_DEALLOCATE_TX_VFIFO_CP_IN msgrequest */
23403#define MC_CMD_DEALLOCATE_TX_VFIFO_CP_IN_LEN 4
23404/* Common pool ID given when pool allocated */
23405#define MC_CMD_DEALLOCATE_TX_VFIFO_CP_IN_POOL_ID_OFST 0
23406#define MC_CMD_DEALLOCATE_TX_VFIFO_CP_IN_POOL_ID_LEN 4
23407
23408/* MC_CMD_DEALLOCATE_TX_VFIFO_CP_OUT msgresponse */
23409#define MC_CMD_DEALLOCATE_TX_VFIFO_CP_OUT_LEN 0
23410
23411
23412/***********************************/
23413/* MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS
23414 * This interface allows the host to find out how many common pool buffers are
23415 * not yet assigned.
23416 */
23417#define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS 0x124
23418#undef MC_CMD_0x124_PRIVILEGE_CTG
23419
23420#define MC_CMD_0x124_PRIVILEGE_CTG SRIOV_CTG_GENERAL
23421
23422/* MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_IN msgrequest */
23423#define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_IN_LEN 0
23424
23425/* MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT msgresponse */
23426#define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_LEN 8
23427/* Available buffers for the ENG to NET vFIFOs. */
23428#define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_NET_OFST 0
23429#define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_NET_LEN 4
23430/* Available buffers for the ENG to ENG and NET to ENG vFIFOs. */
23431#define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_ENG_OFST 4
23432#define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_ENG_LEN 4
23433
23434
23435/***********************************/
23436/* MC_CMD_SUC_VERSION
23437 * Get the version of the SUC
23438 */
23439#define MC_CMD_SUC_VERSION 0x134
23440#undef MC_CMD_0x134_PRIVILEGE_CTG
23441
23442#define MC_CMD_0x134_PRIVILEGE_CTG SRIOV_CTG_GENERAL
23443
23444/* MC_CMD_SUC_VERSION_IN msgrequest */
23445#define MC_CMD_SUC_VERSION_IN_LEN 0
23446
23447/* MC_CMD_SUC_VERSION_OUT msgresponse */
23448#define MC_CMD_SUC_VERSION_OUT_LEN 24
23449/* The SUC firmware version as four numbers - a.b.c.d */
23450#define MC_CMD_SUC_VERSION_OUT_VERSION_OFST 0
23451#define MC_CMD_SUC_VERSION_OUT_VERSION_LEN 4
23452#define MC_CMD_SUC_VERSION_OUT_VERSION_NUM 4
23453/* The date, in seconds since the Unix epoch, when the firmware image was
23454 * built.
23455 */
23456#define MC_CMD_SUC_VERSION_OUT_BUILD_DATE_OFST 16
23457#define MC_CMD_SUC_VERSION_OUT_BUILD_DATE_LEN 4
23458/* The ID of the SUC chip. This is specific to the platform but typically
23459 * indicates family, memory sizes etc. See SF-116728-SW for further details.
23460 */
23461#define MC_CMD_SUC_VERSION_OUT_CHIP_ID_OFST 20
23462#define MC_CMD_SUC_VERSION_OUT_CHIP_ID_LEN 4
23463
23464/* MC_CMD_SUC_BOOT_VERSION_IN msgrequest: Get the version of the SUC boot
23465 * loader.
23466 */
23467#define MC_CMD_SUC_BOOT_VERSION_IN_LEN 4
23468#define MC_CMD_SUC_BOOT_VERSION_IN_MAGIC_OFST 0
23469#define MC_CMD_SUC_BOOT_VERSION_IN_MAGIC_LEN 4
23470/* enum: Requests the SUC boot version. */
23471#define MC_CMD_SUC_VERSION_GET_BOOT_VERSION 0xb007700b
23472
23473/* MC_CMD_SUC_BOOT_VERSION_OUT msgresponse */
23474#define MC_CMD_SUC_BOOT_VERSION_OUT_LEN 4
23475/* The SUC boot version */
23476#define MC_CMD_SUC_BOOT_VERSION_OUT_VERSION_OFST 0
23477#define MC_CMD_SUC_BOOT_VERSION_OUT_VERSION_LEN 4
23478
23479
23480/***********************************/
23481/* MC_CMD_GET_RX_PREFIX_ID
23482 * This command is part of the mechanism for configuring the format of the RX
23483 * packet prefix. It takes as input a bitmask of the fields the host would like
23484 * to be in the prefix. If the hardware supports RX prefixes with that
23485 * combination of fields, then this command returns a list of prefix-ids,
23486 * opaque identifiers suitable for use in the RX_PREFIX_ID field of a
23487 * MC_CMD_INIT_RXQ_V5_IN message. If the combination of fields is not
23488 * supported, returns ENOTSUP. If the firmware can't create any new prefix-ids
23489 * due to resource constraints, returns ENOSPC.
23490 */
23491#define MC_CMD_GET_RX_PREFIX_ID 0x13b
23492#undef MC_CMD_0x13b_PRIVILEGE_CTG
23493
23494#define MC_CMD_0x13b_PRIVILEGE_CTG SRIOV_CTG_GENERAL
23495
23496/* MC_CMD_GET_RX_PREFIX_ID_IN msgrequest */
23497#define MC_CMD_GET_RX_PREFIX_ID_IN_LEN 8
23498/* Field bitmask. */
23499#define MC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_OFST 0
23500#define MC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_LEN 8
23501#define MC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_LO_OFST 0
23502#define MC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_LO_LEN 4
23503#define MC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_LO_LBN 0
23504#define MC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_LO_WIDTH 32
23505#define MC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_HI_OFST 4
23506#define MC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_HI_LEN 4
23507#define MC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_HI_LBN 32
23508#define MC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_HI_WIDTH 32
23509#define MC_CMD_GET_RX_PREFIX_ID_IN_LENGTH_OFST 0
23510#define MC_CMD_GET_RX_PREFIX_ID_IN_LENGTH_LBN 0
23511#define MC_CMD_GET_RX_PREFIX_ID_IN_LENGTH_WIDTH 1
23512#define MC_CMD_GET_RX_PREFIX_ID_IN_RSS_HASH_VALID_OFST 0
23513#define MC_CMD_GET_RX_PREFIX_ID_IN_RSS_HASH_VALID_LBN 1
23514#define MC_CMD_GET_RX_PREFIX_ID_IN_RSS_HASH_VALID_WIDTH 1
23515#define MC_CMD_GET_RX_PREFIX_ID_IN_USER_FLAG_OFST 0
23516#define MC_CMD_GET_RX_PREFIX_ID_IN_USER_FLAG_LBN 2
23517#define MC_CMD_GET_RX_PREFIX_ID_IN_USER_FLAG_WIDTH 1
23518#define MC_CMD_GET_RX_PREFIX_ID_IN_CLASS_OFST 0
23519#define MC_CMD_GET_RX_PREFIX_ID_IN_CLASS_LBN 3
23520#define MC_CMD_GET_RX_PREFIX_ID_IN_CLASS_WIDTH 1
23521#define MC_CMD_GET_RX_PREFIX_ID_IN_PARTIAL_TSTAMP_OFST 0
23522#define MC_CMD_GET_RX_PREFIX_ID_IN_PARTIAL_TSTAMP_LBN 4
23523#define MC_CMD_GET_RX_PREFIX_ID_IN_PARTIAL_TSTAMP_WIDTH 1
23524#define MC_CMD_GET_RX_PREFIX_ID_IN_RSS_HASH_OFST 0
23525#define MC_CMD_GET_RX_PREFIX_ID_IN_RSS_HASH_LBN 5
23526#define MC_CMD_GET_RX_PREFIX_ID_IN_RSS_HASH_WIDTH 1
23527#define MC_CMD_GET_RX_PREFIX_ID_IN_USER_MARK_OFST 0
23528#define MC_CMD_GET_RX_PREFIX_ID_IN_USER_MARK_LBN 6
23529#define MC_CMD_GET_RX_PREFIX_ID_IN_USER_MARK_WIDTH 1
23530#define MC_CMD_GET_RX_PREFIX_ID_IN_INGRESS_MPORT_OFST 0
23531#define MC_CMD_GET_RX_PREFIX_ID_IN_INGRESS_MPORT_LBN 7
23532#define MC_CMD_GET_RX_PREFIX_ID_IN_INGRESS_MPORT_WIDTH 1
23533#define MC_CMD_GET_RX_PREFIX_ID_IN_INGRESS_VPORT_OFST 0
23534#define MC_CMD_GET_RX_PREFIX_ID_IN_INGRESS_VPORT_LBN 7
23535#define MC_CMD_GET_RX_PREFIX_ID_IN_INGRESS_VPORT_WIDTH 1
23536#define MC_CMD_GET_RX_PREFIX_ID_IN_CSUM_FRAME_OFST 0
23537#define MC_CMD_GET_RX_PREFIX_ID_IN_CSUM_FRAME_LBN 8
23538#define MC_CMD_GET_RX_PREFIX_ID_IN_CSUM_FRAME_WIDTH 1
23539#define MC_CMD_GET_RX_PREFIX_ID_IN_VLAN_STRIP_TCI_OFST 0
23540#define MC_CMD_GET_RX_PREFIX_ID_IN_VLAN_STRIP_TCI_LBN 9
23541#define MC_CMD_GET_RX_PREFIX_ID_IN_VLAN_STRIP_TCI_WIDTH 1
23542#define MC_CMD_GET_RX_PREFIX_ID_IN_VLAN_STRIPPED_OFST 0
23543#define MC_CMD_GET_RX_PREFIX_ID_IN_VLAN_STRIPPED_LBN 10
23544#define MC_CMD_GET_RX_PREFIX_ID_IN_VLAN_STRIPPED_WIDTH 1
23545#define MC_CMD_GET_RX_PREFIX_ID_IN_VSWITCH_STATUS_OFST 0
23546#define MC_CMD_GET_RX_PREFIX_ID_IN_VSWITCH_STATUS_LBN 11
23547#define MC_CMD_GET_RX_PREFIX_ID_IN_VSWITCH_STATUS_WIDTH 1
23548
23549/* MC_CMD_GET_RX_PREFIX_ID_OUT msgresponse */
23550#define MC_CMD_GET_RX_PREFIX_ID_OUT_LENMIN 8
23551#define MC_CMD_GET_RX_PREFIX_ID_OUT_LENMAX 252
23552#define MC_CMD_GET_RX_PREFIX_ID_OUT_LENMAX_MCDI2 1020
23553#define MC_CMD_GET_RX_PREFIX_ID_OUT_LEN(num) (4+4*(num))
23554#define MC_CMD_GET_RX_PREFIX_ID_OUT_RX_PREFIX_ID_NUM(len) (((len)-4)/4)
23555/* Number of prefix-ids returned */
23556#define MC_CMD_GET_RX_PREFIX_ID_OUT_NUM_RX_PREFIX_IDS_OFST 0
23557#define MC_CMD_GET_RX_PREFIX_ID_OUT_NUM_RX_PREFIX_IDS_LEN 4
23558/* Opaque prefix identifiers which can be passed into MC_CMD_INIT_RXQ_V5 or
23559 * MC_CMD_QUERY_PREFIX_ID
23560 */
23561#define MC_CMD_GET_RX_PREFIX_ID_OUT_RX_PREFIX_ID_OFST 4
23562#define MC_CMD_GET_RX_PREFIX_ID_OUT_RX_PREFIX_ID_LEN 4
23563#define MC_CMD_GET_RX_PREFIX_ID_OUT_RX_PREFIX_ID_MINNUM 1
23564#define MC_CMD_GET_RX_PREFIX_ID_OUT_RX_PREFIX_ID_MAXNUM 62
23565#define MC_CMD_GET_RX_PREFIX_ID_OUT_RX_PREFIX_ID_MAXNUM_MCDI2 254
23566
23567/* RX_PREFIX_FIELD_INFO structuredef: Information about a single RX prefix
23568 * field
23569 */
23570#define RX_PREFIX_FIELD_INFO_LEN 4
23571/* The offset of the field from the start of the prefix, in bits */
23572#define RX_PREFIX_FIELD_INFO_OFFSET_BITS_OFST 0
23573#define RX_PREFIX_FIELD_INFO_OFFSET_BITS_LEN 2
23574#define RX_PREFIX_FIELD_INFO_OFFSET_BITS_LBN 0
23575#define RX_PREFIX_FIELD_INFO_OFFSET_BITS_WIDTH 16
23576/* The width of the field, in bits */
23577#define RX_PREFIX_FIELD_INFO_WIDTH_BITS_OFST 2
23578#define RX_PREFIX_FIELD_INFO_WIDTH_BITS_LEN 1
23579#define RX_PREFIX_FIELD_INFO_WIDTH_BITS_LBN 16
23580#define RX_PREFIX_FIELD_INFO_WIDTH_BITS_WIDTH 8
23581/* The type of the field. These enum values are in the same order as the fields
23582 * in the MC_CMD_GET_RX_PREFIX_ID_IN bitmask
23583 */
23584#define RX_PREFIX_FIELD_INFO_TYPE_OFST 3
23585#define RX_PREFIX_FIELD_INFO_TYPE_LEN 1
23586#define RX_PREFIX_FIELD_INFO_LENGTH 0x0 /* enum */
23587#define RX_PREFIX_FIELD_INFO_RSS_HASH_VALID 0x1 /* enum */
23588#define RX_PREFIX_FIELD_INFO_USER_FLAG 0x2 /* enum */
23589#define RX_PREFIX_FIELD_INFO_CLASS 0x3 /* enum */
23590#define RX_PREFIX_FIELD_INFO_PARTIAL_TSTAMP 0x4 /* enum */
23591#define RX_PREFIX_FIELD_INFO_RSS_HASH 0x5 /* enum */
23592#define RX_PREFIX_FIELD_INFO_USER_MARK 0x6 /* enum */
23593#define RX_PREFIX_FIELD_INFO_INGRESS_MPORT 0x7 /* enum */
23594#define RX_PREFIX_FIELD_INFO_INGRESS_VPORT 0x7 /* enum */
23595#define RX_PREFIX_FIELD_INFO_CSUM_FRAME 0x8 /* enum */
23596#define RX_PREFIX_FIELD_INFO_VLAN_STRIP_TCI 0x9 /* enum */
23597#define RX_PREFIX_FIELD_INFO_VLAN_STRIPPED 0xa /* enum */
23598#define RX_PREFIX_FIELD_INFO_VSWITCH_STATUS 0xb /* enum */
23599#define RX_PREFIX_FIELD_INFO_TYPE_LBN 24
23600#define RX_PREFIX_FIELD_INFO_TYPE_WIDTH 8
23601
23602/* RX_PREFIX_FIXED_RESPONSE structuredef: Information about an RX prefix in
23603 * which every field has a fixed offset and width
23604 */
23605#define RX_PREFIX_FIXED_RESPONSE_LENMIN 4
23606#define RX_PREFIX_FIXED_RESPONSE_LENMAX 252
23607#define RX_PREFIX_FIXED_RESPONSE_LENMAX_MCDI2 1020
23608#define RX_PREFIX_FIXED_RESPONSE_LEN(num) (4+4*(num))
23609#define RX_PREFIX_FIXED_RESPONSE_FIELDS_NUM(len) (((len)-4)/4)
23610/* Length of the RX prefix in bytes */
23611#define RX_PREFIX_FIXED_RESPONSE_PREFIX_LENGTH_BYTES_OFST 0
23612#define RX_PREFIX_FIXED_RESPONSE_PREFIX_LENGTH_BYTES_LEN 1
23613#define RX_PREFIX_FIXED_RESPONSE_PREFIX_LENGTH_BYTES_LBN 0
23614#define RX_PREFIX_FIXED_RESPONSE_PREFIX_LENGTH_BYTES_WIDTH 8
23615/* Number of fields present in the prefix */
23616#define RX_PREFIX_FIXED_RESPONSE_FIELD_COUNT_OFST 1
23617#define RX_PREFIX_FIXED_RESPONSE_FIELD_COUNT_LEN 1
23618#define RX_PREFIX_FIXED_RESPONSE_FIELD_COUNT_LBN 8
23619#define RX_PREFIX_FIXED_RESPONSE_FIELD_COUNT_WIDTH 8
23620#define RX_PREFIX_FIXED_RESPONSE_RESERVED_OFST 2
23621#define RX_PREFIX_FIXED_RESPONSE_RESERVED_LEN 2
23622#define RX_PREFIX_FIXED_RESPONSE_RESERVED_LBN 16
23623#define RX_PREFIX_FIXED_RESPONSE_RESERVED_WIDTH 16
23624/* Array of RX_PREFIX_FIELD_INFO structures, of length FIELD_COUNT */
23625#define RX_PREFIX_FIXED_RESPONSE_FIELDS_OFST 4
23626#define RX_PREFIX_FIXED_RESPONSE_FIELDS_LEN 4
23627#define RX_PREFIX_FIXED_RESPONSE_FIELDS_MINNUM 0
23628#define RX_PREFIX_FIXED_RESPONSE_FIELDS_MAXNUM 62
23629#define RX_PREFIX_FIXED_RESPONSE_FIELDS_MAXNUM_MCDI2 254
23630#define RX_PREFIX_FIXED_RESPONSE_FIELDS_LBN 32
23631#define RX_PREFIX_FIXED_RESPONSE_FIELDS_WIDTH 32
23632
23633
23634/***********************************/
23635/* MC_CMD_QUERY_RX_PREFIX_ID
23636 * This command takes an RX prefix id (obtained from MC_CMD_GET_RX_PREFIX_ID)
23637 * and returns a description of the RX prefix of packets delievered to an RXQ
23638 * created with that prefix id
23639 */
23640#define MC_CMD_QUERY_RX_PREFIX_ID 0x13c
23641#undef MC_CMD_0x13c_PRIVILEGE_CTG
23642
23643#define MC_CMD_0x13c_PRIVILEGE_CTG SRIOV_CTG_GENERAL
23644
23645/* MC_CMD_QUERY_RX_PREFIX_ID_IN msgrequest */
23646#define MC_CMD_QUERY_RX_PREFIX_ID_IN_LEN 4
23647/* Prefix id to query */
23648#define MC_CMD_QUERY_RX_PREFIX_ID_IN_RX_PREFIX_ID_OFST 0
23649#define MC_CMD_QUERY_RX_PREFIX_ID_IN_RX_PREFIX_ID_LEN 4
23650
23651/* MC_CMD_QUERY_RX_PREFIX_ID_OUT msgresponse */
23652#define MC_CMD_QUERY_RX_PREFIX_ID_OUT_LENMIN 4
23653#define MC_CMD_QUERY_RX_PREFIX_ID_OUT_LENMAX 252
23654#define MC_CMD_QUERY_RX_PREFIX_ID_OUT_LENMAX_MCDI2 1020
23655#define MC_CMD_QUERY_RX_PREFIX_ID_OUT_LEN(num) (4+1*(num))
23656#define MC_CMD_QUERY_RX_PREFIX_ID_OUT_RESPONSE_NUM(len) (((len)-4)/1)
23657/* An enum describing the structure of this response. */
23658#define MC_CMD_QUERY_RX_PREFIX_ID_OUT_RESPONSE_TYPE_OFST 0
23659#define MC_CMD_QUERY_RX_PREFIX_ID_OUT_RESPONSE_TYPE_LEN 1
23660/* enum: The response is of format RX_PREFIX_FIXED_RESPONSE */
23661#define MC_CMD_QUERY_RX_PREFIX_ID_OUT_RESPONSE_TYPE_FIXED 0x0
23662#define MC_CMD_QUERY_RX_PREFIX_ID_OUT_RESERVED_OFST 1
23663#define MC_CMD_QUERY_RX_PREFIX_ID_OUT_RESERVED_LEN 3
23664/* The response. Its format is as defined by the RESPONSE_TYPE value */
23665#define MC_CMD_QUERY_RX_PREFIX_ID_OUT_RESPONSE_OFST 4
23666#define MC_CMD_QUERY_RX_PREFIX_ID_OUT_RESPONSE_LEN 1
23667#define MC_CMD_QUERY_RX_PREFIX_ID_OUT_RESPONSE_MINNUM 0
23668#define MC_CMD_QUERY_RX_PREFIX_ID_OUT_RESPONSE_MAXNUM 248
23669#define MC_CMD_QUERY_RX_PREFIX_ID_OUT_RESPONSE_MAXNUM_MCDI2 1016
23670
23671
23672/***********************************/
23673/* MC_CMD_BUNDLE
23674 * A command to perform various bundle-related operations on insecure cards.
23675 */
23676#define MC_CMD_BUNDLE 0x13d
23677#undef MC_CMD_0x13d_PRIVILEGE_CTG
23678
23679#define MC_CMD_0x13d_PRIVILEGE_CTG SRIOV_CTG_INSECURE
23680
23681/* MC_CMD_BUNDLE_IN msgrequest */
23682#define MC_CMD_BUNDLE_IN_LEN 4
23683/* Sub-command code */
23684#define MC_CMD_BUNDLE_IN_OP_OFST 0
23685#define MC_CMD_BUNDLE_IN_OP_LEN 4
23686/* enum: Get the current host access mode set on component partitions. */
23687#define MC_CMD_BUNDLE_IN_OP_COMPONENT_ACCESS_GET 0x0
23688/* enum: Set the host access mode set on component partitions. */
23689#define MC_CMD_BUNDLE_IN_OP_COMPONENT_ACCESS_SET 0x1
23690
23691/* MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_GET_IN msgrequest: Retrieve the current
23692 * access mode on component partitions such as MC_FIRMWARE, SUC_FIRMWARE and
23693 * EXPANSION_UEFI. This command only works on engineering (insecure) cards. On
23694 * secure adapters, this command returns MC_CMD_ERR_EPERM.
23695 */
23696#define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_GET_IN_LEN 4
23697/* Sub-command code. Must be OP_COMPONENT_ACCESS_GET. */
23698#define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_GET_IN_OP_OFST 0
23699#define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_GET_IN_OP_LEN 4
23700
23701/* MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_GET_OUT msgresponse: Returns the access
23702 * control mode.
23703 */
23704#define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_GET_OUT_LEN 4
23705/* Access mode of component partitions. */
23706#define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_GET_OUT_ACCESS_MODE_OFST 0
23707#define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_GET_OUT_ACCESS_MODE_LEN 4
23708/* enum: Component partitions are read-only from the host. */
23709#define MC_CMD_BUNDLE_COMPONENTS_READ_ONLY 0x0
23710/* enum: Component partitions can read read-from written-to by the host. */
23711#define MC_CMD_BUNDLE_COMPONENTS_READ_WRITE 0x1
23712
23713/* MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_SET_IN msgrequest: The component
23714 * partitions such as MC_FIRMWARE, SUC_FIRMWARE, EXPANSION_UEFI are set as
23715 * read-only on firmware built with bundle support. This command marks these
23716 * partitions as read/writeable. The access status set by this command does not
23717 * persist across MC reboots. This command only works on engineering (insecure)
23718 * cards. On secure adapters, this command returns MC_CMD_ERR_EPERM.
23719 */
23720#define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_SET_IN_LEN 8
23721/* Sub-command code. Must be OP_COMPONENT_ACCESS_SET. */
23722#define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_SET_IN_OP_OFST 0
23723#define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_SET_IN_OP_LEN 4
23724/* Access mode of component partitions. */
23725#define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_SET_IN_ACCESS_MODE_OFST 4
23726#define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_SET_IN_ACCESS_MODE_LEN 4
23727/* Enum values, see field(s): */
23728/* MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_GET_OUT/ACCESS_MODE */
23729
23730/* MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_SET_OUT msgresponse */
23731#define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_SET_OUT_LEN 0
23732
23733
23734/***********************************/
23735/* MC_CMD_GET_VPD
23736 * Read all VPD starting from a given address
23737 */
23738#define MC_CMD_GET_VPD 0x165
23739#undef MC_CMD_0x165_PRIVILEGE_CTG
23740
23741#define MC_CMD_0x165_PRIVILEGE_CTG SRIOV_CTG_GENERAL
23742
23743/* MC_CMD_GET_VPD_IN msgresponse */
23744#define MC_CMD_GET_VPD_IN_LEN 4
23745/* VPD address to start from. In case VPD is longer than MCDI buffer
23746 * (unlikely), user can make multiple calls with different starting addresses.
23747 */
23748#define MC_CMD_GET_VPD_IN_ADDR_OFST 0
23749#define MC_CMD_GET_VPD_IN_ADDR_LEN 4
23750
23751/* MC_CMD_GET_VPD_OUT msgresponse */
23752#define MC_CMD_GET_VPD_OUT_LENMIN 0
23753#define MC_CMD_GET_VPD_OUT_LENMAX 252
23754#define MC_CMD_GET_VPD_OUT_LENMAX_MCDI2 1020
23755#define MC_CMD_GET_VPD_OUT_LEN(num) (0+1*(num))
23756#define MC_CMD_GET_VPD_OUT_DATA_NUM(len) (((len)-0)/1)
23757/* VPD data returned. */
23758#define MC_CMD_GET_VPD_OUT_DATA_OFST 0
23759#define MC_CMD_GET_VPD_OUT_DATA_LEN 1
23760#define MC_CMD_GET_VPD_OUT_DATA_MINNUM 0
23761#define MC_CMD_GET_VPD_OUT_DATA_MAXNUM 252
23762#define MC_CMD_GET_VPD_OUT_DATA_MAXNUM_MCDI2 1020
23763
23764
23765/***********************************/
23766/* MC_CMD_GET_NCSI_INFO
23767 * Provide information about the NC-SI stack
23768 */
23769#define MC_CMD_GET_NCSI_INFO 0x167
23770#undef MC_CMD_0x167_PRIVILEGE_CTG
23771
23772#define MC_CMD_0x167_PRIVILEGE_CTG SRIOV_CTG_GENERAL
23773
23774/* MC_CMD_GET_NCSI_INFO_IN msgrequest */
23775#define MC_CMD_GET_NCSI_INFO_IN_LEN 8
23776/* Operation to be performed */
23777#define MC_CMD_GET_NCSI_INFO_IN_OP_OFST 0
23778#define MC_CMD_GET_NCSI_INFO_IN_OP_LEN 4
23779/* enum: Information on the link settings. */
23780#define MC_CMD_GET_NCSI_INFO_IN_OP_LINK 0x0
23781/* enum: Statistics associated with the channel */
23782#define MC_CMD_GET_NCSI_INFO_IN_OP_STATISTICS 0x1
23783/* The NC-SI channel on which the operation is to be performed */
23784#define MC_CMD_GET_NCSI_INFO_IN_CHANNEL_OFST 4
23785#define MC_CMD_GET_NCSI_INFO_IN_CHANNEL_LEN 4
23786
23787/* MC_CMD_GET_NCSI_INFO_LINK_OUT msgresponse */
23788#define MC_CMD_GET_NCSI_INFO_LINK_OUT_LEN 12
23789/* Settings as received from BMC. */
23790#define MC_CMD_GET_NCSI_INFO_LINK_OUT_SETTINGS_OFST 0
23791#define MC_CMD_GET_NCSI_INFO_LINK_OUT_SETTINGS_LEN 4
23792/* Advertised capabilities applied to channel. */
23793#define MC_CMD_GET_NCSI_INFO_LINK_OUT_ADV_CAP_OFST 4
23794#define MC_CMD_GET_NCSI_INFO_LINK_OUT_ADV_CAP_LEN 4
23795/* General status */
23796#define MC_CMD_GET_NCSI_INFO_LINK_OUT_STATUS_OFST 8
23797#define MC_CMD_GET_NCSI_INFO_LINK_OUT_STATUS_LEN 4
23798#define MC_CMD_GET_NCSI_INFO_LINK_OUT_STATE_OFST 8
23799#define MC_CMD_GET_NCSI_INFO_LINK_OUT_STATE_LBN 0
23800#define MC_CMD_GET_NCSI_INFO_LINK_OUT_STATE_WIDTH 2
23801#define MC_CMD_GET_NCSI_INFO_LINK_OUT_ENABLE_OFST 8
23802#define MC_CMD_GET_NCSI_INFO_LINK_OUT_ENABLE_LBN 2
23803#define MC_CMD_GET_NCSI_INFO_LINK_OUT_ENABLE_WIDTH 1
23804#define MC_CMD_GET_NCSI_INFO_LINK_OUT_NETWORK_TX_OFST 8
23805#define MC_CMD_GET_NCSI_INFO_LINK_OUT_NETWORK_TX_LBN 3
23806#define MC_CMD_GET_NCSI_INFO_LINK_OUT_NETWORK_TX_WIDTH 1
23807#define MC_CMD_GET_NCSI_INFO_LINK_OUT_ATTACHED_OFST 8
23808#define MC_CMD_GET_NCSI_INFO_LINK_OUT_ATTACHED_LBN 4
23809#define MC_CMD_GET_NCSI_INFO_LINK_OUT_ATTACHED_WIDTH 1
23810
23811/* MC_CMD_GET_NCSI_INFO_STATISTICS_OUT msgresponse */
23812#define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_LEN 28
23813/* The number of NC-SI commands received. */
23814#define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_CMDS_RX_OFST 0
23815#define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_CMDS_RX_LEN 4
23816/* The number of NC-SI commands dropped. */
23817#define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_PKTS_DROPPED_OFST 4
23818#define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_PKTS_DROPPED_LEN 4
23819/* The number of invalid NC-SI commands received. */
23820#define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_CMD_TYPE_ERRS_OFST 8
23821#define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_CMD_TYPE_ERRS_LEN 4
23822/* The number of checksum errors seen. */
23823#define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_CMD_CSUM_ERRS_OFST 12
23824#define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_CMD_CSUM_ERRS_LEN 4
23825/* The number of NC-SI requests received. */
23826#define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_RX_PKTS_OFST 16
23827#define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_RX_PKTS_LEN 4
23828/* The number of NC-SI responses sent (includes AENs) */
23829#define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_TX_PKTS_OFST 20
23830#define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_TX_PKTS_LEN 4
23831/* The number of NC-SI AENs sent */
23832#define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_AENS_SENT_OFST 24
23833#define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_AENS_SENT_LEN 4
23834
23835/* CLIENT_HANDLE structuredef: A client is an abstract entity that can make
23836 * requests of the device and that can own resources managed by the device.
23837 * Examples of clients include PCIe functions and dynamic clients. A client
23838 * handle is a 32b opaque value used to refer to a client. Further details can
23839 * be found within XN-200418-TC.
23840 */
23841#define CLIENT_HANDLE_LEN 4
23842#define CLIENT_HANDLE_OPAQUE_OFST 0
23843#define CLIENT_HANDLE_OPAQUE_LEN 4
23844/* enum: A client handle guaranteed never to refer to a real client. */
23845#define CLIENT_HANDLE_NULL 0xffffffff
23846/* enum: Used to refer to the calling client. */
23847#define CLIENT_HANDLE_SELF 0xfffffffe
23848#define CLIENT_HANDLE_OPAQUE_LBN 0
23849#define CLIENT_HANDLE_OPAQUE_WIDTH 32
23850
23851/* CLOCK_INFO structuredef: Information about a single hardware clock */
23852#define CLOCK_INFO_LEN 28
23853/* Enumeration that uniquely identifies the clock */
23854#define CLOCK_INFO_CLOCK_ID_OFST 0
23855#define CLOCK_INFO_CLOCK_ID_LEN 2
23856/* enum: The Riverhead CMC (card MC) */
23857#define CLOCK_INFO_CLOCK_CMC 0x0
23858/* enum: The Riverhead NMC (network MC) */
23859#define CLOCK_INFO_CLOCK_NMC 0x1
23860/* enum: The Riverhead SDNET slice main logic */
23861#define CLOCK_INFO_CLOCK_SDNET 0x2
23862/* enum: The Riverhead SDNET LUT */
23863#define CLOCK_INFO_CLOCK_SDNET_LUT 0x3
23864/* enum: The Riverhead SDNET control logic */
23865#define CLOCK_INFO_CLOCK_SDNET_CTRL 0x4
23866/* enum: The Riverhead Streaming SubSystem */
23867#define CLOCK_INFO_CLOCK_SSS 0x5
23868/* enum: The Riverhead network MAC and associated CSR registers */
23869#define CLOCK_INFO_CLOCK_MAC 0x6
23870#define CLOCK_INFO_CLOCK_ID_LBN 0
23871#define CLOCK_INFO_CLOCK_ID_WIDTH 16
23872/* Assorted flags */
23873#define CLOCK_INFO_FLAGS_OFST 2
23874#define CLOCK_INFO_FLAGS_LEN 2
23875#define CLOCK_INFO_SETTABLE_OFST 2
23876#define CLOCK_INFO_SETTABLE_LBN 0
23877#define CLOCK_INFO_SETTABLE_WIDTH 1
23878#define CLOCK_INFO_FLAGS_LBN 16
23879#define CLOCK_INFO_FLAGS_WIDTH 16
23880/* The frequency in HZ */
23881#define CLOCK_INFO_FREQUENCY_OFST 4
23882#define CLOCK_INFO_FREQUENCY_LEN 8
23883#define CLOCK_INFO_FREQUENCY_LO_OFST 4
23884#define CLOCK_INFO_FREQUENCY_LO_LEN 4
23885#define CLOCK_INFO_FREQUENCY_LO_LBN 32
23886#define CLOCK_INFO_FREQUENCY_LO_WIDTH 32
23887#define CLOCK_INFO_FREQUENCY_HI_OFST 8
23888#define CLOCK_INFO_FREQUENCY_HI_LEN 4
23889#define CLOCK_INFO_FREQUENCY_HI_LBN 64
23890#define CLOCK_INFO_FREQUENCY_HI_WIDTH 32
23891#define CLOCK_INFO_FREQUENCY_LBN 32
23892#define CLOCK_INFO_FREQUENCY_WIDTH 64
23893/* Human-readable ASCII name for clock, with NUL termination */
23894#define CLOCK_INFO_NAME_OFST 12
23895#define CLOCK_INFO_NAME_LEN 1
23896#define CLOCK_INFO_NAME_NUM 16
23897#define CLOCK_INFO_NAME_LBN 96
23898#define CLOCK_INFO_NAME_WIDTH 8
23899
23900/* SCHED_CREDIT_CHECK_RESULT structuredef */
23901#define SCHED_CREDIT_CHECK_RESULT_LEN 16
23902/* The instance of the scheduler. Refer to XN-200389-AW for the location of
23903 * these schedulers in the hardware.
23904 */
23905#define SCHED_CREDIT_CHECK_RESULT_SCHED_INSTANCE_OFST 0
23906#define SCHED_CREDIT_CHECK_RESULT_SCHED_INSTANCE_LEN 1
23907#define SCHED_CREDIT_CHECK_RESULT_HUB_HOST_A 0x0 /* enum */
23908#define SCHED_CREDIT_CHECK_RESULT_HUB_NET_A 0x1 /* enum */
23909#define SCHED_CREDIT_CHECK_RESULT_HUB_B 0x2 /* enum */
23910#define SCHED_CREDIT_CHECK_RESULT_HUB_HOST_C 0x3 /* enum */
23911#define SCHED_CREDIT_CHECK_RESULT_HUB_NET_TX 0x4 /* enum */
23912#define SCHED_CREDIT_CHECK_RESULT_HUB_HOST_D 0x5 /* enum */
23913#define SCHED_CREDIT_CHECK_RESULT_HUB_REPLAY 0x6 /* enum */
23914#define SCHED_CREDIT_CHECK_RESULT_DMAC_H2C 0x7 /* enum */
23915#define SCHED_CREDIT_CHECK_RESULT_HUB_NET_B 0x8 /* enum */
23916#define SCHED_CREDIT_CHECK_RESULT_HUB_NET_REPLAY 0x9 /* enum */
23917#define SCHED_CREDIT_CHECK_RESULT_SCHED_INSTANCE_LBN 0
23918#define SCHED_CREDIT_CHECK_RESULT_SCHED_INSTANCE_WIDTH 8
23919/* The type of node that this result refers to. */
23920#define SCHED_CREDIT_CHECK_RESULT_NODE_TYPE_OFST 1
23921#define SCHED_CREDIT_CHECK_RESULT_NODE_TYPE_LEN 1
23922/* enum: Destination node */
23923#define SCHED_CREDIT_CHECK_RESULT_DEST 0x0
23924/* enum: Source node */
23925#define SCHED_CREDIT_CHECK_RESULT_SOURCE 0x1
23926#define SCHED_CREDIT_CHECK_RESULT_NODE_TYPE_LBN 8
23927#define SCHED_CREDIT_CHECK_RESULT_NODE_TYPE_WIDTH 8
23928/* Level of node in scheduler hierarchy (level 0 is the bottom of the
23929 * hierarchy, increasing towards the root node).
23930 */
23931#define SCHED_CREDIT_CHECK_RESULT_NODE_LEVEL_OFST 2
23932#define SCHED_CREDIT_CHECK_RESULT_NODE_LEVEL_LEN 2
23933#define SCHED_CREDIT_CHECK_RESULT_NODE_LEVEL_LBN 16
23934#define SCHED_CREDIT_CHECK_RESULT_NODE_LEVEL_WIDTH 16
23935/* Node index */
23936#define SCHED_CREDIT_CHECK_RESULT_NODE_INDEX_OFST 4
23937#define SCHED_CREDIT_CHECK_RESULT_NODE_INDEX_LEN 4
23938#define SCHED_CREDIT_CHECK_RESULT_NODE_INDEX_LBN 32
23939#define SCHED_CREDIT_CHECK_RESULT_NODE_INDEX_WIDTH 32
23940/* The number of credits the node is expected to have. */
23941#define SCHED_CREDIT_CHECK_RESULT_EXPECTED_CREDITS_OFST 8
23942#define SCHED_CREDIT_CHECK_RESULT_EXPECTED_CREDITS_LEN 4
23943#define SCHED_CREDIT_CHECK_RESULT_EXPECTED_CREDITS_LBN 64
23944#define SCHED_CREDIT_CHECK_RESULT_EXPECTED_CREDITS_WIDTH 32
23945/* The number of credits the node actually had. */
23946#define SCHED_CREDIT_CHECK_RESULT_ACTUAL_CREDITS_OFST 12
23947#define SCHED_CREDIT_CHECK_RESULT_ACTUAL_CREDITS_LEN 4
23948#define SCHED_CREDIT_CHECK_RESULT_ACTUAL_CREDITS_LBN 96
23949#define SCHED_CREDIT_CHECK_RESULT_ACTUAL_CREDITS_WIDTH 32
23950
23951
23952/***********************************/
23953/* MC_CMD_GET_CLOCKS_INFO
23954 * Get information about the device clocks
23955 */
23956#define MC_CMD_GET_CLOCKS_INFO 0x166
23957#undef MC_CMD_0x166_PRIVILEGE_CTG
23958
23959#define MC_CMD_0x166_PRIVILEGE_CTG SRIOV_CTG_GENERAL
23960
23961/* MC_CMD_GET_CLOCKS_INFO_IN msgrequest */
23962#define MC_CMD_GET_CLOCKS_INFO_IN_LEN 0
23963
23964/* MC_CMD_GET_CLOCKS_INFO_OUT msgresponse */
23965#define MC_CMD_GET_CLOCKS_INFO_OUT_LENMIN 0
23966#define MC_CMD_GET_CLOCKS_INFO_OUT_LENMAX 252
23967#define MC_CMD_GET_CLOCKS_INFO_OUT_LENMAX_MCDI2 1008
23968#define MC_CMD_GET_CLOCKS_INFO_OUT_LEN(num) (0+28*(num))
23969#define MC_CMD_GET_CLOCKS_INFO_OUT_INFOS_NUM(len) (((len)-0)/28)
23970/* An array of CLOCK_INFO structures. */
23971#define MC_CMD_GET_CLOCKS_INFO_OUT_INFOS_OFST 0
23972#define MC_CMD_GET_CLOCKS_INFO_OUT_INFOS_LEN 28
23973#define MC_CMD_GET_CLOCKS_INFO_OUT_INFOS_MINNUM 0
23974#define MC_CMD_GET_CLOCKS_INFO_OUT_INFOS_MAXNUM 9
23975#define MC_CMD_GET_CLOCKS_INFO_OUT_INFOS_MAXNUM_MCDI2 36
23976
23977
23978/***********************************/
23979/* MC_CMD_VNIC_ENCAP_RULE_ADD
23980 * Add a rule for detecting encapsulations in the VNIC stage. Currently this
23981 * only affects checksum validation in VNIC RX - on TX the send descriptor
23982 * explicitly specifies encapsulation. These rules are per-VNIC, i.e. only
23983 * apply to the current driver. If a rule matches, then the packet is
23984 * considered to have the corresponding encapsulation type, and the inner
23985 * packet is parsed. It is up to the driver to ensure that overlapping rules
23986 * are not inserted. (If a packet would match multiple rules, a random one of
23987 * them will be used.) A rule with the exact same match criteria may not be
23988 * inserted twice (EALREADY). Only a limited number MATCH_FLAGS values are
23989 * supported, use MC_CMD_GET_PARSER_DISP_INFO with OP
23990 * OP_GET_SUPPORTED_VNIC_ENCAP_RULE_MATCHES to get a list of supported
23991 * combinations. Each driver may only have a limited set of active rules -
23992 * returns ENOSPC if the caller's table is full.
23993 */
23994#define MC_CMD_VNIC_ENCAP_RULE_ADD 0x16d
23995#undef MC_CMD_0x16d_PRIVILEGE_CTG
23996
23997#define MC_CMD_0x16d_PRIVILEGE_CTG SRIOV_CTG_GENERAL
23998
23999/* MC_CMD_VNIC_ENCAP_RULE_ADD_IN msgrequest */
24000#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_LEN 36
24001/* Set to MAE_MPORT_SELECTOR_ASSIGNED. In the future this may be relaxed. */
24002#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MPORT_SELECTOR_OFST 0
24003#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MPORT_SELECTOR_LEN 4
24004/* Any non-zero bits other than the ones named below or an unsupported
24005 * combination will cause the NIC to return EOPNOTSUPP. In the future more
24006 * flags may be added.
24007 */
24008#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_FLAGS_OFST 4
24009#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_FLAGS_LEN 4
24010#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_ETHER_TYPE_OFST 4
24011#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_ETHER_TYPE_LBN 0
24012#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_ETHER_TYPE_WIDTH 1
24013#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_OUTER_VLAN_OFST 4
24014#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_OUTER_VLAN_LBN 1
24015#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_OUTER_VLAN_WIDTH 1
24016#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_DST_IP_OFST 4
24017#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_DST_IP_LBN 2
24018#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_DST_IP_WIDTH 1
24019#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_IP_PROTO_OFST 4
24020#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_IP_PROTO_LBN 3
24021#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_IP_PROTO_WIDTH 1
24022#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_DST_PORT_OFST 4
24023#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_DST_PORT_LBN 4
24024#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_DST_PORT_WIDTH 1
24025/* Only if MATCH_ETHER_TYPE is set. Ethertype value as bytes in network order.
24026 * Currently only IPv4 (0x0800) and IPv6 (0x86DD) ethertypes may be used.
24027 */
24028#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_ETHER_TYPE_OFST 8
24029#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_ETHER_TYPE_LEN 2
24030/* Only if MATCH_OUTER_VLAN is set. VID value as bytes in network order.
24031 * (Deprecated)
24032 */
24033#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_OUTER_VLAN_LBN 80
24034#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_OUTER_VLAN_WIDTH 12
24035/* Only if MATCH_OUTER_VLAN is set. Aligned wrapper for OUTER_VLAN_VID. */
24036#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_OUTER_VLAN_WORD_OFST 10
24037#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_OUTER_VLAN_WORD_LEN 2
24038#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_OUTER_VLAN_VID_OFST 10
24039#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_OUTER_VLAN_VID_LBN 0
24040#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_OUTER_VLAN_VID_WIDTH 12
24041/* Only if MATCH_DST_IP is set. IP address as bytes in network order. In the
24042 * case of IPv4, the IP should be in the first 4 bytes and all other bytes
24043 * should be zero.
24044 */
24045#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_DST_IP_OFST 12
24046#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_DST_IP_LEN 16
24047/* Only if MATCH_IP_PROTO is set. Currently only UDP proto (17) may be used. */
24048#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_IP_PROTO_OFST 28
24049#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_IP_PROTO_LEN 1
24050/* Actions that should be applied to packets match the rule. */
24051#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_ACTION_FLAGS_OFST 29
24052#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_ACTION_FLAGS_LEN 1
24053#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_STRIP_OUTER_VLAN_OFST 29
24054#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_STRIP_OUTER_VLAN_LBN 0
24055#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_STRIP_OUTER_VLAN_WIDTH 1
24056#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_RSS_ON_OUTER_OFST 29
24057#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_RSS_ON_OUTER_LBN 1
24058#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_RSS_ON_OUTER_WIDTH 1
24059#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_STEER_ON_OUTER_OFST 29
24060#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_STEER_ON_OUTER_LBN 2
24061#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_STEER_ON_OUTER_WIDTH 1
24062/* Only if MATCH_DST_PORT is set. Port number as bytes in network order. */
24063#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_DST_PORT_OFST 30
24064#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_DST_PORT_LEN 2
24065/* Resulting encapsulation type, as per MAE_MCDI_ENCAP_TYPE enumeration. */
24066#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_ENCAP_TYPE_OFST 32
24067#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_ENCAP_TYPE_LEN 4
24068
24069/* MC_CMD_VNIC_ENCAP_RULE_ADD_OUT msgresponse */
24070#define MC_CMD_VNIC_ENCAP_RULE_ADD_OUT_LEN 4
24071/* Handle to inserted rule. Used for removing the rule. */
24072#define MC_CMD_VNIC_ENCAP_RULE_ADD_OUT_HANDLE_OFST 0
24073#define MC_CMD_VNIC_ENCAP_RULE_ADD_OUT_HANDLE_LEN 4
24074
24075
24076/***********************************/
24077/* MC_CMD_VNIC_ENCAP_RULE_REMOVE
24078 * Remove a VNIC encapsulation rule. Packets which would have previously
24079 * matched the rule will then be considered as unencapsulated. Returns EALREADY
24080 * if the input HANDLE doesn't correspond to an existing rule.
24081 */
24082#define MC_CMD_VNIC_ENCAP_RULE_REMOVE 0x16e
24083#undef MC_CMD_0x16e_PRIVILEGE_CTG
24084
24085#define MC_CMD_0x16e_PRIVILEGE_CTG SRIOV_CTG_GENERAL
24086
24087/* MC_CMD_VNIC_ENCAP_RULE_REMOVE_IN msgrequest */
24088#define MC_CMD_VNIC_ENCAP_RULE_REMOVE_IN_LEN 4
24089/* Handle which was returned by MC_CMD_VNIC_ENCAP_RULE_ADD. */
24090#define MC_CMD_VNIC_ENCAP_RULE_REMOVE_IN_HANDLE_OFST 0
24091#define MC_CMD_VNIC_ENCAP_RULE_REMOVE_IN_HANDLE_LEN 4
24092
24093/* MC_CMD_VNIC_ENCAP_RULE_REMOVE_OUT msgresponse */
24094#define MC_CMD_VNIC_ENCAP_RULE_REMOVE_OUT_LEN 0
24095
24096/* UUID structuredef: An RFC4122 standard UUID. The values here are stored in
24097 * the endianness specified by the RFC; users should ignore the broken-out
24098 * fields and instead do straight memory copies to ensure correct ordering.
24099 */
24100#define UUID_LEN 16
24101#define UUID_TIME_LOW_OFST 0
24102#define UUID_TIME_LOW_LEN 4
24103#define UUID_TIME_LOW_LBN 0
24104#define UUID_TIME_LOW_WIDTH 32
24105#define UUID_TIME_MID_OFST 4
24106#define UUID_TIME_MID_LEN 2
24107#define UUID_TIME_MID_LBN 32
24108#define UUID_TIME_MID_WIDTH 16
24109#define UUID_TIME_HI_LBN 52
24110#define UUID_TIME_HI_WIDTH 12
24111#define UUID_VERSION_LBN 48
24112#define UUID_VERSION_WIDTH 4
24113#define UUID_RESERVED_LBN 64
24114#define UUID_RESERVED_WIDTH 2
24115#define UUID_CLK_SEQ_LBN 66
24116#define UUID_CLK_SEQ_WIDTH 14
24117#define UUID_NODE_OFST 10
24118#define UUID_NODE_LEN 6
24119#define UUID_NODE_LBN 80
24120#define UUID_NODE_WIDTH 48
24121
24122
24123/***********************************/
24124/* MC_CMD_PLUGIN_ALLOC
24125 * Create a handle to a datapath plugin's extension. This involves finding a
24126 * currently-loaded plugin offering the given functionality (as identified by
24127 * the UUID) and allocating a handle to track the usage of it. Plugin
24128 * functionality is identified by 'extension' rather than any other identifier
24129 * so that a single plugin bitfile may offer more than one piece of independent
24130 * functionality. If two bitfiles are loaded which both offer the same
24131 * extension, then the metadata is interrogated further to determine which is
24132 * the newest and that is the one opened. See SF-123625-SW for architectural
24133 * detail on datapath plugins.
24134 */
24135#define MC_CMD_PLUGIN_ALLOC 0x1ad
24136#undef MC_CMD_0x1ad_PRIVILEGE_CTG
24137
24138#define MC_CMD_0x1ad_PRIVILEGE_CTG SRIOV_CTG_GENERAL
24139
24140/* MC_CMD_PLUGIN_ALLOC_IN msgrequest */
24141#define MC_CMD_PLUGIN_ALLOC_IN_LEN 24
24142/* The functionality requested of the plugin, as a UUID structure */
24143#define MC_CMD_PLUGIN_ALLOC_IN_UUID_OFST 0
24144#define MC_CMD_PLUGIN_ALLOC_IN_UUID_LEN 16
24145/* Additional options for opening the handle */
24146#define MC_CMD_PLUGIN_ALLOC_IN_FLAGS_OFST 16
24147#define MC_CMD_PLUGIN_ALLOC_IN_FLAGS_LEN 4
24148#define MC_CMD_PLUGIN_ALLOC_IN_FLAG_INFO_ONLY_OFST 16
24149#define MC_CMD_PLUGIN_ALLOC_IN_FLAG_INFO_ONLY_LBN 0
24150#define MC_CMD_PLUGIN_ALLOC_IN_FLAG_INFO_ONLY_WIDTH 1
24151#define MC_CMD_PLUGIN_ALLOC_IN_FLAG_ALLOW_DISABLED_OFST 16
24152#define MC_CMD_PLUGIN_ALLOC_IN_FLAG_ALLOW_DISABLED_LBN 1
24153#define MC_CMD_PLUGIN_ALLOC_IN_FLAG_ALLOW_DISABLED_WIDTH 1
24154/* Load the extension only if it is in the specified administrative group.
24155 * Specify ANY to load the extension wherever it is found (if there are
24156 * multiple choices then the extension with the highest MINOR_VER/PATCH_VER
24157 * will be loaded). See MC_CMD_PLUGIN_GET_META_GLOBAL for a description of
24158 * administrative groups.
24159 */
24160#define MC_CMD_PLUGIN_ALLOC_IN_ADMIN_GROUP_OFST 20
24161#define MC_CMD_PLUGIN_ALLOC_IN_ADMIN_GROUP_LEN 2
24162/* enum: Load the extension from any ADMIN_GROUP. */
24163#define MC_CMD_PLUGIN_ALLOC_IN_ANY 0xffff
24164/* Reserved */
24165#define MC_CMD_PLUGIN_ALLOC_IN_RESERVED_OFST 22
24166#define MC_CMD_PLUGIN_ALLOC_IN_RESERVED_LEN 2
24167
24168/* MC_CMD_PLUGIN_ALLOC_OUT msgresponse */
24169#define MC_CMD_PLUGIN_ALLOC_OUT_LEN 4
24170/* Unique identifier of this usage */
24171#define MC_CMD_PLUGIN_ALLOC_OUT_HANDLE_OFST 0
24172#define MC_CMD_PLUGIN_ALLOC_OUT_HANDLE_LEN 4
24173
24174
24175/***********************************/
24176/* MC_CMD_PLUGIN_FREE
24177 * Delete a handle to a plugin's extension.
24178 */
24179#define MC_CMD_PLUGIN_FREE 0x1ae
24180#undef MC_CMD_0x1ae_PRIVILEGE_CTG
24181
24182#define MC_CMD_0x1ae_PRIVILEGE_CTG SRIOV_CTG_GENERAL
24183
24184/* MC_CMD_PLUGIN_FREE_IN msgrequest */
24185#define MC_CMD_PLUGIN_FREE_IN_LEN 4
24186/* Handle returned by MC_CMD_PLUGIN_ALLOC_OUT */
24187#define MC_CMD_PLUGIN_FREE_IN_HANDLE_OFST 0
24188#define MC_CMD_PLUGIN_FREE_IN_HANDLE_LEN 4
24189
24190/* MC_CMD_PLUGIN_FREE_OUT msgresponse */
24191#define MC_CMD_PLUGIN_FREE_OUT_LEN 0
24192
24193
24194/***********************************/
24195/* MC_CMD_PLUGIN_GET_META_GLOBAL
24196 * Returns the global metadata applying to the whole plugin extension. See the
24197 * other metadata calls for subtypes of data.
24198 */
24199#define MC_CMD_PLUGIN_GET_META_GLOBAL 0x1af
24200#undef MC_CMD_0x1af_PRIVILEGE_CTG
24201
24202#define MC_CMD_0x1af_PRIVILEGE_CTG SRIOV_CTG_GENERAL
24203
24204/* MC_CMD_PLUGIN_GET_META_GLOBAL_IN msgrequest */
24205#define MC_CMD_PLUGIN_GET_META_GLOBAL_IN_LEN 4
24206/* Handle returned by MC_CMD_PLUGIN_ALLOC_OUT */
24207#define MC_CMD_PLUGIN_GET_META_GLOBAL_IN_HANDLE_OFST 0
24208#define MC_CMD_PLUGIN_GET_META_GLOBAL_IN_HANDLE_LEN 4
24209
24210/* MC_CMD_PLUGIN_GET_META_GLOBAL_OUT msgresponse */
24211#define MC_CMD_PLUGIN_GET_META_GLOBAL_OUT_LEN 36
24212/* Unique identifier of this plugin extension. This is identical to the value
24213 * which was requested when the handle was allocated.
24214 */
24215#define MC_CMD_PLUGIN_GET_META_GLOBAL_OUT_UUID_OFST 0
24216#define MC_CMD_PLUGIN_GET_META_GLOBAL_OUT_UUID_LEN 16
24217/* semver sub-version of this plugin extension */
24218#define MC_CMD_PLUGIN_GET_META_GLOBAL_OUT_MINOR_VER_OFST 16
24219#define MC_CMD_PLUGIN_GET_META_GLOBAL_OUT_MINOR_VER_LEN 2
24220/* semver micro-version of this plugin extension */
24221#define MC_CMD_PLUGIN_GET_META_GLOBAL_OUT_PATCH_VER_OFST 18
24222#define MC_CMD_PLUGIN_GET_META_GLOBAL_OUT_PATCH_VER_LEN 2
24223/* Number of different messages which can be sent to this extension */
24224#define MC_CMD_PLUGIN_GET_META_GLOBAL_OUT_NUM_MSGS_OFST 20
24225#define MC_CMD_PLUGIN_GET_META_GLOBAL_OUT_NUM_MSGS_LEN 4
24226/* Byte offset within the VI window of the plugin's mapped CSR window. */
24227#define MC_CMD_PLUGIN_GET_META_GLOBAL_OUT_MAPPED_CSR_OFFSET_OFST 24
24228#define MC_CMD_PLUGIN_GET_META_GLOBAL_OUT_MAPPED_CSR_OFFSET_LEN 2
24229/* Number of bytes mapped through to the plugin's CSRs. 0 if that feature was
24230 * not requested by the plugin (in which case MAPPED_CSR_OFFSET and
24231 * MAPPED_CSR_FLAGS are ignored).
24232 */
24233#define MC_CMD_PLUGIN_GET_META_GLOBAL_OUT_MAPPED_CSR_SIZE_OFST 26
24234#define MC_CMD_PLUGIN_GET_META_GLOBAL_OUT_MAPPED_CSR_SIZE_LEN 2
24235/* Flags indicating how to perform the CSR window mapping. */
24236#define MC_CMD_PLUGIN_GET_META_GLOBAL_OUT_MAPPED_CSR_FLAGS_OFST 28
24237#define MC_CMD_PLUGIN_GET_META_GLOBAL_OUT_MAPPED_CSR_FLAGS_LEN 4
24238#define MC_CMD_PLUGIN_GET_META_GLOBAL_OUT_MAPPED_CSR_FLAG_READ_OFST 28
24239#define MC_CMD_PLUGIN_GET_META_GLOBAL_OUT_MAPPED_CSR_FLAG_READ_LBN 0
24240#define MC_CMD_PLUGIN_GET_META_GLOBAL_OUT_MAPPED_CSR_FLAG_READ_WIDTH 1
24241#define MC_CMD_PLUGIN_GET_META_GLOBAL_OUT_MAPPED_CSR_FLAG_WRITE_OFST 28
24242#define MC_CMD_PLUGIN_GET_META_GLOBAL_OUT_MAPPED_CSR_FLAG_WRITE_LBN 1
24243#define MC_CMD_PLUGIN_GET_META_GLOBAL_OUT_MAPPED_CSR_FLAG_WRITE_WIDTH 1
24244/* Identifier of the set of extensions which all change state together.
24245 * Extensions having the same ADMIN_GROUP will always load and unload at the
24246 * same time. ADMIN_GROUP values themselves are arbitrary (but they contain a
24247 * generation number as an implementation detail to ensure that they're not
24248 * reused rapidly).
24249 */
24250#define MC_CMD_PLUGIN_GET_META_GLOBAL_OUT_ADMIN_GROUP_OFST 32
24251#define MC_CMD_PLUGIN_GET_META_GLOBAL_OUT_ADMIN_GROUP_LEN 1
24252/* Bitshift in MC_CMD_DEVEL_CLIENT_PRIVILEGE_MODIFY's MASK parameters
24253 * corresponding to this extension, i.e. set the bit 1<<PRIVILEGE_BIT to permit
24254 * access to this extension.
24255 */
24256#define MC_CMD_PLUGIN_GET_META_GLOBAL_OUT_PRIVILEGE_BIT_OFST 33
24257#define MC_CMD_PLUGIN_GET_META_GLOBAL_OUT_PRIVILEGE_BIT_LEN 1
24258/* Reserved */
24259#define MC_CMD_PLUGIN_GET_META_GLOBAL_OUT_RESERVED_OFST 34
24260#define MC_CMD_PLUGIN_GET_META_GLOBAL_OUT_RESERVED_LEN 2
24261
24262
24263/***********************************/
24264/* MC_CMD_PLUGIN_GET_META_PUBLISHER
24265 * Returns metadata supplied by the plugin author which describes this
24266 * extension in a human-readable way. Contrast with
24267 * MC_CMD_PLUGIN_GET_META_GLOBAL, which returns information needed for software
24268 * to operate.
24269 */
24270#define MC_CMD_PLUGIN_GET_META_PUBLISHER 0x1b0
24271#undef MC_CMD_0x1b0_PRIVILEGE_CTG
24272
24273#define MC_CMD_0x1b0_PRIVILEGE_CTG SRIOV_CTG_GENERAL
24274
24275/* MC_CMD_PLUGIN_GET_META_PUBLISHER_IN msgrequest */
24276#define MC_CMD_PLUGIN_GET_META_PUBLISHER_IN_LEN 12
24277/* Handle returned by MC_CMD_PLUGIN_ALLOC_OUT */
24278#define MC_CMD_PLUGIN_GET_META_PUBLISHER_IN_HANDLE_OFST 0
24279#define MC_CMD_PLUGIN_GET_META_PUBLISHER_IN_HANDLE_LEN 4
24280/* Category of data to return */
24281#define MC_CMD_PLUGIN_GET_META_PUBLISHER_IN_SUBTYPE_OFST 4
24282#define MC_CMD_PLUGIN_GET_META_PUBLISHER_IN_SUBTYPE_LEN 4
24283/* enum: Top-level information about the extension. The returned data is an
24284 * array of key/value pairs using the keys in RFC5013 (Dublin Core) to describe
24285 * the extension. The data is a back-to-back list of zero-terminated strings;
24286 * the even-numbered fields (0,2,4,...) are keys and their following odd-
24287 * numbered fields are the corresponding values. Both keys and values are
24288 * nominally UTF-8. Per RFC5013, the same key may be repeated any number of
24289 * times. Note that all information (including the key/value structure itself
24290 * and the UTF-8 encoding) may have been provided by the plugin author, so
24291 * callers must be cautious about parsing it. Callers should parse only the
24292 * top-level structure to separate out the keys and values; the contents of the
24293 * values is not expected to be machine-readable.
24294 */
24295#define MC_CMD_PLUGIN_GET_META_PUBLISHER_IN_EXTENSION_KVS 0x0
24296/* Byte position of the data to be returned within the full data block of the
24297 * given SUBTYPE.
24298 */
24299#define MC_CMD_PLUGIN_GET_META_PUBLISHER_IN_OFFSET_OFST 8
24300#define MC_CMD_PLUGIN_GET_META_PUBLISHER_IN_OFFSET_LEN 4
24301
24302/* MC_CMD_PLUGIN_GET_META_PUBLISHER_OUT msgresponse */
24303#define MC_CMD_PLUGIN_GET_META_PUBLISHER_OUT_LENMIN 4
24304#define MC_CMD_PLUGIN_GET_META_PUBLISHER_OUT_LENMAX 252
24305#define MC_CMD_PLUGIN_GET_META_PUBLISHER_OUT_LENMAX_MCDI2 1020
24306#define MC_CMD_PLUGIN_GET_META_PUBLISHER_OUT_LEN(num) (4+1*(num))
24307#define MC_CMD_PLUGIN_GET_META_PUBLISHER_OUT_DATA_NUM(len) (((len)-4)/1)
24308/* Full length of the data block of the requested SUBTYPE, in bytes. */
24309#define MC_CMD_PLUGIN_GET_META_PUBLISHER_OUT_TOTAL_SIZE_OFST 0
24310#define MC_CMD_PLUGIN_GET_META_PUBLISHER_OUT_TOTAL_SIZE_LEN 4
24311/* The information requested by SUBTYPE. */
24312#define MC_CMD_PLUGIN_GET_META_PUBLISHER_OUT_DATA_OFST 4
24313#define MC_CMD_PLUGIN_GET_META_PUBLISHER_OUT_DATA_LEN 1
24314#define MC_CMD_PLUGIN_GET_META_PUBLISHER_OUT_DATA_MINNUM 0
24315#define MC_CMD_PLUGIN_GET_META_PUBLISHER_OUT_DATA_MAXNUM 248
24316#define MC_CMD_PLUGIN_GET_META_PUBLISHER_OUT_DATA_MAXNUM_MCDI2 1016
24317
24318
24319/***********************************/
24320/* MC_CMD_PLUGIN_GET_META_MSG
24321 * Returns the simple metadata for a specific plugin request message. This
24322 * supplies information necessary for the host to know how to build an
24323 * MC_CMD_PLUGIN_REQ request.
24324 */
24325#define MC_CMD_PLUGIN_GET_META_MSG 0x1b1
24326#undef MC_CMD_0x1b1_PRIVILEGE_CTG
24327
24328#define MC_CMD_0x1b1_PRIVILEGE_CTG SRIOV_CTG_GENERAL
24329
24330/* MC_CMD_PLUGIN_GET_META_MSG_IN msgrequest */
24331#define MC_CMD_PLUGIN_GET_META_MSG_IN_LEN 8
24332/* Handle returned by MC_CMD_PLUGIN_ALLOC_OUT */
24333#define MC_CMD_PLUGIN_GET_META_MSG_IN_HANDLE_OFST 0
24334#define MC_CMD_PLUGIN_GET_META_MSG_IN_HANDLE_LEN 4
24335/* Unique message ID to obtain */
24336#define MC_CMD_PLUGIN_GET_META_MSG_IN_ID_OFST 4
24337#define MC_CMD_PLUGIN_GET_META_MSG_IN_ID_LEN 4
24338
24339/* MC_CMD_PLUGIN_GET_META_MSG_OUT msgresponse */
24340#define MC_CMD_PLUGIN_GET_META_MSG_OUT_LEN 44
24341/* Unique message ID. This is the same value as the input parameter; it exists
24342 * to allow future MCDI extensions which enumerate all messages.
24343 */
24344#define MC_CMD_PLUGIN_GET_META_MSG_OUT_ID_OFST 0
24345#define MC_CMD_PLUGIN_GET_META_MSG_OUT_ID_LEN 4
24346/* Packed index number of this message, assigned by the MC to give each message
24347 * a unique ID in an array to allow for more efficient storage/management.
24348 */
24349#define MC_CMD_PLUGIN_GET_META_MSG_OUT_INDEX_OFST 4
24350#define MC_CMD_PLUGIN_GET_META_MSG_OUT_INDEX_LEN 4
24351/* Short human-readable codename for this message. This is conventionally
24352 * formatted as a C identifier in the basic ASCII character set with any spare
24353 * bytes at the end set to 0, however this convention is not enforced by the MC
24354 * so consumers must check for all potential malformations before using it for
24355 * a trusted purpose.
24356 */
24357#define MC_CMD_PLUGIN_GET_META_MSG_OUT_NAME_OFST 8
24358#define MC_CMD_PLUGIN_GET_META_MSG_OUT_NAME_LEN 32
24359/* Number of bytes of data which must be passed from the host kernel to the MC
24360 * for this message's payload, and which are passed back again in the response.
24361 * The MC's plugin metadata loader will have validated that the number of bytes
24362 * specified here will fit in to MC_CMD_PLUGIN_REQ_IN_DATA in a single MCDI
24363 * message.
24364 */
24365#define MC_CMD_PLUGIN_GET_META_MSG_OUT_DATA_SIZE_OFST 40
24366#define MC_CMD_PLUGIN_GET_META_MSG_OUT_DATA_SIZE_LEN 4
24367
24368/* PLUGIN_EXTENSION structuredef: Used within MC_CMD_PLUGIN_GET_ALL to describe
24369 * an individual extension.
24370 */
24371#define PLUGIN_EXTENSION_LEN 20
24372#define PLUGIN_EXTENSION_UUID_OFST 0
24373#define PLUGIN_EXTENSION_UUID_LEN 16
24374#define PLUGIN_EXTENSION_UUID_LBN 0
24375#define PLUGIN_EXTENSION_UUID_WIDTH 128
24376#define PLUGIN_EXTENSION_ADMIN_GROUP_OFST 16
24377#define PLUGIN_EXTENSION_ADMIN_GROUP_LEN 1
24378#define PLUGIN_EXTENSION_ADMIN_GROUP_LBN 128
24379#define PLUGIN_EXTENSION_ADMIN_GROUP_WIDTH 8
24380#define PLUGIN_EXTENSION_FLAG_ENABLED_LBN 136
24381#define PLUGIN_EXTENSION_FLAG_ENABLED_WIDTH 1
24382#define PLUGIN_EXTENSION_RESERVED_LBN 137
24383#define PLUGIN_EXTENSION_RESERVED_WIDTH 23
24384
24385
24386/***********************************/
24387/* MC_CMD_PLUGIN_GET_ALL
24388 * Returns a list of all plugin extensions currently loaded and available. The
24389 * UUIDs returned can be passed to MC_CMD_PLUGIN_ALLOC in order to obtain more
24390 * detailed metadata via the MC_CMD_PLUGIN_GET_META_* family of requests. The
24391 * ADMIN_GROUP field collects how extensions are grouped in to units which are
24392 * loaded/unloaded together; extensions with the same value are in the same
24393 * group.
24394 */
24395#define MC_CMD_PLUGIN_GET_ALL 0x1b2
24396#undef MC_CMD_0x1b2_PRIVILEGE_CTG
24397
24398#define MC_CMD_0x1b2_PRIVILEGE_CTG SRIOV_CTG_GENERAL
24399
24400/* MC_CMD_PLUGIN_GET_ALL_IN msgrequest */
24401#define MC_CMD_PLUGIN_GET_ALL_IN_LEN 4
24402/* Additional options for querying. Note that if neither FLAG_INCLUDE_ENABLED
24403 * nor FLAG_INCLUDE_DISABLED are specified then the result set will be empty.
24404 */
24405#define MC_CMD_PLUGIN_GET_ALL_IN_FLAGS_OFST 0
24406#define MC_CMD_PLUGIN_GET_ALL_IN_FLAGS_LEN 4
24407#define MC_CMD_PLUGIN_GET_ALL_IN_FLAG_INCLUDE_ENABLED_OFST 0
24408#define MC_CMD_PLUGIN_GET_ALL_IN_FLAG_INCLUDE_ENABLED_LBN 0
24409#define MC_CMD_PLUGIN_GET_ALL_IN_FLAG_INCLUDE_ENABLED_WIDTH 1
24410#define MC_CMD_PLUGIN_GET_ALL_IN_FLAG_INCLUDE_DISABLED_OFST 0
24411#define MC_CMD_PLUGIN_GET_ALL_IN_FLAG_INCLUDE_DISABLED_LBN 1
24412#define MC_CMD_PLUGIN_GET_ALL_IN_FLAG_INCLUDE_DISABLED_WIDTH 1
24413
24414/* MC_CMD_PLUGIN_GET_ALL_OUT msgresponse */
24415#define MC_CMD_PLUGIN_GET_ALL_OUT_LENMIN 0
24416#define MC_CMD_PLUGIN_GET_ALL_OUT_LENMAX 240
24417#define MC_CMD_PLUGIN_GET_ALL_OUT_LENMAX_MCDI2 1020
24418#define MC_CMD_PLUGIN_GET_ALL_OUT_LEN(num) (0+20*(num))
24419#define MC_CMD_PLUGIN_GET_ALL_OUT_EXTENSIONS_NUM(len) (((len)-0)/20)
24420/* The list of available plugin extensions, as an array of PLUGIN_EXTENSION
24421 * structs.
24422 */
24423#define MC_CMD_PLUGIN_GET_ALL_OUT_EXTENSIONS_OFST 0
24424#define MC_CMD_PLUGIN_GET_ALL_OUT_EXTENSIONS_LEN 20
24425#define MC_CMD_PLUGIN_GET_ALL_OUT_EXTENSIONS_MINNUM 0
24426#define MC_CMD_PLUGIN_GET_ALL_OUT_EXTENSIONS_MAXNUM 12
24427#define MC_CMD_PLUGIN_GET_ALL_OUT_EXTENSIONS_MAXNUM_MCDI2 51
24428
24429
24430/***********************************/
24431/* MC_CMD_PLUGIN_REQ
24432 * Send a command to a plugin. A plugin may define an arbitrary number of
24433 * 'messages' which it allows applications on the host system to send, each
24434 * identified by a 32-bit ID.
24435 */
24436#define MC_CMD_PLUGIN_REQ 0x1b3
24437#undef MC_CMD_0x1b3_PRIVILEGE_CTG
24438
24439#define MC_CMD_0x1b3_PRIVILEGE_CTG SRIOV_CTG_GENERAL
24440
24441/* MC_CMD_PLUGIN_REQ_IN msgrequest */
24442#define MC_CMD_PLUGIN_REQ_IN_LENMIN 8
24443#define MC_CMD_PLUGIN_REQ_IN_LENMAX 252
24444#define MC_CMD_PLUGIN_REQ_IN_LENMAX_MCDI2 1020
24445#define MC_CMD_PLUGIN_REQ_IN_LEN(num) (8+1*(num))
24446#define MC_CMD_PLUGIN_REQ_IN_DATA_NUM(len) (((len)-8)/1)
24447/* Handle returned by MC_CMD_PLUGIN_ALLOC_OUT */
24448#define MC_CMD_PLUGIN_REQ_IN_HANDLE_OFST 0
24449#define MC_CMD_PLUGIN_REQ_IN_HANDLE_LEN 4
24450/* Message ID defined by the plugin author */
24451#define MC_CMD_PLUGIN_REQ_IN_ID_OFST 4
24452#define MC_CMD_PLUGIN_REQ_IN_ID_LEN 4
24453/* Data blob being the parameter to the message. This must be of the length
24454 * specified by MC_CMD_PLUGIN_GET_META_MSG_IN_MCDI_PARAM_SIZE.
24455 */
24456#define MC_CMD_PLUGIN_REQ_IN_DATA_OFST 8
24457#define MC_CMD_PLUGIN_REQ_IN_DATA_LEN 1
24458#define MC_CMD_PLUGIN_REQ_IN_DATA_MINNUM 0
24459#define MC_CMD_PLUGIN_REQ_IN_DATA_MAXNUM 244
24460#define MC_CMD_PLUGIN_REQ_IN_DATA_MAXNUM_MCDI2 1012
24461
24462/* MC_CMD_PLUGIN_REQ_OUT msgresponse */
24463#define MC_CMD_PLUGIN_REQ_OUT_LENMIN 0
24464#define MC_CMD_PLUGIN_REQ_OUT_LENMAX 252
24465#define MC_CMD_PLUGIN_REQ_OUT_LENMAX_MCDI2 1020
24466#define MC_CMD_PLUGIN_REQ_OUT_LEN(num) (0+1*(num))
24467#define MC_CMD_PLUGIN_REQ_OUT_DATA_NUM(len) (((len)-0)/1)
24468/* The input data, as transformed and/or updated by the plugin's eBPF. Will be
24469 * the same size as the input DATA parameter.
24470 */
24471#define MC_CMD_PLUGIN_REQ_OUT_DATA_OFST 0
24472#define MC_CMD_PLUGIN_REQ_OUT_DATA_LEN 1
24473#define MC_CMD_PLUGIN_REQ_OUT_DATA_MINNUM 0
24474#define MC_CMD_PLUGIN_REQ_OUT_DATA_MAXNUM 252
24475#define MC_CMD_PLUGIN_REQ_OUT_DATA_MAXNUM_MCDI2 1020
24476
24477/* DESC_ADDR_REGION structuredef: Describes a contiguous region of DESC_ADDR
24478 * space that maps to a contiguous region of TRGT_ADDR space. Addresses
24479 * DESC_ADDR in the range [DESC_ADDR_BASE:DESC_ADDR_BASE + 1 <<
24480 * WINDOW_SIZE_LOG2) map to TRGT_ADDR = DESC_ADDR - DESC_ADDR_BASE +
24481 * TRGT_ADDR_BASE.
24482 */
24483#define DESC_ADDR_REGION_LEN 32
24484/* The start of the region in DESC_ADDR space. */
24485#define DESC_ADDR_REGION_DESC_ADDR_BASE_OFST 0
24486#define DESC_ADDR_REGION_DESC_ADDR_BASE_LEN 8
24487#define DESC_ADDR_REGION_DESC_ADDR_BASE_LO_OFST 0
24488#define DESC_ADDR_REGION_DESC_ADDR_BASE_LO_LEN 4
24489#define DESC_ADDR_REGION_DESC_ADDR_BASE_LO_LBN 0
24490#define DESC_ADDR_REGION_DESC_ADDR_BASE_LO_WIDTH 32
24491#define DESC_ADDR_REGION_DESC_ADDR_BASE_HI_OFST 4
24492#define DESC_ADDR_REGION_DESC_ADDR_BASE_HI_LEN 4
24493#define DESC_ADDR_REGION_DESC_ADDR_BASE_HI_LBN 32
24494#define DESC_ADDR_REGION_DESC_ADDR_BASE_HI_WIDTH 32
24495#define DESC_ADDR_REGION_DESC_ADDR_BASE_LBN 0
24496#define DESC_ADDR_REGION_DESC_ADDR_BASE_WIDTH 64
24497/* The start of the region in TRGT_ADDR space. Drivers can set this via
24498 * MC_CMD_SET_DESC_ADDR_REGIONS.
24499 */
24500#define DESC_ADDR_REGION_TRGT_ADDR_BASE_OFST 8
24501#define DESC_ADDR_REGION_TRGT_ADDR_BASE_LEN 8
24502#define DESC_ADDR_REGION_TRGT_ADDR_BASE_LO_OFST 8
24503#define DESC_ADDR_REGION_TRGT_ADDR_BASE_LO_LEN 4
24504#define DESC_ADDR_REGION_TRGT_ADDR_BASE_LO_LBN 64
24505#define DESC_ADDR_REGION_TRGT_ADDR_BASE_LO_WIDTH 32
24506#define DESC_ADDR_REGION_TRGT_ADDR_BASE_HI_OFST 12
24507#define DESC_ADDR_REGION_TRGT_ADDR_BASE_HI_LEN 4
24508#define DESC_ADDR_REGION_TRGT_ADDR_BASE_HI_LBN 96
24509#define DESC_ADDR_REGION_TRGT_ADDR_BASE_HI_WIDTH 32
24510#define DESC_ADDR_REGION_TRGT_ADDR_BASE_LBN 64
24511#define DESC_ADDR_REGION_TRGT_ADDR_BASE_WIDTH 64
24512/* The size of the region. */
24513#define DESC_ADDR_REGION_WINDOW_SIZE_LOG2_OFST 16
24514#define DESC_ADDR_REGION_WINDOW_SIZE_LOG2_LEN 4
24515#define DESC_ADDR_REGION_WINDOW_SIZE_LOG2_LBN 128
24516#define DESC_ADDR_REGION_WINDOW_SIZE_LOG2_WIDTH 32
24517/* The alignment restriction on TRGT_ADDR. TRGT_ADDR values set by the driver
24518 * must be a multiple of 1 << TRGT_ADDR_ALIGN_LOG2.
24519 */
24520#define DESC_ADDR_REGION_TRGT_ADDR_ALIGN_LOG2_OFST 20
24521#define DESC_ADDR_REGION_TRGT_ADDR_ALIGN_LOG2_LEN 4
24522#define DESC_ADDR_REGION_TRGT_ADDR_ALIGN_LOG2_LBN 160
24523#define DESC_ADDR_REGION_TRGT_ADDR_ALIGN_LOG2_WIDTH 32
24524#define DESC_ADDR_REGION_RSVD_OFST 24
24525#define DESC_ADDR_REGION_RSVD_LEN 8
24526#define DESC_ADDR_REGION_RSVD_LO_OFST 24
24527#define DESC_ADDR_REGION_RSVD_LO_LEN 4
24528#define DESC_ADDR_REGION_RSVD_LO_LBN 192
24529#define DESC_ADDR_REGION_RSVD_LO_WIDTH 32
24530#define DESC_ADDR_REGION_RSVD_HI_OFST 28
24531#define DESC_ADDR_REGION_RSVD_HI_LEN 4
24532#define DESC_ADDR_REGION_RSVD_HI_LBN 224
24533#define DESC_ADDR_REGION_RSVD_HI_WIDTH 32
24534#define DESC_ADDR_REGION_RSVD_LBN 192
24535#define DESC_ADDR_REGION_RSVD_WIDTH 64
24536
24537
24538/***********************************/
24539/* MC_CMD_GET_DESC_ADDR_INFO
24540 * Returns a description of the mapping from DESC_ADDR to TRGT_ADDR for the calling function's address space.
24541 */
24542#define MC_CMD_GET_DESC_ADDR_INFO 0x1b7
24543#undef MC_CMD_0x1b7_PRIVILEGE_CTG
24544
24545#define MC_CMD_0x1b7_PRIVILEGE_CTG SRIOV_CTG_GENERAL
24546
24547/* MC_CMD_GET_DESC_ADDR_INFO_IN msgrequest */
24548#define MC_CMD_GET_DESC_ADDR_INFO_IN_LEN 0
24549
24550/* MC_CMD_GET_DESC_ADDR_INFO_OUT msgresponse */
24551#define MC_CMD_GET_DESC_ADDR_INFO_OUT_LEN 4
24552/* The type of mapping; see SF-nnnnnn-xx (EF100 driver writer's guide, once
24553 * written) for details of each type.
24554 */
24555#define MC_CMD_GET_DESC_ADDR_INFO_OUT_MAPPING_TYPE_OFST 0
24556#define MC_CMD_GET_DESC_ADDR_INFO_OUT_MAPPING_TYPE_LEN 4
24557/* enum: TRGT_ADDR = DESC_ADDR */
24558#define MC_CMD_GET_DESC_ADDR_INFO_OUT_MAPPING_FLAT 0x0
24559/* enum: DESC_ADDR has one or more regions that map into TRGT_ADDR. The base
24560 * TRGT_ADDR for each region is programmable via MCDI.
24561 */
24562#define MC_CMD_GET_DESC_ADDR_INFO_OUT_MAPPING_REGIONED 0x1
24563
24564
24565/***********************************/
24566/* MC_CMD_GET_DESC_ADDR_REGIONS
24567 * Returns a list of the DESC_ADDR regions for the calling function's address space. Only valid if that function's address space has the REGIONED mapping from DESC_ADDR to TRGT_ADDR.
24568 */
24569#define MC_CMD_GET_DESC_ADDR_REGIONS 0x1b8
24570#undef MC_CMD_0x1b8_PRIVILEGE_CTG
24571
24572#define MC_CMD_0x1b8_PRIVILEGE_CTG SRIOV_CTG_GENERAL
24573
24574/* MC_CMD_GET_DESC_ADDR_REGIONS_IN msgrequest */
24575#define MC_CMD_GET_DESC_ADDR_REGIONS_IN_LEN 0
24576
24577/* MC_CMD_GET_DESC_ADDR_REGIONS_OUT msgresponse */
24578#define MC_CMD_GET_DESC_ADDR_REGIONS_OUT_LENMIN 32
24579#define MC_CMD_GET_DESC_ADDR_REGIONS_OUT_LENMAX 224
24580#define MC_CMD_GET_DESC_ADDR_REGIONS_OUT_LENMAX_MCDI2 992
24581#define MC_CMD_GET_DESC_ADDR_REGIONS_OUT_LEN(num) (0+32*(num))
24582#define MC_CMD_GET_DESC_ADDR_REGIONS_OUT_REGIONS_NUM(len) (((len)-0)/32)
24583/* An array of DESC_ADDR_REGION strutures. The number of entries in the array
24584 * indicates the number of available regions.
24585 */
24586#define MC_CMD_GET_DESC_ADDR_REGIONS_OUT_REGIONS_OFST 0
24587#define MC_CMD_GET_DESC_ADDR_REGIONS_OUT_REGIONS_LEN 32
24588#define MC_CMD_GET_DESC_ADDR_REGIONS_OUT_REGIONS_MINNUM 1
24589#define MC_CMD_GET_DESC_ADDR_REGIONS_OUT_REGIONS_MAXNUM 7
24590#define MC_CMD_GET_DESC_ADDR_REGIONS_OUT_REGIONS_MAXNUM_MCDI2 31
24591
24592
24593/***********************************/
24594/* MC_CMD_SET_DESC_ADDR_REGIONS
24595 * Set the base TRGT_ADDR for a set of DESC_ADDR regions for the calling function's address space. Only valid if that function's address space had the REGIONED mapping from DESC_ADDR to TRGT_ADDR.
24596 */
24597#define MC_CMD_SET_DESC_ADDR_REGIONS 0x1b9
24598#undef MC_CMD_0x1b9_PRIVILEGE_CTG
24599
24600#define MC_CMD_0x1b9_PRIVILEGE_CTG SRIOV_CTG_GENERAL
24601
24602/* MC_CMD_SET_DESC_ADDR_REGIONS_IN msgrequest */
24603#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_LENMIN 16
24604#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_LENMAX 248
24605#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_LENMAX_MCDI2 1016
24606#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_LEN(num) (8+8*(num))
24607#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_NUM(len) (((len)-8)/8)
24608/* A bitmask indicating which regions should have their base TRGT_ADDR updated.
24609 * To update the base TRGR_ADDR for a DESC_ADDR region, the corresponding bit
24610 * should be set to 1.
24611 */
24612#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_SET_REGION_MASK_OFST 0
24613#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_SET_REGION_MASK_LEN 4
24614/* Reserved field; must be set to zero. */
24615#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_RSVD_OFST 4
24616#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_RSVD_LEN 4
24617/* An array of values used to updated the base TRGT_ADDR for DESC_ADDR regions.
24618 * Array indices corresponding to region numbers (i.e. the array is sparse, and
24619 * included entries for regions even if the corresponding SET_REGION_MASK bit
24620 * is zero).
24621 */
24622#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_OFST 8
24623#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_LEN 8
24624#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_LO_OFST 8
24625#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_LO_LEN 4
24626#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_LO_LBN 64
24627#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_LO_WIDTH 32
24628#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_HI_OFST 12
24629#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_HI_LEN 4
24630#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_HI_LBN 96
24631#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_HI_WIDTH 32
24632#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_MINNUM 1
24633#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_MAXNUM 30
24634#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_MAXNUM_MCDI2 126
24635
24636/* MC_CMD_SET_DESC_ADDR_REGIONS_OUT msgresponse */
24637#define MC_CMD_SET_DESC_ADDR_REGIONS_OUT_LEN 0
24638
24639
24640/***********************************/
24641/* MC_CMD_CLIENT_CMD
24642 * Execute an arbitrary MCDI command on behalf of a different client. The
24643 * consequences of the command (e.g. ownership of any resources created) apply
24644 * to the indicated client rather than the function client which actually sent
24645 * this command. All inherent permission checks are also performed on the
24646 * indicated client. The given client must be a descendant of the requestor.
24647 * The command to be proxied follows immediately afterward in the host buffer
24648 * (or on the UART). Chaining multiple MC_CMD_CLIENT_CMD is unnecessary and not
24649 * supported. New dynamic clients may be created with MC_CMD_CLIENT_ALLOC.
24650 */
24651#define MC_CMD_CLIENT_CMD 0x1ba
24652#undef MC_CMD_0x1ba_PRIVILEGE_CTG
24653
24654#define MC_CMD_0x1ba_PRIVILEGE_CTG SRIOV_CTG_GENERAL
24655
24656/* MC_CMD_CLIENT_CMD_IN msgrequest */
24657#define MC_CMD_CLIENT_CMD_IN_LEN 4
24658/* The client as which to execute the following command. */
24659#define MC_CMD_CLIENT_CMD_IN_CLIENT_ID_OFST 0
24660#define MC_CMD_CLIENT_CMD_IN_CLIENT_ID_LEN 4
24661
24662/* MC_CMD_CLIENT_CMD_OUT msgresponse */
24663#define MC_CMD_CLIENT_CMD_OUT_LEN 0
24664
24665
24666/***********************************/
24667/* MC_CMD_CLIENT_ALLOC
24668 * Create a new client object. Clients are a system for delineating NIC
24669 * resource ownership, such that groups of resources may be torn down as a
24670 * unit. See also MC_CMD_CLIENT_CMD. See XN-200265-TC for background, concepts
24671 * and a glossary. Clients created by this command are known as "dynamic
24672 * clients". The newly-created client is a child of the client which sent this
24673 * command. The caller must have the GRP_ALLOC_CLIENT privilege. The new client
24674 * initially has no permission to do anything; see
24675 * MC_CMD_DEVEL_CLIENT_PRIVILEGE_MODIFY.
24676 */
24677#define MC_CMD_CLIENT_ALLOC 0x1bb
24678#undef MC_CMD_0x1bb_PRIVILEGE_CTG
24679
24680#define MC_CMD_0x1bb_PRIVILEGE_CTG SRIOV_CTG_ALLOC_CLIENT
24681
24682/* MC_CMD_CLIENT_ALLOC_IN msgrequest */
24683#define MC_CMD_CLIENT_ALLOC_IN_LEN 0
24684
24685/* MC_CMD_CLIENT_ALLOC_OUT msgresponse */
24686#define MC_CMD_CLIENT_ALLOC_OUT_LEN 4
24687/* The ID of the new client object which has been created. */
24688#define MC_CMD_CLIENT_ALLOC_OUT_CLIENT_ID_OFST 0
24689#define MC_CMD_CLIENT_ALLOC_OUT_CLIENT_ID_LEN 4
24690
24691
24692/***********************************/
24693/* MC_CMD_CLIENT_FREE
24694 * Destroy and release an existing client object. All resources owned by that
24695 * client (including its child clients, and thus all resources owned by the
24696 * entire family tree) are freed.
24697 */
24698#define MC_CMD_CLIENT_FREE 0x1bc
24699#undef MC_CMD_0x1bc_PRIVILEGE_CTG
24700
24701#define MC_CMD_0x1bc_PRIVILEGE_CTG SRIOV_CTG_GENERAL
24702
24703/* MC_CMD_CLIENT_FREE_IN msgrequest */
24704#define MC_CMD_CLIENT_FREE_IN_LEN 4
24705/* The ID of the client to be freed. This client must be a descendant of the
24706 * requestor. A client cannot free itself.
24707 */
24708#define MC_CMD_CLIENT_FREE_IN_CLIENT_ID_OFST 0
24709#define MC_CMD_CLIENT_FREE_IN_CLIENT_ID_LEN 4
24710
24711/* MC_CMD_CLIENT_FREE_OUT msgresponse */
24712#define MC_CMD_CLIENT_FREE_OUT_LEN 0
24713
24714
24715/***********************************/
24716/* MC_CMD_SET_VI_USER
24717 * Assign partial rights over this VI to another client. VIs have an 'owner'
24718 * and a 'user'. The owner is the client which allocated the VI
24719 * (MC_CMD_ALLOC_VIS) and cannot be changed. The user is the client which has
24720 * permission to create queues and other resources on that VI. Initially
24721 * user==owner, but the user can be changed by this command; the resources thus
24722 * created are then owned by the user-client. Only the VI owner can call this
24723 * command, and the request will fail if there are any outstanding child
24724 * resources (e.g. queues) currently allocated from this VI.
24725 */
24726#define MC_CMD_SET_VI_USER 0x1be
24727#undef MC_CMD_0x1be_PRIVILEGE_CTG
24728
24729#define MC_CMD_0x1be_PRIVILEGE_CTG SRIOV_CTG_GENERAL
24730
24731/* MC_CMD_SET_VI_USER_IN msgrequest */
24732#define MC_CMD_SET_VI_USER_IN_LEN 8
24733/* Function-relative VI number to modify. */
24734#define MC_CMD_SET_VI_USER_IN_INSTANCE_OFST 0
24735#define MC_CMD_SET_VI_USER_IN_INSTANCE_LEN 4
24736/* Client ID to become the new user. This must be a descendant of the owning
24737 * client, the owning client itself, or the special value MC_CMD_CLIENT_ID_SELF
24738 * which is synonymous with the owning client.
24739 */
24740#define MC_CMD_SET_VI_USER_IN_CLIENT_ID_OFST 4
24741#define MC_CMD_SET_VI_USER_IN_CLIENT_ID_LEN 4
24742
24743/* MC_CMD_SET_VI_USER_OUT msgresponse */
24744#define MC_CMD_SET_VI_USER_OUT_LEN 0
24745
24746
24747/***********************************/
24748/* MC_CMD_GET_CLIENT_MAC_ADDRESSES
24749 * A device reports a set of MAC addresses for each client to use, known as the
24750 * "permanent MAC addresses". Those MAC addresses are provided by the client's
24751 * administrator, e.g. via MC_CMD_SET_CLIENT_MAC_ADDRESSES, and are intended as
24752 * a hint to that client which MAC address its administrator would like to use
24753 * to identity itself. This API exists solely to allow communication of MAC
24754 * address from administrator to adminstree, and has no inherent interaction
24755 * with switching within the device. There is no guarantee that a client will
24756 * be able to send traffic with a source MAC address taken from the list of MAC
24757 * address reported, nor is there a guarantee that a client will be able to
24758 * resource traffic with a destination MAC taken from the list of MAC
24759 * addresses. Likewise, there is no guarantee that a client will not be able to
24760 * use a MAC address not present in the list. Restrictions on switching are
24761 * controlled either through the EVB API if operating in EVB mode, or via MAE
24762 * rules if host software is directly managing the MAE. In order to allow
24763 * tenants to use this API whilst a provider is using the EVB API, the MAC
24764 * addresses reported by MC_CMD_GET_CLIENT_MAC_ADDRESSES will be augmented with
24765 * any MAC addresses associated with the vPort assigned to the caller. In order
24766 * to allow tenants to use the EVB API whilst a provider is using this API, if
24767 * a client queries the MAC addresses for a vPort using the host_evb_port_id
24768 * EVB_PORT_ASSIGNED, that list of MAC addresses will be augmented with the MAC
24769 * addresses assigned to the calling client. This query can either be explicit
24770 * (i.e. MC_CMD_VPORT_GET_MAC_ADDRESSES) or implicit (e.g. creation of a
24771 * vAdaptor with a NULL/automatic MAC address). Changing the MAC address on a
24772 * vAdaptor only affects VNIC steering filters; it has no effect on the MAC
24773 * addresses assigned to the vAdaptor's owner. VirtIO clients behave as EVB
24774 * clients. On VirtIO device reset, a vAdaptor is created with an automatic MAC
24775 * address. Querying the VirtIO device's MAC address queries the underlying
24776 * vAdaptor's MAC address. Setting the VirtIO device's MAC address sets the
24777 * underlying vAdaptor's MAC addresses.
24778 */
24779#define MC_CMD_GET_CLIENT_MAC_ADDRESSES 0x1c4
24780#undef MC_CMD_0x1c4_PRIVILEGE_CTG
24781
24782#define MC_CMD_0x1c4_PRIVILEGE_CTG SRIOV_CTG_GENERAL
24783
24784/* MC_CMD_GET_CLIENT_MAC_ADDRESSES_IN msgrequest */
24785#define MC_CMD_GET_CLIENT_MAC_ADDRESSES_IN_LEN 4
24786/* A handle for the client for whom MAC address should be obtained. Use
24787 * CLIENT_HANDLE_SELF to obtain the MAC addresses assigned to the calling
24788 * client.
24789 */
24790#define MC_CMD_GET_CLIENT_MAC_ADDRESSES_IN_CLIENT_HANDLE_OFST 0
24791#define MC_CMD_GET_CLIENT_MAC_ADDRESSES_IN_CLIENT_HANDLE_LEN 4
24792
24793/* MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT msgresponse */
24794#define MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_LENMIN 0
24795#define MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_LENMAX 252
24796#define MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_LENMAX_MCDI2 1020
24797#define MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_LEN(num) (0+6*(num))
24798#define MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_MAC_ADDRS_NUM(len) (((len)-0)/6)
24799/* An array of MAC addresses assigned to the client. */
24800#define MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_MAC_ADDRS_OFST 0
24801#define MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_MAC_ADDRS_LEN 6
24802#define MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_MAC_ADDRS_MINNUM 0
24803#define MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_MAC_ADDRS_MAXNUM 42
24804#define MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_MAC_ADDRS_MAXNUM_MCDI2 170
24805
24806
24807/***********************************/
24808/* MC_CMD_SET_CLIENT_MAC_ADDRESSES
24809 * Set the permanent MAC addresses for a client. The caller must by an
24810 * administrator of the target client. See MC_CMD_GET_CLIENT_MAC_ADDRESSES for
24811 * additional detail.
24812 */
24813#define MC_CMD_SET_CLIENT_MAC_ADDRESSES 0x1c5
24814#undef MC_CMD_0x1c5_PRIVILEGE_CTG
24815
24816#define MC_CMD_0x1c5_PRIVILEGE_CTG SRIOV_CTG_GENERAL
24817
24818/* MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN msgrequest */
24819#define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_LENMIN 4
24820#define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_LENMAX 250
24821#define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_LENMAX_MCDI2 1018
24822#define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_LEN(num) (4+6*(num))
24823#define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_MAC_ADDRS_NUM(len) (((len)-4)/6)
24824/* A handle for the client for whom MAC addresses should be set */
24825#define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_CLIENT_HANDLE_OFST 0
24826#define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_CLIENT_HANDLE_LEN 4
24827/* An array of MAC addresses to assign to the client. */
24828#define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_MAC_ADDRS_OFST 4
24829#define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_MAC_ADDRS_LEN 6
24830#define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_MAC_ADDRS_MINNUM 0
24831#define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_MAC_ADDRS_MAXNUM 41
24832#define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_MAC_ADDRS_MAXNUM_MCDI2 169
24833
24834/* MC_CMD_SET_CLIENT_MAC_ADDRESSES_OUT msgresponse */
24835#define MC_CMD_SET_CLIENT_MAC_ADDRESSES_OUT_LEN 0
24836
24837
24838/***********************************/
24839/* MC_CMD_GET_BOARD_ATTR
24840 * Retrieve physical build-level board attributes as configured at
24841 * manufacturing stage. Fields originate from EEPROM and per-platform constants
24842 * in firmware. Fields are used in development to identify/ differentiate
24843 * boards based on build levels/parameters, and also in manufacturing to cross
24844 * check "what was programmed in manufacturing" is same as "what firmware
24845 * thinks has been programmed" as there are two layers to translation within
24846 * firmware before the attributes reach this MCDI handler. Some parameters are
24847 * retrieved as part of other commands and therefore not replicated here. See
24848 * GET_VERSION_OUT.
24849 */
24850#define MC_CMD_GET_BOARD_ATTR 0x1c6
24851#undef MC_CMD_0x1c6_PRIVILEGE_CTG
24852
24853#define MC_CMD_0x1c6_PRIVILEGE_CTG SRIOV_CTG_GENERAL
24854
24855/* MC_CMD_GET_BOARD_ATTR_IN msgrequest */
24856#define MC_CMD_GET_BOARD_ATTR_IN_LEN 0
24857
24858/* MC_CMD_GET_BOARD_ATTR_OUT msgresponse */
24859#define MC_CMD_GET_BOARD_ATTR_OUT_LEN 16
24860/* Defines board capabilities and validity of attributes returned in this
24861 * response-message.
24862 */
24863#define MC_CMD_GET_BOARD_ATTR_OUT_FLAGS_OFST 0
24864#define MC_CMD_GET_BOARD_ATTR_OUT_FLAGS_LEN 4
24865#define MC_CMD_GET_BOARD_ATTR_OUT_HAS_FAN_OFST 0
24866#define MC_CMD_GET_BOARD_ATTR_OUT_HAS_FAN_LBN 0
24867#define MC_CMD_GET_BOARD_ATTR_OUT_HAS_FAN_WIDTH 1
24868#define MC_CMD_GET_BOARD_ATTR_OUT_HAS_SOC_OFST 0
24869#define MC_CMD_GET_BOARD_ATTR_OUT_HAS_SOC_LBN 1
24870#define MC_CMD_GET_BOARD_ATTR_OUT_HAS_SOC_WIDTH 1
24871#define MC_CMD_GET_BOARD_ATTR_OUT_HAS_AUX_POWER_OFST 0
24872#define MC_CMD_GET_BOARD_ATTR_OUT_HAS_AUX_POWER_LBN 2
24873#define MC_CMD_GET_BOARD_ATTR_OUT_HAS_AUX_POWER_WIDTH 1
24874#define MC_CMD_GET_BOARD_ATTR_OUT_ATTRIBUTES_OFST 4
24875#define MC_CMD_GET_BOARD_ATTR_OUT_ATTRIBUTES_LEN 4
24876#define MC_CMD_GET_BOARD_ATTR_OUT_SOC_EE_OFST 4
24877#define MC_CMD_GET_BOARD_ATTR_OUT_SOC_EE_LBN 0
24878#define MC_CMD_GET_BOARD_ATTR_OUT_SOC_EE_WIDTH 1
24879#define MC_CMD_GET_BOARD_ATTR_OUT_SUC_EE_OFST 4
24880#define MC_CMD_GET_BOARD_ATTR_OUT_SUC_EE_LBN 1
24881#define MC_CMD_GET_BOARD_ATTR_OUT_SUC_EE_WIDTH 1
24882#define MC_CMD_GET_BOARD_ATTR_OUT_FPGA_VOLTAGES_SUPPORTED_OFST 4
24883#define MC_CMD_GET_BOARD_ATTR_OUT_FPGA_VOLTAGES_SUPPORTED_LBN 16
24884#define MC_CMD_GET_BOARD_ATTR_OUT_FPGA_VOLTAGES_SUPPORTED_WIDTH 8
24885/* enum: The FPGA voltage on the adapter can be set to low */
24886#define MC_CMD_FPGA_VOLTAGE_LOW 0x0
24887/* enum: The FPGA voltage on the adapter can be set to regular */
24888#define MC_CMD_FPGA_VOLTAGE_REG 0x1
24889/* enum: The FPGA voltage on the adapter can be set to high */
24890#define MC_CMD_FPGA_VOLTAGE_HIGH 0x2
24891#define MC_CMD_GET_BOARD_ATTR_OUT_CAGE_COUNT_OFST 4
24892#define MC_CMD_GET_BOARD_ATTR_OUT_CAGE_COUNT_LBN 24
24893#define MC_CMD_GET_BOARD_ATTR_OUT_CAGE_COUNT_WIDTH 8
24894/* An array of cage types on the board */
24895#define MC_CMD_GET_BOARD_ATTR_OUT_CAGE_TYPE_OFST 8
24896#define MC_CMD_GET_BOARD_ATTR_OUT_CAGE_TYPE_LEN 1
24897#define MC_CMD_GET_BOARD_ATTR_OUT_CAGE_TYPE_NUM 8
24898/* enum: The cages are not known */
24899#define MC_CMD_GET_BOARD_ATTR_OUT_CAGE_TYPE_UNKNOWN 0x0
24900/* enum: The cages are SFP/SFP+ */
24901#define MC_CMD_GET_BOARD_ATTR_OUT_CAGE_TYPE_SFP 0x1
24902/* enum: The cages are QSFP/QSFP+ */
24903#define MC_CMD_GET_BOARD_ATTR_OUT_CAGE_TYPE_QSFP 0x2
24904
24905
24906/***********************************/
24907/* MC_CMD_GET_SOC_STATE
24908 * Retrieve current state of the System-on-Chip. This command is valid when
24909 * MC_CMD_GET_BOARD_ATTR:HAS_SOC is set.
24910 */
24911#define MC_CMD_GET_SOC_STATE 0x1c7
24912#undef MC_CMD_0x1c7_PRIVILEGE_CTG
24913
24914#define MC_CMD_0x1c7_PRIVILEGE_CTG SRIOV_CTG_GENERAL
24915
24916/* MC_CMD_GET_SOC_STATE_IN msgrequest */
24917#define MC_CMD_GET_SOC_STATE_IN_LEN 0
24918
24919/* MC_CMD_GET_SOC_STATE_OUT msgresponse */
24920#define MC_CMD_GET_SOC_STATE_OUT_LEN 12
24921/* Status flags for the SoC */
24922#define MC_CMD_GET_SOC_STATE_OUT_FLAGS_OFST 0
24923#define MC_CMD_GET_SOC_STATE_OUT_FLAGS_LEN 4
24924#define MC_CMD_GET_SOC_STATE_OUT_SHOULD_THROTTLE_OFST 0
24925#define MC_CMD_GET_SOC_STATE_OUT_SHOULD_THROTTLE_LBN 0
24926#define MC_CMD_GET_SOC_STATE_OUT_SHOULD_THROTTLE_WIDTH 1
24927#define MC_CMD_GET_SOC_STATE_OUT_OS_RECOVERY_REQUIRED_OFST 0
24928#define MC_CMD_GET_SOC_STATE_OUT_OS_RECOVERY_REQUIRED_LBN 1
24929#define MC_CMD_GET_SOC_STATE_OUT_OS_RECOVERY_REQUIRED_WIDTH 1
24930#define MC_CMD_GET_SOC_STATE_OUT_WDT_FIRED_OFST 0
24931#define MC_CMD_GET_SOC_STATE_OUT_WDT_FIRED_LBN 2
24932#define MC_CMD_GET_SOC_STATE_OUT_WDT_FIRED_WIDTH 1
24933/* Status fields for the SoC */
24934#define MC_CMD_GET_SOC_STATE_OUT_ATTRIBUTES_OFST 4
24935#define MC_CMD_GET_SOC_STATE_OUT_ATTRIBUTES_LEN 4
24936#define MC_CMD_GET_SOC_STATE_OUT_RUN_STATE_OFST 4
24937#define MC_CMD_GET_SOC_STATE_OUT_RUN_STATE_LBN 0
24938#define MC_CMD_GET_SOC_STATE_OUT_RUN_STATE_WIDTH 8
24939/* enum: Power on (set by SUC on power up) */
24940#define MC_CMD_GET_SOC_STATE_OUT_SOC_BOOT 0x0
24941/* enum: Running bootloader */
24942#define MC_CMD_GET_SOC_STATE_OUT_SOC_BOOTLOADER 0x1
24943/* enum: Bootloader has started OS. OS is booting */
24944#define MC_CMD_GET_SOC_STATE_OUT_SOC_OS_START 0x2
24945/* enum: OS is running */
24946#define MC_CMD_GET_SOC_STATE_OUT_SOC_OS_RUNNING 0x3
24947/* enum: Maintenance OS is running */
24948#define MC_CMD_GET_SOC_STATE_OUT_SOC_OS_MAINTENANCE 0x4
24949/* Number of SoC resets since power on */
24950#define MC_CMD_GET_SOC_STATE_OUT_RESET_COUNT_OFST 8
24951#define MC_CMD_GET_SOC_STATE_OUT_RESET_COUNT_LEN 4
24952
24953
24954/***********************************/
24955/* MC_CMD_CHECK_SCHEDULER_CREDITS
24956 * For debugging purposes. For each source and destination node in the hardware
24957 * schedulers, check whether the number of credits is as it should be. This
24958 * should only be used when the NIC is idle, because collection is not atomic
24959 * and because the expected credit counts are only meaningful when no traffic
24960 * is flowing.
24961 */
24962#define MC_CMD_CHECK_SCHEDULER_CREDITS 0x1c8
24963#undef MC_CMD_0x1c8_PRIVILEGE_CTG
24964
24965#define MC_CMD_0x1c8_PRIVILEGE_CTG SRIOV_CTG_ADMIN
24966
24967/* MC_CMD_CHECK_SCHEDULER_CREDITS_IN msgrequest */
24968#define MC_CMD_CHECK_SCHEDULER_CREDITS_IN_LEN 8
24969/* Flags for the request */
24970#define MC_CMD_CHECK_SCHEDULER_CREDITS_IN_FLAGS_OFST 0
24971#define MC_CMD_CHECK_SCHEDULER_CREDITS_IN_FLAGS_LEN 4
24972#define MC_CMD_CHECK_SCHEDULER_CREDITS_IN_REPORT_ALL_OFST 0
24973#define MC_CMD_CHECK_SCHEDULER_CREDITS_IN_REPORT_ALL_LBN 0
24974#define MC_CMD_CHECK_SCHEDULER_CREDITS_IN_REPORT_ALL_WIDTH 1
24975/* If there are too many results to fit into an MCDI response, they're split
24976 * into pages. This field specifies which (0-indexed) page to request. A
24977 * request with PAGE=0 will snapshot the results, and subsequent requests with
24978 * PAGE>0 will return data from the most recent snapshot. The GENERATION field
24979 * in the response allows callers to verify that all responses correspond to
24980 * the same snapshot.
24981 */
24982#define MC_CMD_CHECK_SCHEDULER_CREDITS_IN_PAGE_OFST 4
24983#define MC_CMD_CHECK_SCHEDULER_CREDITS_IN_PAGE_LEN 4
24984
24985/* MC_CMD_CHECK_SCHEDULER_CREDITS_OUT msgresponse */
24986#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_LENMIN 16
24987#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_LENMAX 240
24988#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_LENMAX_MCDI2 1008
24989#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_LEN(num) (16+16*(num))
24990#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_RESULTS_NUM(len) (((len)-16)/16)
24991/* The total number of results (across all pages). */
24992#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_TOTAL_RESULTS_OFST 0
24993#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_TOTAL_RESULTS_LEN 4
24994/* The number of pages that the response is split across. */
24995#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_NUM_PAGES_OFST 4
24996#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_NUM_PAGES_LEN 4
24997/* The number of results in this response. */
24998#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_RESULTS_THIS_PAGE_OFST 8
24999#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_RESULTS_THIS_PAGE_LEN 4
25000/* Result generation count. Incremented any time a request is made with PAGE=0.
25001 */
25002#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_GENERATION_OFST 12
25003#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_GENERATION_LEN 4
25004/* The results, as an array of SCHED_CREDIT_CHECK_RESULT structures. */
25005#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_RESULTS_OFST 16
25006#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_RESULTS_LEN 16
25007#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_RESULTS_MINNUM 0
25008#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_RESULTS_MAXNUM 14
25009#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_RESULTS_MAXNUM_MCDI2 62
25010
25011
25012/***********************************/
25013/* MC_CMD_TXQ_STATS
25014 * Query per-TXQ statistics.
25015 */
25016#define MC_CMD_TXQ_STATS 0x1d5
25017#undef MC_CMD_0x1d5_PRIVILEGE_CTG
25018
25019#define MC_CMD_0x1d5_PRIVILEGE_CTG SRIOV_CTG_GENERAL
25020
25021/* MC_CMD_TXQ_STATS_IN msgrequest */
25022#define MC_CMD_TXQ_STATS_IN_LEN 8
25023/* Instance of TXQ to retrieve statistics for */
25024#define MC_CMD_TXQ_STATS_IN_INSTANCE_OFST 0
25025#define MC_CMD_TXQ_STATS_IN_INSTANCE_LEN 4
25026/* Flags for the request */
25027#define MC_CMD_TXQ_STATS_IN_FLAGS_OFST 4
25028#define MC_CMD_TXQ_STATS_IN_FLAGS_LEN 4
25029#define MC_CMD_TXQ_STATS_IN_CLEAR_OFST 4
25030#define MC_CMD_TXQ_STATS_IN_CLEAR_LBN 0
25031#define MC_CMD_TXQ_STATS_IN_CLEAR_WIDTH 1
25032
25033/* MC_CMD_TXQ_STATS_OUT msgresponse */
25034#define MC_CMD_TXQ_STATS_OUT_LENMIN 0
25035#define MC_CMD_TXQ_STATS_OUT_LENMAX 248
25036#define MC_CMD_TXQ_STATS_OUT_LENMAX_MCDI2 1016
25037#define MC_CMD_TXQ_STATS_OUT_LEN(num) (0+8*(num))
25038#define MC_CMD_TXQ_STATS_OUT_STATISTICS_NUM(len) (((len)-0)/8)
25039#define MC_CMD_TXQ_STATS_OUT_STATISTICS_OFST 0
25040#define MC_CMD_TXQ_STATS_OUT_STATISTICS_LEN 8
25041#define MC_CMD_TXQ_STATS_OUT_STATISTICS_LO_OFST 0
25042#define MC_CMD_TXQ_STATS_OUT_STATISTICS_LO_LEN 4
25043#define MC_CMD_TXQ_STATS_OUT_STATISTICS_LO_LBN 0
25044#define MC_CMD_TXQ_STATS_OUT_STATISTICS_LO_WIDTH 32
25045#define MC_CMD_TXQ_STATS_OUT_STATISTICS_HI_OFST 4
25046#define MC_CMD_TXQ_STATS_OUT_STATISTICS_HI_LEN 4
25047#define MC_CMD_TXQ_STATS_OUT_STATISTICS_HI_LBN 32
25048#define MC_CMD_TXQ_STATS_OUT_STATISTICS_HI_WIDTH 32
25049#define MC_CMD_TXQ_STATS_OUT_STATISTICS_MINNUM 0
25050#define MC_CMD_TXQ_STATS_OUT_STATISTICS_MAXNUM 31
25051#define MC_CMD_TXQ_STATS_OUT_STATISTICS_MAXNUM_MCDI2 127
25052#define MC_CMD_TXQ_STATS_CTPIO_MAX_FILL 0x0 /* enum */
25053
25054/* FUNCTION_PERSONALITY structuredef: The meanings of the personalities are
25055 * defined in SF-120734-TC with more information in SF-122717-TC.
25056 */
25057#define FUNCTION_PERSONALITY_LEN 4
25058#define FUNCTION_PERSONALITY_ID_OFST 0
25059#define FUNCTION_PERSONALITY_ID_LEN 4
25060/* enum: Function has no assigned personality */
25061#define FUNCTION_PERSONALITY_NULL 0x0
25062/* enum: Function has an EF100-style function control window and VI windows
25063 * with both EF100 and vDPA doorbells.
25064 */
25065#define FUNCTION_PERSONALITY_EF100 0x1
25066/* enum: Function has virtio net device configuration registers and doorbells
25067 * for virtio queue pairs.
25068 */
25069#define FUNCTION_PERSONALITY_VIRTIO_NET 0x2
25070/* enum: Function has virtio block device configuration registers and a
25071 * doorbell for a single virtqueue.
25072 */
25073#define FUNCTION_PERSONALITY_VIRTIO_BLK 0x3
25074/* enum: Function is a Xilinx acceleration device - management function */
25075#define FUNCTION_PERSONALITY_ACCEL_MGMT 0x4
25076/* enum: Function is a Xilinx acceleration device - user function */
25077#define FUNCTION_PERSONALITY_ACCEL_USR 0x5
25078#define FUNCTION_PERSONALITY_ID_LBN 0
25079#define FUNCTION_PERSONALITY_ID_WIDTH 32
25080
25081
25082/***********************************/
25083/* MC_CMD_VIRTIO_GET_FEATURES
25084 * Get a list of the virtio features supported by the device.
25085 */
25086#define MC_CMD_VIRTIO_GET_FEATURES 0x168
25087#undef MC_CMD_0x168_PRIVILEGE_CTG
25088
25089#define MC_CMD_0x168_PRIVILEGE_CTG SRIOV_CTG_GENERAL
25090
25091/* MC_CMD_VIRTIO_GET_FEATURES_IN msgrequest */
25092#define MC_CMD_VIRTIO_GET_FEATURES_IN_LEN 4
25093/* Type of device to get features for. Matches the device id as defined by the
25094 * virtio spec.
25095 */
25096#define MC_CMD_VIRTIO_GET_FEATURES_IN_DEVICE_ID_OFST 0
25097#define MC_CMD_VIRTIO_GET_FEATURES_IN_DEVICE_ID_LEN 4
25098/* enum: Reserved. Do not use. */
25099#define MC_CMD_VIRTIO_GET_FEATURES_IN_RESERVED 0x0
25100/* enum: Net device. */
25101#define MC_CMD_VIRTIO_GET_FEATURES_IN_NET 0x1
25102/* enum: Block device. */
25103#define MC_CMD_VIRTIO_GET_FEATURES_IN_BLOCK 0x2
25104
25105/* MC_CMD_VIRTIO_GET_FEATURES_OUT msgresponse */
25106#define MC_CMD_VIRTIO_GET_FEATURES_OUT_LEN 8
25107/* Features supported by the device. The result is a bitfield in the format of
25108 * the feature bits of the specified device type as defined in the virtIO 1.1
25109 * specification ( https://docs.oasis-
25110 * open.org/virtio/virtio/v1.1/csprd01/virtio-v1.1-csprd01.pdf )
25111 */
25112#define MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_OFST 0
25113#define MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_LEN 8
25114#define MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_LO_OFST 0
25115#define MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_LO_LEN 4
25116#define MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_LO_LBN 0
25117#define MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_LO_WIDTH 32
25118#define MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_HI_OFST 4
25119#define MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_HI_LEN 4
25120#define MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_HI_LBN 32
25121#define MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_HI_WIDTH 32
25122
25123
25124/***********************************/
25125/* MC_CMD_VIRTIO_TEST_FEATURES
25126 * Query whether a given set of features is supported. Fails with ENOSUP if the
25127 * driver requests a feature the device doesn't support. Fails with EINVAL if
25128 * the driver fails to request a feature which the device requires.
25129 */
25130#define MC_CMD_VIRTIO_TEST_FEATURES 0x169
25131#undef MC_CMD_0x169_PRIVILEGE_CTG
25132
25133#define MC_CMD_0x169_PRIVILEGE_CTG SRIOV_CTG_GENERAL
25134
25135/* MC_CMD_VIRTIO_TEST_FEATURES_IN msgrequest */
25136#define MC_CMD_VIRTIO_TEST_FEATURES_IN_LEN 16
25137/* Type of device to test features for. Matches the device id as defined by the
25138 * virtio spec.
25139 */
25140#define MC_CMD_VIRTIO_TEST_FEATURES_IN_DEVICE_ID_OFST 0
25141#define MC_CMD_VIRTIO_TEST_FEATURES_IN_DEVICE_ID_LEN 4
25142/* Enum values, see field(s): */
25143/* MC_CMD_VIRTIO_GET_FEATURES/MC_CMD_VIRTIO_GET_FEATURES_IN/DEVICE_ID */
25144#define MC_CMD_VIRTIO_TEST_FEATURES_IN_RESERVED_OFST 4
25145#define MC_CMD_VIRTIO_TEST_FEATURES_IN_RESERVED_LEN 4
25146/* Features requested. Same format as the returned value from
25147 * MC_CMD_VIRTIO_GET_FEATURES.
25148 */
25149#define MC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_OFST 8
25150#define MC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_LEN 8
25151#define MC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_LO_OFST 8
25152#define MC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_LO_LEN 4
25153#define MC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_LO_LBN 64
25154#define MC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_LO_WIDTH 32
25155#define MC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_HI_OFST 12
25156#define MC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_HI_LEN 4
25157#define MC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_HI_LBN 96
25158#define MC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_HI_WIDTH 32
25159
25160/* MC_CMD_VIRTIO_TEST_FEATURES_OUT msgresponse */
25161#define MC_CMD_VIRTIO_TEST_FEATURES_OUT_LEN 0
25162
25163
25164/***********************************/
25165/* MC_CMD_VIRTIO_GET_CAPABILITIES
25166 * Get virtio capabilities supported by the device. Returns general virtio
25167 * capabilities and limitations of the hardware / firmware implementation
25168 * (hardware device as a whole), rather than that of individual configured
25169 * virtio devices. At present, only the absolute maximum number of queues
25170 * allowed on multi-queue devices is returned. Response is expected to be
25171 * extended as necessary in the future.
25172 */
25173#define MC_CMD_VIRTIO_GET_CAPABILITIES 0x1d3
25174#undef MC_CMD_0x1d3_PRIVILEGE_CTG
25175
25176#define MC_CMD_0x1d3_PRIVILEGE_CTG SRIOV_CTG_GENERAL
25177
25178/* MC_CMD_VIRTIO_GET_CAPABILITIES_IN msgrequest */
25179#define MC_CMD_VIRTIO_GET_CAPABILITIES_IN_LEN 4
25180/* Type of device to get capabilities for. Matches the device id as defined by
25181 * the virtio spec.
25182 */
25183#define MC_CMD_VIRTIO_GET_CAPABILITIES_IN_DEVICE_ID_OFST 0
25184#define MC_CMD_VIRTIO_GET_CAPABILITIES_IN_DEVICE_ID_LEN 4
25185/* Enum values, see field(s): */
25186/* MC_CMD_VIRTIO_GET_FEATURES/MC_CMD_VIRTIO_GET_FEATURES_IN/DEVICE_ID */
25187
25188/* MC_CMD_VIRTIO_GET_CAPABILITIES_OUT msgresponse */
25189#define MC_CMD_VIRTIO_GET_CAPABILITIES_OUT_LEN 4
25190/* Maximum number of queues supported for a single device instance */
25191#define MC_CMD_VIRTIO_GET_CAPABILITIES_OUT_MAX_QUEUES_OFST 0
25192#define MC_CMD_VIRTIO_GET_CAPABILITIES_OUT_MAX_QUEUES_LEN 4
25193
25194
25195/***********************************/
25196/* MC_CMD_VIRTIO_INIT_QUEUE
25197 * Create a virtio virtqueue. Fails with EALREADY if the queue already exists.
25198 * Fails with ENOSUP if a feature is requested that isn't supported. Fails with
25199 * EINVAL if a required feature isn't requested, or any other parameter is
25200 * invalid.
25201 */
25202#define MC_CMD_VIRTIO_INIT_QUEUE 0x16a
25203#undef MC_CMD_0x16a_PRIVILEGE_CTG
25204
25205#define MC_CMD_0x16a_PRIVILEGE_CTG SRIOV_CTG_GENERAL
25206
25207/* MC_CMD_VIRTIO_INIT_QUEUE_REQ msgrequest */
25208#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_LEN 68
25209/* Type of virtqueue to create. A network rxq and a txq can exist at the same
25210 * time on a single VI.
25211 */
25212#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_QUEUE_TYPE_OFST 0
25213#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_QUEUE_TYPE_LEN 1
25214/* enum: A network device receive queue */
25215#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_NET_RXQ 0x0
25216/* enum: A network device transmit queue */
25217#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_NET_TXQ 0x1
25218/* enum: A block device request queue */
25219#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_BLOCK 0x2
25220#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_RESERVED_OFST 1
25221#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_RESERVED_LEN 1
25222/* If the calling function is a PF and this field is not VF_NULL, create the
25223 * queue on the specified child VF instead of on the PF.
25224 */
25225#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_TARGET_VF_OFST 2
25226#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_TARGET_VF_LEN 2
25227/* enum: No VF, create queue on the PF. */
25228#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_VF_NULL 0xffff
25229/* Desired instance. This is the function-local index of the associated VI, not
25230 * the virtqueue number as counted by the virtqueue spec.
25231 */
25232#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_INSTANCE_OFST 4
25233#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_INSTANCE_LEN 4
25234/* Queue size, in entries. Must be a power of two. */
25235#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_SIZE_OFST 8
25236#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_SIZE_LEN 4
25237/* Flags */
25238#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_FLAGS_OFST 12
25239#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_FLAGS_LEN 4
25240#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_USE_PASID_OFST 12
25241#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_USE_PASID_LBN 0
25242#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_USE_PASID_WIDTH 1
25243/* Address of the descriptor table in the virtqueue. */
25244#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_OFST 16
25245#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_LEN 8
25246#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_LO_OFST 16
25247#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_LO_LEN 4
25248#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_LO_LBN 128
25249#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_LO_WIDTH 32
25250#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_HI_OFST 20
25251#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_HI_LEN 4
25252#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_HI_LBN 160
25253#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_HI_WIDTH 32
25254/* Address of the available ring in the virtqueue. */
25255#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_OFST 24
25256#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_LEN 8
25257#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_LO_OFST 24
25258#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_LO_LEN 4
25259#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_LO_LBN 192
25260#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_LO_WIDTH 32
25261#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_HI_OFST 28
25262#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_HI_LEN 4
25263#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_HI_LBN 224
25264#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_HI_WIDTH 32
25265/* Address of the used ring in the virtqueue. */
25266#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_OFST 32
25267#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_LEN 8
25268#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_LO_OFST 32
25269#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_LO_LEN 4
25270#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_LO_LBN 256
25271#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_LO_WIDTH 32
25272#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_HI_OFST 36
25273#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_HI_LEN 4
25274#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_HI_LBN 288
25275#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_HI_WIDTH 32
25276/* PASID to use on PCIe transactions involving this queue. Ignored if the
25277 * USE_PASID flag is not set.
25278 */
25279#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_PASID_OFST 40
25280#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_PASID_LEN 4
25281/* Which MSIX vector to use for this virtqueue, or NO_VECTOR if MSIX should not
25282 * be used.
25283 */
25284#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_MSIX_VECTOR_OFST 44
25285#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_MSIX_VECTOR_LEN 2
25286/* enum: Do not enable interrupts for this virtqueue */
25287#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_NO_VECTOR 0xffff
25288#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_RESERVED2_OFST 46
25289#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_RESERVED2_LEN 2
25290/* Virtio features to apply to this queue. Same format as the in the virtio
25291 * spec and in the return from MC_CMD_VIRTIO_GET_FEATURES. Must be a subset of
25292 * the features returned from MC_CMD_VIRTIO_GET_FEATURES. Features are per-
25293 * queue because with vDPA multiple queues on the same function can be passed
25294 * through to different virtual hosts as independent devices.
25295 */
25296#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_OFST 48
25297#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_LEN 8
25298#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_LO_OFST 48
25299#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_LO_LEN 4
25300#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_LO_LBN 384
25301#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_LO_WIDTH 32
25302#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_HI_OFST 52
25303#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_HI_LEN 4
25304#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_HI_LBN 416
25305#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_HI_WIDTH 32
25306/* Enum values, see field(s): */
25307/* MC_CMD_VIRTIO_GET_FEATURES/MC_CMD_VIRTIO_GET_FEATURES_OUT/FEATURES */
25308/* The initial available index for this virtqueue. If this queue is being
25309 * created to be migrated into, this should be the FINAL_AVAIL_IDX value
25310 * returned by MC_CMD_VIRTIO_FINI_QUEUE of the queue being migrated from (or
25311 * equivalent if the original queue was on a thirdparty device). Otherwise, it
25312 * should be zero.
25313 */
25314#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_INITIAL_AVAIL_IDX_OFST 56
25315#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_INITIAL_AVAIL_IDX_LEN 4
25316/* Alias of INITIAL_AVAIL_IDX, kept for compatibility. */
25317#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_INITIAL_PIDX_OFST 56
25318#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_INITIAL_PIDX_LEN 4
25319/* The initial used index for this virtqueue. If this queue is being created to
25320 * be migrated into, this should be the FINAL_USED_IDX value returned by
25321 * MC_CMD_VIRTIO_FINI_QUEUE of the queue being migrated from (or equivalent if
25322 * the original queue was on a thirdparty device). Otherwise, it should be
25323 * zero.
25324 */
25325#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_INITIAL_USED_IDX_OFST 60
25326#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_INITIAL_USED_IDX_LEN 4
25327/* Alias of INITIAL_USED_IDX, kept for compatibility. */
25328#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_INITIAL_CIDX_OFST 60
25329#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_INITIAL_CIDX_LEN 4
25330/* A MAE_MPORT_SELECTOR defining which mport this queue should be associated
25331 * with. Use MAE_MPORT_SELECTOR_ASSIGNED to request the default mport for the
25332 * function this queue is being created on.
25333 */
25334#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_MPORT_SELECTOR_OFST 64
25335#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_MPORT_SELECTOR_LEN 4
25336
25337/* MC_CMD_VIRTIO_INIT_QUEUE_RESP msgresponse */
25338#define MC_CMD_VIRTIO_INIT_QUEUE_RESP_LEN 0
25339
25340
25341/***********************************/
25342/* MC_CMD_VIRTIO_FINI_QUEUE
25343 * Destroy a virtio virtqueue
25344 */
25345#define MC_CMD_VIRTIO_FINI_QUEUE 0x16b
25346#undef MC_CMD_0x16b_PRIVILEGE_CTG
25347
25348#define MC_CMD_0x16b_PRIVILEGE_CTG SRIOV_CTG_GENERAL
25349
25350/* MC_CMD_VIRTIO_FINI_QUEUE_REQ msgrequest */
25351#define MC_CMD_VIRTIO_FINI_QUEUE_REQ_LEN 8
25352/* Type of virtqueue to destroy. */
25353#define MC_CMD_VIRTIO_FINI_QUEUE_REQ_QUEUE_TYPE_OFST 0
25354#define MC_CMD_VIRTIO_FINI_QUEUE_REQ_QUEUE_TYPE_LEN 1
25355/* Enum values, see field(s): */
25356/* MC_CMD_VIRTIO_INIT_QUEUE/MC_CMD_VIRTIO_INIT_QUEUE_REQ/QUEUE_TYPE */
25357#define MC_CMD_VIRTIO_FINI_QUEUE_REQ_RESERVED_OFST 1
25358#define MC_CMD_VIRTIO_FINI_QUEUE_REQ_RESERVED_LEN 1
25359/* If the calling function is a PF and this field is not VF_NULL, destroy the
25360 * queue on the specified child VF instead of on the PF.
25361 */
25362#define MC_CMD_VIRTIO_FINI_QUEUE_REQ_TARGET_VF_OFST 2
25363#define MC_CMD_VIRTIO_FINI_QUEUE_REQ_TARGET_VF_LEN 2
25364/* enum: No VF, destroy the queue on the PF. */
25365#define MC_CMD_VIRTIO_FINI_QUEUE_REQ_VF_NULL 0xffff
25366/* Instance to destroy */
25367#define MC_CMD_VIRTIO_FINI_QUEUE_REQ_INSTANCE_OFST 4
25368#define MC_CMD_VIRTIO_FINI_QUEUE_REQ_INSTANCE_LEN 4
25369
25370/* MC_CMD_VIRTIO_FINI_QUEUE_RESP msgresponse */
25371#define MC_CMD_VIRTIO_FINI_QUEUE_RESP_LEN 8
25372/* The available index of the virtqueue when the queue was stopped. */
25373#define MC_CMD_VIRTIO_FINI_QUEUE_RESP_FINAL_AVAIL_IDX_OFST 0
25374#define MC_CMD_VIRTIO_FINI_QUEUE_RESP_FINAL_AVAIL_IDX_LEN 4
25375/* Alias of FINAL_AVAIL_IDX, kept for compatibility. */
25376#define MC_CMD_VIRTIO_FINI_QUEUE_RESP_FINAL_PIDX_OFST 0
25377#define MC_CMD_VIRTIO_FINI_QUEUE_RESP_FINAL_PIDX_LEN 4
25378/* The used index of the virtqueue when the queue was stopped. */
25379#define MC_CMD_VIRTIO_FINI_QUEUE_RESP_FINAL_USED_IDX_OFST 4
25380#define MC_CMD_VIRTIO_FINI_QUEUE_RESP_FINAL_USED_IDX_LEN 4
25381/* Alias of FINAL_USED_IDX, kept for compatibility. */
25382#define MC_CMD_VIRTIO_FINI_QUEUE_RESP_FINAL_CIDX_OFST 4
25383#define MC_CMD_VIRTIO_FINI_QUEUE_RESP_FINAL_CIDX_LEN 4
25384
25385
25386/***********************************/
25387/* MC_CMD_VIRTIO_GET_DOORBELL_OFFSET
25388 * Get the offset in the BAR of the doorbells for a VI. Doesn't require the
25389 * queue(s) to be allocated.
25390 */
25391#define MC_CMD_VIRTIO_GET_DOORBELL_OFFSET 0x16c
25392#undef MC_CMD_0x16c_PRIVILEGE_CTG
25393
25394#define MC_CMD_0x16c_PRIVILEGE_CTG SRIOV_CTG_GENERAL
25395
25396/* MC_CMD_VIRTIO_GET_DOORBELL_OFFSET_REQ msgrequest */
25397#define MC_CMD_VIRTIO_GET_DOORBELL_OFFSET_REQ_LEN 8
25398/* Type of device to get information for. Matches the device id as defined by
25399 * the virtio spec.
25400 */
25401#define MC_CMD_VIRTIO_GET_DOORBELL_OFFSET_REQ_DEVICE_ID_OFST 0
25402#define MC_CMD_VIRTIO_GET_DOORBELL_OFFSET_REQ_DEVICE_ID_LEN 1
25403/* Enum values, see field(s): */
25404/* MC_CMD_VIRTIO_GET_FEATURES/MC_CMD_VIRTIO_GET_FEATURES_IN/DEVICE_ID */
25405#define MC_CMD_VIRTIO_GET_DOORBELL_OFFSET_REQ_RESERVED_OFST 1
25406#define MC_CMD_VIRTIO_GET_DOORBELL_OFFSET_REQ_RESERVED_LEN 1
25407/* If the calling function is a PF and this field is not VF_NULL, query the VI
25408 * on the specified child VF instead of on the PF.
25409 */
25410#define MC_CMD_VIRTIO_GET_DOORBELL_OFFSET_REQ_TARGET_VF_OFST 2
25411#define MC_CMD_VIRTIO_GET_DOORBELL_OFFSET_REQ_TARGET_VF_LEN 2
25412/* enum: No VF, query the PF. */
25413#define MC_CMD_VIRTIO_GET_DOORBELL_OFFSET_REQ_VF_NULL 0xffff
25414/* VI instance to query */
25415#define MC_CMD_VIRTIO_GET_DOORBELL_OFFSET_REQ_INSTANCE_OFST 4
25416#define MC_CMD_VIRTIO_GET_DOORBELL_OFFSET_REQ_INSTANCE_LEN 4
25417
25418/* MC_CMD_VIRTIO_GET_NET_DOORBELL_OFFSET_RESP msgresponse */
25419#define MC_CMD_VIRTIO_GET_NET_DOORBELL_OFFSET_RESP_LEN 8
25420/* Offset of RX doorbell in BAR */
25421#define MC_CMD_VIRTIO_GET_NET_DOORBELL_OFFSET_RESP_RX_DBL_OFFSET_OFST 0
25422#define MC_CMD_VIRTIO_GET_NET_DOORBELL_OFFSET_RESP_RX_DBL_OFFSET_LEN 4
25423/* Offset of TX doorbell in BAR */
25424#define MC_CMD_VIRTIO_GET_NET_DOORBELL_OFFSET_RESP_TX_DBL_OFFSET_OFST 4
25425#define MC_CMD_VIRTIO_GET_NET_DOORBELL_OFFSET_RESP_TX_DBL_OFFSET_LEN 4
25426
25427/* MC_CMD_VIRTIO_GET_BLOCK_DOORBELL_OFFSET_RESP msgresponse */
25428#define MC_CMD_VIRTIO_GET_BLOCK_DOORBELL_OFFSET_RESP_LEN 4
25429/* Offset of request doorbell in BAR */
25430#define MC_CMD_VIRTIO_GET_BLOCK_DOORBELL_OFFSET_RESP_DBL_OFFSET_OFST 0
25431#define MC_CMD_VIRTIO_GET_BLOCK_DOORBELL_OFFSET_RESP_DBL_OFFSET_LEN 4
25432
25433/* PCIE_FUNCTION structuredef: Structure representing a PCIe function ID
25434 * (interface/PF/VF tuple)
25435 */
25436#define PCIE_FUNCTION_LEN 8
25437/* PCIe PF function number */
25438#define PCIE_FUNCTION_PF_OFST 0
25439#define PCIE_FUNCTION_PF_LEN 2
25440/* enum: Wildcard value representing any available function (e.g in resource
25441 * allocation requests)
25442 */
25443#define PCIE_FUNCTION_PF_ANY 0xfffe
25444/* enum: Value representing invalid (null) function */
25445#define PCIE_FUNCTION_PF_NULL 0xffff
25446#define PCIE_FUNCTION_PF_LBN 0
25447#define PCIE_FUNCTION_PF_WIDTH 16
25448/* PCIe VF Function number (PF relative) */
25449#define PCIE_FUNCTION_VF_OFST 2
25450#define PCIE_FUNCTION_VF_LEN 2
25451/* enum: Wildcard value representing any available function (e.g in resource
25452 * allocation requests)
25453 */
25454#define PCIE_FUNCTION_VF_ANY 0xfffe
25455/* enum: Function is a PF (when PF != PF_NULL) or invalid function (when PF ==
25456 * PF_NULL)
25457 */
25458#define PCIE_FUNCTION_VF_NULL 0xffff
25459#define PCIE_FUNCTION_VF_LBN 16
25460#define PCIE_FUNCTION_VF_WIDTH 16
25461/* PCIe interface of the function. Values should be taken from the
25462 * PCIE_INTERFACE enum
25463 */
25464#define PCIE_FUNCTION_INTF_OFST 4
25465#define PCIE_FUNCTION_INTF_LEN 4
25466/* enum: Host PCIe interface. (Alias for HOST_PRIMARY, provided for backwards
25467 * compatibility)
25468 */
25469#define PCIE_FUNCTION_INTF_HOST 0x0
25470/* enum: Application Processor interface (alias for NIC_EMBEDDED, provided for
25471 * backwards compatibility)
25472 */
25473#define PCIE_FUNCTION_INTF_AP 0x1
25474#define PCIE_FUNCTION_INTF_LBN 32
25475#define PCIE_FUNCTION_INTF_WIDTH 32
25476
25477/* QUEUE_ID structuredef: Structure representing an absolute queue identifier
25478 * (absolute VI number + VI relative queue number). On Keystone, a VI can
25479 * contain multiple queues (at present, up to 2), each with separate controls
25480 * for direction. This structure is required to uniquely identify the absolute
25481 * source queue for descriptor proxy functions.
25482 */
25483#define QUEUE_ID_LEN 4
25484/* Absolute VI number */
25485#define QUEUE_ID_ABS_VI_OFST 0
25486#define QUEUE_ID_ABS_VI_LEN 2
25487#define QUEUE_ID_ABS_VI_LBN 0
25488#define QUEUE_ID_ABS_VI_WIDTH 16
25489/* Relative queue number within the VI */
25490#define QUEUE_ID_REL_QUEUE_LBN 16
25491#define QUEUE_ID_REL_QUEUE_WIDTH 1
25492#define QUEUE_ID_RESERVED_LBN 17
25493#define QUEUE_ID_RESERVED_WIDTH 15
25494
25495
25496/***********************************/
25497/* MC_CMD_DESC_PROXY_FUNC_CREATE
25498 * Descriptor proxy functions are abstract devices that forward all request
25499 * submitted to the host PCIe function (descriptors submitted to Virtio or
25500 * EF100 queues) to be handled on another function (most commonly on the
25501 * embedded Application Processor), via EF100 descriptor proxy, memory-to-
25502 * memory and descriptor-to-completion mechanisms. Primary user is Virtio-blk
25503 * subsystem, see SF-122927-TC. This function allocates a new descriptor proxy
25504 * function on the host and assigns a user-defined label. The actual function
25505 * configuration is not persisted until the caller configures it with
25506 * MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN and commits with
25507 * MC_CMD_DESC_PROXY_FUNC_COMMIT_IN.
25508 */
25509#define MC_CMD_DESC_PROXY_FUNC_CREATE 0x172
25510#undef MC_CMD_0x172_PRIVILEGE_CTG
25511
25512#define MC_CMD_0x172_PRIVILEGE_CTG SRIOV_CTG_ADMIN
25513
25514/* MC_CMD_DESC_PROXY_FUNC_CREATE_IN msgrequest */
25515#define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_LEN 52
25516/* PCIe Function ID to allocate (as struct PCIE_FUNCTION). Set to
25517 * {PF_ANY,VF_ANY,interface} for "any available function" Set to
25518 * {PF_ANY,VF_NULL,interface} for "any available PF"
25519 */
25520#define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_OFST 0
25521#define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_LEN 8
25522#define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_LO_OFST 0
25523#define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_LO_LEN 4
25524#define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_LO_LBN 0
25525#define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_LO_WIDTH 32
25526#define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_HI_OFST 4
25527#define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_HI_LEN 4
25528#define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_HI_LBN 32
25529#define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_HI_WIDTH 32
25530#define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_PF_OFST 0
25531#define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_PF_LEN 2
25532#define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_VF_OFST 2
25533#define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_VF_LEN 2
25534#define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_INTF_OFST 4
25535#define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_INTF_LEN 4
25536/* The personality to set. The meanings of the personalities are defined in
25537 * SF-120734-TC with more information in SF-122717-TC. At present, we only
25538 * support proxying for VIRTIO_BLK
25539 */
25540#define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_PERSONALITY_OFST 8
25541#define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_PERSONALITY_LEN 4
25542/* Enum values, see field(s): */
25543/* FUNCTION_PERSONALITY/ID */
25544/* User-defined label (zero-terminated ASCII string) to uniquely identify the
25545 * function
25546 */
25547#define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_LABEL_OFST 12
25548#define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_LABEL_LEN 40
25549
25550/* MC_CMD_DESC_PROXY_FUNC_CREATE_OUT msgresponse */
25551#define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_LEN 12
25552/* Handle to the descriptor proxy function */
25553#define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_HANDLE_OFST 0
25554#define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_HANDLE_LEN 4
25555/* Allocated function ID (as struct PCIE_FUNCTION) */
25556#define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_OFST 4
25557#define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_LEN 8
25558#define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_LO_OFST 4
25559#define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_LO_LEN 4
25560#define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_LO_LBN 32
25561#define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_LO_WIDTH 32
25562#define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_HI_OFST 8
25563#define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_HI_LEN 4
25564#define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_HI_LBN 64
25565#define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_HI_WIDTH 32
25566#define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_PF_OFST 4
25567#define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_PF_LEN 2
25568#define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_VF_OFST 6
25569#define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_VF_LEN 2
25570#define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_INTF_OFST 8
25571#define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_INTF_LEN 4
25572
25573
25574/***********************************/
25575/* MC_CMD_DESC_PROXY_FUNC_DESTROY
25576 * Remove an existing descriptor proxy function. Underlying function
25577 * personality and configuration reverts back to factory default. Function
25578 * configuration is committed immediately to specified store and any function
25579 * ownership is released.
25580 */
25581#define MC_CMD_DESC_PROXY_FUNC_DESTROY 0x173
25582#undef MC_CMD_0x173_PRIVILEGE_CTG
25583
25584#define MC_CMD_0x173_PRIVILEGE_CTG SRIOV_CTG_ADMIN
25585
25586/* MC_CMD_DESC_PROXY_FUNC_DESTROY_IN msgrequest */
25587#define MC_CMD_DESC_PROXY_FUNC_DESTROY_IN_LEN 44
25588/* User-defined label (zero-terminated ASCII string) to uniquely identify the
25589 * function
25590 */
25591#define MC_CMD_DESC_PROXY_FUNC_DESTROY_IN_LABEL_OFST 0
25592#define MC_CMD_DESC_PROXY_FUNC_DESTROY_IN_LABEL_LEN 40
25593/* Store from which to remove function configuration */
25594#define MC_CMD_DESC_PROXY_FUNC_DESTROY_IN_STORE_OFST 40
25595#define MC_CMD_DESC_PROXY_FUNC_DESTROY_IN_STORE_LEN 4
25596/* Enum values, see field(s): */
25597/* MC_CMD_DESC_PROXY_FUNC_COMMIT/MC_CMD_DESC_PROXY_FUNC_COMMIT_IN/STORE */
25598
25599/* MC_CMD_DESC_PROXY_FUNC_DESTROY_OUT msgresponse */
25600#define MC_CMD_DESC_PROXY_FUNC_DESTROY_OUT_LEN 0
25601
25602/* VIRTIO_BLK_CONFIG structuredef: Virtio block device configuration. See
25603 * Virtio specification v1.1, Sections 5.2.3 and 6 for definition of feature
25604 * bits. See Virtio specification v1.1, Section 5.2.4 (struct
25605 * virtio_blk_config) for definition of remaining configuration fields
25606 */
25607#define VIRTIO_BLK_CONFIG_LEN 68
25608/* Virtio block device features to advertise, per Virtio 1.1, 5.2.3 and 6 */
25609#define VIRTIO_BLK_CONFIG_FEATURES_OFST 0
25610#define VIRTIO_BLK_CONFIG_FEATURES_LEN 8
25611#define VIRTIO_BLK_CONFIG_FEATURES_LO_OFST 0
25612#define VIRTIO_BLK_CONFIG_FEATURES_LO_LEN 4
25613#define VIRTIO_BLK_CONFIG_FEATURES_LO_LBN 0
25614#define VIRTIO_BLK_CONFIG_FEATURES_LO_WIDTH 32
25615#define VIRTIO_BLK_CONFIG_FEATURES_HI_OFST 4
25616#define VIRTIO_BLK_CONFIG_FEATURES_HI_LEN 4
25617#define VIRTIO_BLK_CONFIG_FEATURES_HI_LBN 32
25618#define VIRTIO_BLK_CONFIG_FEATURES_HI_WIDTH 32
25619#define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_BARRIER_OFST 0
25620#define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_BARRIER_LBN 0
25621#define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_BARRIER_WIDTH 1
25622#define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_SIZE_MAX_OFST 0
25623#define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_SIZE_MAX_LBN 1
25624#define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_SIZE_MAX_WIDTH 1
25625#define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_SEG_MAX_OFST 0
25626#define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_SEG_MAX_LBN 2
25627#define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_SEG_MAX_WIDTH 1
25628#define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_GEOMETRY_OFST 0
25629#define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_GEOMETRY_LBN 4
25630#define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_GEOMETRY_WIDTH 1
25631#define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_RO_OFST 0
25632#define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_RO_LBN 5
25633#define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_RO_WIDTH 1
25634#define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_BLK_SIZE_OFST 0
25635#define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_BLK_SIZE_LBN 6
25636#define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_BLK_SIZE_WIDTH 1
25637#define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_SCSI_OFST 0
25638#define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_SCSI_LBN 7
25639#define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_SCSI_WIDTH 1
25640#define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_FLUSH_OFST 0
25641#define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_FLUSH_LBN 9
25642#define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_FLUSH_WIDTH 1
25643#define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_TOPOLOGY_OFST 0
25644#define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_TOPOLOGY_LBN 10
25645#define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_TOPOLOGY_WIDTH 1
25646#define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_CONFIG_WCE_OFST 0
25647#define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_CONFIG_WCE_LBN 11
25648#define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_CONFIG_WCE_WIDTH 1
25649#define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_MQ_OFST 0
25650#define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_MQ_LBN 12
25651#define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_MQ_WIDTH 1
25652#define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_DISCARD_OFST 0
25653#define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_DISCARD_LBN 13
25654#define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_DISCARD_WIDTH 1
25655#define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_WRITE_ZEROES_OFST 0
25656#define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_WRITE_ZEROES_LBN 14
25657#define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_WRITE_ZEROES_WIDTH 1
25658#define VIRTIO_BLK_CONFIG_VIRTIO_F_RING_INDIRECT_DESC_OFST 0
25659#define VIRTIO_BLK_CONFIG_VIRTIO_F_RING_INDIRECT_DESC_LBN 28
25660#define VIRTIO_BLK_CONFIG_VIRTIO_F_RING_INDIRECT_DESC_WIDTH 1
25661#define VIRTIO_BLK_CONFIG_VIRTIO_F_RING_EVENT_IDX_OFST 0
25662#define VIRTIO_BLK_CONFIG_VIRTIO_F_RING_EVENT_IDX_LBN 29
25663#define VIRTIO_BLK_CONFIG_VIRTIO_F_RING_EVENT_IDX_WIDTH 1
25664#define VIRTIO_BLK_CONFIG_VIRTIO_F_VERSION_1_OFST 0
25665#define VIRTIO_BLK_CONFIG_VIRTIO_F_VERSION_1_LBN 32
25666#define VIRTIO_BLK_CONFIG_VIRTIO_F_VERSION_1_WIDTH 1
25667#define VIRTIO_BLK_CONFIG_VIRTIO_F_ACCESS_PLATFORM_OFST 0
25668#define VIRTIO_BLK_CONFIG_VIRTIO_F_ACCESS_PLATFORM_LBN 33
25669#define VIRTIO_BLK_CONFIG_VIRTIO_F_ACCESS_PLATFORM_WIDTH 1
25670#define VIRTIO_BLK_CONFIG_VIRTIO_F_RING_PACKED_OFST 0
25671#define VIRTIO_BLK_CONFIG_VIRTIO_F_RING_PACKED_LBN 34
25672#define VIRTIO_BLK_CONFIG_VIRTIO_F_RING_PACKED_WIDTH 1
25673#define VIRTIO_BLK_CONFIG_VIRTIO_F_IN_ORDER_OFST 0
25674#define VIRTIO_BLK_CONFIG_VIRTIO_F_IN_ORDER_LBN 35
25675#define VIRTIO_BLK_CONFIG_VIRTIO_F_IN_ORDER_WIDTH 1
25676#define VIRTIO_BLK_CONFIG_VIRTIO_F_ORDER_PLATFORM_OFST 0
25677#define VIRTIO_BLK_CONFIG_VIRTIO_F_ORDER_PLATFORM_LBN 36
25678#define VIRTIO_BLK_CONFIG_VIRTIO_F_ORDER_PLATFORM_WIDTH 1
25679#define VIRTIO_BLK_CONFIG_VIRTIO_F_SR_IOV_OFST 0
25680#define VIRTIO_BLK_CONFIG_VIRTIO_F_SR_IOV_LBN 37
25681#define VIRTIO_BLK_CONFIG_VIRTIO_F_SR_IOV_WIDTH 1
25682#define VIRTIO_BLK_CONFIG_VIRTIO_F_NOTIFICATION_DATA_OFST 0
25683#define VIRTIO_BLK_CONFIG_VIRTIO_F_NOTIFICATION_DATA_LBN 38
25684#define VIRTIO_BLK_CONFIG_VIRTIO_F_NOTIFICATION_DATA_WIDTH 1
25685#define VIRTIO_BLK_CONFIG_FEATURES_LBN 0
25686#define VIRTIO_BLK_CONFIG_FEATURES_WIDTH 64
25687/* The capacity of the device (expressed in 512-byte sectors) */
25688#define VIRTIO_BLK_CONFIG_CAPACITY_OFST 8
25689#define VIRTIO_BLK_CONFIG_CAPACITY_LEN 8
25690#define VIRTIO_BLK_CONFIG_CAPACITY_LO_OFST 8
25691#define VIRTIO_BLK_CONFIG_CAPACITY_LO_LEN 4
25692#define VIRTIO_BLK_CONFIG_CAPACITY_LO_LBN 64
25693#define VIRTIO_BLK_CONFIG_CAPACITY_LO_WIDTH 32
25694#define VIRTIO_BLK_CONFIG_CAPACITY_HI_OFST 12
25695#define VIRTIO_BLK_CONFIG_CAPACITY_HI_LEN 4
25696#define VIRTIO_BLK_CONFIG_CAPACITY_HI_LBN 96
25697#define VIRTIO_BLK_CONFIG_CAPACITY_HI_WIDTH 32
25698#define VIRTIO_BLK_CONFIG_CAPACITY_LBN 64
25699#define VIRTIO_BLK_CONFIG_CAPACITY_WIDTH 64
25700/* Maximum size of any single segment. Only valid when VIRTIO_BLK_F_SIZE_MAX is
25701 * set.
25702 */
25703#define VIRTIO_BLK_CONFIG_SIZE_MAX_OFST 16
25704#define VIRTIO_BLK_CONFIG_SIZE_MAX_LEN 4
25705#define VIRTIO_BLK_CONFIG_SIZE_MAX_LBN 128
25706#define VIRTIO_BLK_CONFIG_SIZE_MAX_WIDTH 32
25707/* Maximum number of segments in a request. Only valid when
25708 * VIRTIO_BLK_F_SEG_MAX is set.
25709 */
25710#define VIRTIO_BLK_CONFIG_SEG_MAX_OFST 20
25711#define VIRTIO_BLK_CONFIG_SEG_MAX_LEN 4
25712#define VIRTIO_BLK_CONFIG_SEG_MAX_LBN 160
25713#define VIRTIO_BLK_CONFIG_SEG_MAX_WIDTH 32
25714/* Disk-style geometry - cylinders. Only valid when VIRTIO_BLK_F_GEOMETRY is
25715 * set.
25716 */
25717#define VIRTIO_BLK_CONFIG_CYLINDERS_OFST 24
25718#define VIRTIO_BLK_CONFIG_CYLINDERS_LEN 2
25719#define VIRTIO_BLK_CONFIG_CYLINDERS_LBN 192
25720#define VIRTIO_BLK_CONFIG_CYLINDERS_WIDTH 16
25721/* Disk-style geometry - heads. Only valid when VIRTIO_BLK_F_GEOMETRY is set.
25722 */
25723#define VIRTIO_BLK_CONFIG_HEADS_OFST 26
25724#define VIRTIO_BLK_CONFIG_HEADS_LEN 1
25725#define VIRTIO_BLK_CONFIG_HEADS_LBN 208
25726#define VIRTIO_BLK_CONFIG_HEADS_WIDTH 8
25727/* Disk-style geometry - sectors. Only valid when VIRTIO_BLK_F_GEOMETRY is set.
25728 */
25729#define VIRTIO_BLK_CONFIG_SECTORS_OFST 27
25730#define VIRTIO_BLK_CONFIG_SECTORS_LEN 1
25731#define VIRTIO_BLK_CONFIG_SECTORS_LBN 216
25732#define VIRTIO_BLK_CONFIG_SECTORS_WIDTH 8
25733/* Block size of disk. Only valid when VIRTIO_BLK_F_BLK_SIZE is set. */
25734#define VIRTIO_BLK_CONFIG_BLK_SIZE_OFST 28
25735#define VIRTIO_BLK_CONFIG_BLK_SIZE_LEN 4
25736#define VIRTIO_BLK_CONFIG_BLK_SIZE_LBN 224
25737#define VIRTIO_BLK_CONFIG_BLK_SIZE_WIDTH 32
25738/* Block topology - number of logical blocks per physical block (log2). Only
25739 * valid when VIRTIO_BLK_F_TOPOLOGY is set.
25740 */
25741#define VIRTIO_BLK_CONFIG_PHYSICAL_BLOCK_EXP_OFST 32
25742#define VIRTIO_BLK_CONFIG_PHYSICAL_BLOCK_EXP_LEN 1
25743#define VIRTIO_BLK_CONFIG_PHYSICAL_BLOCK_EXP_LBN 256
25744#define VIRTIO_BLK_CONFIG_PHYSICAL_BLOCK_EXP_WIDTH 8
25745/* Block topology - offset of first aligned logical block. Only valid when
25746 * VIRTIO_BLK_F_TOPOLOGY is set.
25747 */
25748#define VIRTIO_BLK_CONFIG_ALIGNMENT_OFFSET_OFST 33
25749#define VIRTIO_BLK_CONFIG_ALIGNMENT_OFFSET_LEN 1
25750#define VIRTIO_BLK_CONFIG_ALIGNMENT_OFFSET_LBN 264
25751#define VIRTIO_BLK_CONFIG_ALIGNMENT_OFFSET_WIDTH 8
25752/* Block topology - suggested minimum I/O size in blocks. Only valid when
25753 * VIRTIO_BLK_F_TOPOLOGY is set.
25754 */
25755#define VIRTIO_BLK_CONFIG_MIN_IO_SIZE_OFST 34
25756#define VIRTIO_BLK_CONFIG_MIN_IO_SIZE_LEN 2
25757#define VIRTIO_BLK_CONFIG_MIN_IO_SIZE_LBN 272
25758#define VIRTIO_BLK_CONFIG_MIN_IO_SIZE_WIDTH 16
25759/* Block topology - optimal (suggested maximum) I/O size in blocks. Only valid
25760 * when VIRTIO_BLK_F_TOPOLOGY is set.
25761 */
25762#define VIRTIO_BLK_CONFIG_OPT_IO_SIZE_OFST 36
25763#define VIRTIO_BLK_CONFIG_OPT_IO_SIZE_LEN 4
25764#define VIRTIO_BLK_CONFIG_OPT_IO_SIZE_LBN 288
25765#define VIRTIO_BLK_CONFIG_OPT_IO_SIZE_WIDTH 32
25766/* Unused, set to zero. Note that virtio_blk_config.writeback is volatile and
25767 * not carried in config data.
25768 */
25769#define VIRTIO_BLK_CONFIG_UNUSED0_OFST 40
25770#define VIRTIO_BLK_CONFIG_UNUSED0_LEN 2
25771#define VIRTIO_BLK_CONFIG_UNUSED0_LBN 320
25772#define VIRTIO_BLK_CONFIG_UNUSED0_WIDTH 16
25773/* Number of queues. Only valid if the VIRTIO_BLK_F_MQ feature is negotiated.
25774 */
25775#define VIRTIO_BLK_CONFIG_NUM_QUEUES_OFST 42
25776#define VIRTIO_BLK_CONFIG_NUM_QUEUES_LEN 2
25777#define VIRTIO_BLK_CONFIG_NUM_QUEUES_LBN 336
25778#define VIRTIO_BLK_CONFIG_NUM_QUEUES_WIDTH 16
25779/* Maximum discard sectors size, in 512-byte units. Only valid if
25780 * VIRTIO_BLK_F_DISCARD is set.
25781 */
25782#define VIRTIO_BLK_CONFIG_MAX_DISCARD_SECTORS_OFST 44
25783#define VIRTIO_BLK_CONFIG_MAX_DISCARD_SECTORS_LEN 4
25784#define VIRTIO_BLK_CONFIG_MAX_DISCARD_SECTORS_LBN 352
25785#define VIRTIO_BLK_CONFIG_MAX_DISCARD_SECTORS_WIDTH 32
25786/* Maximum discard segment number. Only valid if VIRTIO_BLK_F_DISCARD is set.
25787 */
25788#define VIRTIO_BLK_CONFIG_MAX_DISCARD_SEG_OFST 48
25789#define VIRTIO_BLK_CONFIG_MAX_DISCARD_SEG_LEN 4
25790#define VIRTIO_BLK_CONFIG_MAX_DISCARD_SEG_LBN 384
25791#define VIRTIO_BLK_CONFIG_MAX_DISCARD_SEG_WIDTH 32
25792/* Discard sector alignment, in 512-byte units. Only valid if
25793 * VIRTIO_BLK_F_DISCARD is set.
25794 */
25795#define VIRTIO_BLK_CONFIG_DISCARD_SECTOR_ALIGNMENT_OFST 52
25796#define VIRTIO_BLK_CONFIG_DISCARD_SECTOR_ALIGNMENT_LEN 4
25797#define VIRTIO_BLK_CONFIG_DISCARD_SECTOR_ALIGNMENT_LBN 416
25798#define VIRTIO_BLK_CONFIG_DISCARD_SECTOR_ALIGNMENT_WIDTH 32
25799/* Maximum write zeroes sectors size, in 512-byte units. Only valid if
25800 * VIRTIO_BLK_F_WRITE_ZEROES is set.
25801 */
25802#define VIRTIO_BLK_CONFIG_MAX_WRITE_ZEROES_SECTORS_OFST 56
25803#define VIRTIO_BLK_CONFIG_MAX_WRITE_ZEROES_SECTORS_LEN 4
25804#define VIRTIO_BLK_CONFIG_MAX_WRITE_ZEROES_SECTORS_LBN 448
25805#define VIRTIO_BLK_CONFIG_MAX_WRITE_ZEROES_SECTORS_WIDTH 32
25806/* Maximum write zeroes segment number. Only valid if VIRTIO_BLK_F_WRITE_ZEROES
25807 * is set.
25808 */
25809#define VIRTIO_BLK_CONFIG_MAX_WRITE_ZEROES_SEG_OFST 60
25810#define VIRTIO_BLK_CONFIG_MAX_WRITE_ZEROES_SEG_LEN 4
25811#define VIRTIO_BLK_CONFIG_MAX_WRITE_ZEROES_SEG_LBN 480
25812#define VIRTIO_BLK_CONFIG_MAX_WRITE_ZEROES_SEG_WIDTH 32
25813/* Write zeroes request can result in deallocating one or more sectors. Only
25814 * valid if VIRTIO_BLK_F_WRITE_ZEROES is set.
25815 */
25816#define VIRTIO_BLK_CONFIG_WRITE_ZEROES_MAY_UNMAP_OFST 64
25817#define VIRTIO_BLK_CONFIG_WRITE_ZEROES_MAY_UNMAP_LEN 1
25818#define VIRTIO_BLK_CONFIG_WRITE_ZEROES_MAY_UNMAP_LBN 512
25819#define VIRTIO_BLK_CONFIG_WRITE_ZEROES_MAY_UNMAP_WIDTH 8
25820/* Unused, set to zero. */
25821#define VIRTIO_BLK_CONFIG_UNUSED1_OFST 65
25822#define VIRTIO_BLK_CONFIG_UNUSED1_LEN 3
25823#define VIRTIO_BLK_CONFIG_UNUSED1_LBN 520
25824#define VIRTIO_BLK_CONFIG_UNUSED1_WIDTH 24
25825
25826
25827/***********************************/
25828/* MC_CMD_DESC_PROXY_FUNC_CONFIG_SET
25829 * Set configuration for an existing descriptor proxy function. Configuration
25830 * data must match function personality. The actual function configuration is
25831 * not persisted until the caller commits with MC_CMD_DESC_PROXY_FUNC_COMMIT_IN
25832 */
25833#define MC_CMD_DESC_PROXY_FUNC_CONFIG_SET 0x174
25834#undef MC_CMD_0x174_PRIVILEGE_CTG
25835
25836#define MC_CMD_0x174_PRIVILEGE_CTG SRIOV_CTG_ADMIN
25837
25838/* MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN msgrequest */
25839#define MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_LENMIN 20
25840#define MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_LENMAX 252
25841#define MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_LENMAX_MCDI2 1020
25842#define MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_LEN(num) (20+1*(num))
25843#define MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_CONFIG_NUM(len) (((len)-20)/1)
25844/* Handle to descriptor proxy function (as returned by
25845 * MC_CMD_DESC_PROXY_FUNC_OPEN)
25846 */
25847#define MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_HANDLE_OFST 0
25848#define MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_HANDLE_LEN 4
25849/* Reserved for future extension, set to zero. */
25850#define MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_RESERVED_OFST 4
25851#define MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_RESERVED_LEN 16
25852/* Configuration data. Format of configuration data is determined implicitly
25853 * from function personality referred to by HANDLE. Currently, only supported
25854 * format is VIRTIO_BLK_CONFIG.
25855 */
25856#define MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_CONFIG_OFST 20
25857#define MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_CONFIG_LEN 1
25858#define MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_CONFIG_MINNUM 0
25859#define MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_CONFIG_MAXNUM 232
25860#define MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_CONFIG_MAXNUM_MCDI2 1000
25861
25862/* MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_OUT msgresponse */
25863#define MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_OUT_LEN 0
25864
25865
25866/***********************************/
25867/* MC_CMD_DESC_PROXY_FUNC_COMMIT
25868 * Commit function configuration to non-volatile or volatile store. Once
25869 * configuration is applied to hardware (which may happen immediately or on
25870 * next function/device reset) a DESC_PROXY_FUNC_CONFIG_SET MCDI event will be
25871 * delivered to callers MCDI event queue.
25872 */
25873#define MC_CMD_DESC_PROXY_FUNC_COMMIT 0x175
25874#undef MC_CMD_0x175_PRIVILEGE_CTG
25875
25876#define MC_CMD_0x175_PRIVILEGE_CTG SRIOV_CTG_ADMIN
25877
25878/* MC_CMD_DESC_PROXY_FUNC_COMMIT_IN msgrequest */
25879#define MC_CMD_DESC_PROXY_FUNC_COMMIT_IN_LEN 8
25880/* Handle to descriptor proxy function (as returned by
25881 * MC_CMD_DESC_PROXY_FUNC_OPEN)
25882 */
25883#define MC_CMD_DESC_PROXY_FUNC_COMMIT_IN_HANDLE_OFST 0
25884#define MC_CMD_DESC_PROXY_FUNC_COMMIT_IN_HANDLE_LEN 4
25885#define MC_CMD_DESC_PROXY_FUNC_COMMIT_IN_STORE_OFST 4
25886#define MC_CMD_DESC_PROXY_FUNC_COMMIT_IN_STORE_LEN 4
25887/* enum: Store into non-volatile (dynamic) config */
25888#define MC_CMD_DESC_PROXY_FUNC_COMMIT_IN_NON_VOLATILE 0x0
25889/* enum: Store into volatile (ephemeral) config */
25890#define MC_CMD_DESC_PROXY_FUNC_COMMIT_IN_VOLATILE 0x1
25891
25892/* MC_CMD_DESC_PROXY_FUNC_COMMIT_OUT msgresponse */
25893#define MC_CMD_DESC_PROXY_FUNC_COMMIT_OUT_LEN 4
25894/* Generation count to be delivered in an event once configuration becomes live
25895 */
25896#define MC_CMD_DESC_PROXY_FUNC_COMMIT_OUT_CONFIG_GENERATION_OFST 0
25897#define MC_CMD_DESC_PROXY_FUNC_COMMIT_OUT_CONFIG_GENERATION_LEN 4
25898
25899
25900/***********************************/
25901/* MC_CMD_DESC_PROXY_FUNC_OPEN
25902 * Retrieve a handle for an existing descriptor proxy function. Returns an
25903 * integer handle, valid until function is deallocated, MC rebooted or power-
25904 * cycle. Returns ENODEV if no function with given label exists.
25905 */
25906#define MC_CMD_DESC_PROXY_FUNC_OPEN 0x176
25907#undef MC_CMD_0x176_PRIVILEGE_CTG
25908
25909#define MC_CMD_0x176_PRIVILEGE_CTG SRIOV_CTG_ADMIN
25910
25911/* MC_CMD_DESC_PROXY_FUNC_OPEN_IN msgrequest */
25912#define MC_CMD_DESC_PROXY_FUNC_OPEN_IN_LEN 40
25913/* User-defined label (zero-terminated ASCII string) to uniquely identify the
25914 * function
25915 */
25916#define MC_CMD_DESC_PROXY_FUNC_OPEN_IN_LABEL_OFST 0
25917#define MC_CMD_DESC_PROXY_FUNC_OPEN_IN_LABEL_LEN 40
25918
25919/* MC_CMD_DESC_PROXY_FUNC_OPEN_OUT msgresponse */
25920#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_LENMIN 40
25921#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_LENMAX 252
25922#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_LENMAX_MCDI2 1020
25923#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_LEN(num) (40+1*(num))
25924#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_CONFIG_NUM(len) (((len)-40)/1)
25925/* Handle to the descriptor proxy function */
25926#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_HANDLE_OFST 0
25927#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_HANDLE_LEN 4
25928/* PCIe Function ID (as struct PCIE_FUNCTION) */
25929#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_OFST 4
25930#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_LEN 8
25931#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_LO_OFST 4
25932#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_LO_LEN 4
25933#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_LO_LBN 32
25934#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_LO_WIDTH 32
25935#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_HI_OFST 8
25936#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_HI_LEN 4
25937#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_HI_LBN 64
25938#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_HI_WIDTH 32
25939#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_PF_OFST 4
25940#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_PF_LEN 2
25941#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_VF_OFST 6
25942#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_VF_LEN 2
25943#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_INTF_OFST 8
25944#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_INTF_LEN 4
25945/* Function personality */
25946#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_PERSONALITY_OFST 12
25947#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_PERSONALITY_LEN 4
25948/* Enum values, see field(s): */
25949/* FUNCTION_PERSONALITY/ID */
25950/* Function configuration state */
25951#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_CONFIG_STATUS_OFST 16
25952#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_CONFIG_STATUS_LEN 4
25953/* enum: Function configuration is visible to the host (live) */
25954#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_LIVE 0x0
25955/* enum: Function configuration is pending reset */
25956#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_PENDING 0x1
25957/* enum: Function configuration is missing (created, but no configuration
25958 * committed)
25959 */
25960#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_UNCONFIGURED 0x2
25961/* Generation count to be delivered in an event once the configuration becomes
25962 * live (if status is "pending")
25963 */
25964#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_CONFIG_GENERATION_OFST 20
25965#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_CONFIG_GENERATION_LEN 4
25966/* Reserved for future extension, set to zero. */
25967#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_RESERVED_OFST 24
25968#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_RESERVED_LEN 16
25969/* Configuration data corresponding to function personality. Currently, only
25970 * supported format is VIRTIO_BLK_CONFIG. Not valid if status is UNCONFIGURED.
25971 */
25972#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_CONFIG_OFST 40
25973#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_CONFIG_LEN 1
25974#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_CONFIG_MINNUM 0
25975#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_CONFIG_MAXNUM 212
25976#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_CONFIG_MAXNUM_MCDI2 980
25977
25978
25979/***********************************/
25980/* MC_CMD_DESC_PROXY_FUNC_CLOSE
25981 * Releases a handle for an open descriptor proxy function. If proxying was
25982 * enabled on the device, the caller is expected to gracefully stop it using
25983 * MC_CMD_DESC_PROXY_FUNC_DISABLE prior to calling this function. Closing an
25984 * active device without disabling proxying will result in forced close, which
25985 * will put the device into a failed state and signal the host driver of the
25986 * error (for virtio, DEVICE_NEEDS_RESET flag would be set on the host side)
25987 */
25988#define MC_CMD_DESC_PROXY_FUNC_CLOSE 0x1a1
25989#undef MC_CMD_0x1a1_PRIVILEGE_CTG
25990
25991#define MC_CMD_0x1a1_PRIVILEGE_CTG SRIOV_CTG_ADMIN
25992
25993/* MC_CMD_DESC_PROXY_FUNC_CLOSE_IN msgrequest */
25994#define MC_CMD_DESC_PROXY_FUNC_CLOSE_IN_LEN 4
25995/* Handle to the descriptor proxy function */
25996#define MC_CMD_DESC_PROXY_FUNC_CLOSE_IN_HANDLE_OFST 0
25997#define MC_CMD_DESC_PROXY_FUNC_CLOSE_IN_HANDLE_LEN 4
25998
25999/* MC_CMD_DESC_PROXY_FUNC_CLOSE_OUT msgresponse */
26000#define MC_CMD_DESC_PROXY_FUNC_CLOSE_OUT_LEN 0
26001
26002/* DESC_PROXY_FUNC_MAP structuredef */
26003#define DESC_PROXY_FUNC_MAP_LEN 52
26004/* PCIe function ID (as struct PCIE_FUNCTION) */
26005#define DESC_PROXY_FUNC_MAP_FUNC_OFST 0
26006#define DESC_PROXY_FUNC_MAP_FUNC_LEN 8
26007#define DESC_PROXY_FUNC_MAP_FUNC_LO_OFST 0
26008#define DESC_PROXY_FUNC_MAP_FUNC_LO_LEN 4
26009#define DESC_PROXY_FUNC_MAP_FUNC_LO_LBN 0
26010#define DESC_PROXY_FUNC_MAP_FUNC_LO_WIDTH 32
26011#define DESC_PROXY_FUNC_MAP_FUNC_HI_OFST 4
26012#define DESC_PROXY_FUNC_MAP_FUNC_HI_LEN 4
26013#define DESC_PROXY_FUNC_MAP_FUNC_HI_LBN 32
26014#define DESC_PROXY_FUNC_MAP_FUNC_HI_WIDTH 32
26015#define DESC_PROXY_FUNC_MAP_FUNC_LBN 0
26016#define DESC_PROXY_FUNC_MAP_FUNC_WIDTH 64
26017#define DESC_PROXY_FUNC_MAP_FUNC_PF_OFST 0
26018#define DESC_PROXY_FUNC_MAP_FUNC_PF_LEN 2
26019#define DESC_PROXY_FUNC_MAP_FUNC_PF_LBN 0
26020#define DESC_PROXY_FUNC_MAP_FUNC_PF_WIDTH 16
26021#define DESC_PROXY_FUNC_MAP_FUNC_VF_OFST 2
26022#define DESC_PROXY_FUNC_MAP_FUNC_VF_LEN 2
26023#define DESC_PROXY_FUNC_MAP_FUNC_VF_LBN 16
26024#define DESC_PROXY_FUNC_MAP_FUNC_VF_WIDTH 16
26025#define DESC_PROXY_FUNC_MAP_FUNC_INTF_OFST 4
26026#define DESC_PROXY_FUNC_MAP_FUNC_INTF_LEN 4
26027#define DESC_PROXY_FUNC_MAP_FUNC_INTF_LBN 32
26028#define DESC_PROXY_FUNC_MAP_FUNC_INTF_WIDTH 32
26029/* Function personality */
26030#define DESC_PROXY_FUNC_MAP_PERSONALITY_OFST 8
26031#define DESC_PROXY_FUNC_MAP_PERSONALITY_LEN 4
26032/* Enum values, see field(s): */
26033/* FUNCTION_PERSONALITY/ID */
26034#define DESC_PROXY_FUNC_MAP_PERSONALITY_LBN 64
26035#define DESC_PROXY_FUNC_MAP_PERSONALITY_WIDTH 32
26036/* User-defined label (zero-terminated ASCII string) to uniquely identify the
26037 * function
26038 */
26039#define DESC_PROXY_FUNC_MAP_LABEL_OFST 12
26040#define DESC_PROXY_FUNC_MAP_LABEL_LEN 40
26041#define DESC_PROXY_FUNC_MAP_LABEL_LBN 96
26042#define DESC_PROXY_FUNC_MAP_LABEL_WIDTH 320
26043
26044
26045/***********************************/
26046/* MC_CMD_DESC_PROXY_FUNC_ENUM
26047 * Enumerate existing descriptor proxy functions
26048 */
26049#define MC_CMD_DESC_PROXY_FUNC_ENUM 0x177
26050#undef MC_CMD_0x177_PRIVILEGE_CTG
26051
26052#define MC_CMD_0x177_PRIVILEGE_CTG SRIOV_CTG_ADMIN
26053
26054/* MC_CMD_DESC_PROXY_FUNC_ENUM_IN msgrequest */
26055#define MC_CMD_DESC_PROXY_FUNC_ENUM_IN_LEN 4
26056/* Starting index, set to 0 on first request. See
26057 * MC_CMD_DESC_PROXY_FUNC_ENUM_OUT/FLAGS.
26058 */
26059#define MC_CMD_DESC_PROXY_FUNC_ENUM_IN_START_IDX_OFST 0
26060#define MC_CMD_DESC_PROXY_FUNC_ENUM_IN_START_IDX_LEN 4
26061
26062/* MC_CMD_DESC_PROXY_FUNC_ENUM_OUT msgresponse */
26063#define MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_LENMIN 4
26064#define MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_LENMAX 212
26065#define MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_LENMAX_MCDI2 992
26066#define MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_LEN(num) (4+52*(num))
26067#define MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_FUNC_MAP_NUM(len) (((len)-4)/52)
26068#define MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_FLAGS_OFST 0
26069#define MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_FLAGS_LEN 4
26070#define MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_MORE_DATA_OFST 0
26071#define MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_MORE_DATA_LBN 0
26072#define MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_MORE_DATA_WIDTH 1
26073/* Function map, as array of DESC_PROXY_FUNC_MAP */
26074#define MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_FUNC_MAP_OFST 4
26075#define MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_FUNC_MAP_LEN 52
26076#define MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_FUNC_MAP_MINNUM 0
26077#define MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_FUNC_MAP_MAXNUM 4
26078#define MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_FUNC_MAP_MAXNUM_MCDI2 19
26079
26080
26081/***********************************/
26082/* MC_CMD_DESC_PROXY_FUNC_ENABLE
26083 * Enable descriptor proxying for function into target event queue. Returns VI
26084 * allocation info for the proxy source function, so that the caller can map
26085 * absolute VI IDs from descriptor proxy events back to the originating
26086 * function. This is a legacy function that only supports single queue proxy
26087 * devices. It is also limited in that it can only be called after host driver
26088 * attach (once VI allocation is known) and will return MC_CMD_ERR_ENOTCONN
26089 * otherwise. For new code, see MC_CMD_DESC_PROXY_FUNC_ENABLE_QUEUE which
26090 * supports multi-queue devices and has no dependency on host driver attach.
26091 */
26092#define MC_CMD_DESC_PROXY_FUNC_ENABLE 0x178
26093#undef MC_CMD_0x178_PRIVILEGE_CTG
26094
26095#define MC_CMD_0x178_PRIVILEGE_CTG SRIOV_CTG_ADMIN
26096
26097/* MC_CMD_DESC_PROXY_FUNC_ENABLE_IN msgrequest */
26098#define MC_CMD_DESC_PROXY_FUNC_ENABLE_IN_LEN 8
26099/* Handle to descriptor proxy function (as returned by
26100 * MC_CMD_DESC_PROXY_FUNC_OPEN)
26101 */
26102#define MC_CMD_DESC_PROXY_FUNC_ENABLE_IN_HANDLE_OFST 0
26103#define MC_CMD_DESC_PROXY_FUNC_ENABLE_IN_HANDLE_LEN 4
26104/* Descriptor proxy sink queue (caller function relative). Must be extended
26105 * width event queue
26106 */
26107#define MC_CMD_DESC_PROXY_FUNC_ENABLE_IN_TARGET_EVQ_OFST 4
26108#define MC_CMD_DESC_PROXY_FUNC_ENABLE_IN_TARGET_EVQ_LEN 4
26109
26110/* MC_CMD_DESC_PROXY_FUNC_ENABLE_OUT msgresponse */
26111#define MC_CMD_DESC_PROXY_FUNC_ENABLE_OUT_LEN 8
26112/* The number of VIs allocated on the function */
26113#define MC_CMD_DESC_PROXY_FUNC_ENABLE_OUT_VI_COUNT_OFST 0
26114#define MC_CMD_DESC_PROXY_FUNC_ENABLE_OUT_VI_COUNT_LEN 4
26115/* The base absolute VI number allocated to the function. */
26116#define MC_CMD_DESC_PROXY_FUNC_ENABLE_OUT_VI_BASE_OFST 4
26117#define MC_CMD_DESC_PROXY_FUNC_ENABLE_OUT_VI_BASE_LEN 4
26118
26119
26120/***********************************/
26121/* MC_CMD_DESC_PROXY_FUNC_ENABLE_QUEUE
26122 * Enable descriptor proxying for a source queue on a host function into target
26123 * event queue. Source queue number is a relative virtqueue number on the
26124 * source function (0 to max_virtqueues-1). For a multi-queue device, the
26125 * caller must enable all source queues individually. To retrieve absolute VI
26126 * information for the source function (so that VI IDs from descriptor proxy
26127 * events can be mapped back to source function / queue) see
26128 * MC_CMD_DESC_PROXY_FUNC_GET_VI_INFO
26129 */
26130#define MC_CMD_DESC_PROXY_FUNC_ENABLE_QUEUE 0x1d0
26131#undef MC_CMD_0x1d0_PRIVILEGE_CTG
26132
26133#define MC_CMD_0x1d0_PRIVILEGE_CTG SRIOV_CTG_ADMIN
26134
26135/* MC_CMD_DESC_PROXY_FUNC_ENABLE_QUEUE_IN msgrequest */
26136#define MC_CMD_DESC_PROXY_FUNC_ENABLE_QUEUE_IN_LEN 12
26137/* Handle to descriptor proxy function (as returned by
26138 * MC_CMD_DESC_PROXY_FUNC_OPEN)
26139 */
26140#define MC_CMD_DESC_PROXY_FUNC_ENABLE_QUEUE_IN_HANDLE_OFST 0
26141#define MC_CMD_DESC_PROXY_FUNC_ENABLE_QUEUE_IN_HANDLE_LEN 4
26142/* Source relative queue number to enable proxying on */
26143#define MC_CMD_DESC_PROXY_FUNC_ENABLE_QUEUE_IN_SOURCE_QUEUE_OFST 4
26144#define MC_CMD_DESC_PROXY_FUNC_ENABLE_QUEUE_IN_SOURCE_QUEUE_LEN 4
26145/* Descriptor proxy sink queue (caller function relative). Must be extended
26146 * width event queue
26147 */
26148#define MC_CMD_DESC_PROXY_FUNC_ENABLE_QUEUE_IN_TARGET_EVQ_OFST 8
26149#define MC_CMD_DESC_PROXY_FUNC_ENABLE_QUEUE_IN_TARGET_EVQ_LEN 4
26150
26151/* MC_CMD_DESC_PROXY_FUNC_ENABLE_QUEUE_OUT msgresponse */
26152#define MC_CMD_DESC_PROXY_FUNC_ENABLE_QUEUE_OUT_LEN 0
26153
26154
26155/***********************************/
26156/* MC_CMD_DESC_PROXY_FUNC_DISABLE
26157 * Disable descriptor proxying for function. For multi-queue functions,
26158 * disables all queues.
26159 */
26160#define MC_CMD_DESC_PROXY_FUNC_DISABLE 0x179
26161#undef MC_CMD_0x179_PRIVILEGE_CTG
26162
26163#define MC_CMD_0x179_PRIVILEGE_CTG SRIOV_CTG_ADMIN
26164
26165/* MC_CMD_DESC_PROXY_FUNC_DISABLE_IN msgrequest */
26166#define MC_CMD_DESC_PROXY_FUNC_DISABLE_IN_LEN 4
26167/* Handle to descriptor proxy function (as returned by
26168 * MC_CMD_DESC_PROXY_FUNC_OPEN)
26169 */
26170#define MC_CMD_DESC_PROXY_FUNC_DISABLE_IN_HANDLE_OFST 0
26171#define MC_CMD_DESC_PROXY_FUNC_DISABLE_IN_HANDLE_LEN 4
26172
26173/* MC_CMD_DESC_PROXY_FUNC_DISABLE_OUT msgresponse */
26174#define MC_CMD_DESC_PROXY_FUNC_DISABLE_OUT_LEN 0
26175
26176
26177/***********************************/
26178/* MC_CMD_DESC_PROXY_FUNC_DISABLE_QUEUE
26179 * Disable descriptor proxying for a specific source queue on a function.
26180 */
26181#define MC_CMD_DESC_PROXY_FUNC_DISABLE_QUEUE 0x1d1
26182#undef MC_CMD_0x1d1_PRIVILEGE_CTG
26183
26184#define MC_CMD_0x1d1_PRIVILEGE_CTG SRIOV_CTG_ADMIN
26185
26186/* MC_CMD_DESC_PROXY_FUNC_DISABLE_QUEUE_IN msgrequest */
26187#define MC_CMD_DESC_PROXY_FUNC_DISABLE_QUEUE_IN_LEN 8
26188/* Handle to descriptor proxy function (as returned by
26189 * MC_CMD_DESC_PROXY_FUNC_OPEN)
26190 */
26191#define MC_CMD_DESC_PROXY_FUNC_DISABLE_QUEUE_IN_HANDLE_OFST 0
26192#define MC_CMD_DESC_PROXY_FUNC_DISABLE_QUEUE_IN_HANDLE_LEN 4
26193/* Source relative queue number to disable proxying on */
26194#define MC_CMD_DESC_PROXY_FUNC_DISABLE_QUEUE_IN_SOURCE_QUEUE_OFST 4
26195#define MC_CMD_DESC_PROXY_FUNC_DISABLE_QUEUE_IN_SOURCE_QUEUE_LEN 4
26196
26197/* MC_CMD_DESC_PROXY_FUNC_DISABLE_QUEUE_OUT msgresponse */
26198#define MC_CMD_DESC_PROXY_FUNC_DISABLE_QUEUE_OUT_LEN 0
26199
26200
26201/***********************************/
26202/* MC_CMD_DESC_PROXY_GET_VI_INFO
26203 * Returns absolute VI allocation information for the descriptor proxy source
26204 * function referenced by HANDLE, so that the caller can map absolute VI IDs
26205 * from descriptor proxy events back to the originating function and queue. The
26206 * call is only valid after the host driver for the source function has
26207 * attached (after receiving a driver attach event for the descriptor proxy
26208 * function) and will fail with ENOTCONN otherwise.
26209 */
26210#define MC_CMD_DESC_PROXY_GET_VI_INFO 0x1d2
26211#undef MC_CMD_0x1d2_PRIVILEGE_CTG
26212
26213#define MC_CMD_0x1d2_PRIVILEGE_CTG SRIOV_CTG_ADMIN
26214
26215/* MC_CMD_DESC_PROXY_GET_VI_INFO_IN msgrequest */
26216#define MC_CMD_DESC_PROXY_GET_VI_INFO_IN_LEN 4
26217/* Handle to descriptor proxy function (as returned by
26218 * MC_CMD_DESC_PROXY_FUNC_OPEN)
26219 */
26220#define MC_CMD_DESC_PROXY_GET_VI_INFO_IN_HANDLE_OFST 0
26221#define MC_CMD_DESC_PROXY_GET_VI_INFO_IN_HANDLE_LEN 4
26222
26223/* MC_CMD_DESC_PROXY_FUNC_GET_VI_INFO_OUT msgresponse */
26224#define MC_CMD_DESC_PROXY_FUNC_GET_VI_INFO_OUT_LENMIN 0
26225#define MC_CMD_DESC_PROXY_FUNC_GET_VI_INFO_OUT_LENMAX 252
26226#define MC_CMD_DESC_PROXY_FUNC_GET_VI_INFO_OUT_LENMAX_MCDI2 1020
26227#define MC_CMD_DESC_PROXY_FUNC_GET_VI_INFO_OUT_LEN(num) (0+4*(num))
26228#define MC_CMD_DESC_PROXY_FUNC_GET_VI_INFO_OUT_VI_MAP_NUM(len) (((len)-0)/4)
26229/* VI information (VI ID + VI relative queue number) for each of the source
26230 * queues (in order from 0 to max_virtqueues-1), as array of QUEUE_ID
26231 * structures.
26232 */
26233#define MC_CMD_DESC_PROXY_FUNC_GET_VI_INFO_OUT_VI_MAP_OFST 0
26234#define MC_CMD_DESC_PROXY_FUNC_GET_VI_INFO_OUT_VI_MAP_LEN 4
26235#define MC_CMD_DESC_PROXY_FUNC_GET_VI_INFO_OUT_VI_MAP_MINNUM 0
26236#define MC_CMD_DESC_PROXY_FUNC_GET_VI_INFO_OUT_VI_MAP_MAXNUM 63
26237#define MC_CMD_DESC_PROXY_FUNC_GET_VI_INFO_OUT_VI_MAP_MAXNUM_MCDI2 255
26238#define MC_CMD_DESC_PROXY_FUNC_GET_VI_INFO_OUT_VI_MAP_ABS_VI_OFST 0
26239#define MC_CMD_DESC_PROXY_FUNC_GET_VI_INFO_OUT_VI_MAP_ABS_VI_LEN 2
26240#define MC_CMD_DESC_PROXY_FUNC_GET_VI_INFO_OUT_VI_MAP_REL_QUEUE_LBN 16
26241#define MC_CMD_DESC_PROXY_FUNC_GET_VI_INFO_OUT_VI_MAP_REL_QUEUE_WIDTH 1
26242#define MC_CMD_DESC_PROXY_FUNC_GET_VI_INFO_OUT_VI_MAP_RESERVED_LBN 17
26243#define MC_CMD_DESC_PROXY_FUNC_GET_VI_INFO_OUT_VI_MAP_RESERVED_WIDTH 15
26244
26245
26246/***********************************/
26247/* MC_CMD_GET_ADDR_SPC_ID
26248 * Get Address space identifier for use in mem2mem descriptors for a given
26249 * target. See SF-120734-TC for details on ADDR_SPC_IDs and mem2mem
26250 * descriptors.
26251 */
26252#define MC_CMD_GET_ADDR_SPC_ID 0x1a0
26253#undef MC_CMD_0x1a0_PRIVILEGE_CTG
26254
26255#define MC_CMD_0x1a0_PRIVILEGE_CTG SRIOV_CTG_ADMIN
26256
26257/* MC_CMD_GET_ADDR_SPC_ID_IN msgrequest */
26258#define MC_CMD_GET_ADDR_SPC_ID_IN_LEN 16
26259/* Resource type to get ADDR_SPC_ID for */
26260#define MC_CMD_GET_ADDR_SPC_ID_IN_TYPE_OFST 0
26261#define MC_CMD_GET_ADDR_SPC_ID_IN_TYPE_LEN 4
26262/* enum: Address space ID for host/AP memory DMA over the same interface this
26263 * MCDI was called on
26264 */
26265#define MC_CMD_GET_ADDR_SPC_ID_IN_SELF 0x0
26266/* enum: Address space ID for host/AP memory DMA via PCI interface and function
26267 * specified by FUNC
26268 */
26269#define MC_CMD_GET_ADDR_SPC_ID_IN_PCI_FUNC 0x1
26270/* enum: Address space ID for host/AP memory DMA via PCI interface and function
26271 * specified by FUNC with PASID value specified by PASID
26272 */
26273#define MC_CMD_GET_ADDR_SPC_ID_IN_PCI_FUNC_PASID 0x2
26274/* enum: Address space ID for host/AP memory DMA via PCI interface and function
26275 * specified by FUNC with PASID value of relative VI specified by VI
26276 */
26277#define MC_CMD_GET_ADDR_SPC_ID_IN_REL_VI 0x3
26278/* enum: Address space ID for host/AP memory DMA via PCI interface, function
26279 * and PASID value of absolute VI specified by VI
26280 */
26281#define MC_CMD_GET_ADDR_SPC_ID_IN_ABS_VI 0x4
26282/* enum: Address space ID for host memory DMA via PCI interface and function of
26283 * descriptor proxy function specified by HANDLE
26284 */
26285#define MC_CMD_GET_ADDR_SPC_ID_IN_DESC_PROXY_HANDLE 0x5
26286/* enum: Address space ID for DMA to/from MC memory */
26287#define MC_CMD_GET_ADDR_SPC_ID_IN_MC_MEM 0x6
26288/* enum: Address space ID for DMA to/from other SmartNIC memory (on-chip, DDR)
26289 */
26290#define MC_CMD_GET_ADDR_SPC_ID_IN_NIC_MEM 0x7
26291/* PCIe Function ID (as struct PCIE_FUNCTION). Only valid if TYPE is PCI_FUNC,
26292 * PCI_FUNC_PASID or REL_VI.
26293 */
26294#define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_OFST 4
26295#define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_LEN 8
26296#define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_LO_OFST 4
26297#define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_LO_LEN 4
26298#define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_LO_LBN 32
26299#define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_LO_WIDTH 32
26300#define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_HI_OFST 8
26301#define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_HI_LEN 4
26302#define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_HI_LBN 64
26303#define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_HI_WIDTH 32
26304#define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_PF_OFST 4
26305#define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_PF_LEN 2
26306#define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_VF_OFST 6
26307#define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_VF_LEN 2
26308#define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_INTF_OFST 8
26309#define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_INTF_LEN 4
26310/* PASID value. Only valid if TYPE is PCI_FUNC_PASID. */
26311#define MC_CMD_GET_ADDR_SPC_ID_IN_PASID_OFST 12
26312#define MC_CMD_GET_ADDR_SPC_ID_IN_PASID_LEN 4
26313/* Relative or absolute VI number. Only valid if TYPE is REL_VI or ABS_VI */
26314#define MC_CMD_GET_ADDR_SPC_ID_IN_VI_OFST 12
26315#define MC_CMD_GET_ADDR_SPC_ID_IN_VI_LEN 4
26316/* Descriptor proxy function handle. Only valid if TYPE is DESC_PROXY_HANDLE.
26317 */
26318#define MC_CMD_GET_ADDR_SPC_ID_IN_HANDLE_OFST 4
26319#define MC_CMD_GET_ADDR_SPC_ID_IN_HANDLE_LEN 4
26320
26321/* MC_CMD_GET_ADDR_SPC_ID_OUT msgresponse */
26322#define MC_CMD_GET_ADDR_SPC_ID_OUT_LEN 8
26323/* Address Space ID for the requested target. Only the lower 36 bits are valid
26324 * in the current SmartNIC implementation.
26325 */
26326#define MC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_OFST 0
26327#define MC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_LEN 8
26328#define MC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_LO_OFST 0
26329#define MC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_LO_LEN 4
26330#define MC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_LO_LBN 0
26331#define MC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_LO_WIDTH 32
26332#define MC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_HI_OFST 4
26333#define MC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_HI_LEN 4
26334#define MC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_HI_LBN 32
26335#define MC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_HI_WIDTH 32
26336
26337
26338/***********************************/
26339/* MC_CMD_GET_CLIENT_HANDLE
26340 * Obtain a handle for a client given a description of that client. N.B. this
26341 * command is subject to change given the open discussion about how PCIe
26342 * functions should be referenced on an iEP (integrated endpoint: functions
26343 * span multiple buses) and multihost (multiple PCIe interfaces) system.
26344 */
26345#define MC_CMD_GET_CLIENT_HANDLE 0x1c3
26346#undef MC_CMD_0x1c3_PRIVILEGE_CTG
26347
26348#define MC_CMD_0x1c3_PRIVILEGE_CTG SRIOV_CTG_GENERAL
26349
26350/* MC_CMD_GET_CLIENT_HANDLE_IN msgrequest */
26351#define MC_CMD_GET_CLIENT_HANDLE_IN_LEN 12
26352/* Type of client to get a client handle for */
26353#define MC_CMD_GET_CLIENT_HANDLE_IN_TYPE_OFST 0
26354#define MC_CMD_GET_CLIENT_HANDLE_IN_TYPE_LEN 4
26355/* enum: Obtain a client handle for a PCIe function-type client. */
26356#define MC_CMD_GET_CLIENT_HANDLE_IN_TYPE_FUNC 0x0
26357/* PCIe Function ID (as struct PCIE_FUNCTION). Valid when TYPE==FUNC. Use: -
26358 * INTF=CALLER, PF=PF_NULL, VF=VF_NULL to refer to the calling function -
26359 * INTF=CALLER, PF=PF_NULL, VF=... to refer to a VF child of the calling PF or
26360 * a sibling VF of the calling VF. - INTF=CALLER, PF=..., VF=VF_NULL to refer
26361 * to a PF on the calling interface - INTF=CALLER, PF=..., VF=... to refer to a
26362 * VF on the calling interface - INTF=..., PF=..., VF=VF_NULL to refer to a PF
26363 * on a named interface - INTF=..., PF=..., VF=... to refer to a VF on a named
26364 * interface where ... refers to a small integer for the VF/PF fields, and to
26365 * values from the PCIE_INTERFACE enum for for the INTF field. It's only
26366 * meaningful to use INTF=CALLER within a structure that's an argument to
26367 * MC_CMD_DEVEL_GET_CLIENT_HANDLE.
26368 */
26369#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_OFST 4
26370#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_LEN 8
26371#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_LO_OFST 4
26372#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_LO_LEN 4
26373#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_LO_LBN 32
26374#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_LO_WIDTH 32
26375#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_HI_OFST 8
26376#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_HI_LEN 4
26377#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_HI_LBN 64
26378#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_HI_WIDTH 32
26379/* enum: NULL value for the INTF field of struct PCIE_FUNCTION. Provided for
26380 * backwards compatibility only, callers should use PCIE_INTERFACE_CALLER.
26381 */
26382#define MC_CMD_GET_CLIENT_HANDLE_IN_PCIE_FUNCTION_INTF_NULL 0xffffffff
26383#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_PF_OFST 4
26384#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_PF_LEN 2
26385#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_VF_OFST 6
26386#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_VF_LEN 2
26387#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_INTF_OFST 8
26388#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_INTF_LEN 4
26389
26390/* MC_CMD_GET_CLIENT_HANDLE_OUT msgresponse */
26391#define MC_CMD_GET_CLIENT_HANDLE_OUT_LEN 4
26392#define MC_CMD_GET_CLIENT_HANDLE_OUT_HANDLE_OFST 0
26393#define MC_CMD_GET_CLIENT_HANDLE_OUT_HANDLE_LEN 4
26394
26395/* MAE_FIELD_FLAGS structuredef */
26396#define MAE_FIELD_FLAGS_LEN 4
26397#define MAE_FIELD_FLAGS_FLAT_OFST 0
26398#define MAE_FIELD_FLAGS_FLAT_LEN 4
26399#define MAE_FIELD_FLAGS_SUPPORT_STATUS_OFST 0
26400#define MAE_FIELD_FLAGS_SUPPORT_STATUS_LBN 0
26401#define MAE_FIELD_FLAGS_SUPPORT_STATUS_WIDTH 6
26402#define MAE_FIELD_FLAGS_MASK_AFFECTS_CLASS_OFST 0
26403#define MAE_FIELD_FLAGS_MASK_AFFECTS_CLASS_LBN 6
26404#define MAE_FIELD_FLAGS_MASK_AFFECTS_CLASS_WIDTH 1
26405#define MAE_FIELD_FLAGS_MATCH_AFFECTS_CLASS_OFST 0
26406#define MAE_FIELD_FLAGS_MATCH_AFFECTS_CLASS_LBN 7
26407#define MAE_FIELD_FLAGS_MATCH_AFFECTS_CLASS_WIDTH 1
26408#define MAE_FIELD_FLAGS_FLAT_LBN 0
26409#define MAE_FIELD_FLAGS_FLAT_WIDTH 32
26410
26411/* MAE_ENC_FIELD_PAIRS structuredef: Mask and value pairs for all fields that
26412 * it makes sense to use to determine the encapsulation type of a packet. Its
26413 * intended use is to keep a common packing of fields across multiple MCDI
26414 * commands, keeping things inherently sychronised and allowing code shared. To
26415 * use in an MCDI command, the command should end with a variable length byte
26416 * array populated with this structure. Do not extend this structure. Instead,
26417 * create _Vx versions with the necessary fields appended. That way, the
26418 * existing semantics for extending MCDI commands are preserved.
26419 */
26420#define MAE_ENC_FIELD_PAIRS_LEN 156
26421#define MAE_ENC_FIELD_PAIRS_INGRESS_MPORT_SELECTOR_OFST 0
26422#define MAE_ENC_FIELD_PAIRS_INGRESS_MPORT_SELECTOR_LEN 4
26423#define MAE_ENC_FIELD_PAIRS_INGRESS_MPORT_SELECTOR_LBN 0
26424#define MAE_ENC_FIELD_PAIRS_INGRESS_MPORT_SELECTOR_WIDTH 32
26425#define MAE_ENC_FIELD_PAIRS_INGRESS_MPORT_SELECTOR_MASK_OFST 4
26426#define MAE_ENC_FIELD_PAIRS_INGRESS_MPORT_SELECTOR_MASK_LEN 4
26427#define MAE_ENC_FIELD_PAIRS_INGRESS_MPORT_SELECTOR_MASK_LBN 32
26428#define MAE_ENC_FIELD_PAIRS_INGRESS_MPORT_SELECTOR_MASK_WIDTH 32
26429#define MAE_ENC_FIELD_PAIRS_ENC_ETHER_TYPE_BE_OFST 8
26430#define MAE_ENC_FIELD_PAIRS_ENC_ETHER_TYPE_BE_LEN 2
26431#define MAE_ENC_FIELD_PAIRS_ENC_ETHER_TYPE_BE_LBN 64
26432#define MAE_ENC_FIELD_PAIRS_ENC_ETHER_TYPE_BE_WIDTH 16
26433#define MAE_ENC_FIELD_PAIRS_ENC_ETHER_TYPE_BE_MASK_OFST 10
26434#define MAE_ENC_FIELD_PAIRS_ENC_ETHER_TYPE_BE_MASK_LEN 2
26435#define MAE_ENC_FIELD_PAIRS_ENC_ETHER_TYPE_BE_MASK_LBN 80
26436#define MAE_ENC_FIELD_PAIRS_ENC_ETHER_TYPE_BE_MASK_WIDTH 16
26437#define MAE_ENC_FIELD_PAIRS_ENC_VLAN0_TCI_BE_OFST 12
26438#define MAE_ENC_FIELD_PAIRS_ENC_VLAN0_TCI_BE_LEN 2
26439#define MAE_ENC_FIELD_PAIRS_ENC_VLAN0_TCI_BE_LBN 96
26440#define MAE_ENC_FIELD_PAIRS_ENC_VLAN0_TCI_BE_WIDTH 16
26441#define MAE_ENC_FIELD_PAIRS_ENC_VLAN0_TCI_BE_MASK_OFST 14
26442#define MAE_ENC_FIELD_PAIRS_ENC_VLAN0_TCI_BE_MASK_LEN 2
26443#define MAE_ENC_FIELD_PAIRS_ENC_VLAN0_TCI_BE_MASK_LBN 112
26444#define MAE_ENC_FIELD_PAIRS_ENC_VLAN0_TCI_BE_MASK_WIDTH 16
26445#define MAE_ENC_FIELD_PAIRS_ENC_VLAN0_PROTO_BE_OFST 16
26446#define MAE_ENC_FIELD_PAIRS_ENC_VLAN0_PROTO_BE_LEN 2
26447#define MAE_ENC_FIELD_PAIRS_ENC_VLAN0_PROTO_BE_LBN 128
26448#define MAE_ENC_FIELD_PAIRS_ENC_VLAN0_PROTO_BE_WIDTH 16
26449#define MAE_ENC_FIELD_PAIRS_ENC_VLAN0_PROTO_BE_MASK_OFST 18
26450#define MAE_ENC_FIELD_PAIRS_ENC_VLAN0_PROTO_BE_MASK_LEN 2
26451#define MAE_ENC_FIELD_PAIRS_ENC_VLAN0_PROTO_BE_MASK_LBN 144
26452#define MAE_ENC_FIELD_PAIRS_ENC_VLAN0_PROTO_BE_MASK_WIDTH 16
26453#define MAE_ENC_FIELD_PAIRS_ENC_VLAN1_TCI_BE_OFST 20
26454#define MAE_ENC_FIELD_PAIRS_ENC_VLAN1_TCI_BE_LEN 2
26455#define MAE_ENC_FIELD_PAIRS_ENC_VLAN1_TCI_BE_LBN 160
26456#define MAE_ENC_FIELD_PAIRS_ENC_VLAN1_TCI_BE_WIDTH 16
26457#define MAE_ENC_FIELD_PAIRS_ENC_VLAN1_TCI_BE_MASK_OFST 22
26458#define MAE_ENC_FIELD_PAIRS_ENC_VLAN1_TCI_BE_MASK_LEN 2
26459#define MAE_ENC_FIELD_PAIRS_ENC_VLAN1_TCI_BE_MASK_LBN 176
26460#define MAE_ENC_FIELD_PAIRS_ENC_VLAN1_TCI_BE_MASK_WIDTH 16
26461#define MAE_ENC_FIELD_PAIRS_ENC_VLAN1_PROTO_BE_OFST 24
26462#define MAE_ENC_FIELD_PAIRS_ENC_VLAN1_PROTO_BE_LEN 2
26463#define MAE_ENC_FIELD_PAIRS_ENC_VLAN1_PROTO_BE_LBN 192
26464#define MAE_ENC_FIELD_PAIRS_ENC_VLAN1_PROTO_BE_WIDTH 16
26465#define MAE_ENC_FIELD_PAIRS_ENC_VLAN1_PROTO_BE_MASK_OFST 26
26466#define MAE_ENC_FIELD_PAIRS_ENC_VLAN1_PROTO_BE_MASK_LEN 2
26467#define MAE_ENC_FIELD_PAIRS_ENC_VLAN1_PROTO_BE_MASK_LBN 208
26468#define MAE_ENC_FIELD_PAIRS_ENC_VLAN1_PROTO_BE_MASK_WIDTH 16
26469#define MAE_ENC_FIELD_PAIRS_ENC_ETH_SADDR_BE_OFST 28
26470#define MAE_ENC_FIELD_PAIRS_ENC_ETH_SADDR_BE_LEN 6
26471#define MAE_ENC_FIELD_PAIRS_ENC_ETH_SADDR_BE_LBN 224
26472#define MAE_ENC_FIELD_PAIRS_ENC_ETH_SADDR_BE_WIDTH 48
26473#define MAE_ENC_FIELD_PAIRS_ENC_ETH_SADDR_BE_MASK_OFST 34
26474#define MAE_ENC_FIELD_PAIRS_ENC_ETH_SADDR_BE_MASK_LEN 6
26475#define MAE_ENC_FIELD_PAIRS_ENC_ETH_SADDR_BE_MASK_LBN 272
26476#define MAE_ENC_FIELD_PAIRS_ENC_ETH_SADDR_BE_MASK_WIDTH 48
26477#define MAE_ENC_FIELD_PAIRS_ENC_ETH_DADDR_BE_OFST 40
26478#define MAE_ENC_FIELD_PAIRS_ENC_ETH_DADDR_BE_LEN 6
26479#define MAE_ENC_FIELD_PAIRS_ENC_ETH_DADDR_BE_LBN 320
26480#define MAE_ENC_FIELD_PAIRS_ENC_ETH_DADDR_BE_WIDTH 48
26481#define MAE_ENC_FIELD_PAIRS_ENC_ETH_DADDR_BE_MASK_OFST 46
26482#define MAE_ENC_FIELD_PAIRS_ENC_ETH_DADDR_BE_MASK_LEN 6
26483#define MAE_ENC_FIELD_PAIRS_ENC_ETH_DADDR_BE_MASK_LBN 368
26484#define MAE_ENC_FIELD_PAIRS_ENC_ETH_DADDR_BE_MASK_WIDTH 48
26485#define MAE_ENC_FIELD_PAIRS_ENC_SRC_IP4_BE_OFST 52
26486#define MAE_ENC_FIELD_PAIRS_ENC_SRC_IP4_BE_LEN 4
26487#define MAE_ENC_FIELD_PAIRS_ENC_SRC_IP4_BE_LBN 416
26488#define MAE_ENC_FIELD_PAIRS_ENC_SRC_IP4_BE_WIDTH 32
26489#define MAE_ENC_FIELD_PAIRS_ENC_SRC_IP4_BE_MASK_OFST 56
26490#define MAE_ENC_FIELD_PAIRS_ENC_SRC_IP4_BE_MASK_LEN 4
26491#define MAE_ENC_FIELD_PAIRS_ENC_SRC_IP4_BE_MASK_LBN 448
26492#define MAE_ENC_FIELD_PAIRS_ENC_SRC_IP4_BE_MASK_WIDTH 32
26493#define MAE_ENC_FIELD_PAIRS_ENC_SRC_IP6_BE_OFST 60
26494#define MAE_ENC_FIELD_PAIRS_ENC_SRC_IP6_BE_LEN 16
26495#define MAE_ENC_FIELD_PAIRS_ENC_SRC_IP6_BE_LBN 480
26496#define MAE_ENC_FIELD_PAIRS_ENC_SRC_IP6_BE_WIDTH 128
26497#define MAE_ENC_FIELD_PAIRS_ENC_SRC_IP6_BE_MASK_OFST 76
26498#define MAE_ENC_FIELD_PAIRS_ENC_SRC_IP6_BE_MASK_LEN 16
26499#define MAE_ENC_FIELD_PAIRS_ENC_SRC_IP6_BE_MASK_LBN 608
26500#define MAE_ENC_FIELD_PAIRS_ENC_SRC_IP6_BE_MASK_WIDTH 128
26501#define MAE_ENC_FIELD_PAIRS_ENC_DST_IP4_BE_OFST 92
26502#define MAE_ENC_FIELD_PAIRS_ENC_DST_IP4_BE_LEN 4
26503#define MAE_ENC_FIELD_PAIRS_ENC_DST_IP4_BE_LBN 736
26504#define MAE_ENC_FIELD_PAIRS_ENC_DST_IP4_BE_WIDTH 32
26505#define MAE_ENC_FIELD_PAIRS_ENC_DST_IP4_BE_MASK_OFST 96
26506#define MAE_ENC_FIELD_PAIRS_ENC_DST_IP4_BE_MASK_LEN 4
26507#define MAE_ENC_FIELD_PAIRS_ENC_DST_IP4_BE_MASK_LBN 768
26508#define MAE_ENC_FIELD_PAIRS_ENC_DST_IP4_BE_MASK_WIDTH 32
26509#define MAE_ENC_FIELD_PAIRS_ENC_DST_IP6_BE_OFST 100
26510#define MAE_ENC_FIELD_PAIRS_ENC_DST_IP6_BE_LEN 16
26511#define MAE_ENC_FIELD_PAIRS_ENC_DST_IP6_BE_LBN 800
26512#define MAE_ENC_FIELD_PAIRS_ENC_DST_IP6_BE_WIDTH 128
26513#define MAE_ENC_FIELD_PAIRS_ENC_DST_IP6_BE_MASK_OFST 116
26514#define MAE_ENC_FIELD_PAIRS_ENC_DST_IP6_BE_MASK_LEN 16
26515#define MAE_ENC_FIELD_PAIRS_ENC_DST_IP6_BE_MASK_LBN 928
26516#define MAE_ENC_FIELD_PAIRS_ENC_DST_IP6_BE_MASK_WIDTH 128
26517#define MAE_ENC_FIELD_PAIRS_ENC_IP_PROTO_OFST 132
26518#define MAE_ENC_FIELD_PAIRS_ENC_IP_PROTO_LEN 1
26519#define MAE_ENC_FIELD_PAIRS_ENC_IP_PROTO_LBN 1056
26520#define MAE_ENC_FIELD_PAIRS_ENC_IP_PROTO_WIDTH 8
26521#define MAE_ENC_FIELD_PAIRS_ENC_IP_PROTO_MASK_OFST 133
26522#define MAE_ENC_FIELD_PAIRS_ENC_IP_PROTO_MASK_LEN 1
26523#define MAE_ENC_FIELD_PAIRS_ENC_IP_PROTO_MASK_LBN 1064
26524#define MAE_ENC_FIELD_PAIRS_ENC_IP_PROTO_MASK_WIDTH 8
26525#define MAE_ENC_FIELD_PAIRS_ENC_IP_TOS_OFST 134
26526#define MAE_ENC_FIELD_PAIRS_ENC_IP_TOS_LEN 1
26527#define MAE_ENC_FIELD_PAIRS_ENC_IP_TOS_LBN 1072
26528#define MAE_ENC_FIELD_PAIRS_ENC_IP_TOS_WIDTH 8
26529#define MAE_ENC_FIELD_PAIRS_ENC_IP_TOS_MASK_OFST 135
26530#define MAE_ENC_FIELD_PAIRS_ENC_IP_TOS_MASK_LEN 1
26531#define MAE_ENC_FIELD_PAIRS_ENC_IP_TOS_MASK_LBN 1080
26532#define MAE_ENC_FIELD_PAIRS_ENC_IP_TOS_MASK_WIDTH 8
26533#define MAE_ENC_FIELD_PAIRS_ENC_IP_TTL_OFST 136
26534#define MAE_ENC_FIELD_PAIRS_ENC_IP_TTL_LEN 1
26535#define MAE_ENC_FIELD_PAIRS_ENC_IP_TTL_LBN 1088
26536#define MAE_ENC_FIELD_PAIRS_ENC_IP_TTL_WIDTH 8
26537#define MAE_ENC_FIELD_PAIRS_ENC_IP_TTL_MASK_OFST 137
26538#define MAE_ENC_FIELD_PAIRS_ENC_IP_TTL_MASK_LEN 1
26539#define MAE_ENC_FIELD_PAIRS_ENC_IP_TTL_MASK_LBN 1096
26540#define MAE_ENC_FIELD_PAIRS_ENC_IP_TTL_MASK_WIDTH 8
26541/* Deprecated in favour of ENC_FLAGS alias. */
26542#define MAE_ENC_FIELD_PAIRS_ENC_VLAN_FLAGS_OFST 138
26543#define MAE_ENC_FIELD_PAIRS_ENC_VLAN_FLAGS_LEN 1
26544#define MAE_ENC_FIELD_PAIRS_ENC_HAS_OVLAN_OFST 138
26545#define MAE_ENC_FIELD_PAIRS_ENC_HAS_OVLAN_LBN 0
26546#define MAE_ENC_FIELD_PAIRS_ENC_HAS_OVLAN_WIDTH 1
26547#define MAE_ENC_FIELD_PAIRS_ENC_HAS_IVLAN_OFST 138
26548#define MAE_ENC_FIELD_PAIRS_ENC_HAS_IVLAN_LBN 1
26549#define MAE_ENC_FIELD_PAIRS_ENC_HAS_IVLAN_WIDTH 1
26550#define MAE_ENC_FIELD_PAIRS_ENC_IP_FRAG_OFST 138
26551#define MAE_ENC_FIELD_PAIRS_ENC_IP_FRAG_LBN 2
26552#define MAE_ENC_FIELD_PAIRS_ENC_IP_FRAG_WIDTH 1
26553#define MAE_ENC_FIELD_PAIRS_ENC_VLAN_FLAGS_LBN 1104
26554#define MAE_ENC_FIELD_PAIRS_ENC_VLAN_FLAGS_WIDTH 8
26555/* More generic alias for ENC_VLAN_FLAGS. */
26556#define MAE_ENC_FIELD_PAIRS_ENC_FLAGS_OFST 138
26557#define MAE_ENC_FIELD_PAIRS_ENC_FLAGS_LEN 1
26558#define MAE_ENC_FIELD_PAIRS_ENC_FLAGS_LBN 1104
26559#define MAE_ENC_FIELD_PAIRS_ENC_FLAGS_WIDTH 8
26560/* Deprecated in favour of ENC_FLAGS_MASK alias. */
26561#define MAE_ENC_FIELD_PAIRS_ENC_VLAN_FLAGS_MASK_OFST 139
26562#define MAE_ENC_FIELD_PAIRS_ENC_VLAN_FLAGS_MASK_LEN 1
26563#define MAE_ENC_FIELD_PAIRS_ENC_HAS_OVLAN_MASK_OFST 139
26564#define MAE_ENC_FIELD_PAIRS_ENC_HAS_OVLAN_MASK_LBN 0
26565#define MAE_ENC_FIELD_PAIRS_ENC_HAS_OVLAN_MASK_WIDTH 1
26566#define MAE_ENC_FIELD_PAIRS_ENC_HAS_IVLAN_MASK_OFST 139
26567#define MAE_ENC_FIELD_PAIRS_ENC_HAS_IVLAN_MASK_LBN 1
26568#define MAE_ENC_FIELD_PAIRS_ENC_HAS_IVLAN_MASK_WIDTH 1
26569#define MAE_ENC_FIELD_PAIRS_ENC_IP_FRAG_MASK_OFST 139
26570#define MAE_ENC_FIELD_PAIRS_ENC_IP_FRAG_MASK_LBN 2
26571#define MAE_ENC_FIELD_PAIRS_ENC_IP_FRAG_MASK_WIDTH 1
26572#define MAE_ENC_FIELD_PAIRS_ENC_VLAN_FLAGS_MASK_LBN 1112
26573#define MAE_ENC_FIELD_PAIRS_ENC_VLAN_FLAGS_MASK_WIDTH 8
26574/* More generic alias for ENC_FLAGS_MASK. */
26575#define MAE_ENC_FIELD_PAIRS_ENC_FLAGS_MASK_OFST 139
26576#define MAE_ENC_FIELD_PAIRS_ENC_FLAGS_MASK_LEN 1
26577#define MAE_ENC_FIELD_PAIRS_ENC_FLAGS_MASK_LBN 1112
26578#define MAE_ENC_FIELD_PAIRS_ENC_FLAGS_MASK_WIDTH 8
26579#define MAE_ENC_FIELD_PAIRS_ENC_IP_FLAGS_BE_OFST 140
26580#define MAE_ENC_FIELD_PAIRS_ENC_IP_FLAGS_BE_LEN 4
26581#define MAE_ENC_FIELD_PAIRS_ENC_IP_FLAGS_BE_LBN 1120
26582#define MAE_ENC_FIELD_PAIRS_ENC_IP_FLAGS_BE_WIDTH 32
26583#define MAE_ENC_FIELD_PAIRS_ENC_IP_FLAGS_BE_MASK_OFST 144
26584#define MAE_ENC_FIELD_PAIRS_ENC_IP_FLAGS_BE_MASK_LEN 4
26585#define MAE_ENC_FIELD_PAIRS_ENC_IP_FLAGS_BE_MASK_LBN 1152
26586#define MAE_ENC_FIELD_PAIRS_ENC_IP_FLAGS_BE_MASK_WIDTH 32
26587#define MAE_ENC_FIELD_PAIRS_ENC_L4_SPORT_BE_OFST 148
26588#define MAE_ENC_FIELD_PAIRS_ENC_L4_SPORT_BE_LEN 2
26589#define MAE_ENC_FIELD_PAIRS_ENC_L4_SPORT_BE_LBN 1184
26590#define MAE_ENC_FIELD_PAIRS_ENC_L4_SPORT_BE_WIDTH 16
26591#define MAE_ENC_FIELD_PAIRS_ENC_L4_SPORT_BE_MASK_OFST 150
26592#define MAE_ENC_FIELD_PAIRS_ENC_L4_SPORT_BE_MASK_LEN 2
26593#define MAE_ENC_FIELD_PAIRS_ENC_L4_SPORT_BE_MASK_LBN 1200
26594#define MAE_ENC_FIELD_PAIRS_ENC_L4_SPORT_BE_MASK_WIDTH 16
26595#define MAE_ENC_FIELD_PAIRS_ENC_L4_DPORT_BE_OFST 152
26596#define MAE_ENC_FIELD_PAIRS_ENC_L4_DPORT_BE_LEN 2
26597#define MAE_ENC_FIELD_PAIRS_ENC_L4_DPORT_BE_LBN 1216
26598#define MAE_ENC_FIELD_PAIRS_ENC_L4_DPORT_BE_WIDTH 16
26599#define MAE_ENC_FIELD_PAIRS_ENC_L4_DPORT_BE_MASK_OFST 154
26600#define MAE_ENC_FIELD_PAIRS_ENC_L4_DPORT_BE_MASK_LEN 2
26601#define MAE_ENC_FIELD_PAIRS_ENC_L4_DPORT_BE_MASK_LBN 1232
26602#define MAE_ENC_FIELD_PAIRS_ENC_L4_DPORT_BE_MASK_WIDTH 16
26603
26604/* MAE_FIELD_MASK_VALUE_PAIRS structuredef: Mask and value pairs for all fields
26605 * currently defined. Same semantics as MAE_ENC_FIELD_PAIRS.
26606 */
26607#define MAE_FIELD_MASK_VALUE_PAIRS_LEN 344
26608#define MAE_FIELD_MASK_VALUE_PAIRS_INGRESS_MPORT_SELECTOR_OFST 0
26609#define MAE_FIELD_MASK_VALUE_PAIRS_INGRESS_MPORT_SELECTOR_LEN 4
26610#define MAE_FIELD_MASK_VALUE_PAIRS_INGRESS_MPORT_SELECTOR_LBN 0
26611#define MAE_FIELD_MASK_VALUE_PAIRS_INGRESS_MPORT_SELECTOR_WIDTH 32
26612#define MAE_FIELD_MASK_VALUE_PAIRS_INGRESS_MPORT_SELECTOR_MASK_OFST 4
26613#define MAE_FIELD_MASK_VALUE_PAIRS_INGRESS_MPORT_SELECTOR_MASK_LEN 4
26614#define MAE_FIELD_MASK_VALUE_PAIRS_INGRESS_MPORT_SELECTOR_MASK_LBN 32
26615#define MAE_FIELD_MASK_VALUE_PAIRS_INGRESS_MPORT_SELECTOR_MASK_WIDTH 32
26616#define MAE_FIELD_MASK_VALUE_PAIRS_MARK_OFST 8
26617#define MAE_FIELD_MASK_VALUE_PAIRS_MARK_LEN 4
26618#define MAE_FIELD_MASK_VALUE_PAIRS_MARK_LBN 64
26619#define MAE_FIELD_MASK_VALUE_PAIRS_MARK_WIDTH 32
26620#define MAE_FIELD_MASK_VALUE_PAIRS_MARK_MASK_OFST 12
26621#define MAE_FIELD_MASK_VALUE_PAIRS_MARK_MASK_LEN 4
26622#define MAE_FIELD_MASK_VALUE_PAIRS_MARK_MASK_LBN 96
26623#define MAE_FIELD_MASK_VALUE_PAIRS_MARK_MASK_WIDTH 32
26624#define MAE_FIELD_MASK_VALUE_PAIRS_ETHER_TYPE_BE_OFST 16
26625#define MAE_FIELD_MASK_VALUE_PAIRS_ETHER_TYPE_BE_LEN 2
26626#define MAE_FIELD_MASK_VALUE_PAIRS_ETHER_TYPE_BE_LBN 128
26627#define MAE_FIELD_MASK_VALUE_PAIRS_ETHER_TYPE_BE_WIDTH 16
26628#define MAE_FIELD_MASK_VALUE_PAIRS_ETHER_TYPE_BE_MASK_OFST 18
26629#define MAE_FIELD_MASK_VALUE_PAIRS_ETHER_TYPE_BE_MASK_LEN 2
26630#define MAE_FIELD_MASK_VALUE_PAIRS_ETHER_TYPE_BE_MASK_LBN 144
26631#define MAE_FIELD_MASK_VALUE_PAIRS_ETHER_TYPE_BE_MASK_WIDTH 16
26632#define MAE_FIELD_MASK_VALUE_PAIRS_VLAN0_TCI_BE_OFST 20
26633#define MAE_FIELD_MASK_VALUE_PAIRS_VLAN0_TCI_BE_LEN 2
26634#define MAE_FIELD_MASK_VALUE_PAIRS_VLAN0_TCI_BE_LBN 160
26635#define MAE_FIELD_MASK_VALUE_PAIRS_VLAN0_TCI_BE_WIDTH 16
26636#define MAE_FIELD_MASK_VALUE_PAIRS_VLAN0_TCI_BE_MASK_OFST 22
26637#define MAE_FIELD_MASK_VALUE_PAIRS_VLAN0_TCI_BE_MASK_LEN 2
26638#define MAE_FIELD_MASK_VALUE_PAIRS_VLAN0_TCI_BE_MASK_LBN 176
26639#define MAE_FIELD_MASK_VALUE_PAIRS_VLAN0_TCI_BE_MASK_WIDTH 16
26640#define MAE_FIELD_MASK_VALUE_PAIRS_VLAN0_PROTO_BE_OFST 24
26641#define MAE_FIELD_MASK_VALUE_PAIRS_VLAN0_PROTO_BE_LEN 2
26642#define MAE_FIELD_MASK_VALUE_PAIRS_VLAN0_PROTO_BE_LBN 192
26643#define MAE_FIELD_MASK_VALUE_PAIRS_VLAN0_PROTO_BE_WIDTH 16
26644#define MAE_FIELD_MASK_VALUE_PAIRS_VLAN0_PROTO_BE_MASK_OFST 26
26645#define MAE_FIELD_MASK_VALUE_PAIRS_VLAN0_PROTO_BE_MASK_LEN 2
26646#define MAE_FIELD_MASK_VALUE_PAIRS_VLAN0_PROTO_BE_MASK_LBN 208
26647#define MAE_FIELD_MASK_VALUE_PAIRS_VLAN0_PROTO_BE_MASK_WIDTH 16
26648#define MAE_FIELD_MASK_VALUE_PAIRS_VLAN1_TCI_BE_OFST 28
26649#define MAE_FIELD_MASK_VALUE_PAIRS_VLAN1_TCI_BE_LEN 2
26650#define MAE_FIELD_MASK_VALUE_PAIRS_VLAN1_TCI_BE_LBN 224
26651#define MAE_FIELD_MASK_VALUE_PAIRS_VLAN1_TCI_BE_WIDTH 16
26652#define MAE_FIELD_MASK_VALUE_PAIRS_VLAN1_TCI_BE_MASK_OFST 30
26653#define MAE_FIELD_MASK_VALUE_PAIRS_VLAN1_TCI_BE_MASK_LEN 2
26654#define MAE_FIELD_MASK_VALUE_PAIRS_VLAN1_TCI_BE_MASK_LBN 240
26655#define MAE_FIELD_MASK_VALUE_PAIRS_VLAN1_TCI_BE_MASK_WIDTH 16
26656#define MAE_FIELD_MASK_VALUE_PAIRS_VLAN1_PROTO_BE_OFST 32
26657#define MAE_FIELD_MASK_VALUE_PAIRS_VLAN1_PROTO_BE_LEN 2
26658#define MAE_FIELD_MASK_VALUE_PAIRS_VLAN1_PROTO_BE_LBN 256
26659#define MAE_FIELD_MASK_VALUE_PAIRS_VLAN1_PROTO_BE_WIDTH 16
26660#define MAE_FIELD_MASK_VALUE_PAIRS_VLAN1_PROTO_BE_MASK_OFST 34
26661#define MAE_FIELD_MASK_VALUE_PAIRS_VLAN1_PROTO_BE_MASK_LEN 2
26662#define MAE_FIELD_MASK_VALUE_PAIRS_VLAN1_PROTO_BE_MASK_LBN 272
26663#define MAE_FIELD_MASK_VALUE_PAIRS_VLAN1_PROTO_BE_MASK_WIDTH 16
26664#define MAE_FIELD_MASK_VALUE_PAIRS_ETH_SADDR_BE_OFST 36
26665#define MAE_FIELD_MASK_VALUE_PAIRS_ETH_SADDR_BE_LEN 6
26666#define MAE_FIELD_MASK_VALUE_PAIRS_ETH_SADDR_BE_LBN 288
26667#define MAE_FIELD_MASK_VALUE_PAIRS_ETH_SADDR_BE_WIDTH 48
26668#define MAE_FIELD_MASK_VALUE_PAIRS_ETH_SADDR_BE_MASK_OFST 42
26669#define MAE_FIELD_MASK_VALUE_PAIRS_ETH_SADDR_BE_MASK_LEN 6
26670#define MAE_FIELD_MASK_VALUE_PAIRS_ETH_SADDR_BE_MASK_LBN 336
26671#define MAE_FIELD_MASK_VALUE_PAIRS_ETH_SADDR_BE_MASK_WIDTH 48
26672#define MAE_FIELD_MASK_VALUE_PAIRS_ETH_DADDR_BE_OFST 48
26673#define MAE_FIELD_MASK_VALUE_PAIRS_ETH_DADDR_BE_LEN 6
26674#define MAE_FIELD_MASK_VALUE_PAIRS_ETH_DADDR_BE_LBN 384
26675#define MAE_FIELD_MASK_VALUE_PAIRS_ETH_DADDR_BE_WIDTH 48
26676#define MAE_FIELD_MASK_VALUE_PAIRS_ETH_DADDR_BE_MASK_OFST 54
26677#define MAE_FIELD_MASK_VALUE_PAIRS_ETH_DADDR_BE_MASK_LEN 6
26678#define MAE_FIELD_MASK_VALUE_PAIRS_ETH_DADDR_BE_MASK_LBN 432
26679#define MAE_FIELD_MASK_VALUE_PAIRS_ETH_DADDR_BE_MASK_WIDTH 48
26680#define MAE_FIELD_MASK_VALUE_PAIRS_SRC_IP4_BE_OFST 60
26681#define MAE_FIELD_MASK_VALUE_PAIRS_SRC_IP4_BE_LEN 4
26682#define MAE_FIELD_MASK_VALUE_PAIRS_SRC_IP4_BE_LBN 480
26683#define MAE_FIELD_MASK_VALUE_PAIRS_SRC_IP4_BE_WIDTH 32
26684#define MAE_FIELD_MASK_VALUE_PAIRS_SRC_IP4_BE_MASK_OFST 64
26685#define MAE_FIELD_MASK_VALUE_PAIRS_SRC_IP4_BE_MASK_LEN 4
26686#define MAE_FIELD_MASK_VALUE_PAIRS_SRC_IP4_BE_MASK_LBN 512
26687#define MAE_FIELD_MASK_VALUE_PAIRS_SRC_IP4_BE_MASK_WIDTH 32
26688#define MAE_FIELD_MASK_VALUE_PAIRS_SRC_IP6_BE_OFST 68
26689#define MAE_FIELD_MASK_VALUE_PAIRS_SRC_IP6_BE_LEN 16
26690#define MAE_FIELD_MASK_VALUE_PAIRS_SRC_IP6_BE_LBN 544
26691#define MAE_FIELD_MASK_VALUE_PAIRS_SRC_IP6_BE_WIDTH 128
26692#define MAE_FIELD_MASK_VALUE_PAIRS_SRC_IP6_BE_MASK_OFST 84
26693#define MAE_FIELD_MASK_VALUE_PAIRS_SRC_IP6_BE_MASK_LEN 16
26694#define MAE_FIELD_MASK_VALUE_PAIRS_SRC_IP6_BE_MASK_LBN 672
26695#define MAE_FIELD_MASK_VALUE_PAIRS_SRC_IP6_BE_MASK_WIDTH 128
26696#define MAE_FIELD_MASK_VALUE_PAIRS_DST_IP4_BE_OFST 100
26697#define MAE_FIELD_MASK_VALUE_PAIRS_DST_IP4_BE_LEN 4
26698#define MAE_FIELD_MASK_VALUE_PAIRS_DST_IP4_BE_LBN 800
26699#define MAE_FIELD_MASK_VALUE_PAIRS_DST_IP4_BE_WIDTH 32
26700#define MAE_FIELD_MASK_VALUE_PAIRS_DST_IP4_BE_MASK_OFST 104
26701#define MAE_FIELD_MASK_VALUE_PAIRS_DST_IP4_BE_MASK_LEN 4
26702#define MAE_FIELD_MASK_VALUE_PAIRS_DST_IP4_BE_MASK_LBN 832
26703#define MAE_FIELD_MASK_VALUE_PAIRS_DST_IP4_BE_MASK_WIDTH 32
26704#define MAE_FIELD_MASK_VALUE_PAIRS_DST_IP6_BE_OFST 108
26705#define MAE_FIELD_MASK_VALUE_PAIRS_DST_IP6_BE_LEN 16
26706#define MAE_FIELD_MASK_VALUE_PAIRS_DST_IP6_BE_LBN 864
26707#define MAE_FIELD_MASK_VALUE_PAIRS_DST_IP6_BE_WIDTH 128
26708#define MAE_FIELD_MASK_VALUE_PAIRS_DST_IP6_BE_MASK_OFST 124
26709#define MAE_FIELD_MASK_VALUE_PAIRS_DST_IP6_BE_MASK_LEN 16
26710#define MAE_FIELD_MASK_VALUE_PAIRS_DST_IP6_BE_MASK_LBN 992
26711#define MAE_FIELD_MASK_VALUE_PAIRS_DST_IP6_BE_MASK_WIDTH 128
26712#define MAE_FIELD_MASK_VALUE_PAIRS_IP_PROTO_OFST 140
26713#define MAE_FIELD_MASK_VALUE_PAIRS_IP_PROTO_LEN 1
26714#define MAE_FIELD_MASK_VALUE_PAIRS_IP_PROTO_LBN 1120
26715#define MAE_FIELD_MASK_VALUE_PAIRS_IP_PROTO_WIDTH 8
26716#define MAE_FIELD_MASK_VALUE_PAIRS_IP_PROTO_MASK_OFST 141
26717#define MAE_FIELD_MASK_VALUE_PAIRS_IP_PROTO_MASK_LEN 1
26718#define MAE_FIELD_MASK_VALUE_PAIRS_IP_PROTO_MASK_LBN 1128
26719#define MAE_FIELD_MASK_VALUE_PAIRS_IP_PROTO_MASK_WIDTH 8
26720#define MAE_FIELD_MASK_VALUE_PAIRS_IP_TOS_OFST 142
26721#define MAE_FIELD_MASK_VALUE_PAIRS_IP_TOS_LEN 1
26722#define MAE_FIELD_MASK_VALUE_PAIRS_IP_TOS_LBN 1136
26723#define MAE_FIELD_MASK_VALUE_PAIRS_IP_TOS_WIDTH 8
26724#define MAE_FIELD_MASK_VALUE_PAIRS_IP_TOS_MASK_OFST 143
26725#define MAE_FIELD_MASK_VALUE_PAIRS_IP_TOS_MASK_LEN 1
26726#define MAE_FIELD_MASK_VALUE_PAIRS_IP_TOS_MASK_LBN 1144
26727#define MAE_FIELD_MASK_VALUE_PAIRS_IP_TOS_MASK_WIDTH 8
26728/* Due to hardware limitations, firmware may return
26729 * MC_CMD_ERR_EINVAL(BAD_IP_TTL) when attempting to match on an IP_TTL value
26730 * other than 1.
26731 */
26732#define MAE_FIELD_MASK_VALUE_PAIRS_IP_TTL_OFST 144
26733#define MAE_FIELD_MASK_VALUE_PAIRS_IP_TTL_LEN 1
26734#define MAE_FIELD_MASK_VALUE_PAIRS_IP_TTL_LBN 1152
26735#define MAE_FIELD_MASK_VALUE_PAIRS_IP_TTL_WIDTH 8
26736#define MAE_FIELD_MASK_VALUE_PAIRS_IP_TTL_MASK_OFST 145
26737#define MAE_FIELD_MASK_VALUE_PAIRS_IP_TTL_MASK_LEN 1
26738#define MAE_FIELD_MASK_VALUE_PAIRS_IP_TTL_MASK_LBN 1160
26739#define MAE_FIELD_MASK_VALUE_PAIRS_IP_TTL_MASK_WIDTH 8
26740#define MAE_FIELD_MASK_VALUE_PAIRS_IP_FLAGS_BE_OFST 148
26741#define MAE_FIELD_MASK_VALUE_PAIRS_IP_FLAGS_BE_LEN 4
26742#define MAE_FIELD_MASK_VALUE_PAIRS_IP_FLAGS_BE_LBN 1184
26743#define MAE_FIELD_MASK_VALUE_PAIRS_IP_FLAGS_BE_WIDTH 32
26744#define MAE_FIELD_MASK_VALUE_PAIRS_IP_FLAGS_BE_MASK_OFST 152
26745#define MAE_FIELD_MASK_VALUE_PAIRS_IP_FLAGS_BE_MASK_LEN 4
26746#define MAE_FIELD_MASK_VALUE_PAIRS_IP_FLAGS_BE_MASK_LBN 1216
26747#define MAE_FIELD_MASK_VALUE_PAIRS_IP_FLAGS_BE_MASK_WIDTH 32
26748#define MAE_FIELD_MASK_VALUE_PAIRS_L4_SPORT_BE_OFST 156
26749#define MAE_FIELD_MASK_VALUE_PAIRS_L4_SPORT_BE_LEN 2
26750#define MAE_FIELD_MASK_VALUE_PAIRS_L4_SPORT_BE_LBN 1248
26751#define MAE_FIELD_MASK_VALUE_PAIRS_L4_SPORT_BE_WIDTH 16
26752#define MAE_FIELD_MASK_VALUE_PAIRS_L4_SPORT_BE_MASK_OFST 158
26753#define MAE_FIELD_MASK_VALUE_PAIRS_L4_SPORT_BE_MASK_LEN 2
26754#define MAE_FIELD_MASK_VALUE_PAIRS_L4_SPORT_BE_MASK_LBN 1264
26755#define MAE_FIELD_MASK_VALUE_PAIRS_L4_SPORT_BE_MASK_WIDTH 16
26756#define MAE_FIELD_MASK_VALUE_PAIRS_L4_DPORT_BE_OFST 160
26757#define MAE_FIELD_MASK_VALUE_PAIRS_L4_DPORT_BE_LEN 2
26758#define MAE_FIELD_MASK_VALUE_PAIRS_L4_DPORT_BE_LBN 1280
26759#define MAE_FIELD_MASK_VALUE_PAIRS_L4_DPORT_BE_WIDTH 16
26760#define MAE_FIELD_MASK_VALUE_PAIRS_L4_DPORT_BE_MASK_OFST 162
26761#define MAE_FIELD_MASK_VALUE_PAIRS_L4_DPORT_BE_MASK_LEN 2
26762#define MAE_FIELD_MASK_VALUE_PAIRS_L4_DPORT_BE_MASK_LBN 1296
26763#define MAE_FIELD_MASK_VALUE_PAIRS_L4_DPORT_BE_MASK_WIDTH 16
26764#define MAE_FIELD_MASK_VALUE_PAIRS_TCP_FLAGS_BE_OFST 164
26765#define MAE_FIELD_MASK_VALUE_PAIRS_TCP_FLAGS_BE_LEN 2
26766#define MAE_FIELD_MASK_VALUE_PAIRS_TCP_FLAGS_BE_LBN 1312
26767#define MAE_FIELD_MASK_VALUE_PAIRS_TCP_FLAGS_BE_WIDTH 16
26768#define MAE_FIELD_MASK_VALUE_PAIRS_TCP_FLAGS_BE_MASK_OFST 166
26769#define MAE_FIELD_MASK_VALUE_PAIRS_TCP_FLAGS_BE_MASK_LEN 2
26770#define MAE_FIELD_MASK_VALUE_PAIRS_TCP_FLAGS_BE_MASK_LBN 1328
26771#define MAE_FIELD_MASK_VALUE_PAIRS_TCP_FLAGS_BE_MASK_WIDTH 16
26772#define MAE_FIELD_MASK_VALUE_PAIRS_ENCAP_TYPE_OFST 168
26773#define MAE_FIELD_MASK_VALUE_PAIRS_ENCAP_TYPE_LEN 4
26774#define MAE_FIELD_MASK_VALUE_PAIRS_ENCAP_TYPE_LBN 1344
26775#define MAE_FIELD_MASK_VALUE_PAIRS_ENCAP_TYPE_WIDTH 32
26776#define MAE_FIELD_MASK_VALUE_PAIRS_ENCAP_TYPE_MASK_OFST 172
26777#define MAE_FIELD_MASK_VALUE_PAIRS_ENCAP_TYPE_MASK_LEN 4
26778#define MAE_FIELD_MASK_VALUE_PAIRS_ENCAP_TYPE_MASK_LBN 1376
26779#define MAE_FIELD_MASK_VALUE_PAIRS_ENCAP_TYPE_MASK_WIDTH 32
26780#define MAE_FIELD_MASK_VALUE_PAIRS_OUTER_RULE_ID_OFST 176
26781#define MAE_FIELD_MASK_VALUE_PAIRS_OUTER_RULE_ID_LEN 4
26782#define MAE_FIELD_MASK_VALUE_PAIRS_OUTER_RULE_ID_LBN 1408
26783#define MAE_FIELD_MASK_VALUE_PAIRS_OUTER_RULE_ID_WIDTH 32
26784#define MAE_FIELD_MASK_VALUE_PAIRS_OUTER_RULE_ID_MASK_OFST 180
26785#define MAE_FIELD_MASK_VALUE_PAIRS_OUTER_RULE_ID_MASK_LEN 4
26786#define MAE_FIELD_MASK_VALUE_PAIRS_OUTER_RULE_ID_MASK_LBN 1440
26787#define MAE_FIELD_MASK_VALUE_PAIRS_OUTER_RULE_ID_MASK_WIDTH 32
26788#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_ETHER_TYPE_BE_OFST 184
26789#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_ETHER_TYPE_BE_LEN 2
26790#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_ETHER_TYPE_BE_LBN 1472
26791#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_ETHER_TYPE_BE_WIDTH 16
26792#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_ETHER_TYPE_BE_MASK_OFST 188
26793#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_ETHER_TYPE_BE_MASK_LEN 2
26794#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_ETHER_TYPE_BE_MASK_LBN 1504
26795#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_ETHER_TYPE_BE_MASK_WIDTH 16
26796#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN0_TCI_BE_OFST 192
26797#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN0_TCI_BE_LEN 2
26798#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN0_TCI_BE_LBN 1536
26799#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN0_TCI_BE_WIDTH 16
26800#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN0_TCI_BE_MASK_OFST 194
26801#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN0_TCI_BE_MASK_LEN 2
26802#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN0_TCI_BE_MASK_LBN 1552
26803#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN0_TCI_BE_MASK_WIDTH 16
26804#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN0_PROTO_BE_OFST 196
26805#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN0_PROTO_BE_LEN 2
26806#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN0_PROTO_BE_LBN 1568
26807#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN0_PROTO_BE_WIDTH 16
26808#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN0_PROTO_BE_MASK_OFST 198
26809#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN0_PROTO_BE_MASK_LEN 2
26810#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN0_PROTO_BE_MASK_LBN 1584
26811#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN0_PROTO_BE_MASK_WIDTH 16
26812#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN1_TCI_BE_OFST 200
26813#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN1_TCI_BE_LEN 2
26814#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN1_TCI_BE_LBN 1600
26815#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN1_TCI_BE_WIDTH 16
26816#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN1_TCI_BE_MASK_OFST 202
26817#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN1_TCI_BE_MASK_LEN 2
26818#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN1_TCI_BE_MASK_LBN 1616
26819#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN1_TCI_BE_MASK_WIDTH 16
26820#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN1_PROTO_BE_OFST 204
26821#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN1_PROTO_BE_LEN 2
26822#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN1_PROTO_BE_LBN 1632
26823#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN1_PROTO_BE_WIDTH 16
26824#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN1_PROTO_BE_MASK_OFST 206
26825#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN1_PROTO_BE_MASK_LEN 2
26826#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN1_PROTO_BE_MASK_LBN 1648
26827#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN1_PROTO_BE_MASK_WIDTH 16
26828#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_ETH_SADDR_BE_OFST 208
26829#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_ETH_SADDR_BE_LEN 6
26830#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_ETH_SADDR_BE_LBN 1664
26831#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_ETH_SADDR_BE_WIDTH 48
26832#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_ETH_SADDR_BE_MASK_OFST 214
26833#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_ETH_SADDR_BE_MASK_LEN 6
26834#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_ETH_SADDR_BE_MASK_LBN 1712
26835#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_ETH_SADDR_BE_MASK_WIDTH 48
26836#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_ETH_DADDR_BE_OFST 220
26837#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_ETH_DADDR_BE_LEN 6
26838#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_ETH_DADDR_BE_LBN 1760
26839#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_ETH_DADDR_BE_WIDTH 48
26840#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_ETH_DADDR_BE_MASK_OFST 226
26841#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_ETH_DADDR_BE_MASK_LEN 6
26842#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_ETH_DADDR_BE_MASK_LBN 1808
26843#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_ETH_DADDR_BE_MASK_WIDTH 48
26844#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_SRC_IP4_BE_OFST 232
26845#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_SRC_IP4_BE_LEN 4
26846#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_SRC_IP4_BE_LBN 1856
26847#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_SRC_IP4_BE_WIDTH 32
26848#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_SRC_IP4_BE_MASK_OFST 236
26849#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_SRC_IP4_BE_MASK_LEN 4
26850#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_SRC_IP4_BE_MASK_LBN 1888
26851#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_SRC_IP4_BE_MASK_WIDTH 32
26852#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_SRC_IP6_BE_OFST 240
26853#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_SRC_IP6_BE_LEN 16
26854#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_SRC_IP6_BE_LBN 1920
26855#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_SRC_IP6_BE_WIDTH 128
26856#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_SRC_IP6_BE_MASK_OFST 256
26857#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_SRC_IP6_BE_MASK_LEN 16
26858#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_SRC_IP6_BE_MASK_LBN 2048
26859#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_SRC_IP6_BE_MASK_WIDTH 128
26860#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_DST_IP4_BE_OFST 272
26861#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_DST_IP4_BE_LEN 4
26862#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_DST_IP4_BE_LBN 2176
26863#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_DST_IP4_BE_WIDTH 32
26864#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_DST_IP4_BE_MASK_OFST 276
26865#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_DST_IP4_BE_MASK_LEN 4
26866#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_DST_IP4_BE_MASK_LBN 2208
26867#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_DST_IP4_BE_MASK_WIDTH 32
26868#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_DST_IP6_BE_OFST 280
26869#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_DST_IP6_BE_LEN 16
26870#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_DST_IP6_BE_LBN 2240
26871#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_DST_IP6_BE_WIDTH 128
26872#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_DST_IP6_BE_MASK_OFST 296
26873#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_DST_IP6_BE_MASK_LEN 16
26874#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_DST_IP6_BE_MASK_LBN 2368
26875#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_DST_IP6_BE_MASK_WIDTH 128
26876#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_PROTO_OFST 312
26877#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_PROTO_LEN 1
26878#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_PROTO_LBN 2496
26879#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_PROTO_WIDTH 8
26880#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_PROTO_MASK_OFST 313
26881#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_PROTO_MASK_LEN 1
26882#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_PROTO_MASK_LBN 2504
26883#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_PROTO_MASK_WIDTH 8
26884#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_TOS_OFST 314
26885#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_TOS_LEN 1
26886#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_TOS_LBN 2512
26887#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_TOS_WIDTH 8
26888#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_TOS_MASK_OFST 315
26889#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_TOS_MASK_LEN 1
26890#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_TOS_MASK_LBN 2520
26891#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_TOS_MASK_WIDTH 8
26892#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_TTL_OFST 316
26893#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_TTL_LEN 1
26894#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_TTL_LBN 2528
26895#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_TTL_WIDTH 8
26896#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_TTL_MASK_OFST 317
26897#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_TTL_MASK_LEN 1
26898#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_TTL_MASK_LBN 2536
26899#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_TTL_MASK_WIDTH 8
26900#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_FLAGS_BE_OFST 320
26901#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_FLAGS_BE_LEN 4
26902#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_FLAGS_BE_LBN 2560
26903#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_FLAGS_BE_WIDTH 32
26904#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_FLAGS_BE_MASK_OFST 324
26905#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_FLAGS_BE_MASK_LEN 4
26906#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_FLAGS_BE_MASK_LBN 2592
26907#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_FLAGS_BE_MASK_WIDTH 32
26908#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_L4_SPORT_BE_OFST 328
26909#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_L4_SPORT_BE_LEN 2
26910#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_L4_SPORT_BE_LBN 2624
26911#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_L4_SPORT_BE_WIDTH 16
26912#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_L4_SPORT_BE_MASK_OFST 330
26913#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_L4_SPORT_BE_MASK_LEN 2
26914#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_L4_SPORT_BE_MASK_LBN 2640
26915#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_L4_SPORT_BE_MASK_WIDTH 16
26916#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_L4_DPORT_BE_OFST 332
26917#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_L4_DPORT_BE_LEN 2
26918#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_L4_DPORT_BE_LBN 2656
26919#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_L4_DPORT_BE_WIDTH 16
26920#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_L4_DPORT_BE_MASK_OFST 334
26921#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_L4_DPORT_BE_MASK_LEN 2
26922#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_L4_DPORT_BE_MASK_LBN 2672
26923#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_L4_DPORT_BE_MASK_WIDTH 16
26924#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VNET_ID_BE_OFST 336
26925#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VNET_ID_BE_LEN 4
26926#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VNET_ID_BE_LBN 2688
26927#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VNET_ID_BE_WIDTH 32
26928#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VNET_ID_BE_MASK_OFST 340
26929#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VNET_ID_BE_MASK_LEN 4
26930#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VNET_ID_BE_MASK_LBN 2720
26931#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VNET_ID_BE_MASK_WIDTH 32
26932
26933/* MAE_FIELD_MASK_VALUE_PAIRS_V2 structuredef */
26934#define MAE_FIELD_MASK_VALUE_PAIRS_V2_LEN 372
26935#define MAE_FIELD_MASK_VALUE_PAIRS_V2_INGRESS_MPORT_SELECTOR_OFST 0
26936#define MAE_FIELD_MASK_VALUE_PAIRS_V2_INGRESS_MPORT_SELECTOR_LEN 4
26937#define MAE_FIELD_MASK_VALUE_PAIRS_V2_INGRESS_MPORT_SELECTOR_LBN 0
26938#define MAE_FIELD_MASK_VALUE_PAIRS_V2_INGRESS_MPORT_SELECTOR_WIDTH 32
26939#define MAE_FIELD_MASK_VALUE_PAIRS_V2_INGRESS_MPORT_SELECTOR_MASK_OFST 4
26940#define MAE_FIELD_MASK_VALUE_PAIRS_V2_INGRESS_MPORT_SELECTOR_MASK_LEN 4
26941#define MAE_FIELD_MASK_VALUE_PAIRS_V2_INGRESS_MPORT_SELECTOR_MASK_LBN 32
26942#define MAE_FIELD_MASK_VALUE_PAIRS_V2_INGRESS_MPORT_SELECTOR_MASK_WIDTH 32
26943#define MAE_FIELD_MASK_VALUE_PAIRS_V2_MARK_OFST 8
26944#define MAE_FIELD_MASK_VALUE_PAIRS_V2_MARK_LEN 4
26945#define MAE_FIELD_MASK_VALUE_PAIRS_V2_MARK_LBN 64
26946#define MAE_FIELD_MASK_VALUE_PAIRS_V2_MARK_WIDTH 32
26947#define MAE_FIELD_MASK_VALUE_PAIRS_V2_MARK_MASK_OFST 12
26948#define MAE_FIELD_MASK_VALUE_PAIRS_V2_MARK_MASK_LEN 4
26949#define MAE_FIELD_MASK_VALUE_PAIRS_V2_MARK_MASK_LBN 96
26950#define MAE_FIELD_MASK_VALUE_PAIRS_V2_MARK_MASK_WIDTH 32
26951#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ETHER_TYPE_BE_OFST 16
26952#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ETHER_TYPE_BE_LEN 2
26953#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ETHER_TYPE_BE_LBN 128
26954#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ETHER_TYPE_BE_WIDTH 16
26955#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ETHER_TYPE_BE_MASK_OFST 18
26956#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ETHER_TYPE_BE_MASK_LEN 2
26957#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ETHER_TYPE_BE_MASK_LBN 144
26958#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ETHER_TYPE_BE_MASK_WIDTH 16
26959#define MAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN0_TCI_BE_OFST 20
26960#define MAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN0_TCI_BE_LEN 2
26961#define MAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN0_TCI_BE_LBN 160
26962#define MAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN0_TCI_BE_WIDTH 16
26963#define MAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN0_TCI_BE_MASK_OFST 22
26964#define MAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN0_TCI_BE_MASK_LEN 2
26965#define MAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN0_TCI_BE_MASK_LBN 176
26966#define MAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN0_TCI_BE_MASK_WIDTH 16
26967#define MAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN0_PROTO_BE_OFST 24
26968#define MAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN0_PROTO_BE_LEN 2
26969#define MAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN0_PROTO_BE_LBN 192
26970#define MAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN0_PROTO_BE_WIDTH 16
26971#define MAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN0_PROTO_BE_MASK_OFST 26
26972#define MAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN0_PROTO_BE_MASK_LEN 2
26973#define MAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN0_PROTO_BE_MASK_LBN 208
26974#define MAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN0_PROTO_BE_MASK_WIDTH 16
26975#define MAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN1_TCI_BE_OFST 28
26976#define MAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN1_TCI_BE_LEN 2
26977#define MAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN1_TCI_BE_LBN 224
26978#define MAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN1_TCI_BE_WIDTH 16
26979#define MAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN1_TCI_BE_MASK_OFST 30
26980#define MAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN1_TCI_BE_MASK_LEN 2
26981#define MAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN1_TCI_BE_MASK_LBN 240
26982#define MAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN1_TCI_BE_MASK_WIDTH 16
26983#define MAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN1_PROTO_BE_OFST 32
26984#define MAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN1_PROTO_BE_LEN 2
26985#define MAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN1_PROTO_BE_LBN 256
26986#define MAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN1_PROTO_BE_WIDTH 16
26987#define MAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN1_PROTO_BE_MASK_OFST 34
26988#define MAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN1_PROTO_BE_MASK_LEN 2
26989#define MAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN1_PROTO_BE_MASK_LBN 272
26990#define MAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN1_PROTO_BE_MASK_WIDTH 16
26991#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ETH_SADDR_BE_OFST 36
26992#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ETH_SADDR_BE_LEN 6
26993#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ETH_SADDR_BE_LBN 288
26994#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ETH_SADDR_BE_WIDTH 48
26995#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ETH_SADDR_BE_MASK_OFST 42
26996#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ETH_SADDR_BE_MASK_LEN 6
26997#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ETH_SADDR_BE_MASK_LBN 336
26998#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ETH_SADDR_BE_MASK_WIDTH 48
26999#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ETH_DADDR_BE_OFST 48
27000#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ETH_DADDR_BE_LEN 6
27001#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ETH_DADDR_BE_LBN 384
27002#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ETH_DADDR_BE_WIDTH 48
27003#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ETH_DADDR_BE_MASK_OFST 54
27004#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ETH_DADDR_BE_MASK_LEN 6
27005#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ETH_DADDR_BE_MASK_LBN 432
27006#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ETH_DADDR_BE_MASK_WIDTH 48
27007#define MAE_FIELD_MASK_VALUE_PAIRS_V2_SRC_IP4_BE_OFST 60
27008#define MAE_FIELD_MASK_VALUE_PAIRS_V2_SRC_IP4_BE_LEN 4
27009#define MAE_FIELD_MASK_VALUE_PAIRS_V2_SRC_IP4_BE_LBN 480
27010#define MAE_FIELD_MASK_VALUE_PAIRS_V2_SRC_IP4_BE_WIDTH 32
27011#define MAE_FIELD_MASK_VALUE_PAIRS_V2_SRC_IP4_BE_MASK_OFST 64
27012#define MAE_FIELD_MASK_VALUE_PAIRS_V2_SRC_IP4_BE_MASK_LEN 4
27013#define MAE_FIELD_MASK_VALUE_PAIRS_V2_SRC_IP4_BE_MASK_LBN 512
27014#define MAE_FIELD_MASK_VALUE_PAIRS_V2_SRC_IP4_BE_MASK_WIDTH 32
27015#define MAE_FIELD_MASK_VALUE_PAIRS_V2_SRC_IP6_BE_OFST 68
27016#define MAE_FIELD_MASK_VALUE_PAIRS_V2_SRC_IP6_BE_LEN 16
27017#define MAE_FIELD_MASK_VALUE_PAIRS_V2_SRC_IP6_BE_LBN 544
27018#define MAE_FIELD_MASK_VALUE_PAIRS_V2_SRC_IP6_BE_WIDTH 128
27019#define MAE_FIELD_MASK_VALUE_PAIRS_V2_SRC_IP6_BE_MASK_OFST 84
27020#define MAE_FIELD_MASK_VALUE_PAIRS_V2_SRC_IP6_BE_MASK_LEN 16
27021#define MAE_FIELD_MASK_VALUE_PAIRS_V2_SRC_IP6_BE_MASK_LBN 672
27022#define MAE_FIELD_MASK_VALUE_PAIRS_V2_SRC_IP6_BE_MASK_WIDTH 128
27023#define MAE_FIELD_MASK_VALUE_PAIRS_V2_DST_IP4_BE_OFST 100
27024#define MAE_FIELD_MASK_VALUE_PAIRS_V2_DST_IP4_BE_LEN 4
27025#define MAE_FIELD_MASK_VALUE_PAIRS_V2_DST_IP4_BE_LBN 800
27026#define MAE_FIELD_MASK_VALUE_PAIRS_V2_DST_IP4_BE_WIDTH 32
27027#define MAE_FIELD_MASK_VALUE_PAIRS_V2_DST_IP4_BE_MASK_OFST 104
27028#define MAE_FIELD_MASK_VALUE_PAIRS_V2_DST_IP4_BE_MASK_LEN 4
27029#define MAE_FIELD_MASK_VALUE_PAIRS_V2_DST_IP4_BE_MASK_LBN 832
27030#define MAE_FIELD_MASK_VALUE_PAIRS_V2_DST_IP4_BE_MASK_WIDTH 32
27031#define MAE_FIELD_MASK_VALUE_PAIRS_V2_DST_IP6_BE_OFST 108
27032#define MAE_FIELD_MASK_VALUE_PAIRS_V2_DST_IP6_BE_LEN 16
27033#define MAE_FIELD_MASK_VALUE_PAIRS_V2_DST_IP6_BE_LBN 864
27034#define MAE_FIELD_MASK_VALUE_PAIRS_V2_DST_IP6_BE_WIDTH 128
27035#define MAE_FIELD_MASK_VALUE_PAIRS_V2_DST_IP6_BE_MASK_OFST 124
27036#define MAE_FIELD_MASK_VALUE_PAIRS_V2_DST_IP6_BE_MASK_LEN 16
27037#define MAE_FIELD_MASK_VALUE_PAIRS_V2_DST_IP6_BE_MASK_LBN 992
27038#define MAE_FIELD_MASK_VALUE_PAIRS_V2_DST_IP6_BE_MASK_WIDTH 128
27039#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_PROTO_OFST 140
27040#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_PROTO_LEN 1
27041#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_PROTO_LBN 1120
27042#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_PROTO_WIDTH 8
27043#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_PROTO_MASK_OFST 141
27044#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_PROTO_MASK_LEN 1
27045#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_PROTO_MASK_LBN 1128
27046#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_PROTO_MASK_WIDTH 8
27047#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_TOS_OFST 142
27048#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_TOS_LEN 1
27049#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_TOS_LBN 1136
27050#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_TOS_WIDTH 8
27051#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_TOS_MASK_OFST 143
27052#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_TOS_MASK_LEN 1
27053#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_TOS_MASK_LBN 1144
27054#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_TOS_MASK_WIDTH 8
27055/* Due to hardware limitations, firmware may return
27056 * MC_CMD_ERR_EINVAL(BAD_IP_TTL) when attempting to match on an IP_TTL value
27057 * other than 1.
27058 */
27059#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_TTL_OFST 144
27060#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_TTL_LEN 1
27061#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_TTL_LBN 1152
27062#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_TTL_WIDTH 8
27063#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_TTL_MASK_OFST 145
27064#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_TTL_MASK_LEN 1
27065#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_TTL_MASK_LBN 1160
27066#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_TTL_MASK_WIDTH 8
27067#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_FLAGS_BE_OFST 148
27068#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_FLAGS_BE_LEN 4
27069#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_FLAGS_BE_LBN 1184
27070#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_FLAGS_BE_WIDTH 32
27071#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_FLAGS_BE_MASK_OFST 152
27072#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_FLAGS_BE_MASK_LEN 4
27073#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_FLAGS_BE_MASK_LBN 1216
27074#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_FLAGS_BE_MASK_WIDTH 32
27075#define MAE_FIELD_MASK_VALUE_PAIRS_V2_L4_SPORT_BE_OFST 156
27076#define MAE_FIELD_MASK_VALUE_PAIRS_V2_L4_SPORT_BE_LEN 2
27077#define MAE_FIELD_MASK_VALUE_PAIRS_V2_L4_SPORT_BE_LBN 1248
27078#define MAE_FIELD_MASK_VALUE_PAIRS_V2_L4_SPORT_BE_WIDTH 16
27079#define MAE_FIELD_MASK_VALUE_PAIRS_V2_L4_SPORT_BE_MASK_OFST 158
27080#define MAE_FIELD_MASK_VALUE_PAIRS_V2_L4_SPORT_BE_MASK_LEN 2
27081#define MAE_FIELD_MASK_VALUE_PAIRS_V2_L4_SPORT_BE_MASK_LBN 1264
27082#define MAE_FIELD_MASK_VALUE_PAIRS_V2_L4_SPORT_BE_MASK_WIDTH 16
27083#define MAE_FIELD_MASK_VALUE_PAIRS_V2_L4_DPORT_BE_OFST 160
27084#define MAE_FIELD_MASK_VALUE_PAIRS_V2_L4_DPORT_BE_LEN 2
27085#define MAE_FIELD_MASK_VALUE_PAIRS_V2_L4_DPORT_BE_LBN 1280
27086#define MAE_FIELD_MASK_VALUE_PAIRS_V2_L4_DPORT_BE_WIDTH 16
27087#define MAE_FIELD_MASK_VALUE_PAIRS_V2_L4_DPORT_BE_MASK_OFST 162
27088#define MAE_FIELD_MASK_VALUE_PAIRS_V2_L4_DPORT_BE_MASK_LEN 2
27089#define MAE_FIELD_MASK_VALUE_PAIRS_V2_L4_DPORT_BE_MASK_LBN 1296
27090#define MAE_FIELD_MASK_VALUE_PAIRS_V2_L4_DPORT_BE_MASK_WIDTH 16
27091#define MAE_FIELD_MASK_VALUE_PAIRS_V2_TCP_FLAGS_BE_OFST 164
27092#define MAE_FIELD_MASK_VALUE_PAIRS_V2_TCP_FLAGS_BE_LEN 2
27093#define MAE_FIELD_MASK_VALUE_PAIRS_V2_TCP_FLAGS_BE_LBN 1312
27094#define MAE_FIELD_MASK_VALUE_PAIRS_V2_TCP_FLAGS_BE_WIDTH 16
27095#define MAE_FIELD_MASK_VALUE_PAIRS_V2_TCP_FLAGS_BE_MASK_OFST 166
27096#define MAE_FIELD_MASK_VALUE_PAIRS_V2_TCP_FLAGS_BE_MASK_LEN 2
27097#define MAE_FIELD_MASK_VALUE_PAIRS_V2_TCP_FLAGS_BE_MASK_LBN 1328
27098#define MAE_FIELD_MASK_VALUE_PAIRS_V2_TCP_FLAGS_BE_MASK_WIDTH 16
27099#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENCAP_TYPE_OFST 168
27100#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENCAP_TYPE_LEN 4
27101#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENCAP_TYPE_LBN 1344
27102#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENCAP_TYPE_WIDTH 32
27103#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENCAP_TYPE_MASK_OFST 172
27104#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENCAP_TYPE_MASK_LEN 4
27105#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENCAP_TYPE_MASK_LBN 1376
27106#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENCAP_TYPE_MASK_WIDTH 32
27107#define MAE_FIELD_MASK_VALUE_PAIRS_V2_OUTER_RULE_ID_OFST 176
27108#define MAE_FIELD_MASK_VALUE_PAIRS_V2_OUTER_RULE_ID_LEN 4
27109#define MAE_FIELD_MASK_VALUE_PAIRS_V2_OUTER_RULE_ID_LBN 1408
27110#define MAE_FIELD_MASK_VALUE_PAIRS_V2_OUTER_RULE_ID_WIDTH 32
27111#define MAE_FIELD_MASK_VALUE_PAIRS_V2_OUTER_RULE_ID_MASK_OFST 180
27112#define MAE_FIELD_MASK_VALUE_PAIRS_V2_OUTER_RULE_ID_MASK_LEN 4
27113#define MAE_FIELD_MASK_VALUE_PAIRS_V2_OUTER_RULE_ID_MASK_LBN 1440
27114#define MAE_FIELD_MASK_VALUE_PAIRS_V2_OUTER_RULE_ID_MASK_WIDTH 32
27115#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_ETHER_TYPE_BE_OFST 184
27116#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_ETHER_TYPE_BE_LEN 2
27117#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_ETHER_TYPE_BE_LBN 1472
27118#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_ETHER_TYPE_BE_WIDTH 16
27119#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_ETHER_TYPE_BE_MASK_OFST 188
27120#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_ETHER_TYPE_BE_MASK_LEN 2
27121#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_ETHER_TYPE_BE_MASK_LBN 1504
27122#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_ETHER_TYPE_BE_MASK_WIDTH 16
27123#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN0_TCI_BE_OFST 192
27124#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN0_TCI_BE_LEN 2
27125#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN0_TCI_BE_LBN 1536
27126#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN0_TCI_BE_WIDTH 16
27127#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN0_TCI_BE_MASK_OFST 194
27128#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN0_TCI_BE_MASK_LEN 2
27129#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN0_TCI_BE_MASK_LBN 1552
27130#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN0_TCI_BE_MASK_WIDTH 16
27131#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN0_PROTO_BE_OFST 196
27132#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN0_PROTO_BE_LEN 2
27133#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN0_PROTO_BE_LBN 1568
27134#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN0_PROTO_BE_WIDTH 16
27135#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN0_PROTO_BE_MASK_OFST 198
27136#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN0_PROTO_BE_MASK_LEN 2
27137#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN0_PROTO_BE_MASK_LBN 1584
27138#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN0_PROTO_BE_MASK_WIDTH 16
27139#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN1_TCI_BE_OFST 200
27140#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN1_TCI_BE_LEN 2
27141#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN1_TCI_BE_LBN 1600
27142#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN1_TCI_BE_WIDTH 16
27143#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN1_TCI_BE_MASK_OFST 202
27144#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN1_TCI_BE_MASK_LEN 2
27145#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN1_TCI_BE_MASK_LBN 1616
27146#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN1_TCI_BE_MASK_WIDTH 16
27147#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN1_PROTO_BE_OFST 204
27148#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN1_PROTO_BE_LEN 2
27149#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN1_PROTO_BE_LBN 1632
27150#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN1_PROTO_BE_WIDTH 16
27151#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN1_PROTO_BE_MASK_OFST 206
27152#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN1_PROTO_BE_MASK_LEN 2
27153#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN1_PROTO_BE_MASK_LBN 1648
27154#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN1_PROTO_BE_MASK_WIDTH 16
27155#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_ETH_SADDR_BE_OFST 208
27156#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_ETH_SADDR_BE_LEN 6
27157#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_ETH_SADDR_BE_LBN 1664
27158#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_ETH_SADDR_BE_WIDTH 48
27159#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_ETH_SADDR_BE_MASK_OFST 214
27160#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_ETH_SADDR_BE_MASK_LEN 6
27161#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_ETH_SADDR_BE_MASK_LBN 1712
27162#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_ETH_SADDR_BE_MASK_WIDTH 48
27163#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_ETH_DADDR_BE_OFST 220
27164#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_ETH_DADDR_BE_LEN 6
27165#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_ETH_DADDR_BE_LBN 1760
27166#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_ETH_DADDR_BE_WIDTH 48
27167#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_ETH_DADDR_BE_MASK_OFST 226
27168#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_ETH_DADDR_BE_MASK_LEN 6
27169#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_ETH_DADDR_BE_MASK_LBN 1808
27170#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_ETH_DADDR_BE_MASK_WIDTH 48
27171#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_SRC_IP4_BE_OFST 232
27172#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_SRC_IP4_BE_LEN 4
27173#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_SRC_IP4_BE_LBN 1856
27174#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_SRC_IP4_BE_WIDTH 32
27175#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_SRC_IP4_BE_MASK_OFST 236
27176#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_SRC_IP4_BE_MASK_LEN 4
27177#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_SRC_IP4_BE_MASK_LBN 1888
27178#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_SRC_IP4_BE_MASK_WIDTH 32
27179#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_SRC_IP6_BE_OFST 240
27180#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_SRC_IP6_BE_LEN 16
27181#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_SRC_IP6_BE_LBN 1920
27182#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_SRC_IP6_BE_WIDTH 128
27183#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_SRC_IP6_BE_MASK_OFST 256
27184#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_SRC_IP6_BE_MASK_LEN 16
27185#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_SRC_IP6_BE_MASK_LBN 2048
27186#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_SRC_IP6_BE_MASK_WIDTH 128
27187#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_DST_IP4_BE_OFST 272
27188#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_DST_IP4_BE_LEN 4
27189#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_DST_IP4_BE_LBN 2176
27190#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_DST_IP4_BE_WIDTH 32
27191#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_DST_IP4_BE_MASK_OFST 276
27192#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_DST_IP4_BE_MASK_LEN 4
27193#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_DST_IP4_BE_MASK_LBN 2208
27194#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_DST_IP4_BE_MASK_WIDTH 32
27195#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_DST_IP6_BE_OFST 280
27196#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_DST_IP6_BE_LEN 16
27197#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_DST_IP6_BE_LBN 2240
27198#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_DST_IP6_BE_WIDTH 128
27199#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_DST_IP6_BE_MASK_OFST 296
27200#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_DST_IP6_BE_MASK_LEN 16
27201#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_DST_IP6_BE_MASK_LBN 2368
27202#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_DST_IP6_BE_MASK_WIDTH 128
27203#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_PROTO_OFST 312
27204#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_PROTO_LEN 1
27205#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_PROTO_LBN 2496
27206#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_PROTO_WIDTH 8
27207#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_PROTO_MASK_OFST 313
27208#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_PROTO_MASK_LEN 1
27209#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_PROTO_MASK_LBN 2504
27210#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_PROTO_MASK_WIDTH 8
27211#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_TOS_OFST 314
27212#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_TOS_LEN 1
27213#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_TOS_LBN 2512
27214#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_TOS_WIDTH 8
27215#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_TOS_MASK_OFST 315
27216#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_TOS_MASK_LEN 1
27217#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_TOS_MASK_LBN 2520
27218#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_TOS_MASK_WIDTH 8
27219#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_TTL_OFST 316
27220#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_TTL_LEN 1
27221#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_TTL_LBN 2528
27222#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_TTL_WIDTH 8
27223#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_TTL_MASK_OFST 317
27224#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_TTL_MASK_LEN 1
27225#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_TTL_MASK_LBN 2536
27226#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_TTL_MASK_WIDTH 8
27227#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_FLAGS_BE_OFST 320
27228#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_FLAGS_BE_LEN 4
27229#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_FLAGS_BE_LBN 2560
27230#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_FLAGS_BE_WIDTH 32
27231#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_FLAGS_BE_MASK_OFST 324
27232#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_FLAGS_BE_MASK_LEN 4
27233#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_FLAGS_BE_MASK_LBN 2592
27234#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_FLAGS_BE_MASK_WIDTH 32
27235#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_L4_SPORT_BE_OFST 328
27236#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_L4_SPORT_BE_LEN 2
27237#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_L4_SPORT_BE_LBN 2624
27238#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_L4_SPORT_BE_WIDTH 16
27239#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_L4_SPORT_BE_MASK_OFST 330
27240#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_L4_SPORT_BE_MASK_LEN 2
27241#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_L4_SPORT_BE_MASK_LBN 2640
27242#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_L4_SPORT_BE_MASK_WIDTH 16
27243#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_L4_DPORT_BE_OFST 332
27244#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_L4_DPORT_BE_LEN 2
27245#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_L4_DPORT_BE_LBN 2656
27246#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_L4_DPORT_BE_WIDTH 16
27247#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_L4_DPORT_BE_MASK_OFST 334
27248#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_L4_DPORT_BE_MASK_LEN 2
27249#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_L4_DPORT_BE_MASK_LBN 2672
27250#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_L4_DPORT_BE_MASK_WIDTH 16
27251#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VNET_ID_BE_OFST 336
27252#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VNET_ID_BE_LEN 4
27253#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VNET_ID_BE_LBN 2688
27254#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VNET_ID_BE_WIDTH 32
27255#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VNET_ID_BE_MASK_OFST 340
27256#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VNET_ID_BE_MASK_LEN 4
27257#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VNET_ID_BE_MASK_LBN 2720
27258#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VNET_ID_BE_MASK_WIDTH 32
27259#define MAE_FIELD_MASK_VALUE_PAIRS_V2_FLAGS_OFST 344
27260#define MAE_FIELD_MASK_VALUE_PAIRS_V2_FLAGS_LEN 4
27261#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IS_IP_FRAG_OFST 344
27262#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IS_IP_FRAG_LBN 0
27263#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IS_IP_FRAG_WIDTH 1
27264#define MAE_FIELD_MASK_VALUE_PAIRS_V2_DO_CT_OFST 344
27265#define MAE_FIELD_MASK_VALUE_PAIRS_V2_DO_CT_LBN 1
27266#define MAE_FIELD_MASK_VALUE_PAIRS_V2_DO_CT_WIDTH 1
27267#define MAE_FIELD_MASK_VALUE_PAIRS_V2_CT_HIT_OFST 344
27268#define MAE_FIELD_MASK_VALUE_PAIRS_V2_CT_HIT_LBN 2
27269#define MAE_FIELD_MASK_VALUE_PAIRS_V2_CT_HIT_WIDTH 1
27270#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IS_FROM_NETWORK_OFST 344
27271#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IS_FROM_NETWORK_LBN 3
27272#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IS_FROM_NETWORK_WIDTH 1
27273#define MAE_FIELD_MASK_VALUE_PAIRS_V2_HAS_OVLAN_OFST 344
27274#define MAE_FIELD_MASK_VALUE_PAIRS_V2_HAS_OVLAN_LBN 4
27275#define MAE_FIELD_MASK_VALUE_PAIRS_V2_HAS_OVLAN_WIDTH 1
27276#define MAE_FIELD_MASK_VALUE_PAIRS_V2_HAS_IVLAN_OFST 344
27277#define MAE_FIELD_MASK_VALUE_PAIRS_V2_HAS_IVLAN_LBN 5
27278#define MAE_FIELD_MASK_VALUE_PAIRS_V2_HAS_IVLAN_WIDTH 1
27279#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_HAS_OVLAN_OFST 344
27280#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_HAS_OVLAN_LBN 6
27281#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_HAS_OVLAN_WIDTH 1
27282#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_HAS_IVLAN_OFST 344
27283#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_HAS_IVLAN_LBN 7
27284#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_HAS_IVLAN_WIDTH 1
27285#define MAE_FIELD_MASK_VALUE_PAIRS_V2_TCP_SYN_FIN_RST_OFST 344
27286#define MAE_FIELD_MASK_VALUE_PAIRS_V2_TCP_SYN_FIN_RST_LBN 8
27287#define MAE_FIELD_MASK_VALUE_PAIRS_V2_TCP_SYN_FIN_RST_WIDTH 1
27288#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_FIRST_FRAG_OFST 344
27289#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_FIRST_FRAG_LBN 9
27290#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_FIRST_FRAG_WIDTH 1
27291#define MAE_FIELD_MASK_VALUE_PAIRS_V2_FLAGS_LBN 2752
27292#define MAE_FIELD_MASK_VALUE_PAIRS_V2_FLAGS_WIDTH 32
27293#define MAE_FIELD_MASK_VALUE_PAIRS_V2_FLAGS_MASK_OFST 348
27294#define MAE_FIELD_MASK_VALUE_PAIRS_V2_FLAGS_MASK_LEN 4
27295#define MAE_FIELD_MASK_VALUE_PAIRS_V2_FLAGS_MASK_LBN 2784
27296#define MAE_FIELD_MASK_VALUE_PAIRS_V2_FLAGS_MASK_WIDTH 32
27297#define MAE_FIELD_MASK_VALUE_PAIRS_V2_CT_DOMAIN_OFST 352
27298#define MAE_FIELD_MASK_VALUE_PAIRS_V2_CT_DOMAIN_LEN 2
27299#define MAE_FIELD_MASK_VALUE_PAIRS_V2_CT_DOMAIN_LBN 2816
27300#define MAE_FIELD_MASK_VALUE_PAIRS_V2_CT_DOMAIN_WIDTH 16
27301#define MAE_FIELD_MASK_VALUE_PAIRS_V2_CT_DOMAIN_MASK_OFST 354
27302#define MAE_FIELD_MASK_VALUE_PAIRS_V2_CT_DOMAIN_MASK_LEN 2
27303#define MAE_FIELD_MASK_VALUE_PAIRS_V2_CT_DOMAIN_MASK_LBN 2832
27304#define MAE_FIELD_MASK_VALUE_PAIRS_V2_CT_DOMAIN_MASK_WIDTH 16
27305#define MAE_FIELD_MASK_VALUE_PAIRS_V2_CT_MARK_OFST 356
27306#define MAE_FIELD_MASK_VALUE_PAIRS_V2_CT_MARK_LEN 4
27307#define MAE_FIELD_MASK_VALUE_PAIRS_V2_CT_MARK_LBN 2848
27308#define MAE_FIELD_MASK_VALUE_PAIRS_V2_CT_MARK_WIDTH 32
27309#define MAE_FIELD_MASK_VALUE_PAIRS_V2_CT_MARK_MASK_OFST 360
27310#define MAE_FIELD_MASK_VALUE_PAIRS_V2_CT_MARK_MASK_LEN 4
27311#define MAE_FIELD_MASK_VALUE_PAIRS_V2_CT_MARK_MASK_LBN 2880
27312#define MAE_FIELD_MASK_VALUE_PAIRS_V2_CT_MARK_MASK_WIDTH 32
27313#define MAE_FIELD_MASK_VALUE_PAIRS_V2_CT_PRIVATE_FLAGS_OFST 364
27314#define MAE_FIELD_MASK_VALUE_PAIRS_V2_CT_PRIVATE_FLAGS_LEN 1
27315#define MAE_FIELD_MASK_VALUE_PAIRS_V2_CT_PRIVATE_FLAGS_LBN 2912
27316#define MAE_FIELD_MASK_VALUE_PAIRS_V2_CT_PRIVATE_FLAGS_WIDTH 8
27317/* Set to zero. */
27318#define MAE_FIELD_MASK_VALUE_PAIRS_V2_RSVD2_OFST 365
27319#define MAE_FIELD_MASK_VALUE_PAIRS_V2_RSVD2_LEN 1
27320#define MAE_FIELD_MASK_VALUE_PAIRS_V2_RSVD2_LBN 2920
27321#define MAE_FIELD_MASK_VALUE_PAIRS_V2_RSVD2_WIDTH 8
27322#define MAE_FIELD_MASK_VALUE_PAIRS_V2_CT_PRIVATE_FLAGS_MASK_OFST 366
27323#define MAE_FIELD_MASK_VALUE_PAIRS_V2_CT_PRIVATE_FLAGS_MASK_LEN 1
27324#define MAE_FIELD_MASK_VALUE_PAIRS_V2_CT_PRIVATE_FLAGS_MASK_LBN 2928
27325#define MAE_FIELD_MASK_VALUE_PAIRS_V2_CT_PRIVATE_FLAGS_MASK_WIDTH 8
27326/* Set to zero. */
27327#define MAE_FIELD_MASK_VALUE_PAIRS_V2_RSVD3_OFST 367
27328#define MAE_FIELD_MASK_VALUE_PAIRS_V2_RSVD3_LEN 1
27329#define MAE_FIELD_MASK_VALUE_PAIRS_V2_RSVD3_LBN 2936
27330#define MAE_FIELD_MASK_VALUE_PAIRS_V2_RSVD3_WIDTH 8
27331#define MAE_FIELD_MASK_VALUE_PAIRS_V2_RECIRC_ID_OFST 368
27332#define MAE_FIELD_MASK_VALUE_PAIRS_V2_RECIRC_ID_LEN 1
27333#define MAE_FIELD_MASK_VALUE_PAIRS_V2_RECIRC_ID_LBN 2944
27334#define MAE_FIELD_MASK_VALUE_PAIRS_V2_RECIRC_ID_WIDTH 8
27335/* Set to zero */
27336#define MAE_FIELD_MASK_VALUE_PAIRS_V2_RSVD4_OFST 369
27337#define MAE_FIELD_MASK_VALUE_PAIRS_V2_RSVD4_LEN 1
27338#define MAE_FIELD_MASK_VALUE_PAIRS_V2_RSVD4_LBN 2952
27339#define MAE_FIELD_MASK_VALUE_PAIRS_V2_RSVD4_WIDTH 8
27340#define MAE_FIELD_MASK_VALUE_PAIRS_V2_RECIRC_ID_MASK_OFST 370
27341#define MAE_FIELD_MASK_VALUE_PAIRS_V2_RECIRC_ID_MASK_LEN 1
27342#define MAE_FIELD_MASK_VALUE_PAIRS_V2_RECIRC_ID_MASK_LBN 2960
27343#define MAE_FIELD_MASK_VALUE_PAIRS_V2_RECIRC_ID_MASK_WIDTH 8
27344/* Set to zero */
27345#define MAE_FIELD_MASK_VALUE_PAIRS_V2_RSVD5_OFST 371
27346#define MAE_FIELD_MASK_VALUE_PAIRS_V2_RSVD5_LEN 1
27347#define MAE_FIELD_MASK_VALUE_PAIRS_V2_RSVD5_LBN 2968
27348#define MAE_FIELD_MASK_VALUE_PAIRS_V2_RSVD5_WIDTH 8
27349
27350/* MAE_MPORT_SELECTOR structuredef: MPORTS are identified by an opaque unsigned
27351 * integer value (mport_id) that is guaranteed to be representable within
27352 * 32-bits or within any NIC interface field that needs store the value
27353 * (whichever is narrowers). This selector structure provides a stable way to
27354 * refer to m-ports.
27355 */
27356#define MAE_MPORT_SELECTOR_LEN 4
27357/* Used to force the tools to output bitfield-style defines for this structure.
27358 */
27359#define MAE_MPORT_SELECTOR_FLAT_OFST 0
27360#define MAE_MPORT_SELECTOR_FLAT_LEN 4
27361/* enum: An m-port selector value that is guaranteed never to represent a real
27362 * mport
27363 */
27364#define MAE_MPORT_SELECTOR_NULL 0x0
27365/* enum: The m-port assigned to the calling client. */
27366#define MAE_MPORT_SELECTOR_ASSIGNED 0x1000000
27367#define MAE_MPORT_SELECTOR_TYPE_OFST 0
27368#define MAE_MPORT_SELECTOR_TYPE_LBN 24
27369#define MAE_MPORT_SELECTOR_TYPE_WIDTH 8
27370/* enum: The MPORT connected to a given physical port */
27371#define MAE_MPORT_SELECTOR_TYPE_PPORT 0x2
27372/* enum: The MPORT assigned to a given PCIe function. Deprecated in favour of
27373 * MH_FUNC.
27374 */
27375#define MAE_MPORT_SELECTOR_TYPE_FUNC 0x3
27376/* enum: An mport_id */
27377#define MAE_MPORT_SELECTOR_TYPE_MPORT_ID 0x4
27378/* enum: The MPORT assigned to a given PCIe function (see also FWRIVERHD-1108)
27379 */
27380#define MAE_MPORT_SELECTOR_TYPE_MH_FUNC 0x5
27381/* enum: This is guaranteed never to be a valid selector type */
27382#define MAE_MPORT_SELECTOR_TYPE_INVALID 0xff
27383#define MAE_MPORT_SELECTOR_MPORT_ID_OFST 0
27384#define MAE_MPORT_SELECTOR_MPORT_ID_LBN 0
27385#define MAE_MPORT_SELECTOR_MPORT_ID_WIDTH 24
27386#define MAE_MPORT_SELECTOR_PPORT_ID_OFST 0
27387#define MAE_MPORT_SELECTOR_PPORT_ID_LBN 0
27388#define MAE_MPORT_SELECTOR_PPORT_ID_WIDTH 4
27389#define MAE_MPORT_SELECTOR_FUNC_INTF_ID_OFST 0
27390#define MAE_MPORT_SELECTOR_FUNC_INTF_ID_LBN 20
27391#define MAE_MPORT_SELECTOR_FUNC_INTF_ID_WIDTH 4
27392#define MAE_MPORT_SELECTOR_HOST_PRIMARY 0x1 /* enum */
27393#define MAE_MPORT_SELECTOR_NIC_EMBEDDED 0x2 /* enum */
27394/* enum: Deprecated, use CALLER_INTF instead. */
27395#define MAE_MPORT_SELECTOR_CALLER 0xf
27396#define MAE_MPORT_SELECTOR_CALLER_INTF 0xf /* enum */
27397#define MAE_MPORT_SELECTOR_FUNC_MH_PF_ID_OFST 0
27398#define MAE_MPORT_SELECTOR_FUNC_MH_PF_ID_LBN 16
27399#define MAE_MPORT_SELECTOR_FUNC_MH_PF_ID_WIDTH 4
27400#define MAE_MPORT_SELECTOR_FUNC_PF_ID_OFST 0
27401#define MAE_MPORT_SELECTOR_FUNC_PF_ID_LBN 16
27402#define MAE_MPORT_SELECTOR_FUNC_PF_ID_WIDTH 8
27403#define MAE_MPORT_SELECTOR_FUNC_VF_ID_OFST 0
27404#define MAE_MPORT_SELECTOR_FUNC_VF_ID_LBN 0
27405#define MAE_MPORT_SELECTOR_FUNC_VF_ID_WIDTH 16
27406/* enum: Used for VF_ID to indicate a physical function. */
27407#define MAE_MPORT_SELECTOR_FUNC_VF_ID_NULL 0xffff
27408/* enum: Used for PF_ID to indicate the physical function of the calling
27409 * client. - When used by a PF with VF_ID == VF_ID_NULL, the mport selector
27410 * relates to the calling function. (For clarity, it is recommended that
27411 * clients use ASSIGNED to achieve this behaviour). - When used by a PF with
27412 * VF_ID != VF_ID_NULL, the mport selector relates to a VF child of the calling
27413 * function. - When used by a VF with VF_ID == VF_ID_NULL, the mport selector
27414 * relates to the PF owning the calling function. - When used by a VF with
27415 * VF_ID != VF_ID_NULL, the mport selector relates to a sibling VF of the
27416 * calling function. - Not meaningful used by a client that is not a PCIe
27417 * function.
27418 */
27419#define MAE_MPORT_SELECTOR_FUNC_PF_ID_CALLER 0xff
27420/* enum: Same as PF_ID_CALLER, but for use in the smaller MH_PF_ID field. Only
27421 * valid if FUNC_INTF_ID is CALLER.
27422 */
27423#define MAE_MPORT_SELECTOR_FUNC_MH_PF_ID_CALLER 0xf
27424#define MAE_MPORT_SELECTOR_FLAT_LBN 0
27425#define MAE_MPORT_SELECTOR_FLAT_WIDTH 32
27426
27427/* MAE_LINK_ENDPOINT_SELECTOR structuredef: Structure that identifies a real or
27428 * virtual network port by MAE port and link end
27429 */
27430#define MAE_LINK_ENDPOINT_SELECTOR_LEN 8
27431/* The MAE MPORT of interest */
27432#define MAE_LINK_ENDPOINT_SELECTOR_MPORT_SELECTOR_OFST 0
27433#define MAE_LINK_ENDPOINT_SELECTOR_MPORT_SELECTOR_LEN 4
27434#define MAE_LINK_ENDPOINT_SELECTOR_MPORT_SELECTOR_LBN 0
27435#define MAE_LINK_ENDPOINT_SELECTOR_MPORT_SELECTOR_WIDTH 32
27436/* Which end of the link identified by MPORT to consider */
27437#define MAE_LINK_ENDPOINT_SELECTOR_LINK_END_OFST 4
27438#define MAE_LINK_ENDPOINT_SELECTOR_LINK_END_LEN 4
27439/* Enum values, see field(s): */
27440/* MAE_MPORT_END */
27441#define MAE_LINK_ENDPOINT_SELECTOR_LINK_END_LBN 32
27442#define MAE_LINK_ENDPOINT_SELECTOR_LINK_END_WIDTH 32
27443/* A field for accessing the endpoint selector as a collection of bits */
27444#define MAE_LINK_ENDPOINT_SELECTOR_FLAT_OFST 0
27445#define MAE_LINK_ENDPOINT_SELECTOR_FLAT_LEN 8
27446#define MAE_LINK_ENDPOINT_SELECTOR_FLAT_LO_OFST 0
27447#define MAE_LINK_ENDPOINT_SELECTOR_FLAT_LO_LEN 4
27448#define MAE_LINK_ENDPOINT_SELECTOR_FLAT_LO_LBN 0
27449#define MAE_LINK_ENDPOINT_SELECTOR_FLAT_LO_WIDTH 32
27450#define MAE_LINK_ENDPOINT_SELECTOR_FLAT_HI_OFST 4
27451#define MAE_LINK_ENDPOINT_SELECTOR_FLAT_HI_LEN 4
27452#define MAE_LINK_ENDPOINT_SELECTOR_FLAT_HI_LBN 32
27453#define MAE_LINK_ENDPOINT_SELECTOR_FLAT_HI_WIDTH 32
27454/* enum: Set FLAT to this value to obtain backward-compatible behaviour in
27455 * commands that have been extended to take a MAE_LINK_ENDPOINT_SELECTOR
27456 * argument. New commands that are designed to take such an argument from the
27457 * start will not support this.
27458 */
27459#define MAE_LINK_ENDPOINT_SELECTOR_MAE_LINK_ENDPOINT_COMPAT 0x0
27460#define MAE_LINK_ENDPOINT_SELECTOR_FLAT_LBN 0
27461#define MAE_LINK_ENDPOINT_SELECTOR_FLAT_WIDTH 64
27462
27463
27464/***********************************/
27465/* MC_CMD_MAE_GET_CAPS
27466 * Describes capabilities of the MAE (Match-Action Engine)
27467 */
27468#define MC_CMD_MAE_GET_CAPS 0x140
27469#undef MC_CMD_0x140_PRIVILEGE_CTG
27470
27471#define MC_CMD_0x140_PRIVILEGE_CTG SRIOV_CTG_GENERAL
27472
27473/* MC_CMD_MAE_GET_CAPS_IN msgrequest */
27474#define MC_CMD_MAE_GET_CAPS_IN_LEN 0
27475
27476/* MC_CMD_MAE_GET_CAPS_OUT msgresponse */
27477#define MC_CMD_MAE_GET_CAPS_OUT_LEN 52
27478/* The number of field IDs that the NIC supports. Any field with a ID greater
27479 * than or equal to the value returned in this field must be treated as having
27480 * a support level of MAE_FIELD_UNSUPPORTED in all requests.
27481 */
27482#define MC_CMD_MAE_GET_CAPS_OUT_MATCH_FIELD_COUNT_OFST 0
27483#define MC_CMD_MAE_GET_CAPS_OUT_MATCH_FIELD_COUNT_LEN 4
27484#define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPES_SUPPORTED_OFST 4
27485#define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPES_SUPPORTED_LEN 4
27486#define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_VXLAN_OFST 4
27487#define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_VXLAN_LBN 0
27488#define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_VXLAN_WIDTH 1
27489#define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_NVGRE_OFST 4
27490#define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_NVGRE_LBN 1
27491#define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_NVGRE_WIDTH 1
27492#define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_GENEVE_OFST 4
27493#define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_GENEVE_LBN 2
27494#define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_GENEVE_WIDTH 1
27495#define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_L2GRE_OFST 4
27496#define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_L2GRE_LBN 3
27497#define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_L2GRE_WIDTH 1
27498/* Deprecated alias for AR_COUNTERS. */
27499#define MC_CMD_MAE_GET_CAPS_OUT_COUNTERS_OFST 8
27500#define MC_CMD_MAE_GET_CAPS_OUT_COUNTERS_LEN 4
27501/* The total number of AR counters available to allocate. */
27502#define MC_CMD_MAE_GET_CAPS_OUT_AR_COUNTERS_OFST 8
27503#define MC_CMD_MAE_GET_CAPS_OUT_AR_COUNTERS_LEN 4
27504/* The total number of counters lists available to allocate. A value of zero
27505 * indicates that counter lists are not supported by the NIC. (But single
27506 * counters may still be.)
27507 */
27508#define MC_CMD_MAE_GET_CAPS_OUT_COUNTER_LISTS_OFST 12
27509#define MC_CMD_MAE_GET_CAPS_OUT_COUNTER_LISTS_LEN 4
27510/* The total number of encap header structures available to allocate. */
27511#define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_HEADER_LIMIT_OFST 16
27512#define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_HEADER_LIMIT_LEN 4
27513/* Reserved. Should be zero. */
27514#define MC_CMD_MAE_GET_CAPS_OUT_RSVD_OFST 20
27515#define MC_CMD_MAE_GET_CAPS_OUT_RSVD_LEN 4
27516/* The total number of action sets available to allocate. */
27517#define MC_CMD_MAE_GET_CAPS_OUT_ACTION_SETS_OFST 24
27518#define MC_CMD_MAE_GET_CAPS_OUT_ACTION_SETS_LEN 4
27519/* The total number of action set lists available to allocate. */
27520#define MC_CMD_MAE_GET_CAPS_OUT_ACTION_SET_LISTS_OFST 28
27521#define MC_CMD_MAE_GET_CAPS_OUT_ACTION_SET_LISTS_LEN 4
27522/* The total number of outer rules available to allocate. */
27523#define MC_CMD_MAE_GET_CAPS_OUT_OUTER_RULES_OFST 32
27524#define MC_CMD_MAE_GET_CAPS_OUT_OUTER_RULES_LEN 4
27525/* The total number of action rules available to allocate. */
27526#define MC_CMD_MAE_GET_CAPS_OUT_ACTION_RULES_OFST 36
27527#define MC_CMD_MAE_GET_CAPS_OUT_ACTION_RULES_LEN 4
27528/* The number of priorities available for ACTION_RULE filters. It is invalid to
27529 * install a MATCH_ACTION filter with a priority number >= ACTION_PRIOS.
27530 */
27531#define MC_CMD_MAE_GET_CAPS_OUT_ACTION_PRIOS_OFST 40
27532#define MC_CMD_MAE_GET_CAPS_OUT_ACTION_PRIOS_LEN 4
27533/* The number of priorities available for OUTER_RULE filters. It is invalid to
27534 * install an OUTER_RULE filter with a priority number >= OUTER_PRIOS.
27535 */
27536#define MC_CMD_MAE_GET_CAPS_OUT_OUTER_PRIOS_OFST 44
27537#define MC_CMD_MAE_GET_CAPS_OUT_OUTER_PRIOS_LEN 4
27538/* MAE API major version. Currently 1. If this field is not present in the
27539 * response (i.e. response shorter than 384 bits), then its value is zero. If
27540 * the value does not match the client's expectations, the client should raise
27541 * a fatal error.
27542 */
27543#define MC_CMD_MAE_GET_CAPS_OUT_API_VER_OFST 48
27544#define MC_CMD_MAE_GET_CAPS_OUT_API_VER_LEN 4
27545
27546/* MC_CMD_MAE_GET_CAPS_V2_OUT msgresponse */
27547#define MC_CMD_MAE_GET_CAPS_V2_OUT_LEN 60
27548/* The number of field IDs that the NIC supports. Any field with a ID greater
27549 * than or equal to the value returned in this field must be treated as having
27550 * a support level of MAE_FIELD_UNSUPPORTED in all requests.
27551 */
27552#define MC_CMD_MAE_GET_CAPS_V2_OUT_MATCH_FIELD_COUNT_OFST 0
27553#define MC_CMD_MAE_GET_CAPS_V2_OUT_MATCH_FIELD_COUNT_LEN 4
27554#define MC_CMD_MAE_GET_CAPS_V2_OUT_ENCAP_TYPES_SUPPORTED_OFST 4
27555#define MC_CMD_MAE_GET_CAPS_V2_OUT_ENCAP_TYPES_SUPPORTED_LEN 4
27556#define MC_CMD_MAE_GET_CAPS_V2_OUT_ENCAP_TYPE_VXLAN_OFST 4
27557#define MC_CMD_MAE_GET_CAPS_V2_OUT_ENCAP_TYPE_VXLAN_LBN 0
27558#define MC_CMD_MAE_GET_CAPS_V2_OUT_ENCAP_TYPE_VXLAN_WIDTH 1
27559#define MC_CMD_MAE_GET_CAPS_V2_OUT_ENCAP_TYPE_NVGRE_OFST 4
27560#define MC_CMD_MAE_GET_CAPS_V2_OUT_ENCAP_TYPE_NVGRE_LBN 1
27561#define MC_CMD_MAE_GET_CAPS_V2_OUT_ENCAP_TYPE_NVGRE_WIDTH 1
27562#define MC_CMD_MAE_GET_CAPS_V2_OUT_ENCAP_TYPE_GENEVE_OFST 4
27563#define MC_CMD_MAE_GET_CAPS_V2_OUT_ENCAP_TYPE_GENEVE_LBN 2
27564#define MC_CMD_MAE_GET_CAPS_V2_OUT_ENCAP_TYPE_GENEVE_WIDTH 1
27565#define MC_CMD_MAE_GET_CAPS_V2_OUT_ENCAP_TYPE_L2GRE_OFST 4
27566#define MC_CMD_MAE_GET_CAPS_V2_OUT_ENCAP_TYPE_L2GRE_LBN 3
27567#define MC_CMD_MAE_GET_CAPS_V2_OUT_ENCAP_TYPE_L2GRE_WIDTH 1
27568/* Deprecated alias for AR_COUNTERS. */
27569#define MC_CMD_MAE_GET_CAPS_V2_OUT_COUNTERS_OFST 8
27570#define MC_CMD_MAE_GET_CAPS_V2_OUT_COUNTERS_LEN 4
27571/* The total number of AR counters available to allocate. */
27572#define MC_CMD_MAE_GET_CAPS_V2_OUT_AR_COUNTERS_OFST 8
27573#define MC_CMD_MAE_GET_CAPS_V2_OUT_AR_COUNTERS_LEN 4
27574/* The total number of counters lists available to allocate. A value of zero
27575 * indicates that counter lists are not supported by the NIC. (But single
27576 * counters may still be.)
27577 */
27578#define MC_CMD_MAE_GET_CAPS_V2_OUT_COUNTER_LISTS_OFST 12
27579#define MC_CMD_MAE_GET_CAPS_V2_OUT_COUNTER_LISTS_LEN 4
27580/* The total number of encap header structures available to allocate. */
27581#define MC_CMD_MAE_GET_CAPS_V2_OUT_ENCAP_HEADER_LIMIT_OFST 16
27582#define MC_CMD_MAE_GET_CAPS_V2_OUT_ENCAP_HEADER_LIMIT_LEN 4
27583/* Reserved. Should be zero. */
27584#define MC_CMD_MAE_GET_CAPS_V2_OUT_RSVD_OFST 20
27585#define MC_CMD_MAE_GET_CAPS_V2_OUT_RSVD_LEN 4
27586/* The total number of action sets available to allocate. */
27587#define MC_CMD_MAE_GET_CAPS_V2_OUT_ACTION_SETS_OFST 24
27588#define MC_CMD_MAE_GET_CAPS_V2_OUT_ACTION_SETS_LEN 4
27589/* The total number of action set lists available to allocate. */
27590#define MC_CMD_MAE_GET_CAPS_V2_OUT_ACTION_SET_LISTS_OFST 28
27591#define MC_CMD_MAE_GET_CAPS_V2_OUT_ACTION_SET_LISTS_LEN 4
27592/* The total number of outer rules available to allocate. */
27593#define MC_CMD_MAE_GET_CAPS_V2_OUT_OUTER_RULES_OFST 32
27594#define MC_CMD_MAE_GET_CAPS_V2_OUT_OUTER_RULES_LEN 4
27595/* The total number of action rules available to allocate. */
27596#define MC_CMD_MAE_GET_CAPS_V2_OUT_ACTION_RULES_OFST 36
27597#define MC_CMD_MAE_GET_CAPS_V2_OUT_ACTION_RULES_LEN 4
27598/* The number of priorities available for ACTION_RULE filters. It is invalid to
27599 * install a MATCH_ACTION filter with a priority number >= ACTION_PRIOS.
27600 */
27601#define MC_CMD_MAE_GET_CAPS_V2_OUT_ACTION_PRIOS_OFST 40
27602#define MC_CMD_MAE_GET_CAPS_V2_OUT_ACTION_PRIOS_LEN 4
27603/* The number of priorities available for OUTER_RULE filters. It is invalid to
27604 * install an OUTER_RULE filter with a priority number >= OUTER_PRIOS.
27605 */
27606#define MC_CMD_MAE_GET_CAPS_V2_OUT_OUTER_PRIOS_OFST 44
27607#define MC_CMD_MAE_GET_CAPS_V2_OUT_OUTER_PRIOS_LEN 4
27608/* MAE API major version. Currently 1. If this field is not present in the
27609 * response (i.e. response shorter than 384 bits), then its value is zero. If
27610 * the value does not match the client's expectations, the client should raise
27611 * a fatal error.
27612 */
27613#define MC_CMD_MAE_GET_CAPS_V2_OUT_API_VER_OFST 48
27614#define MC_CMD_MAE_GET_CAPS_V2_OUT_API_VER_LEN 4
27615/* Mask of supported counter types. Each bit position corresponds to a value of
27616 * the MAE_COUNTER_TYPE enum. If this field is missing (i.e. V1 response),
27617 * clients must assume that only AR counters are supported (i.e.
27618 * COUNTER_TYPES_SUPPORTED==0x1). See also
27619 * MC_CMD_MAE_COUNTERS_STREAM_START/COUNTER_TYPES_MASK.
27620 */
27621#define MC_CMD_MAE_GET_CAPS_V2_OUT_COUNTER_TYPES_SUPPORTED_OFST 52
27622#define MC_CMD_MAE_GET_CAPS_V2_OUT_COUNTER_TYPES_SUPPORTED_LEN 4
27623/* The total number of conntrack counters available to allocate. */
27624#define MC_CMD_MAE_GET_CAPS_V2_OUT_CT_COUNTERS_OFST 56
27625#define MC_CMD_MAE_GET_CAPS_V2_OUT_CT_COUNTERS_LEN 4
27626
27627/* MC_CMD_MAE_GET_CAPS_V3_OUT msgresponse */
27628#define MC_CMD_MAE_GET_CAPS_V3_OUT_LEN 64
27629/* The number of field IDs that the NIC supports. Any field with a ID greater
27630 * than or equal to the value returned in this field must be treated as having
27631 * a support level of MAE_FIELD_UNSUPPORTED in all requests.
27632 */
27633#define MC_CMD_MAE_GET_CAPS_V3_OUT_MATCH_FIELD_COUNT_OFST 0
27634#define MC_CMD_MAE_GET_CAPS_V3_OUT_MATCH_FIELD_COUNT_LEN 4
27635#define MC_CMD_MAE_GET_CAPS_V3_OUT_ENCAP_TYPES_SUPPORTED_OFST 4
27636#define MC_CMD_MAE_GET_CAPS_V3_OUT_ENCAP_TYPES_SUPPORTED_LEN 4
27637#define MC_CMD_MAE_GET_CAPS_V3_OUT_ENCAP_TYPE_VXLAN_OFST 4
27638#define MC_CMD_MAE_GET_CAPS_V3_OUT_ENCAP_TYPE_VXLAN_LBN 0
27639#define MC_CMD_MAE_GET_CAPS_V3_OUT_ENCAP_TYPE_VXLAN_WIDTH 1
27640#define MC_CMD_MAE_GET_CAPS_V3_OUT_ENCAP_TYPE_NVGRE_OFST 4
27641#define MC_CMD_MAE_GET_CAPS_V3_OUT_ENCAP_TYPE_NVGRE_LBN 1
27642#define MC_CMD_MAE_GET_CAPS_V3_OUT_ENCAP_TYPE_NVGRE_WIDTH 1
27643#define MC_CMD_MAE_GET_CAPS_V3_OUT_ENCAP_TYPE_GENEVE_OFST 4
27644#define MC_CMD_MAE_GET_CAPS_V3_OUT_ENCAP_TYPE_GENEVE_LBN 2
27645#define MC_CMD_MAE_GET_CAPS_V3_OUT_ENCAP_TYPE_GENEVE_WIDTH 1
27646#define MC_CMD_MAE_GET_CAPS_V3_OUT_ENCAP_TYPE_L2GRE_OFST 4
27647#define MC_CMD_MAE_GET_CAPS_V3_OUT_ENCAP_TYPE_L2GRE_LBN 3
27648#define MC_CMD_MAE_GET_CAPS_V3_OUT_ENCAP_TYPE_L2GRE_WIDTH 1
27649/* Deprecated alias for AR_COUNTERS. */
27650#define MC_CMD_MAE_GET_CAPS_V3_OUT_COUNTERS_OFST 8
27651#define MC_CMD_MAE_GET_CAPS_V3_OUT_COUNTERS_LEN 4
27652/* The total number of AR counters available to allocate. */
27653#define MC_CMD_MAE_GET_CAPS_V3_OUT_AR_COUNTERS_OFST 8
27654#define MC_CMD_MAE_GET_CAPS_V3_OUT_AR_COUNTERS_LEN 4
27655/* The total number of counters lists available to allocate. A value of zero
27656 * indicates that counter lists are not supported by the NIC. (But single
27657 * counters may still be.)
27658 */
27659#define MC_CMD_MAE_GET_CAPS_V3_OUT_COUNTER_LISTS_OFST 12
27660#define MC_CMD_MAE_GET_CAPS_V3_OUT_COUNTER_LISTS_LEN 4
27661/* The total number of encap header structures available to allocate. */
27662#define MC_CMD_MAE_GET_CAPS_V3_OUT_ENCAP_HEADER_LIMIT_OFST 16
27663#define MC_CMD_MAE_GET_CAPS_V3_OUT_ENCAP_HEADER_LIMIT_LEN 4
27664/* Reserved. Should be zero. */
27665#define MC_CMD_MAE_GET_CAPS_V3_OUT_RSVD_OFST 20
27666#define MC_CMD_MAE_GET_CAPS_V3_OUT_RSVD_LEN 4
27667/* The total number of action sets available to allocate. */
27668#define MC_CMD_MAE_GET_CAPS_V3_OUT_ACTION_SETS_OFST 24
27669#define MC_CMD_MAE_GET_CAPS_V3_OUT_ACTION_SETS_LEN 4
27670/* The total number of action set lists available to allocate. */
27671#define MC_CMD_MAE_GET_CAPS_V3_OUT_ACTION_SET_LISTS_OFST 28
27672#define MC_CMD_MAE_GET_CAPS_V3_OUT_ACTION_SET_LISTS_LEN 4
27673/* The total number of outer rules available to allocate. */
27674#define MC_CMD_MAE_GET_CAPS_V3_OUT_OUTER_RULES_OFST 32
27675#define MC_CMD_MAE_GET_CAPS_V3_OUT_OUTER_RULES_LEN 4
27676/* The total number of action rules available to allocate. */
27677#define MC_CMD_MAE_GET_CAPS_V3_OUT_ACTION_RULES_OFST 36
27678#define MC_CMD_MAE_GET_CAPS_V3_OUT_ACTION_RULES_LEN 4
27679/* The number of priorities available for ACTION_RULE filters. It is invalid to
27680 * install a MATCH_ACTION filter with a priority number >= ACTION_PRIOS.
27681 */
27682#define MC_CMD_MAE_GET_CAPS_V3_OUT_ACTION_PRIOS_OFST 40
27683#define MC_CMD_MAE_GET_CAPS_V3_OUT_ACTION_PRIOS_LEN 4
27684/* The number of priorities available for OUTER_RULE filters. It is invalid to
27685 * install an OUTER_RULE filter with a priority number >= OUTER_PRIOS.
27686 */
27687#define MC_CMD_MAE_GET_CAPS_V3_OUT_OUTER_PRIOS_OFST 44
27688#define MC_CMD_MAE_GET_CAPS_V3_OUT_OUTER_PRIOS_LEN 4
27689/* MAE API major version. Currently 1. If this field is not present in the
27690 * response (i.e. response shorter than 384 bits), then its value is zero. If
27691 * the value does not match the client's expectations, the client should raise
27692 * a fatal error.
27693 */
27694#define MC_CMD_MAE_GET_CAPS_V3_OUT_API_VER_OFST 48
27695#define MC_CMD_MAE_GET_CAPS_V3_OUT_API_VER_LEN 4
27696/* Mask of supported counter types. Each bit position corresponds to a value of
27697 * the MAE_COUNTER_TYPE enum. If this field is missing (i.e. V1 response),
27698 * clients must assume that only AR counters are supported (i.e.
27699 * COUNTER_TYPES_SUPPORTED==0x1). See also
27700 * MC_CMD_MAE_COUNTERS_STREAM_START/COUNTER_TYPES_MASK.
27701 */
27702#define MC_CMD_MAE_GET_CAPS_V3_OUT_COUNTER_TYPES_SUPPORTED_OFST 52
27703#define MC_CMD_MAE_GET_CAPS_V3_OUT_COUNTER_TYPES_SUPPORTED_LEN 4
27704/* The total number of conntrack counters available to allocate. */
27705#define MC_CMD_MAE_GET_CAPS_V3_OUT_CT_COUNTERS_OFST 56
27706#define MC_CMD_MAE_GET_CAPS_V3_OUT_CT_COUNTERS_LEN 4
27707/* The total number of Outer Rule counters available to allocate. */
27708#define MC_CMD_MAE_GET_CAPS_V3_OUT_OR_COUNTERS_OFST 60
27709#define MC_CMD_MAE_GET_CAPS_V3_OUT_OR_COUNTERS_LEN 4
27710
27711
27712/***********************************/
27713/* MC_CMD_MAE_GET_AR_CAPS
27714 * Get a level of support for match fields when used in match-action rules
27715 */
27716#define MC_CMD_MAE_GET_AR_CAPS 0x141
27717#undef MC_CMD_0x141_PRIVILEGE_CTG
27718
27719#define MC_CMD_0x141_PRIVILEGE_CTG SRIOV_CTG_MAE
27720
27721/* MC_CMD_MAE_GET_AR_CAPS_IN msgrequest */
27722#define MC_CMD_MAE_GET_AR_CAPS_IN_LEN 0
27723
27724/* MC_CMD_MAE_GET_AR_CAPS_OUT msgresponse */
27725#define MC_CMD_MAE_GET_AR_CAPS_OUT_LENMIN 4
27726#define MC_CMD_MAE_GET_AR_CAPS_OUT_LENMAX 252
27727#define MC_CMD_MAE_GET_AR_CAPS_OUT_LENMAX_MCDI2 1020
27728#define MC_CMD_MAE_GET_AR_CAPS_OUT_LEN(num) (4+4*(num))
27729#define MC_CMD_MAE_GET_AR_CAPS_OUT_FIELD_FLAGS_NUM(len) (((len)-4)/4)
27730/* Number of fields actually returned in FIELD_FLAGS. */
27731#define MC_CMD_MAE_GET_AR_CAPS_OUT_COUNT_OFST 0
27732#define MC_CMD_MAE_GET_AR_CAPS_OUT_COUNT_LEN 4
27733/* Array of values indicating the NIC's support for a given field, indexed by
27734 * field id. The driver must ensure space for
27735 * MC_CMD_MAE_GET_CAPS.MATCH_FIELD_COUNT entries in the array..
27736 */
27737#define MC_CMD_MAE_GET_AR_CAPS_OUT_FIELD_FLAGS_OFST 4
27738#define MC_CMD_MAE_GET_AR_CAPS_OUT_FIELD_FLAGS_LEN 4
27739#define MC_CMD_MAE_GET_AR_CAPS_OUT_FIELD_FLAGS_MINNUM 0
27740#define MC_CMD_MAE_GET_AR_CAPS_OUT_FIELD_FLAGS_MAXNUM 62
27741#define MC_CMD_MAE_GET_AR_CAPS_OUT_FIELD_FLAGS_MAXNUM_MCDI2 254
27742
27743
27744/***********************************/
27745/* MC_CMD_MAE_GET_OR_CAPS
27746 * Get a level of support for fields used in outer rule keys.
27747 */
27748#define MC_CMD_MAE_GET_OR_CAPS 0x142
27749#undef MC_CMD_0x142_PRIVILEGE_CTG
27750
27751#define MC_CMD_0x142_PRIVILEGE_CTG SRIOV_CTG_MAE
27752
27753/* MC_CMD_MAE_GET_OR_CAPS_IN msgrequest */
27754#define MC_CMD_MAE_GET_OR_CAPS_IN_LEN 0
27755
27756/* MC_CMD_MAE_GET_OR_CAPS_OUT msgresponse */
27757#define MC_CMD_MAE_GET_OR_CAPS_OUT_LENMIN 4
27758#define MC_CMD_MAE_GET_OR_CAPS_OUT_LENMAX 252
27759#define MC_CMD_MAE_GET_OR_CAPS_OUT_LENMAX_MCDI2 1020
27760#define MC_CMD_MAE_GET_OR_CAPS_OUT_LEN(num) (4+4*(num))
27761#define MC_CMD_MAE_GET_OR_CAPS_OUT_FIELD_FLAGS_NUM(len) (((len)-4)/4)
27762/* Number of fields actually returned in FIELD_FLAGS. */
27763#define MC_CMD_MAE_GET_OR_CAPS_OUT_COUNT_OFST 0
27764#define MC_CMD_MAE_GET_OR_CAPS_OUT_COUNT_LEN 4
27765/* Same semantics as MC_CMD_MAE_GET_AR_CAPS.MAE_FIELD_FLAGS */
27766#define MC_CMD_MAE_GET_OR_CAPS_OUT_FIELD_FLAGS_OFST 4
27767#define MC_CMD_MAE_GET_OR_CAPS_OUT_FIELD_FLAGS_LEN 4
27768#define MC_CMD_MAE_GET_OR_CAPS_OUT_FIELD_FLAGS_MINNUM 0
27769#define MC_CMD_MAE_GET_OR_CAPS_OUT_FIELD_FLAGS_MAXNUM 62
27770#define MC_CMD_MAE_GET_OR_CAPS_OUT_FIELD_FLAGS_MAXNUM_MCDI2 254
27771
27772
27773/***********************************/
27774/* MC_CMD_MAE_COUNTER_ALLOC
27775 * Allocate match-action-engine counters, which can be referenced in various
27776 * tables.
27777 */
27778#define MC_CMD_MAE_COUNTER_ALLOC 0x143
27779#undef MC_CMD_0x143_PRIVILEGE_CTG
27780
27781#define MC_CMD_0x143_PRIVILEGE_CTG SRIOV_CTG_MAE
27782
27783/* MC_CMD_MAE_COUNTER_ALLOC_IN msgrequest: Using this is equivalent to using V2
27784 * with COUNTER_TYPE=AR.
27785 */
27786#define MC_CMD_MAE_COUNTER_ALLOC_IN_LEN 4
27787/* The number of counters that the driver would like allocated */
27788#define MC_CMD_MAE_COUNTER_ALLOC_IN_REQUESTED_COUNT_OFST 0
27789#define MC_CMD_MAE_COUNTER_ALLOC_IN_REQUESTED_COUNT_LEN 4
27790
27791/* MC_CMD_MAE_COUNTER_ALLOC_V2_IN msgrequest */
27792#define MC_CMD_MAE_COUNTER_ALLOC_V2_IN_LEN 8
27793/* The number of counters that the driver would like allocated */
27794#define MC_CMD_MAE_COUNTER_ALLOC_V2_IN_REQUESTED_COUNT_OFST 0
27795#define MC_CMD_MAE_COUNTER_ALLOC_V2_IN_REQUESTED_COUNT_LEN 4
27796/* Which type of counter to allocate. */
27797#define MC_CMD_MAE_COUNTER_ALLOC_V2_IN_COUNTER_TYPE_OFST 4
27798#define MC_CMD_MAE_COUNTER_ALLOC_V2_IN_COUNTER_TYPE_LEN 4
27799/* Enum values, see field(s): */
27800/* MAE_COUNTER_TYPE */
27801
27802/* MC_CMD_MAE_COUNTER_ALLOC_OUT msgresponse */
27803#define MC_CMD_MAE_COUNTER_ALLOC_OUT_LENMIN 12
27804#define MC_CMD_MAE_COUNTER_ALLOC_OUT_LENMAX 252
27805#define MC_CMD_MAE_COUNTER_ALLOC_OUT_LENMAX_MCDI2 1020
27806#define MC_CMD_MAE_COUNTER_ALLOC_OUT_LEN(num) (8+4*(num))
27807#define MC_CMD_MAE_COUNTER_ALLOC_OUT_COUNTER_ID_NUM(len) (((len)-8)/4)
27808/* Generation count. Packets with generation count >= GENERATION_COUNT will
27809 * contain valid counter values for counter IDs allocated in this call, unless
27810 * the counter values are zero and zero squash is enabled. Note that there is
27811 * an independent GENERATION_COUNT object per counter type, and that generation
27812 * counts wrap from 0xffffffff to 1.
27813 */
27814#define MC_CMD_MAE_COUNTER_ALLOC_OUT_GENERATION_COUNT_OFST 0
27815#define MC_CMD_MAE_COUNTER_ALLOC_OUT_GENERATION_COUNT_LEN 4
27816/* enum: Generation counter 0 is reserved and unused. */
27817#define MC_CMD_MAE_COUNTER_ALLOC_OUT_GENERATION_COUNT_INVALID 0x0
27818/* The number of counter IDs that the NIC allocated. It is never less than 1;
27819 * failure to allocate a single counter will cause an error to be returned. It
27820 * is never greater than REQUESTED_COUNT, but may be less.
27821 */
27822#define MC_CMD_MAE_COUNTER_ALLOC_OUT_COUNTER_ID_COUNT_OFST 4
27823#define MC_CMD_MAE_COUNTER_ALLOC_OUT_COUNTER_ID_COUNT_LEN 4
27824/* An array containing the IDs for the counters allocated. */
27825#define MC_CMD_MAE_COUNTER_ALLOC_OUT_COUNTER_ID_OFST 8
27826#define MC_CMD_MAE_COUNTER_ALLOC_OUT_COUNTER_ID_LEN 4
27827#define MC_CMD_MAE_COUNTER_ALLOC_OUT_COUNTER_ID_MINNUM 1
27828#define MC_CMD_MAE_COUNTER_ALLOC_OUT_COUNTER_ID_MAXNUM 61
27829#define MC_CMD_MAE_COUNTER_ALLOC_OUT_COUNTER_ID_MAXNUM_MCDI2 253
27830/* enum: A counter ID that is guaranteed never to represent a real counter */
27831#define MC_CMD_MAE_COUNTER_ALLOC_OUT_COUNTER_ID_NULL 0xffffffff
27832
27833
27834/***********************************/
27835/* MC_CMD_MAE_COUNTER_FREE
27836 * Free match-action-engine counters
27837 */
27838#define MC_CMD_MAE_COUNTER_FREE 0x144
27839#undef MC_CMD_0x144_PRIVILEGE_CTG
27840
27841#define MC_CMD_0x144_PRIVILEGE_CTG SRIOV_CTG_MAE
27842
27843/* MC_CMD_MAE_COUNTER_FREE_IN msgrequest: Using this is equivalent to using V2
27844 * with COUNTER_TYPE=AR.
27845 */
27846#define MC_CMD_MAE_COUNTER_FREE_IN_LENMIN 8
27847#define MC_CMD_MAE_COUNTER_FREE_IN_LENMAX 132
27848#define MC_CMD_MAE_COUNTER_FREE_IN_LENMAX_MCDI2 132
27849#define MC_CMD_MAE_COUNTER_FREE_IN_LEN(num) (4+4*(num))
27850#define MC_CMD_MAE_COUNTER_FREE_IN_FREE_COUNTER_ID_NUM(len) (((len)-4)/4)
27851/* The number of counter IDs to be freed. */
27852#define MC_CMD_MAE_COUNTER_FREE_IN_COUNTER_ID_COUNT_OFST 0
27853#define MC_CMD_MAE_COUNTER_FREE_IN_COUNTER_ID_COUNT_LEN 4
27854/* An array containing the counter IDs to be freed. */
27855#define MC_CMD_MAE_COUNTER_FREE_IN_FREE_COUNTER_ID_OFST 4
27856#define MC_CMD_MAE_COUNTER_FREE_IN_FREE_COUNTER_ID_LEN 4
27857#define MC_CMD_MAE_COUNTER_FREE_IN_FREE_COUNTER_ID_MINNUM 1
27858#define MC_CMD_MAE_COUNTER_FREE_IN_FREE_COUNTER_ID_MAXNUM 32
27859#define MC_CMD_MAE_COUNTER_FREE_IN_FREE_COUNTER_ID_MAXNUM_MCDI2 32
27860
27861/* MC_CMD_MAE_COUNTER_FREE_V2_IN msgrequest */
27862#define MC_CMD_MAE_COUNTER_FREE_V2_IN_LEN 136
27863/* The number of counter IDs to be freed. */
27864#define MC_CMD_MAE_COUNTER_FREE_V2_IN_COUNTER_ID_COUNT_OFST 0
27865#define MC_CMD_MAE_COUNTER_FREE_V2_IN_COUNTER_ID_COUNT_LEN 4
27866/* An array containing the counter IDs to be freed. */
27867#define MC_CMD_MAE_COUNTER_FREE_V2_IN_FREE_COUNTER_ID_OFST 4
27868#define MC_CMD_MAE_COUNTER_FREE_V2_IN_FREE_COUNTER_ID_LEN 4
27869#define MC_CMD_MAE_COUNTER_FREE_V2_IN_FREE_COUNTER_ID_MINNUM 1
27870#define MC_CMD_MAE_COUNTER_FREE_V2_IN_FREE_COUNTER_ID_MAXNUM 32
27871#define MC_CMD_MAE_COUNTER_FREE_V2_IN_FREE_COUNTER_ID_MAXNUM_MCDI2 32
27872/* Which type of counter to free. */
27873#define MC_CMD_MAE_COUNTER_FREE_V2_IN_COUNTER_TYPE_OFST 132
27874#define MC_CMD_MAE_COUNTER_FREE_V2_IN_COUNTER_TYPE_LEN 4
27875/* Enum values, see field(s): */
27876/* MAE_COUNTER_TYPE */
27877
27878/* MC_CMD_MAE_COUNTER_FREE_OUT msgresponse */
27879#define MC_CMD_MAE_COUNTER_FREE_OUT_LENMIN 12
27880#define MC_CMD_MAE_COUNTER_FREE_OUT_LENMAX 136
27881#define MC_CMD_MAE_COUNTER_FREE_OUT_LENMAX_MCDI2 136
27882#define MC_CMD_MAE_COUNTER_FREE_OUT_LEN(num) (8+4*(num))
27883#define MC_CMD_MAE_COUNTER_FREE_OUT_FREED_COUNTER_ID_NUM(len) (((len)-8)/4)
27884/* Generation count. A packet with generation count == GENERATION_COUNT will
27885 * contain the final values for these counter IDs, unless the counter values
27886 * are zero and zero squash is enabled. Note that the GENERATION_COUNT value is
27887 * specific to the COUNTER_TYPE (IDENTIFIER field in packet header). Receiving
27888 * a packet with generation count > GENERATION_COUNT guarantees that no more
27889 * values will be written for these counters. If values for these counter IDs
27890 * are present, the counter ID has been reallocated. A counter ID will not be
27891 * reallocated within a single read cycle as this would merge increments from
27892 * the 'old' and 'new' counters. GENERATION_COUNT_INVALID is reserved and
27893 * unused.
27894 */
27895#define MC_CMD_MAE_COUNTER_FREE_OUT_GENERATION_COUNT_OFST 0
27896#define MC_CMD_MAE_COUNTER_FREE_OUT_GENERATION_COUNT_LEN 4
27897/* The number of counter IDs actually freed. It is never less than 1; failure
27898 * to free a single counter will cause an error to be returned. It is never
27899 * greater than the number that were requested to be freed, but may be less if
27900 * counters could not be freed.
27901 */
27902#define MC_CMD_MAE_COUNTER_FREE_OUT_COUNTER_ID_COUNT_OFST 4
27903#define MC_CMD_MAE_COUNTER_FREE_OUT_COUNTER_ID_COUNT_LEN 4
27904/* An array containing the IDs for the counters to that were freed. Note,
27905 * failure to free a counter can only occur on incorrect driver behaviour, so
27906 * asserting that the expected counters were freed is reasonable. When
27907 * debugging, attempting to free a single counter at a time will provide a
27908 * reason for the failure to free said counter.
27909 */
27910#define MC_CMD_MAE_COUNTER_FREE_OUT_FREED_COUNTER_ID_OFST 8
27911#define MC_CMD_MAE_COUNTER_FREE_OUT_FREED_COUNTER_ID_LEN 4
27912#define MC_CMD_MAE_COUNTER_FREE_OUT_FREED_COUNTER_ID_MINNUM 1
27913#define MC_CMD_MAE_COUNTER_FREE_OUT_FREED_COUNTER_ID_MAXNUM 32
27914#define MC_CMD_MAE_COUNTER_FREE_OUT_FREED_COUNTER_ID_MAXNUM_MCDI2 32
27915
27916
27917/***********************************/
27918/* MC_CMD_MAE_COUNTERS_STREAM_START
27919 * Start streaming counter values, specifying an RxQ to deliver packets to.
27920 * Counters allocated to the calling function will be written in a round robin
27921 * at a fixed cycle rate, assuming sufficient credits are available. The driver
27922 * may cause the counter values to be written at a slower rate by constraining
27923 * the availability of credits. Note that if the driver wishes to deliver
27924 * packets to a different queue, it must call MAE_COUNTERS_STREAM_STOP to stop
27925 * delivering packets to the current queue first.
27926 */
27927#define MC_CMD_MAE_COUNTERS_STREAM_START 0x151
27928#undef MC_CMD_0x151_PRIVILEGE_CTG
27929
27930#define MC_CMD_0x151_PRIVILEGE_CTG SRIOV_CTG_MAE
27931
27932/* MC_CMD_MAE_COUNTERS_STREAM_START_IN msgrequest: Using V1 is equivalent to V2
27933 * with COUNTER_TYPES_MASK=0x1 (i.e. AR counters only).
27934 */
27935#define MC_CMD_MAE_COUNTERS_STREAM_START_IN_LEN 8
27936/* The RxQ to write packets to. */
27937#define MC_CMD_MAE_COUNTERS_STREAM_START_IN_QID_OFST 0
27938#define MC_CMD_MAE_COUNTERS_STREAM_START_IN_QID_LEN 2
27939/* Maximum size in bytes of packets that may be written to the RxQ. */
27940#define MC_CMD_MAE_COUNTERS_STREAM_START_IN_PACKET_SIZE_OFST 2
27941#define MC_CMD_MAE_COUNTERS_STREAM_START_IN_PACKET_SIZE_LEN 2
27942/* Optional flags. */
27943#define MC_CMD_MAE_COUNTERS_STREAM_START_IN_FLAGS_OFST 4
27944#define MC_CMD_MAE_COUNTERS_STREAM_START_IN_FLAGS_LEN 4
27945#define MC_CMD_MAE_COUNTERS_STREAM_START_IN_ZERO_SQUASH_DISABLE_OFST 4
27946#define MC_CMD_MAE_COUNTERS_STREAM_START_IN_ZERO_SQUASH_DISABLE_LBN 0
27947#define MC_CMD_MAE_COUNTERS_STREAM_START_IN_ZERO_SQUASH_DISABLE_WIDTH 1
27948#define MC_CMD_MAE_COUNTERS_STREAM_START_IN_COUNTER_STALL_EN_OFST 4
27949#define MC_CMD_MAE_COUNTERS_STREAM_START_IN_COUNTER_STALL_EN_LBN 1
27950#define MC_CMD_MAE_COUNTERS_STREAM_START_IN_COUNTER_STALL_EN_WIDTH 1
27951
27952/* MC_CMD_MAE_COUNTERS_STREAM_START_V2_IN msgrequest */
27953#define MC_CMD_MAE_COUNTERS_STREAM_START_V2_IN_LEN 12
27954/* The RxQ to write packets to. */
27955#define MC_CMD_MAE_COUNTERS_STREAM_START_V2_IN_QID_OFST 0
27956#define MC_CMD_MAE_COUNTERS_STREAM_START_V2_IN_QID_LEN 2
27957/* Maximum size in bytes of packets that may be written to the RxQ. */
27958#define MC_CMD_MAE_COUNTERS_STREAM_START_V2_IN_PACKET_SIZE_OFST 2
27959#define MC_CMD_MAE_COUNTERS_STREAM_START_V2_IN_PACKET_SIZE_LEN 2
27960/* Optional flags. */
27961#define MC_CMD_MAE_COUNTERS_STREAM_START_V2_IN_FLAGS_OFST 4
27962#define MC_CMD_MAE_COUNTERS_STREAM_START_V2_IN_FLAGS_LEN 4
27963#define MC_CMD_MAE_COUNTERS_STREAM_START_V2_IN_ZERO_SQUASH_DISABLE_OFST 4
27964#define MC_CMD_MAE_COUNTERS_STREAM_START_V2_IN_ZERO_SQUASH_DISABLE_LBN 0
27965#define MC_CMD_MAE_COUNTERS_STREAM_START_V2_IN_ZERO_SQUASH_DISABLE_WIDTH 1
27966#define MC_CMD_MAE_COUNTERS_STREAM_START_V2_IN_COUNTER_STALL_EN_OFST 4
27967#define MC_CMD_MAE_COUNTERS_STREAM_START_V2_IN_COUNTER_STALL_EN_LBN 1
27968#define MC_CMD_MAE_COUNTERS_STREAM_START_V2_IN_COUNTER_STALL_EN_WIDTH 1
27969/* Mask of which counter types should be reported. Each bit position
27970 * corresponds to a value of the MAE_COUNTER_TYPE enum. For example a value of
27971 * 0x3 requests both AR and CT counters. A value of zero is invalid. Counter
27972 * types not selected by the mask value won't be included in the stream. If a
27973 * client wishes to change which counter types are reported, it must first call
27974 * MAE_COUNTERS_STREAM_STOP, then restart it with the new mask value.
27975 * Requesting a counter type which isn't supported by firmware (reported in
27976 * MC_CMD_MAE_GET_CAPS/COUNTER_TYPES_SUPPORTED) will result in ENOTSUP.
27977 */
27978#define MC_CMD_MAE_COUNTERS_STREAM_START_V2_IN_COUNTER_TYPES_MASK_OFST 8
27979#define MC_CMD_MAE_COUNTERS_STREAM_START_V2_IN_COUNTER_TYPES_MASK_LEN 4
27980
27981/* MC_CMD_MAE_COUNTERS_STREAM_START_OUT msgresponse */
27982#define MC_CMD_MAE_COUNTERS_STREAM_START_OUT_LEN 4
27983#define MC_CMD_MAE_COUNTERS_STREAM_START_OUT_FLAGS_OFST 0
27984#define MC_CMD_MAE_COUNTERS_STREAM_START_OUT_FLAGS_LEN 4
27985#define MC_CMD_MAE_COUNTERS_STREAM_START_OUT_USES_CREDITS_OFST 0
27986#define MC_CMD_MAE_COUNTERS_STREAM_START_OUT_USES_CREDITS_LBN 0
27987#define MC_CMD_MAE_COUNTERS_STREAM_START_OUT_USES_CREDITS_WIDTH 1
27988
27989
27990/***********************************/
27991/* MC_CMD_MAE_COUNTERS_STREAM_STOP
27992 * Stop streaming counter values to the specified RxQ.
27993 */
27994#define MC_CMD_MAE_COUNTERS_STREAM_STOP 0x152
27995#undef MC_CMD_0x152_PRIVILEGE_CTG
27996
27997#define MC_CMD_0x152_PRIVILEGE_CTG SRIOV_CTG_MAE
27998
27999/* MC_CMD_MAE_COUNTERS_STREAM_STOP_IN msgrequest */
28000#define MC_CMD_MAE_COUNTERS_STREAM_STOP_IN_LEN 2
28001/* The RxQ to stop writing packets to. */
28002#define MC_CMD_MAE_COUNTERS_STREAM_STOP_IN_QID_OFST 0
28003#define MC_CMD_MAE_COUNTERS_STREAM_STOP_IN_QID_LEN 2
28004
28005/* MC_CMD_MAE_COUNTERS_STREAM_STOP_OUT msgresponse */
28006#define MC_CMD_MAE_COUNTERS_STREAM_STOP_OUT_LEN 4
28007/* Generation count for AR counters. The final set of AR counter values will be
28008 * written out in packets with count == GENERATION_COUNT. An empty packet with
28009 * count > GENERATION_COUNT indicates that no more counter values of this type
28010 * will be written to this stream. GENERATION_COUNT_INVALID is reserved and
28011 * unused.
28012 */
28013#define MC_CMD_MAE_COUNTERS_STREAM_STOP_OUT_GENERATION_COUNT_OFST 0
28014#define MC_CMD_MAE_COUNTERS_STREAM_STOP_OUT_GENERATION_COUNT_LEN 4
28015
28016/* MC_CMD_MAE_COUNTERS_STREAM_STOP_V2_OUT msgresponse */
28017#define MC_CMD_MAE_COUNTERS_STREAM_STOP_V2_OUT_LENMIN 4
28018#define MC_CMD_MAE_COUNTERS_STREAM_STOP_V2_OUT_LENMAX 32
28019#define MC_CMD_MAE_COUNTERS_STREAM_STOP_V2_OUT_LENMAX_MCDI2 32
28020#define MC_CMD_MAE_COUNTERS_STREAM_STOP_V2_OUT_LEN(num) (0+4*(num))
28021#define MC_CMD_MAE_COUNTERS_STREAM_STOP_V2_OUT_GENERATION_COUNT_NUM(len) (((len)-0)/4)
28022/* Array of generation counts, indexed by MAE_COUNTER_TYPE. Note that since
28023 * MAE_COUNTER_TYPE_AR==0, this response is backwards-compatible with V1. The
28024 * final set of counter values will be written out in packets with count ==
28025 * GENERATION_COUNT. An empty packet with count > GENERATION_COUNT indicates
28026 * that no more counter values of this type will be written to this stream.
28027 * GENERATION_COUNT_INVALID is reserved and unused.
28028 */
28029#define MC_CMD_MAE_COUNTERS_STREAM_STOP_V2_OUT_GENERATION_COUNT_OFST 0
28030#define MC_CMD_MAE_COUNTERS_STREAM_STOP_V2_OUT_GENERATION_COUNT_LEN 4
28031#define MC_CMD_MAE_COUNTERS_STREAM_STOP_V2_OUT_GENERATION_COUNT_MINNUM 1
28032#define MC_CMD_MAE_COUNTERS_STREAM_STOP_V2_OUT_GENERATION_COUNT_MAXNUM 8
28033#define MC_CMD_MAE_COUNTERS_STREAM_STOP_V2_OUT_GENERATION_COUNT_MAXNUM_MCDI2 8
28034
28035
28036/***********************************/
28037/* MC_CMD_MAE_COUNTERS_STREAM_GIVE_CREDITS
28038 * Give a number of credits to the packetiser. Each credit received allows the
28039 * MC to write one packet to the RxQ, therefore for each credit the driver must
28040 * have written sufficient descriptors for a packet of length
28041 * MAE_COUNTERS_PACKETISER_STREAM_START/PACKET_SIZE and rung the doorbell.
28042 */
28043#define MC_CMD_MAE_COUNTERS_STREAM_GIVE_CREDITS 0x153
28044#undef MC_CMD_0x153_PRIVILEGE_CTG
28045
28046#define MC_CMD_0x153_PRIVILEGE_CTG SRIOV_CTG_MAE
28047
28048/* MC_CMD_MAE_COUNTERS_STREAM_GIVE_CREDITS_IN msgrequest */
28049#define MC_CMD_MAE_COUNTERS_STREAM_GIVE_CREDITS_IN_LEN 4
28050/* Number of credits to give to the packetiser. */
28051#define MC_CMD_MAE_COUNTERS_STREAM_GIVE_CREDITS_IN_NUM_CREDITS_OFST 0
28052#define MC_CMD_MAE_COUNTERS_STREAM_GIVE_CREDITS_IN_NUM_CREDITS_LEN 4
28053
28054/* MC_CMD_MAE_COUNTERS_STREAM_GIVE_CREDITS_OUT msgresponse */
28055#define MC_CMD_MAE_COUNTERS_STREAM_GIVE_CREDITS_OUT_LEN 0
28056
28057
28058/***********************************/
28059/* MC_CMD_MAE_ENCAP_HEADER_ALLOC
28060 * Allocate an encapsulation header to be used in an Action Rule response. The
28061 * header must be constructed as a valid packet with 0-length payload.
28062 * Specifically, the L3/L4 lengths & checksums will only be incrementally fixed
28063 * by the NIC, rather than recomputed entirely. Currently only IPv4, IPv6 and
28064 * UDP are supported. If the maximum number of headers have already been
28065 * allocated then the command will fail with MC_CMD_ERR_ENOSPC.
28066 */
28067#define MC_CMD_MAE_ENCAP_HEADER_ALLOC 0x148
28068#undef MC_CMD_0x148_PRIVILEGE_CTG
28069
28070#define MC_CMD_0x148_PRIVILEGE_CTG SRIOV_CTG_MAE
28071
28072/* MC_CMD_MAE_ENCAP_HEADER_ALLOC_IN msgrequest */
28073#define MC_CMD_MAE_ENCAP_HEADER_ALLOC_IN_LENMIN 4
28074#define MC_CMD_MAE_ENCAP_HEADER_ALLOC_IN_LENMAX 252
28075#define MC_CMD_MAE_ENCAP_HEADER_ALLOC_IN_LENMAX_MCDI2 1020
28076#define MC_CMD_MAE_ENCAP_HEADER_ALLOC_IN_LEN(num) (4+1*(num))
28077#define MC_CMD_MAE_ENCAP_HEADER_ALLOC_IN_HDR_DATA_NUM(len) (((len)-4)/1)
28078#define MC_CMD_MAE_ENCAP_HEADER_ALLOC_IN_ENCAP_TYPE_OFST 0
28079#define MC_CMD_MAE_ENCAP_HEADER_ALLOC_IN_ENCAP_TYPE_LEN 4
28080#define MC_CMD_MAE_ENCAP_HEADER_ALLOC_IN_HDR_DATA_OFST 4
28081#define MC_CMD_MAE_ENCAP_HEADER_ALLOC_IN_HDR_DATA_LEN 1
28082#define MC_CMD_MAE_ENCAP_HEADER_ALLOC_IN_HDR_DATA_MINNUM 0
28083#define MC_CMD_MAE_ENCAP_HEADER_ALLOC_IN_HDR_DATA_MAXNUM 248
28084#define MC_CMD_MAE_ENCAP_HEADER_ALLOC_IN_HDR_DATA_MAXNUM_MCDI2 1016
28085
28086/* MC_CMD_MAE_ENCAP_HEADER_ALLOC_OUT msgresponse */
28087#define MC_CMD_MAE_ENCAP_HEADER_ALLOC_OUT_LEN 4
28088#define MC_CMD_MAE_ENCAP_HEADER_ALLOC_OUT_ENCAP_HEADER_ID_OFST 0
28089#define MC_CMD_MAE_ENCAP_HEADER_ALLOC_OUT_ENCAP_HEADER_ID_LEN 4
28090/* enum: An encap metadata ID that is guaranteed never to represent real encap
28091 * metadata
28092 */
28093#define MC_CMD_MAE_ENCAP_HEADER_ALLOC_OUT_ENCAP_HEADER_ID_NULL 0xffffffff
28094
28095
28096/***********************************/
28097/* MC_CMD_MAE_ENCAP_HEADER_UPDATE
28098 * Update encap action metadata. See comments for MAE_ENCAP_HEADER_ALLOC.
28099 */
28100#define MC_CMD_MAE_ENCAP_HEADER_UPDATE 0x149
28101#undef MC_CMD_0x149_PRIVILEGE_CTG
28102
28103#define MC_CMD_0x149_PRIVILEGE_CTG SRIOV_CTG_MAE
28104
28105/* MC_CMD_MAE_ENCAP_HEADER_UPDATE_IN msgrequest */
28106#define MC_CMD_MAE_ENCAP_HEADER_UPDATE_IN_LENMIN 8
28107#define MC_CMD_MAE_ENCAP_HEADER_UPDATE_IN_LENMAX 252
28108#define MC_CMD_MAE_ENCAP_HEADER_UPDATE_IN_LENMAX_MCDI2 1020
28109#define MC_CMD_MAE_ENCAP_HEADER_UPDATE_IN_LEN(num) (8+1*(num))
28110#define MC_CMD_MAE_ENCAP_HEADER_UPDATE_IN_HDR_DATA_NUM(len) (((len)-8)/1)
28111#define MC_CMD_MAE_ENCAP_HEADER_UPDATE_IN_EH_ID_OFST 0
28112#define MC_CMD_MAE_ENCAP_HEADER_UPDATE_IN_EH_ID_LEN 4
28113#define MC_CMD_MAE_ENCAP_HEADER_UPDATE_IN_ENCAP_TYPE_OFST 4
28114#define MC_CMD_MAE_ENCAP_HEADER_UPDATE_IN_ENCAP_TYPE_LEN 4
28115#define MC_CMD_MAE_ENCAP_HEADER_UPDATE_IN_HDR_DATA_OFST 8
28116#define MC_CMD_MAE_ENCAP_HEADER_UPDATE_IN_HDR_DATA_LEN 1
28117#define MC_CMD_MAE_ENCAP_HEADER_UPDATE_IN_HDR_DATA_MINNUM 0
28118#define MC_CMD_MAE_ENCAP_HEADER_UPDATE_IN_HDR_DATA_MAXNUM 244
28119#define MC_CMD_MAE_ENCAP_HEADER_UPDATE_IN_HDR_DATA_MAXNUM_MCDI2 1012
28120
28121/* MC_CMD_MAE_ENCAP_HEADER_UPDATE_OUT msgresponse */
28122#define MC_CMD_MAE_ENCAP_HEADER_UPDATE_OUT_LEN 0
28123
28124
28125/***********************************/
28126/* MC_CMD_MAE_ENCAP_HEADER_FREE
28127 * Free encap action metadata
28128 */
28129#define MC_CMD_MAE_ENCAP_HEADER_FREE 0x14a
28130#undef MC_CMD_0x14a_PRIVILEGE_CTG
28131
28132#define MC_CMD_0x14a_PRIVILEGE_CTG SRIOV_CTG_MAE
28133
28134/* MC_CMD_MAE_ENCAP_HEADER_FREE_IN msgrequest */
28135#define MC_CMD_MAE_ENCAP_HEADER_FREE_IN_LENMIN 4
28136#define MC_CMD_MAE_ENCAP_HEADER_FREE_IN_LENMAX 128
28137#define MC_CMD_MAE_ENCAP_HEADER_FREE_IN_LENMAX_MCDI2 128
28138#define MC_CMD_MAE_ENCAP_HEADER_FREE_IN_LEN(num) (0+4*(num))
28139#define MC_CMD_MAE_ENCAP_HEADER_FREE_IN_EH_ID_NUM(len) (((len)-0)/4)
28140/* Same semantics as MC_CMD_MAE_COUNTER_FREE */
28141#define MC_CMD_MAE_ENCAP_HEADER_FREE_IN_EH_ID_OFST 0
28142#define MC_CMD_MAE_ENCAP_HEADER_FREE_IN_EH_ID_LEN 4
28143#define MC_CMD_MAE_ENCAP_HEADER_FREE_IN_EH_ID_MINNUM 1
28144#define MC_CMD_MAE_ENCAP_HEADER_FREE_IN_EH_ID_MAXNUM 32
28145#define MC_CMD_MAE_ENCAP_HEADER_FREE_IN_EH_ID_MAXNUM_MCDI2 32
28146
28147/* MC_CMD_MAE_ENCAP_HEADER_FREE_OUT msgresponse */
28148#define MC_CMD_MAE_ENCAP_HEADER_FREE_OUT_LENMIN 4
28149#define MC_CMD_MAE_ENCAP_HEADER_FREE_OUT_LENMAX 128
28150#define MC_CMD_MAE_ENCAP_HEADER_FREE_OUT_LENMAX_MCDI2 128
28151#define MC_CMD_MAE_ENCAP_HEADER_FREE_OUT_LEN(num) (0+4*(num))
28152#define MC_CMD_MAE_ENCAP_HEADER_FREE_OUT_FREED_EH_ID_NUM(len) (((len)-0)/4)
28153/* Same semantics as MC_CMD_MAE_COUNTER_FREE */
28154#define MC_CMD_MAE_ENCAP_HEADER_FREE_OUT_FREED_EH_ID_OFST 0
28155#define MC_CMD_MAE_ENCAP_HEADER_FREE_OUT_FREED_EH_ID_LEN 4
28156#define MC_CMD_MAE_ENCAP_HEADER_FREE_OUT_FREED_EH_ID_MINNUM 1
28157#define MC_CMD_MAE_ENCAP_HEADER_FREE_OUT_FREED_EH_ID_MAXNUM 32
28158#define MC_CMD_MAE_ENCAP_HEADER_FREE_OUT_FREED_EH_ID_MAXNUM_MCDI2 32
28159
28160
28161/***********************************/
28162/* MC_CMD_MAE_MAC_ADDR_ALLOC
28163 * Allocate MAC address. Hardware implementations have MAC addresses programmed
28164 * into an indirection table, and clients should take care not to allocate the
28165 * same MAC address twice (but instead reuse its ID). If the maximum number of
28166 * MAC addresses have already been allocated then the command will fail with
28167 * MC_CMD_ERR_ENOSPC.
28168 */
28169#define MC_CMD_MAE_MAC_ADDR_ALLOC 0x15e
28170#undef MC_CMD_0x15e_PRIVILEGE_CTG
28171
28172#define MC_CMD_0x15e_PRIVILEGE_CTG SRIOV_CTG_MAE
28173
28174/* MC_CMD_MAE_MAC_ADDR_ALLOC_IN msgrequest */
28175#define MC_CMD_MAE_MAC_ADDR_ALLOC_IN_LEN 6
28176/* MAC address as bytes in network order. */
28177#define MC_CMD_MAE_MAC_ADDR_ALLOC_IN_MAC_ADDR_OFST 0
28178#define MC_CMD_MAE_MAC_ADDR_ALLOC_IN_MAC_ADDR_LEN 6
28179
28180/* MC_CMD_MAE_MAC_ADDR_ALLOC_OUT msgresponse */
28181#define MC_CMD_MAE_MAC_ADDR_ALLOC_OUT_LEN 4
28182#define MC_CMD_MAE_MAC_ADDR_ALLOC_OUT_MAC_ID_OFST 0
28183#define MC_CMD_MAE_MAC_ADDR_ALLOC_OUT_MAC_ID_LEN 4
28184/* enum: An MAC address ID that is guaranteed never to represent a real MAC
28185 * address.
28186 */
28187#define MC_CMD_MAE_MAC_ADDR_ALLOC_OUT_MAC_ID_NULL 0xffffffff
28188
28189
28190/***********************************/
28191/* MC_CMD_MAE_MAC_ADDR_FREE
28192 * Free MAC address.
28193 */
28194#define MC_CMD_MAE_MAC_ADDR_FREE 0x15f
28195#undef MC_CMD_0x15f_PRIVILEGE_CTG
28196
28197#define MC_CMD_0x15f_PRIVILEGE_CTG SRIOV_CTG_MAE
28198
28199/* MC_CMD_MAE_MAC_ADDR_FREE_IN msgrequest */
28200#define MC_CMD_MAE_MAC_ADDR_FREE_IN_LENMIN 4
28201#define MC_CMD_MAE_MAC_ADDR_FREE_IN_LENMAX 128
28202#define MC_CMD_MAE_MAC_ADDR_FREE_IN_LENMAX_MCDI2 128
28203#define MC_CMD_MAE_MAC_ADDR_FREE_IN_LEN(num) (0+4*(num))
28204#define MC_CMD_MAE_MAC_ADDR_FREE_IN_MAC_ID_NUM(len) (((len)-0)/4)
28205/* Same semantics as MC_CMD_MAE_COUNTER_FREE */
28206#define MC_CMD_MAE_MAC_ADDR_FREE_IN_MAC_ID_OFST 0
28207#define MC_CMD_MAE_MAC_ADDR_FREE_IN_MAC_ID_LEN 4
28208#define MC_CMD_MAE_MAC_ADDR_FREE_IN_MAC_ID_MINNUM 1
28209#define MC_CMD_MAE_MAC_ADDR_FREE_IN_MAC_ID_MAXNUM 32
28210#define MC_CMD_MAE_MAC_ADDR_FREE_IN_MAC_ID_MAXNUM_MCDI2 32
28211
28212/* MC_CMD_MAE_MAC_ADDR_FREE_OUT msgresponse */
28213#define MC_CMD_MAE_MAC_ADDR_FREE_OUT_LENMIN 4
28214#define MC_CMD_MAE_MAC_ADDR_FREE_OUT_LENMAX 128
28215#define MC_CMD_MAE_MAC_ADDR_FREE_OUT_LENMAX_MCDI2 128
28216#define MC_CMD_MAE_MAC_ADDR_FREE_OUT_LEN(num) (0+4*(num))
28217#define MC_CMD_MAE_MAC_ADDR_FREE_OUT_FREED_MAC_ID_NUM(len) (((len)-0)/4)
28218/* Same semantics as MC_CMD_MAE_COUNTER_FREE */
28219#define MC_CMD_MAE_MAC_ADDR_FREE_OUT_FREED_MAC_ID_OFST 0
28220#define MC_CMD_MAE_MAC_ADDR_FREE_OUT_FREED_MAC_ID_LEN 4
28221#define MC_CMD_MAE_MAC_ADDR_FREE_OUT_FREED_MAC_ID_MINNUM 1
28222#define MC_CMD_MAE_MAC_ADDR_FREE_OUT_FREED_MAC_ID_MAXNUM 32
28223#define MC_CMD_MAE_MAC_ADDR_FREE_OUT_FREED_MAC_ID_MAXNUM_MCDI2 32
28224
28225
28226/***********************************/
28227/* MC_CMD_MAE_ACTION_SET_ALLOC
28228 * Allocate an action set, which can be referenced either in response to an
28229 * Action Rule, or as part of an Action Set List. If the maxmimum number of
28230 * action sets have already been allocated then the command will fail with
28231 * MC_CMD_ERR_ENOSPC.
28232 */
28233#define MC_CMD_MAE_ACTION_SET_ALLOC 0x14d
28234#undef MC_CMD_0x14d_PRIVILEGE_CTG
28235
28236#define MC_CMD_0x14d_PRIVILEGE_CTG SRIOV_CTG_MAE
28237
28238/* MC_CMD_MAE_ACTION_SET_ALLOC_IN msgrequest */
28239#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_LEN 44
28240#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_FLAGS_OFST 0
28241#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_FLAGS_LEN 4
28242#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_VLAN_PUSH_OFST 0
28243#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_VLAN_PUSH_LBN 0
28244#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_VLAN_PUSH_WIDTH 2
28245#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_VLAN_POP_OFST 0
28246#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_VLAN_POP_LBN 4
28247#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_VLAN_POP_WIDTH 2
28248#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DECAP_OFST 0
28249#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DECAP_LBN 8
28250#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DECAP_WIDTH 1
28251#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_MARK_OFST 0
28252#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_MARK_LBN 9
28253#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_MARK_WIDTH 1
28254#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_FLAG_OFST 0
28255#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_FLAG_LBN 10
28256#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_FLAG_WIDTH 1
28257#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_NAT_OFST 0
28258#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_NAT_LBN 11
28259#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_NAT_WIDTH 1
28260#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_DECR_IP_TTL_OFST 0
28261#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_DECR_IP_TTL_LBN 12
28262#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_DECR_IP_TTL_WIDTH 1
28263#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_SET_SRC_MPORT_OFST 0
28264#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_SET_SRC_MPORT_LBN 13
28265#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_SET_SRC_MPORT_WIDTH 1
28266#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_SUPPRESS_SELF_DELIVERY_OFST 0
28267#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_SUPPRESS_SELF_DELIVERY_LBN 14
28268#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_SUPPRESS_SELF_DELIVERY_WIDTH 1
28269/* If VLAN_PUSH >= 1, TCI value to be inserted as outermost VLAN. */
28270#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_VLAN0_TCI_BE_OFST 4
28271#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_VLAN0_TCI_BE_LEN 2
28272/* If VLAN_PUSH >= 1, TPID value to be inserted as outermost VLAN. */
28273#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_VLAN0_PROTO_BE_OFST 6
28274#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_VLAN0_PROTO_BE_LEN 2
28275/* If VLAN_PUSH == 2, inner TCI value to be inserted. */
28276#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_VLAN1_TCI_BE_OFST 8
28277#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_VLAN1_TCI_BE_LEN 2
28278/* If VLAN_PUSH == 2, inner TPID value to be inserted. */
28279#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_VLAN1_PROTO_BE_OFST 10
28280#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_VLAN1_PROTO_BE_LEN 2
28281/* Reserved. Ignored by firmware. Should be set to zero or 0xffffffff. */
28282#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_RSVD_OFST 12
28283#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_RSVD_LEN 4
28284/* Set to ENCAP_HEADER_ID_NULL to request no encap action */
28285#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_ENCAP_HEADER_ID_OFST 16
28286#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_ENCAP_HEADER_ID_LEN 4
28287/* An m-port selector identifying the m-port that the modified packet should be
28288 * delivered to. Set to MPORT_SELECTOR_NULL to request no delivery of the
28289 * packet.
28290 */
28291#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DELIVER_OFST 20
28292#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DELIVER_LEN 4
28293/* Allows an action set to trigger several counter updates. Set to
28294 * COUNTER_LIST_ID_NULL to request no counter action.
28295 */
28296#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_COUNTER_LIST_ID_OFST 24
28297#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_COUNTER_LIST_ID_LEN 4
28298/* If a driver only wished to update one counter within this action set, then
28299 * it can supply a COUNTER_ID instead of allocating a single-element counter
28300 * list. The ID must have been allocated with COUNTER_TYPE=AR. This field
28301 * should be set to COUNTER_ID_NULL if this behaviour is not required. It is
28302 * not valid to supply a non-NULL value for both COUNTER_LIST_ID and
28303 * COUNTER_ID.
28304 */
28305#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_COUNTER_ID_OFST 28
28306#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_COUNTER_ID_LEN 4
28307#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_MARK_VALUE_OFST 32
28308#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_MARK_VALUE_LEN 4
28309/* Set to MAC_ID_NULL to request no source MAC replacement. */
28310#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_SRC_MAC_ID_OFST 36
28311#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_SRC_MAC_ID_LEN 4
28312/* Set to MAC_ID_NULL to request no destination MAC replacement. */
28313#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DST_MAC_ID_OFST 40
28314#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DST_MAC_ID_LEN 4
28315
28316/* MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN msgrequest: Only supported if
28317 * MAE_ACTION_SET_ALLOC_V2_SUPPORTED is advertised in
28318 * MC_CMD_GET_CAPABILITIES_V7_OUT.
28319 */
28320#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_LEN 51
28321#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_FLAGS_OFST 0
28322#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_FLAGS_LEN 4
28323#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN_PUSH_OFST 0
28324#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN_PUSH_LBN 0
28325#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN_PUSH_WIDTH 2
28326#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN_POP_OFST 0
28327#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN_POP_LBN 4
28328#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN_POP_WIDTH 2
28329#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DECAP_OFST 0
28330#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DECAP_LBN 8
28331#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DECAP_WIDTH 1
28332#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_MARK_OFST 0
28333#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_MARK_LBN 9
28334#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_MARK_WIDTH 1
28335#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_FLAG_OFST 0
28336#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_FLAG_LBN 10
28337#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_FLAG_WIDTH 1
28338#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_NAT_OFST 0
28339#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_NAT_LBN 11
28340#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_NAT_WIDTH 1
28341#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_DECR_IP_TTL_OFST 0
28342#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_DECR_IP_TTL_LBN 12
28343#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_DECR_IP_TTL_WIDTH 1
28344#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_SET_SRC_MPORT_OFST 0
28345#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_SET_SRC_MPORT_LBN 13
28346#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_SET_SRC_MPORT_WIDTH 1
28347#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_SUPPRESS_SELF_DELIVERY_OFST 0
28348#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_SUPPRESS_SELF_DELIVERY_LBN 14
28349#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_SUPPRESS_SELF_DELIVERY_WIDTH 1
28350/* If VLAN_PUSH >= 1, TCI value to be inserted as outermost VLAN. */
28351#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN0_TCI_BE_OFST 4
28352#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN0_TCI_BE_LEN 2
28353/* If VLAN_PUSH >= 1, TPID value to be inserted as outermost VLAN. */
28354#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN0_PROTO_BE_OFST 6
28355#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN0_PROTO_BE_LEN 2
28356/* If VLAN_PUSH == 2, inner TCI value to be inserted. */
28357#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN1_TCI_BE_OFST 8
28358#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN1_TCI_BE_LEN 2
28359/* If VLAN_PUSH == 2, inner TPID value to be inserted. */
28360#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN1_PROTO_BE_OFST 10
28361#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN1_PROTO_BE_LEN 2
28362/* Reserved. Ignored by firmware. Should be set to zero or 0xffffffff. */
28363#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_RSVD_OFST 12
28364#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_RSVD_LEN 4
28365/* Set to ENCAP_HEADER_ID_NULL to request no encap action */
28366#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ENCAP_HEADER_ID_OFST 16
28367#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ENCAP_HEADER_ID_LEN 4
28368/* An m-port selector identifying the m-port that the modified packet should be
28369 * delivered to. Set to MPORT_SELECTOR_NULL to request no delivery of the
28370 * packet.
28371 */
28372#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DELIVER_OFST 20
28373#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DELIVER_LEN 4
28374/* Allows an action set to trigger several counter updates. Set to
28375 * COUNTER_LIST_ID_NULL to request no counter action.
28376 */
28377#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_COUNTER_LIST_ID_OFST 24
28378#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_COUNTER_LIST_ID_LEN 4
28379/* If a driver only wished to update one counter within this action set, then
28380 * it can supply a COUNTER_ID instead of allocating a single-element counter
28381 * list. The ID must have been allocated with COUNTER_TYPE=AR. This field
28382 * should be set to COUNTER_ID_NULL if this behaviour is not required. It is
28383 * not valid to supply a non-NULL value for both COUNTER_LIST_ID and
28384 * COUNTER_ID.
28385 */
28386#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_COUNTER_ID_OFST 28
28387#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_COUNTER_ID_LEN 4
28388#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_MARK_VALUE_OFST 32
28389#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_MARK_VALUE_LEN 4
28390/* Set to MAC_ID_NULL to request no source MAC replacement. */
28391#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_SRC_MAC_ID_OFST 36
28392#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_SRC_MAC_ID_LEN 4
28393/* Set to MAC_ID_NULL to request no destination MAC replacement. */
28394#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DST_MAC_ID_OFST 40
28395#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DST_MAC_ID_LEN 4
28396/* Source m-port ID to be reported for DO_SET_SRC_MPORT action. */
28397#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_REPORTED_SRC_MPORT_OFST 44
28398#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_REPORTED_SRC_MPORT_LEN 4
28399/* Actions for modifying the Differentiated Services Code-Point (DSCP) bits
28400 * within IPv4 and IPv6 headers.
28401 */
28402#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DSCP_CONTROL_OFST 48
28403#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DSCP_CONTROL_LEN 2
28404#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_DSCP_ENCAP_COPY_OFST 48
28405#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_DSCP_ENCAP_COPY_LBN 0
28406#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_DSCP_ENCAP_COPY_WIDTH 1
28407#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_DSCP_DECAP_COPY_OFST 48
28408#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_DSCP_DECAP_COPY_LBN 1
28409#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_DSCP_DECAP_COPY_WIDTH 1
28410#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_REPLACE_DSCP_OFST 48
28411#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_REPLACE_DSCP_LBN 2
28412#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_REPLACE_DSCP_WIDTH 1
28413#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DSCP_VALUE_OFST 48
28414#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DSCP_VALUE_LBN 3
28415#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DSCP_VALUE_WIDTH 6
28416/* Actions for modifying the Explicit Congestion Notification (ECN) bits within
28417 * IPv4 and IPv6 headers.
28418 */
28419#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ECN_CONTROL_OFST 50
28420#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ECN_CONTROL_LEN 1
28421#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_ECN_ENCAP_COPY_OFST 50
28422#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_ECN_ENCAP_COPY_LBN 0
28423#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_ECN_ENCAP_COPY_WIDTH 1
28424#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_ECN_DECAP_COPY_OFST 50
28425#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_ECN_DECAP_COPY_LBN 1
28426#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_ECN_DECAP_COPY_WIDTH 1
28427#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_REPLACE_ECN_OFST 50
28428#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_REPLACE_ECN_LBN 2
28429#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_REPLACE_ECN_WIDTH 1
28430#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ECN_VALUE_OFST 50
28431#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ECN_VALUE_LBN 3
28432#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ECN_VALUE_WIDTH 2
28433#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ECN_ECT_0_TO_CE_OFST 50
28434#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ECN_ECT_0_TO_CE_LBN 5
28435#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ECN_ECT_0_TO_CE_WIDTH 1
28436#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ECN_ECT_1_TO_CE_OFST 50
28437#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ECN_ECT_1_TO_CE_LBN 6
28438#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ECN_ECT_1_TO_CE_WIDTH 1
28439
28440/* MC_CMD_MAE_ACTION_SET_ALLOC_OUT msgresponse */
28441#define MC_CMD_MAE_ACTION_SET_ALLOC_OUT_LEN 4
28442/* The MSB of the AS_ID is guaranteed to be clear if the ID is not
28443 * ACTION_SET_ID_NULL. This allows an AS_ID to be distinguished from an ASL_ID
28444 * returned from MC_CMD_MAE_ACTION_SET_LIST_ALLOC.
28445 */
28446#define MC_CMD_MAE_ACTION_SET_ALLOC_OUT_AS_ID_OFST 0
28447#define MC_CMD_MAE_ACTION_SET_ALLOC_OUT_AS_ID_LEN 4
28448/* enum: An action set ID that is guaranteed never to represent an action set
28449 */
28450#define MC_CMD_MAE_ACTION_SET_ALLOC_OUT_ACTION_SET_ID_NULL 0xffffffff
28451
28452
28453/***********************************/
28454/* MC_CMD_MAE_ACTION_SET_FREE
28455 */
28456#define MC_CMD_MAE_ACTION_SET_FREE 0x14e
28457#undef MC_CMD_0x14e_PRIVILEGE_CTG
28458
28459#define MC_CMD_0x14e_PRIVILEGE_CTG SRIOV_CTG_MAE
28460
28461/* MC_CMD_MAE_ACTION_SET_FREE_IN msgrequest */
28462#define MC_CMD_MAE_ACTION_SET_FREE_IN_LENMIN 4
28463#define MC_CMD_MAE_ACTION_SET_FREE_IN_LENMAX 128
28464#define MC_CMD_MAE_ACTION_SET_FREE_IN_LENMAX_MCDI2 128
28465#define MC_CMD_MAE_ACTION_SET_FREE_IN_LEN(num) (0+4*(num))
28466#define MC_CMD_MAE_ACTION_SET_FREE_IN_AS_ID_NUM(len) (((len)-0)/4)
28467/* Same semantics as MC_CMD_MAE_COUNTER_FREE */
28468#define MC_CMD_MAE_ACTION_SET_FREE_IN_AS_ID_OFST 0
28469#define MC_CMD_MAE_ACTION_SET_FREE_IN_AS_ID_LEN 4
28470#define MC_CMD_MAE_ACTION_SET_FREE_IN_AS_ID_MINNUM 1
28471#define MC_CMD_MAE_ACTION_SET_FREE_IN_AS_ID_MAXNUM 32
28472#define MC_CMD_MAE_ACTION_SET_FREE_IN_AS_ID_MAXNUM_MCDI2 32
28473
28474/* MC_CMD_MAE_ACTION_SET_FREE_OUT msgresponse */
28475#define MC_CMD_MAE_ACTION_SET_FREE_OUT_LENMIN 4
28476#define MC_CMD_MAE_ACTION_SET_FREE_OUT_LENMAX 128
28477#define MC_CMD_MAE_ACTION_SET_FREE_OUT_LENMAX_MCDI2 128
28478#define MC_CMD_MAE_ACTION_SET_FREE_OUT_LEN(num) (0+4*(num))
28479#define MC_CMD_MAE_ACTION_SET_FREE_OUT_FREED_AS_ID_NUM(len) (((len)-0)/4)
28480/* Same semantics as MC_CMD_MAE_COUNTER_FREE */
28481#define MC_CMD_MAE_ACTION_SET_FREE_OUT_FREED_AS_ID_OFST 0
28482#define MC_CMD_MAE_ACTION_SET_FREE_OUT_FREED_AS_ID_LEN 4
28483#define MC_CMD_MAE_ACTION_SET_FREE_OUT_FREED_AS_ID_MINNUM 1
28484#define MC_CMD_MAE_ACTION_SET_FREE_OUT_FREED_AS_ID_MAXNUM 32
28485#define MC_CMD_MAE_ACTION_SET_FREE_OUT_FREED_AS_ID_MAXNUM_MCDI2 32
28486
28487
28488/***********************************/
28489/* MC_CMD_MAE_ACTION_SET_LIST_ALLOC
28490 * Allocate an action set list (ASL) that can be referenced by an ID. The ASL
28491 * ID can be used when inserting an action rule, so that for each packet
28492 * matching the rule every action set in the list is applied. If the maximum
28493 * number of ASLs have already been allocated then the command will fail with
28494 * MC_CMD_ERR_ENOSPC.
28495 */
28496#define MC_CMD_MAE_ACTION_SET_LIST_ALLOC 0x14f
28497#undef MC_CMD_0x14f_PRIVILEGE_CTG
28498
28499#define MC_CMD_0x14f_PRIVILEGE_CTG SRIOV_CTG_MAE
28500
28501/* MC_CMD_MAE_ACTION_SET_LIST_ALLOC_IN msgrequest */
28502#define MC_CMD_MAE_ACTION_SET_LIST_ALLOC_IN_LENMIN 8
28503#define MC_CMD_MAE_ACTION_SET_LIST_ALLOC_IN_LENMAX 252
28504#define MC_CMD_MAE_ACTION_SET_LIST_ALLOC_IN_LENMAX_MCDI2 1020
28505#define MC_CMD_MAE_ACTION_SET_LIST_ALLOC_IN_LEN(num) (4+4*(num))
28506#define MC_CMD_MAE_ACTION_SET_LIST_ALLOC_IN_AS_IDS_NUM(len) (((len)-4)/4)
28507/* Number of elements in the AS_IDS field. */
28508#define MC_CMD_MAE_ACTION_SET_LIST_ALLOC_IN_COUNT_OFST 0
28509#define MC_CMD_MAE_ACTION_SET_LIST_ALLOC_IN_COUNT_LEN 4
28510/* The IDs of the action sets in this list. The last element of this list may
28511 * be the ID of an already allocated ASL. In this case the action sets from the
28512 * already allocated ASL will be applied after the action sets supplied by this
28513 * request. This mechanism can be used to reduce resource usage in the case
28514 * where one ASL is a sublist of another ASL. The sublist should be allocated
28515 * first, then the superlist should be allocated by supplying all required
28516 * action set IDs that are not in the sublist followed by the ID of the
28517 * sublist. One sublist can be referenced by multiple superlists.
28518 */
28519#define MC_CMD_MAE_ACTION_SET_LIST_ALLOC_IN_AS_IDS_OFST 4
28520#define MC_CMD_MAE_ACTION_SET_LIST_ALLOC_IN_AS_IDS_LEN 4
28521#define MC_CMD_MAE_ACTION_SET_LIST_ALLOC_IN_AS_IDS_MINNUM 1
28522#define MC_CMD_MAE_ACTION_SET_LIST_ALLOC_IN_AS_IDS_MAXNUM 62
28523#define MC_CMD_MAE_ACTION_SET_LIST_ALLOC_IN_AS_IDS_MAXNUM_MCDI2 254
28524
28525/* MC_CMD_MAE_ACTION_SET_LIST_ALLOC_OUT msgresponse */
28526#define MC_CMD_MAE_ACTION_SET_LIST_ALLOC_OUT_LEN 4
28527/* The MSB of the ASL_ID is guaranteed to be set. This allows an ASL_ID to be
28528 * distinguished from an AS_ID returned from MC_CMD_MAE_ACTION_SET_ALLOC.
28529 */
28530#define MC_CMD_MAE_ACTION_SET_LIST_ALLOC_OUT_ASL_ID_OFST 0
28531#define MC_CMD_MAE_ACTION_SET_LIST_ALLOC_OUT_ASL_ID_LEN 4
28532/* enum: An action set list ID that is guaranteed never to represent an action
28533 * set list
28534 */
28535#define MC_CMD_MAE_ACTION_SET_LIST_ALLOC_OUT_ACTION_SET_LIST_ID_NULL 0xffffffff
28536
28537
28538/***********************************/
28539/* MC_CMD_MAE_ACTION_SET_LIST_FREE
28540 * Free match-action-engine redirect_lists
28541 */
28542#define MC_CMD_MAE_ACTION_SET_LIST_FREE 0x150
28543#undef MC_CMD_0x150_PRIVILEGE_CTG
28544
28545#define MC_CMD_0x150_PRIVILEGE_CTG SRIOV_CTG_MAE
28546
28547/* MC_CMD_MAE_ACTION_SET_LIST_FREE_IN msgrequest */
28548#define MC_CMD_MAE_ACTION_SET_LIST_FREE_IN_LENMIN 4
28549#define MC_CMD_MAE_ACTION_SET_LIST_FREE_IN_LENMAX 128
28550#define MC_CMD_MAE_ACTION_SET_LIST_FREE_IN_LENMAX_MCDI2 128
28551#define MC_CMD_MAE_ACTION_SET_LIST_FREE_IN_LEN(num) (0+4*(num))
28552#define MC_CMD_MAE_ACTION_SET_LIST_FREE_IN_ASL_ID_NUM(len) (((len)-0)/4)
28553/* Same semantics as MC_CMD_MAE_COUNTER_FREE */
28554#define MC_CMD_MAE_ACTION_SET_LIST_FREE_IN_ASL_ID_OFST 0
28555#define MC_CMD_MAE_ACTION_SET_LIST_FREE_IN_ASL_ID_LEN 4
28556#define MC_CMD_MAE_ACTION_SET_LIST_FREE_IN_ASL_ID_MINNUM 1
28557#define MC_CMD_MAE_ACTION_SET_LIST_FREE_IN_ASL_ID_MAXNUM 32
28558#define MC_CMD_MAE_ACTION_SET_LIST_FREE_IN_ASL_ID_MAXNUM_MCDI2 32
28559
28560/* MC_CMD_MAE_ACTION_SET_LIST_FREE_OUT msgresponse */
28561#define MC_CMD_MAE_ACTION_SET_LIST_FREE_OUT_LENMIN 4
28562#define MC_CMD_MAE_ACTION_SET_LIST_FREE_OUT_LENMAX 128
28563#define MC_CMD_MAE_ACTION_SET_LIST_FREE_OUT_LENMAX_MCDI2 128
28564#define MC_CMD_MAE_ACTION_SET_LIST_FREE_OUT_LEN(num) (0+4*(num))
28565#define MC_CMD_MAE_ACTION_SET_LIST_FREE_OUT_FREED_ASL_ID_NUM(len) (((len)-0)/4)
28566/* Same semantics as MC_CMD_MAE_COUNTER_FREE */
28567#define MC_CMD_MAE_ACTION_SET_LIST_FREE_OUT_FREED_ASL_ID_OFST 0
28568#define MC_CMD_MAE_ACTION_SET_LIST_FREE_OUT_FREED_ASL_ID_LEN 4
28569#define MC_CMD_MAE_ACTION_SET_LIST_FREE_OUT_FREED_ASL_ID_MINNUM 1
28570#define MC_CMD_MAE_ACTION_SET_LIST_FREE_OUT_FREED_ASL_ID_MAXNUM 32
28571#define MC_CMD_MAE_ACTION_SET_LIST_FREE_OUT_FREED_ASL_ID_MAXNUM_MCDI2 32
28572
28573
28574/***********************************/
28575/* MC_CMD_MAE_OUTER_RULE_INSERT
28576 * Inserts an Outer Rule, which controls encapsulation parsing, and may
28577 * influence the Lookup Sequence. If the maximum number of rules have already
28578 * been inserted then the command will fail with MC_CMD_ERR_ENOSPC.
28579 */
28580#define MC_CMD_MAE_OUTER_RULE_INSERT 0x15a
28581#undef MC_CMD_0x15a_PRIVILEGE_CTG
28582
28583#define MC_CMD_0x15a_PRIVILEGE_CTG SRIOV_CTG_MAE
28584
28585/* MC_CMD_MAE_OUTER_RULE_INSERT_IN msgrequest */
28586#define MC_CMD_MAE_OUTER_RULE_INSERT_IN_LENMIN 16
28587#define MC_CMD_MAE_OUTER_RULE_INSERT_IN_LENMAX 252
28588#define MC_CMD_MAE_OUTER_RULE_INSERT_IN_LENMAX_MCDI2 1020
28589#define MC_CMD_MAE_OUTER_RULE_INSERT_IN_LEN(num) (16+1*(num))
28590#define MC_CMD_MAE_OUTER_RULE_INSERT_IN_FIELD_MATCH_CRITERIA_NUM(len) (((len)-16)/1)
28591/* Packets matching the rule will be parsed with this encapsulation. */
28592#define MC_CMD_MAE_OUTER_RULE_INSERT_IN_ENCAP_TYPE_OFST 0
28593#define MC_CMD_MAE_OUTER_RULE_INSERT_IN_ENCAP_TYPE_LEN 4
28594/* Enum values, see field(s): */
28595/* MAE_MCDI_ENCAP_TYPE */
28596/* Match priority. Lower values have higher priority. Must be less than
28597 * MC_CMD_MAE_GET_CAPS_OUT.ENCAP_PRIOS If a packet matches two filters with
28598 * equal priority then it is unspecified which takes priority.
28599 */
28600#define MC_CMD_MAE_OUTER_RULE_INSERT_IN_PRIO_OFST 4
28601#define MC_CMD_MAE_OUTER_RULE_INSERT_IN_PRIO_LEN 4
28602/* Deprecated alias for ACTION_CONTROL. */
28603#define MC_CMD_MAE_OUTER_RULE_INSERT_IN_LOOKUP_CONTROL_OFST 8
28604#define MC_CMD_MAE_OUTER_RULE_INSERT_IN_LOOKUP_CONTROL_LEN 4
28605#define MC_CMD_MAE_OUTER_RULE_INSERT_IN_DO_CT_OFST 8
28606#define MC_CMD_MAE_OUTER_RULE_INSERT_IN_DO_CT_LBN 0
28607#define MC_CMD_MAE_OUTER_RULE_INSERT_IN_DO_CT_WIDTH 1
28608#define MC_CMD_MAE_OUTER_RULE_INSERT_IN_CT_VNI_MODE_OFST 8
28609#define MC_CMD_MAE_OUTER_RULE_INSERT_IN_CT_VNI_MODE_LBN 1
28610#define MC_CMD_MAE_OUTER_RULE_INSERT_IN_CT_VNI_MODE_WIDTH 2
28611/* Enum values, see field(s): */
28612/* MAE_CT_VNI_MODE */
28613#define MC_CMD_MAE_OUTER_RULE_INSERT_IN_DO_COUNT_OFST 8
28614#define MC_CMD_MAE_OUTER_RULE_INSERT_IN_DO_COUNT_LBN 3
28615#define MC_CMD_MAE_OUTER_RULE_INSERT_IN_DO_COUNT_WIDTH 1
28616#define MC_CMD_MAE_OUTER_RULE_INSERT_IN_CT_TCP_FLAGS_INHIBIT_OFST 8
28617#define MC_CMD_MAE_OUTER_RULE_INSERT_IN_CT_TCP_FLAGS_INHIBIT_LBN 4
28618#define MC_CMD_MAE_OUTER_RULE_INSERT_IN_CT_TCP_FLAGS_INHIBIT_WIDTH 1
28619#define MC_CMD_MAE_OUTER_RULE_INSERT_IN_RECIRC_ID_OFST 8
28620#define MC_CMD_MAE_OUTER_RULE_INSERT_IN_RECIRC_ID_LBN 8
28621#define MC_CMD_MAE_OUTER_RULE_INSERT_IN_RECIRC_ID_WIDTH 8
28622#define MC_CMD_MAE_OUTER_RULE_INSERT_IN_CT_DOMAIN_OFST 8
28623#define MC_CMD_MAE_OUTER_RULE_INSERT_IN_CT_DOMAIN_LBN 16
28624#define MC_CMD_MAE_OUTER_RULE_INSERT_IN_CT_DOMAIN_WIDTH 16
28625/* This field controls the actions that are performed when a rule is hit. */
28626#define MC_CMD_MAE_OUTER_RULE_INSERT_IN_ACTION_CONTROL_OFST 8
28627#define MC_CMD_MAE_OUTER_RULE_INSERT_IN_ACTION_CONTROL_LEN 4
28628/* ID of counter to increment when the rule is hit. Only used if the DO_COUNT
28629 * flag is set. The ID must have been allocated with COUNTER_TYPE=OR.
28630 */
28631#define MC_CMD_MAE_OUTER_RULE_INSERT_IN_COUNTER_ID_OFST 12
28632#define MC_CMD_MAE_OUTER_RULE_INSERT_IN_COUNTER_ID_LEN 4
28633/* Structure of the format MAE_ENC_FIELD_PAIRS. */
28634#define MC_CMD_MAE_OUTER_RULE_INSERT_IN_FIELD_MATCH_CRITERIA_OFST 16
28635#define MC_CMD_MAE_OUTER_RULE_INSERT_IN_FIELD_MATCH_CRITERIA_LEN 1
28636#define MC_CMD_MAE_OUTER_RULE_INSERT_IN_FIELD_MATCH_CRITERIA_MINNUM 0
28637#define MC_CMD_MAE_OUTER_RULE_INSERT_IN_FIELD_MATCH_CRITERIA_MAXNUM 236
28638#define MC_CMD_MAE_OUTER_RULE_INSERT_IN_FIELD_MATCH_CRITERIA_MAXNUM_MCDI2 1004
28639
28640/* MC_CMD_MAE_OUTER_RULE_INSERT_OUT msgresponse */
28641#define MC_CMD_MAE_OUTER_RULE_INSERT_OUT_LEN 4
28642#define MC_CMD_MAE_OUTER_RULE_INSERT_OUT_OR_ID_OFST 0
28643#define MC_CMD_MAE_OUTER_RULE_INSERT_OUT_OR_ID_LEN 4
28644/* enum: An outer match ID that is guaranteed never to represent an outer match
28645 */
28646#define MC_CMD_MAE_OUTER_RULE_INSERT_OUT_OUTER_RULE_ID_NULL 0xffffffff
28647
28648
28649/***********************************/
28650/* MC_CMD_MAE_OUTER_RULE_REMOVE
28651 */
28652#define MC_CMD_MAE_OUTER_RULE_REMOVE 0x15b
28653#undef MC_CMD_0x15b_PRIVILEGE_CTG
28654
28655#define MC_CMD_0x15b_PRIVILEGE_CTG SRIOV_CTG_MAE
28656
28657/* MC_CMD_MAE_OUTER_RULE_REMOVE_IN msgrequest */
28658#define MC_CMD_MAE_OUTER_RULE_REMOVE_IN_LENMIN 4
28659#define MC_CMD_MAE_OUTER_RULE_REMOVE_IN_LENMAX 128
28660#define MC_CMD_MAE_OUTER_RULE_REMOVE_IN_LENMAX_MCDI2 128
28661#define MC_CMD_MAE_OUTER_RULE_REMOVE_IN_LEN(num) (0+4*(num))
28662#define MC_CMD_MAE_OUTER_RULE_REMOVE_IN_OR_ID_NUM(len) (((len)-0)/4)
28663/* Same semantics as MC_CMD_MAE_COUNTER_FREE */
28664#define MC_CMD_MAE_OUTER_RULE_REMOVE_IN_OR_ID_OFST 0
28665#define MC_CMD_MAE_OUTER_RULE_REMOVE_IN_OR_ID_LEN 4
28666#define MC_CMD_MAE_OUTER_RULE_REMOVE_IN_OR_ID_MINNUM 1
28667#define MC_CMD_MAE_OUTER_RULE_REMOVE_IN_OR_ID_MAXNUM 32
28668#define MC_CMD_MAE_OUTER_RULE_REMOVE_IN_OR_ID_MAXNUM_MCDI2 32
28669
28670/* MC_CMD_MAE_OUTER_RULE_REMOVE_OUT msgresponse */
28671#define MC_CMD_MAE_OUTER_RULE_REMOVE_OUT_LENMIN 4
28672#define MC_CMD_MAE_OUTER_RULE_REMOVE_OUT_LENMAX 128
28673#define MC_CMD_MAE_OUTER_RULE_REMOVE_OUT_LENMAX_MCDI2 128
28674#define MC_CMD_MAE_OUTER_RULE_REMOVE_OUT_LEN(num) (0+4*(num))
28675#define MC_CMD_MAE_OUTER_RULE_REMOVE_OUT_REMOVED_OR_ID_NUM(len) (((len)-0)/4)
28676/* Same semantics as MC_CMD_MAE_COUNTER_FREE */
28677#define MC_CMD_MAE_OUTER_RULE_REMOVE_OUT_REMOVED_OR_ID_OFST 0
28678#define MC_CMD_MAE_OUTER_RULE_REMOVE_OUT_REMOVED_OR_ID_LEN 4
28679#define MC_CMD_MAE_OUTER_RULE_REMOVE_OUT_REMOVED_OR_ID_MINNUM 1
28680#define MC_CMD_MAE_OUTER_RULE_REMOVE_OUT_REMOVED_OR_ID_MAXNUM 32
28681#define MC_CMD_MAE_OUTER_RULE_REMOVE_OUT_REMOVED_OR_ID_MAXNUM_MCDI2 32
28682
28683
28684/***********************************/
28685/* MC_CMD_MAE_OUTER_RULE_UPDATE
28686 * Atomically change the response of an Outer Rule.
28687 */
28688#define MC_CMD_MAE_OUTER_RULE_UPDATE 0x17d
28689#undef MC_CMD_0x17d_PRIVILEGE_CTG
28690
28691#define MC_CMD_0x17d_PRIVILEGE_CTG SRIOV_CTG_MAE
28692
28693/* MC_CMD_MAE_OUTER_RULE_UPDATE_IN msgrequest */
28694#define MC_CMD_MAE_OUTER_RULE_UPDATE_IN_LEN 16
28695/* ID of outer rule to update */
28696#define MC_CMD_MAE_OUTER_RULE_UPDATE_IN_OR_ID_OFST 0
28697#define MC_CMD_MAE_OUTER_RULE_UPDATE_IN_OR_ID_LEN 4
28698/* Packets matching the rule will be parsed with this encapsulation. */
28699#define MC_CMD_MAE_OUTER_RULE_UPDATE_IN_ENCAP_TYPE_OFST 4
28700#define MC_CMD_MAE_OUTER_RULE_UPDATE_IN_ENCAP_TYPE_LEN 4
28701/* Enum values, see field(s): */
28702/* MAE_MCDI_ENCAP_TYPE */
28703/* This field controls the actions that are performed when a rule is hit. */
28704#define MC_CMD_MAE_OUTER_RULE_UPDATE_IN_ACTION_CONTROL_OFST 8
28705#define MC_CMD_MAE_OUTER_RULE_UPDATE_IN_ACTION_CONTROL_LEN 4
28706#define MC_CMD_MAE_OUTER_RULE_UPDATE_IN_DO_CT_OFST 8
28707#define MC_CMD_MAE_OUTER_RULE_UPDATE_IN_DO_CT_LBN 0
28708#define MC_CMD_MAE_OUTER_RULE_UPDATE_IN_DO_CT_WIDTH 1
28709#define MC_CMD_MAE_OUTER_RULE_UPDATE_IN_CT_VNI_MODE_OFST 8
28710#define MC_CMD_MAE_OUTER_RULE_UPDATE_IN_CT_VNI_MODE_LBN 1
28711#define MC_CMD_MAE_OUTER_RULE_UPDATE_IN_CT_VNI_MODE_WIDTH 2
28712/* Enum values, see field(s): */
28713/* MAE_CT_VNI_MODE */
28714#define MC_CMD_MAE_OUTER_RULE_UPDATE_IN_DO_COUNT_OFST 8
28715#define MC_CMD_MAE_OUTER_RULE_UPDATE_IN_DO_COUNT_LBN 3
28716#define MC_CMD_MAE_OUTER_RULE_UPDATE_IN_DO_COUNT_WIDTH 1
28717#define MC_CMD_MAE_OUTER_RULE_UPDATE_IN_CT_TCP_FLAGS_INHIBIT_OFST 8
28718#define MC_CMD_MAE_OUTER_RULE_UPDATE_IN_CT_TCP_FLAGS_INHIBIT_LBN 4
28719#define MC_CMD_MAE_OUTER_RULE_UPDATE_IN_CT_TCP_FLAGS_INHIBIT_WIDTH 1
28720#define MC_CMD_MAE_OUTER_RULE_UPDATE_IN_RECIRC_ID_OFST 8
28721#define MC_CMD_MAE_OUTER_RULE_UPDATE_IN_RECIRC_ID_LBN 8
28722#define MC_CMD_MAE_OUTER_RULE_UPDATE_IN_RECIRC_ID_WIDTH 8
28723#define MC_CMD_MAE_OUTER_RULE_UPDATE_IN_CT_DOMAIN_OFST 8
28724#define MC_CMD_MAE_OUTER_RULE_UPDATE_IN_CT_DOMAIN_LBN 16
28725#define MC_CMD_MAE_OUTER_RULE_UPDATE_IN_CT_DOMAIN_WIDTH 16
28726/* ID of counter to increment when the rule is hit. Only used if the DO_COUNT
28727 * flag is set. The ID must have been allocated with COUNTER_TYPE=OR.
28728 */
28729#define MC_CMD_MAE_OUTER_RULE_UPDATE_IN_COUNTER_ID_OFST 12
28730#define MC_CMD_MAE_OUTER_RULE_UPDATE_IN_COUNTER_ID_LEN 4
28731
28732/* MC_CMD_MAE_OUTER_RULE_UPDATE_OUT msgresponse */
28733#define MC_CMD_MAE_OUTER_RULE_UPDATE_OUT_LEN 0
28734
28735/* MAE_ACTION_RULE_RESPONSE structuredef */
28736#define MAE_ACTION_RULE_RESPONSE_LEN 16
28737#define MAE_ACTION_RULE_RESPONSE_ASL_ID_OFST 0
28738#define MAE_ACTION_RULE_RESPONSE_ASL_ID_LEN 4
28739#define MAE_ACTION_RULE_RESPONSE_ASL_ID_LBN 0
28740#define MAE_ACTION_RULE_RESPONSE_ASL_ID_WIDTH 32
28741/* Only one of ASL_ID or AS_ID may have a non-NULL value. */
28742#define MAE_ACTION_RULE_RESPONSE_AS_ID_OFST 4
28743#define MAE_ACTION_RULE_RESPONSE_AS_ID_LEN 4
28744#define MAE_ACTION_RULE_RESPONSE_AS_ID_LBN 32
28745#define MAE_ACTION_RULE_RESPONSE_AS_ID_WIDTH 32
28746/* Controls lookup flow when this rule is hit. See sub-fields for details. More
28747 * info on the lookup sequence can be found in SF-122976-TC. It is an error to
28748 * set both DO_CT and DO_RECIRC.
28749 */
28750#define MAE_ACTION_RULE_RESPONSE_LOOKUP_CONTROL_OFST 8
28751#define MAE_ACTION_RULE_RESPONSE_LOOKUP_CONTROL_LEN 4
28752#define MAE_ACTION_RULE_RESPONSE_DO_CT_OFST 8
28753#define MAE_ACTION_RULE_RESPONSE_DO_CT_LBN 0
28754#define MAE_ACTION_RULE_RESPONSE_DO_CT_WIDTH 1
28755#define MAE_ACTION_RULE_RESPONSE_DO_RECIRC_OFST 8
28756#define MAE_ACTION_RULE_RESPONSE_DO_RECIRC_LBN 1
28757#define MAE_ACTION_RULE_RESPONSE_DO_RECIRC_WIDTH 1
28758#define MAE_ACTION_RULE_RESPONSE_CT_VNI_MODE_OFST 8
28759#define MAE_ACTION_RULE_RESPONSE_CT_VNI_MODE_LBN 2
28760#define MAE_ACTION_RULE_RESPONSE_CT_VNI_MODE_WIDTH 2
28761/* Enum values, see field(s): */
28762/* MAE_CT_VNI_MODE */
28763#define MAE_ACTION_RULE_RESPONSE_RECIRC_ID_OFST 8
28764#define MAE_ACTION_RULE_RESPONSE_RECIRC_ID_LBN 8
28765#define MAE_ACTION_RULE_RESPONSE_RECIRC_ID_WIDTH 8
28766#define MAE_ACTION_RULE_RESPONSE_CT_DOMAIN_OFST 8
28767#define MAE_ACTION_RULE_RESPONSE_CT_DOMAIN_LBN 16
28768#define MAE_ACTION_RULE_RESPONSE_CT_DOMAIN_WIDTH 16
28769#define MAE_ACTION_RULE_RESPONSE_LOOKUP_CONTROL_LBN 64
28770#define MAE_ACTION_RULE_RESPONSE_LOOKUP_CONTROL_WIDTH 32
28771/* Counter ID to increment if DO_CT or DO_RECIRC is set. Must be set to
28772 * COUNTER_ID_NULL otherwise. Counter ID must have been allocated with
28773 * COUNTER_TYPE=AR.
28774 */
28775#define MAE_ACTION_RULE_RESPONSE_COUNTER_ID_OFST 12
28776#define MAE_ACTION_RULE_RESPONSE_COUNTER_ID_LEN 4
28777#define MAE_ACTION_RULE_RESPONSE_COUNTER_ID_LBN 96
28778#define MAE_ACTION_RULE_RESPONSE_COUNTER_ID_WIDTH 32
28779
28780
28781/***********************************/
28782/* MC_CMD_MAE_ACTION_RULE_INSERT
28783 * Insert a rule specify that packets matching a filter be processed according
28784 * to a previous allocated action. Masks can be set as indicated by
28785 * MC_CMD_MAE_GET_MATCH_FIELD_CAPABILITIES. If the maximum number of rules have
28786 * already been inserted then the command will fail with MC_CMD_ERR_ENOSPC.
28787 */
28788#define MC_CMD_MAE_ACTION_RULE_INSERT 0x15c
28789#undef MC_CMD_0x15c_PRIVILEGE_CTG
28790
28791#define MC_CMD_0x15c_PRIVILEGE_CTG SRIOV_CTG_MAE
28792
28793/* MC_CMD_MAE_ACTION_RULE_INSERT_IN msgrequest */
28794#define MC_CMD_MAE_ACTION_RULE_INSERT_IN_LENMIN 28
28795#define MC_CMD_MAE_ACTION_RULE_INSERT_IN_LENMAX 252
28796#define MC_CMD_MAE_ACTION_RULE_INSERT_IN_LENMAX_MCDI2 1020
28797#define MC_CMD_MAE_ACTION_RULE_INSERT_IN_LEN(num) (28+1*(num))
28798#define MC_CMD_MAE_ACTION_RULE_INSERT_IN_MATCH_CRITERIA_NUM(len) (((len)-28)/1)
28799/* See MC_CMD_MAE_OUTER_RULE_REGISTER_IN/PRIO. */
28800#define MC_CMD_MAE_ACTION_RULE_INSERT_IN_PRIO_OFST 0
28801#define MC_CMD_MAE_ACTION_RULE_INSERT_IN_PRIO_LEN 4
28802/* Structure of the format MAE_ACTION_RULE_RESPONSE */
28803#define MC_CMD_MAE_ACTION_RULE_INSERT_IN_RESPONSE_OFST 4
28804#define MC_CMD_MAE_ACTION_RULE_INSERT_IN_RESPONSE_LEN 20
28805/* Reserved for future use. Must be set to zero. */
28806#define MC_CMD_MAE_ACTION_RULE_INSERT_IN_RSVD_OFST 24
28807#define MC_CMD_MAE_ACTION_RULE_INSERT_IN_RSVD_LEN 4
28808/* Structure of the format MAE_FIELD_MASK_VALUE_PAIRS */
28809#define MC_CMD_MAE_ACTION_RULE_INSERT_IN_MATCH_CRITERIA_OFST 28
28810#define MC_CMD_MAE_ACTION_RULE_INSERT_IN_MATCH_CRITERIA_LEN 1
28811#define MC_CMD_MAE_ACTION_RULE_INSERT_IN_MATCH_CRITERIA_MINNUM 0
28812#define MC_CMD_MAE_ACTION_RULE_INSERT_IN_MATCH_CRITERIA_MAXNUM 224
28813#define MC_CMD_MAE_ACTION_RULE_INSERT_IN_MATCH_CRITERIA_MAXNUM_MCDI2 992
28814
28815/* MC_CMD_MAE_ACTION_RULE_INSERT_OUT msgresponse */
28816#define MC_CMD_MAE_ACTION_RULE_INSERT_OUT_LEN 4
28817#define MC_CMD_MAE_ACTION_RULE_INSERT_OUT_AR_ID_OFST 0
28818#define MC_CMD_MAE_ACTION_RULE_INSERT_OUT_AR_ID_LEN 4
28819/* enum: An action rule ID that is guaranteed never to represent an action rule
28820 */
28821#define MC_CMD_MAE_ACTION_RULE_INSERT_OUT_ACTION_RULE_ID_NULL 0xffffffff
28822
28823
28824/***********************************/
28825/* MC_CMD_MAE_ACTION_RULE_UPDATE
28826 * Atomically change the response of an action rule. Firmware may return
28827 * ENOTSUP, in which case the driver should DELETE/INSERT.
28828 */
28829#define MC_CMD_MAE_ACTION_RULE_UPDATE 0x15d
28830#undef MC_CMD_0x15d_PRIVILEGE_CTG
28831
28832#define MC_CMD_0x15d_PRIVILEGE_CTG SRIOV_CTG_MAE
28833
28834/* MC_CMD_MAE_ACTION_RULE_UPDATE_IN msgrequest */
28835#define MC_CMD_MAE_ACTION_RULE_UPDATE_IN_LEN 24
28836/* ID of action rule to update */
28837#define MC_CMD_MAE_ACTION_RULE_UPDATE_IN_AR_ID_OFST 0
28838#define MC_CMD_MAE_ACTION_RULE_UPDATE_IN_AR_ID_LEN 4
28839/* Structure of the format MAE_ACTION_RULE_RESPONSE */
28840#define MC_CMD_MAE_ACTION_RULE_UPDATE_IN_RESPONSE_OFST 4
28841#define MC_CMD_MAE_ACTION_RULE_UPDATE_IN_RESPONSE_LEN 20
28842
28843/* MC_CMD_MAE_ACTION_RULE_UPDATE_OUT msgresponse */
28844#define MC_CMD_MAE_ACTION_RULE_UPDATE_OUT_LEN 0
28845
28846
28847/***********************************/
28848/* MC_CMD_MAE_ACTION_RULE_DELETE
28849 */
28850#define MC_CMD_MAE_ACTION_RULE_DELETE 0x155
28851#undef MC_CMD_0x155_PRIVILEGE_CTG
28852
28853#define MC_CMD_0x155_PRIVILEGE_CTG SRIOV_CTG_MAE
28854
28855/* MC_CMD_MAE_ACTION_RULE_DELETE_IN msgrequest */
28856#define MC_CMD_MAE_ACTION_RULE_DELETE_IN_LENMIN 4
28857#define MC_CMD_MAE_ACTION_RULE_DELETE_IN_LENMAX 128
28858#define MC_CMD_MAE_ACTION_RULE_DELETE_IN_LENMAX_MCDI2 128
28859#define MC_CMD_MAE_ACTION_RULE_DELETE_IN_LEN(num) (0+4*(num))
28860#define MC_CMD_MAE_ACTION_RULE_DELETE_IN_AR_ID_NUM(len) (((len)-0)/4)
28861/* Same semantics as MC_CMD_MAE_COUNTER_FREE */
28862#define MC_CMD_MAE_ACTION_RULE_DELETE_IN_AR_ID_OFST 0
28863#define MC_CMD_MAE_ACTION_RULE_DELETE_IN_AR_ID_LEN 4
28864#define MC_CMD_MAE_ACTION_RULE_DELETE_IN_AR_ID_MINNUM 1
28865#define MC_CMD_MAE_ACTION_RULE_DELETE_IN_AR_ID_MAXNUM 32
28866#define MC_CMD_MAE_ACTION_RULE_DELETE_IN_AR_ID_MAXNUM_MCDI2 32
28867
28868/* MC_CMD_MAE_ACTION_RULE_DELETE_OUT msgresponse */
28869#define MC_CMD_MAE_ACTION_RULE_DELETE_OUT_LENMIN 4
28870#define MC_CMD_MAE_ACTION_RULE_DELETE_OUT_LENMAX 128
28871#define MC_CMD_MAE_ACTION_RULE_DELETE_OUT_LENMAX_MCDI2 128
28872#define MC_CMD_MAE_ACTION_RULE_DELETE_OUT_LEN(num) (0+4*(num))
28873#define MC_CMD_MAE_ACTION_RULE_DELETE_OUT_DELETED_AR_ID_NUM(len) (((len)-0)/4)
28874/* Same semantics as MC_CMD_MAE_COUNTER_FREE */
28875#define MC_CMD_MAE_ACTION_RULE_DELETE_OUT_DELETED_AR_ID_OFST 0
28876#define MC_CMD_MAE_ACTION_RULE_DELETE_OUT_DELETED_AR_ID_LEN 4
28877#define MC_CMD_MAE_ACTION_RULE_DELETE_OUT_DELETED_AR_ID_MINNUM 1
28878#define MC_CMD_MAE_ACTION_RULE_DELETE_OUT_DELETED_AR_ID_MAXNUM 32
28879#define MC_CMD_MAE_ACTION_RULE_DELETE_OUT_DELETED_AR_ID_MAXNUM_MCDI2 32
28880
28881
28882/***********************************/
28883/* MC_CMD_MAE_MPORT_LOOKUP
28884 * Return the m-port corresponding to a selector.
28885 */
28886#define MC_CMD_MAE_MPORT_LOOKUP 0x160
28887#undef MC_CMD_0x160_PRIVILEGE_CTG
28888
28889#define MC_CMD_0x160_PRIVILEGE_CTG SRIOV_CTG_GENERAL
28890
28891/* MC_CMD_MAE_MPORT_LOOKUP_IN msgrequest */
28892#define MC_CMD_MAE_MPORT_LOOKUP_IN_LEN 4
28893#define MC_CMD_MAE_MPORT_LOOKUP_IN_MPORT_SELECTOR_OFST 0
28894#define MC_CMD_MAE_MPORT_LOOKUP_IN_MPORT_SELECTOR_LEN 4
28895
28896/* MC_CMD_MAE_MPORT_LOOKUP_OUT msgresponse */
28897#define MC_CMD_MAE_MPORT_LOOKUP_OUT_LEN 4
28898#define MC_CMD_MAE_MPORT_LOOKUP_OUT_MPORT_ID_OFST 0
28899#define MC_CMD_MAE_MPORT_LOOKUP_OUT_MPORT_ID_LEN 4
28900
28901
28902/***********************************/
28903/* MC_CMD_MAE_MPORT_ALLOC
28904 * Allocates a m-port, which can subsequently be used in action rules as a
28905 * match or delivery argument.
28906 */
28907#define MC_CMD_MAE_MPORT_ALLOC 0x163
28908#undef MC_CMD_0x163_PRIVILEGE_CTG
28909
28910#define MC_CMD_0x163_PRIVILEGE_CTG SRIOV_CTG_MAE
28911
28912/* MC_CMD_MAE_MPORT_ALLOC_IN msgrequest */
28913#define MC_CMD_MAE_MPORT_ALLOC_IN_LEN 20
28914/* The type of m-port to allocate. Firmware may return ENOTSUP for certain
28915 * types.
28916 */
28917#define MC_CMD_MAE_MPORT_ALLOC_IN_TYPE_OFST 0
28918#define MC_CMD_MAE_MPORT_ALLOC_IN_TYPE_LEN 4
28919/* enum: Traffic can be sent to this type of m-port using an override
28920 * descriptor. Traffic received on this type of m-port will go to the VNIC on a
28921 * nominated m-port, and will be delivered with metadata identifying the alias
28922 * m-port.
28923 */
28924#define MC_CMD_MAE_MPORT_ALLOC_IN_MPORT_TYPE_ALIAS 0x1
28925/* enum: This type of m-port has a VNIC attached. Queues can be created on this
28926 * VNIC by specifying the created m-port as an m-port selector at queue
28927 * creation time.
28928 */
28929#define MC_CMD_MAE_MPORT_ALLOC_IN_MPORT_TYPE_VNIC 0x2
28930/* 128-bit value for use by the driver. */
28931#define MC_CMD_MAE_MPORT_ALLOC_IN_UUID_OFST 4
28932#define MC_CMD_MAE_MPORT_ALLOC_IN_UUID_LEN 16
28933
28934/* MC_CMD_MAE_MPORT_ALLOC_ALIAS_IN msgrequest */
28935#define MC_CMD_MAE_MPORT_ALLOC_ALIAS_IN_LEN 24
28936/* The type of m-port to allocate. Firmware may return ENOTSUP for certain
28937 * types.
28938 */
28939#define MC_CMD_MAE_MPORT_ALLOC_ALIAS_IN_TYPE_OFST 0
28940#define MC_CMD_MAE_MPORT_ALLOC_ALIAS_IN_TYPE_LEN 4
28941/* enum: Traffic can be sent to this type of m-port using an override
28942 * descriptor. Traffic received on this type of m-port will go to the VNIC on a
28943 * nominated m-port, and will be delivered with metadata identifying the alias
28944 * m-port.
28945 */
28946#define MC_CMD_MAE_MPORT_ALLOC_ALIAS_IN_MPORT_TYPE_ALIAS 0x1
28947/* enum: This type of m-port has a VNIC attached. Queues can be created on this
28948 * VNIC by specifying the created m-port as an m-port selector at queue
28949 * creation time.
28950 */
28951#define MC_CMD_MAE_MPORT_ALLOC_ALIAS_IN_MPORT_TYPE_VNIC 0x2
28952/* 128-bit value for use by the driver. */
28953#define MC_CMD_MAE_MPORT_ALLOC_ALIAS_IN_UUID_OFST 4
28954#define MC_CMD_MAE_MPORT_ALLOC_ALIAS_IN_UUID_LEN 16
28955/* An m-port selector identifying the VNIC to which traffic should be
28956 * delivered. This must currently be set to MAE_MPORT_SELECTOR_ASSIGNED (i.e.
28957 * the m-port assigned to the calling client).
28958 */
28959#define MC_CMD_MAE_MPORT_ALLOC_ALIAS_IN_DELIVER_MPORT_OFST 20
28960#define MC_CMD_MAE_MPORT_ALLOC_ALIAS_IN_DELIVER_MPORT_LEN 4
28961
28962/* MC_CMD_MAE_MPORT_ALLOC_VNIC_IN msgrequest */
28963#define MC_CMD_MAE_MPORT_ALLOC_VNIC_IN_LEN 20
28964/* The type of m-port to allocate. Firmware may return ENOTSUP for certain
28965 * types.
28966 */
28967#define MC_CMD_MAE_MPORT_ALLOC_VNIC_IN_TYPE_OFST 0
28968#define MC_CMD_MAE_MPORT_ALLOC_VNIC_IN_TYPE_LEN 4
28969/* enum: Traffic can be sent to this type of m-port using an override
28970 * descriptor. Traffic received on this type of m-port will go to the VNIC on a
28971 * nominated m-port, and will be delivered with metadata identifying the alias
28972 * m-port.
28973 */
28974#define MC_CMD_MAE_MPORT_ALLOC_VNIC_IN_MPORT_TYPE_ALIAS 0x1
28975/* enum: This type of m-port has a VNIC attached. Queues can be created on this
28976 * VNIC by specifying the created m-port as an m-port selector at queue
28977 * creation time.
28978 */
28979#define MC_CMD_MAE_MPORT_ALLOC_VNIC_IN_MPORT_TYPE_VNIC 0x2
28980/* 128-bit value for use by the driver. */
28981#define MC_CMD_MAE_MPORT_ALLOC_VNIC_IN_UUID_OFST 4
28982#define MC_CMD_MAE_MPORT_ALLOC_VNIC_IN_UUID_LEN 16
28983
28984/* MC_CMD_MAE_MPORT_ALLOC_OUT msgresponse */
28985#define MC_CMD_MAE_MPORT_ALLOC_OUT_LEN 4
28986/* ID of newly-allocated m-port. */
28987#define MC_CMD_MAE_MPORT_ALLOC_OUT_MPORT_ID_OFST 0
28988#define MC_CMD_MAE_MPORT_ALLOC_OUT_MPORT_ID_LEN 4
28989
28990/* MC_CMD_MAE_MPORT_ALLOC_ALIAS_OUT msgrequest */
28991#define MC_CMD_MAE_MPORT_ALLOC_ALIAS_OUT_LEN 24
28992/* ID of newly-allocated m-port. */
28993#define MC_CMD_MAE_MPORT_ALLOC_ALIAS_OUT_MPORT_ID_OFST 0
28994#define MC_CMD_MAE_MPORT_ALLOC_ALIAS_OUT_MPORT_ID_LEN 4
28995/* A value that will appear in the packet metadata for any packets delivered
28996 * using an alias type m-port. This value is guaranteed unique on the VNIC
28997 * being delivered to, and is guaranteed not to exceed the range of values
28998 * representable in the relevant metadata field.
28999 */
29000#define MC_CMD_MAE_MPORT_ALLOC_ALIAS_OUT_LABEL_OFST 20
29001#define MC_CMD_MAE_MPORT_ALLOC_ALIAS_OUT_LABEL_LEN 4
29002
29003/* MC_CMD_MAE_MPORT_ALLOC_VNIC_OUT msgrequest */
29004#define MC_CMD_MAE_MPORT_ALLOC_VNIC_OUT_LEN 4
29005/* ID of newly-allocated m-port. */
29006#define MC_CMD_MAE_MPORT_ALLOC_VNIC_OUT_MPORT_ID_OFST 0
29007#define MC_CMD_MAE_MPORT_ALLOC_VNIC_OUT_MPORT_ID_LEN 4
29008
29009
29010/***********************************/
29011/* MC_CMD_MAE_MPORT_FREE
29012 * Free a m-port which was previously allocated by the driver.
29013 */
29014#define MC_CMD_MAE_MPORT_FREE 0x164
29015#undef MC_CMD_0x164_PRIVILEGE_CTG
29016
29017#define MC_CMD_0x164_PRIVILEGE_CTG SRIOV_CTG_MAE
29018
29019/* MC_CMD_MAE_MPORT_FREE_IN msgrequest */
29020#define MC_CMD_MAE_MPORT_FREE_IN_LEN 4
29021/* MPORT_ID as returned by MC_CMD_MAE_MPORT_ALLOC. */
29022#define MC_CMD_MAE_MPORT_FREE_IN_MPORT_ID_OFST 0
29023#define MC_CMD_MAE_MPORT_FREE_IN_MPORT_ID_LEN 4
29024
29025/* MC_CMD_MAE_MPORT_FREE_OUT msgresponse */
29026#define MC_CMD_MAE_MPORT_FREE_OUT_LEN 0
29027
29028/* MAE_MPORT_DESC structuredef */
29029#define MAE_MPORT_DESC_LEN 52
29030#define MAE_MPORT_DESC_MPORT_ID_OFST 0
29031#define MAE_MPORT_DESC_MPORT_ID_LEN 4
29032#define MAE_MPORT_DESC_MPORT_ID_LBN 0
29033#define MAE_MPORT_DESC_MPORT_ID_WIDTH 32
29034/* Reserved for future purposes, contains information independent of caller */
29035#define MAE_MPORT_DESC_FLAGS_OFST 4
29036#define MAE_MPORT_DESC_FLAGS_LEN 4
29037#define MAE_MPORT_DESC_FLAGS_LBN 32
29038#define MAE_MPORT_DESC_FLAGS_WIDTH 32
29039#define MAE_MPORT_DESC_CALLER_FLAGS_OFST 8
29040#define MAE_MPORT_DESC_CALLER_FLAGS_LEN 4
29041#define MAE_MPORT_DESC_CAN_RECEIVE_ON_OFST 8
29042#define MAE_MPORT_DESC_CAN_RECEIVE_ON_LBN 0
29043#define MAE_MPORT_DESC_CAN_RECEIVE_ON_WIDTH 1
29044#define MAE_MPORT_DESC_CAN_DELIVER_TO_OFST 8
29045#define MAE_MPORT_DESC_CAN_DELIVER_TO_LBN 1
29046#define MAE_MPORT_DESC_CAN_DELIVER_TO_WIDTH 1
29047#define MAE_MPORT_DESC_CAN_DELETE_OFST 8
29048#define MAE_MPORT_DESC_CAN_DELETE_LBN 2
29049#define MAE_MPORT_DESC_CAN_DELETE_WIDTH 1
29050#define MAE_MPORT_DESC_IS_ZOMBIE_OFST 8
29051#define MAE_MPORT_DESC_IS_ZOMBIE_LBN 3
29052#define MAE_MPORT_DESC_IS_ZOMBIE_WIDTH 1
29053#define MAE_MPORT_DESC_CALLER_FLAGS_LBN 64
29054#define MAE_MPORT_DESC_CALLER_FLAGS_WIDTH 32
29055/* Not the ideal name; it's really the type of thing connected to the m-port */
29056#define MAE_MPORT_DESC_MPORT_TYPE_OFST 12
29057#define MAE_MPORT_DESC_MPORT_TYPE_LEN 4
29058/* enum: Connected to a MAC... */
29059#define MAE_MPORT_DESC_MPORT_TYPE_NET_PORT 0x0
29060/* enum: Adds metadata and delivers to another m-port */
29061#define MAE_MPORT_DESC_MPORT_TYPE_ALIAS 0x1
29062/* enum: Connected to a VNIC. */
29063#define MAE_MPORT_DESC_MPORT_TYPE_VNIC 0x2
29064#define MAE_MPORT_DESC_MPORT_TYPE_LBN 96
29065#define MAE_MPORT_DESC_MPORT_TYPE_WIDTH 32
29066/* 128-bit value available to drivers for m-port identification. */
29067#define MAE_MPORT_DESC_UUID_OFST 16
29068#define MAE_MPORT_DESC_UUID_LEN 16
29069#define MAE_MPORT_DESC_UUID_LBN 128
29070#define MAE_MPORT_DESC_UUID_WIDTH 128
29071/* Big wadge of space reserved for other common properties */
29072#define MAE_MPORT_DESC_RESERVED_OFST 32
29073#define MAE_MPORT_DESC_RESERVED_LEN 8
29074#define MAE_MPORT_DESC_RESERVED_LO_OFST 32
29075#define MAE_MPORT_DESC_RESERVED_LO_LEN 4
29076#define MAE_MPORT_DESC_RESERVED_LO_LBN 256
29077#define MAE_MPORT_DESC_RESERVED_LO_WIDTH 32
29078#define MAE_MPORT_DESC_RESERVED_HI_OFST 36
29079#define MAE_MPORT_DESC_RESERVED_HI_LEN 4
29080#define MAE_MPORT_DESC_RESERVED_HI_LBN 288
29081#define MAE_MPORT_DESC_RESERVED_HI_WIDTH 32
29082#define MAE_MPORT_DESC_RESERVED_LBN 256
29083#define MAE_MPORT_DESC_RESERVED_WIDTH 64
29084/* Logical port index. Only valid when type NET Port. */
29085#define MAE_MPORT_DESC_NET_PORT_IDX_OFST 40
29086#define MAE_MPORT_DESC_NET_PORT_IDX_LEN 4
29087#define MAE_MPORT_DESC_NET_PORT_IDX_LBN 320
29088#define MAE_MPORT_DESC_NET_PORT_IDX_WIDTH 32
29089/* The m-port delivered to */
29090#define MAE_MPORT_DESC_ALIAS_DELIVER_MPORT_ID_OFST 40
29091#define MAE_MPORT_DESC_ALIAS_DELIVER_MPORT_ID_LEN 4
29092#define MAE_MPORT_DESC_ALIAS_DELIVER_MPORT_ID_LBN 320
29093#define MAE_MPORT_DESC_ALIAS_DELIVER_MPORT_ID_WIDTH 32
29094/* The type of thing that owns the VNIC */
29095#define MAE_MPORT_DESC_VNIC_CLIENT_TYPE_OFST 40
29096#define MAE_MPORT_DESC_VNIC_CLIENT_TYPE_LEN 4
29097#define MAE_MPORT_DESC_VNIC_CLIENT_TYPE_FUNCTION 0x1 /* enum */
29098#define MAE_MPORT_DESC_VNIC_CLIENT_TYPE_PLUGIN 0x2 /* enum */
29099#define MAE_MPORT_DESC_VNIC_CLIENT_TYPE_LBN 320
29100#define MAE_MPORT_DESC_VNIC_CLIENT_TYPE_WIDTH 32
29101/* The PCIe interface on which the function lives. CJK: We need an enumeration
29102 * of interfaces that we extend as new interface (types) appear. This belongs
29103 * elsewhere and should be referenced from here
29104 */
29105#define MAE_MPORT_DESC_VNIC_FUNCTION_INTERFACE_OFST 44
29106#define MAE_MPORT_DESC_VNIC_FUNCTION_INTERFACE_LEN 4
29107#define MAE_MPORT_DESC_VNIC_FUNCTION_INTERFACE_LBN 352
29108#define MAE_MPORT_DESC_VNIC_FUNCTION_INTERFACE_WIDTH 32
29109#define MAE_MPORT_DESC_VNIC_FUNCTION_PF_IDX_OFST 48
29110#define MAE_MPORT_DESC_VNIC_FUNCTION_PF_IDX_LEN 2
29111#define MAE_MPORT_DESC_VNIC_FUNCTION_PF_IDX_LBN 384
29112#define MAE_MPORT_DESC_VNIC_FUNCTION_PF_IDX_WIDTH 16
29113#define MAE_MPORT_DESC_VNIC_FUNCTION_VF_IDX_OFST 50
29114#define MAE_MPORT_DESC_VNIC_FUNCTION_VF_IDX_LEN 2
29115/* enum: Indicates that the function is a PF */
29116#define MAE_MPORT_DESC_VF_IDX_NULL 0xffff
29117#define MAE_MPORT_DESC_VNIC_FUNCTION_VF_IDX_LBN 400
29118#define MAE_MPORT_DESC_VNIC_FUNCTION_VF_IDX_WIDTH 16
29119/* Reserved. Should be ignored for now. */
29120#define MAE_MPORT_DESC_VNIC_PLUGIN_TBD_OFST 44
29121#define MAE_MPORT_DESC_VNIC_PLUGIN_TBD_LEN 4
29122#define MAE_MPORT_DESC_VNIC_PLUGIN_TBD_LBN 352
29123#define MAE_MPORT_DESC_VNIC_PLUGIN_TBD_WIDTH 32
29124
29125/* MAE_MPORT_DESC_V2 structuredef */
29126#define MAE_MPORT_DESC_V2_LEN 56
29127#define MAE_MPORT_DESC_V2_MPORT_ID_OFST 0
29128#define MAE_MPORT_DESC_V2_MPORT_ID_LEN 4
29129#define MAE_MPORT_DESC_V2_MPORT_ID_LBN 0
29130#define MAE_MPORT_DESC_V2_MPORT_ID_WIDTH 32
29131/* Reserved for future purposes, contains information independent of caller */
29132#define MAE_MPORT_DESC_V2_FLAGS_OFST 4
29133#define MAE_MPORT_DESC_V2_FLAGS_LEN 4
29134#define MAE_MPORT_DESC_V2_FLAGS_LBN 32
29135#define MAE_MPORT_DESC_V2_FLAGS_WIDTH 32
29136#define MAE_MPORT_DESC_V2_CALLER_FLAGS_OFST 8
29137#define MAE_MPORT_DESC_V2_CALLER_FLAGS_LEN 4
29138#define MAE_MPORT_DESC_V2_CAN_RECEIVE_ON_OFST 8
29139#define MAE_MPORT_DESC_V2_CAN_RECEIVE_ON_LBN 0
29140#define MAE_MPORT_DESC_V2_CAN_RECEIVE_ON_WIDTH 1
29141#define MAE_MPORT_DESC_V2_CAN_DELIVER_TO_OFST 8
29142#define MAE_MPORT_DESC_V2_CAN_DELIVER_TO_LBN 1
29143#define MAE_MPORT_DESC_V2_CAN_DELIVER_TO_WIDTH 1
29144#define MAE_MPORT_DESC_V2_CAN_DELETE_OFST 8
29145#define MAE_MPORT_DESC_V2_CAN_DELETE_LBN 2
29146#define MAE_MPORT_DESC_V2_CAN_DELETE_WIDTH 1
29147#define MAE_MPORT_DESC_V2_IS_ZOMBIE_OFST 8
29148#define MAE_MPORT_DESC_V2_IS_ZOMBIE_LBN 3
29149#define MAE_MPORT_DESC_V2_IS_ZOMBIE_WIDTH 1
29150#define MAE_MPORT_DESC_V2_CALLER_FLAGS_LBN 64
29151#define MAE_MPORT_DESC_V2_CALLER_FLAGS_WIDTH 32
29152/* Not the ideal name; it's really the type of thing connected to the m-port */
29153#define MAE_MPORT_DESC_V2_MPORT_TYPE_OFST 12
29154#define MAE_MPORT_DESC_V2_MPORT_TYPE_LEN 4
29155/* enum: Connected to a MAC... */
29156#define MAE_MPORT_DESC_V2_MPORT_TYPE_NET_PORT 0x0
29157/* enum: Adds metadata and delivers to another m-port */
29158#define MAE_MPORT_DESC_V2_MPORT_TYPE_ALIAS 0x1
29159/* enum: Connected to a VNIC. */
29160#define MAE_MPORT_DESC_V2_MPORT_TYPE_VNIC 0x2
29161#define MAE_MPORT_DESC_V2_MPORT_TYPE_LBN 96
29162#define MAE_MPORT_DESC_V2_MPORT_TYPE_WIDTH 32
29163/* 128-bit value available to drivers for m-port identification. */
29164#define MAE_MPORT_DESC_V2_UUID_OFST 16
29165#define MAE_MPORT_DESC_V2_UUID_LEN 16
29166#define MAE_MPORT_DESC_V2_UUID_LBN 128
29167#define MAE_MPORT_DESC_V2_UUID_WIDTH 128
29168/* Big wadge of space reserved for other common properties */
29169#define MAE_MPORT_DESC_V2_RESERVED_OFST 32
29170#define MAE_MPORT_DESC_V2_RESERVED_LEN 8
29171#define MAE_MPORT_DESC_V2_RESERVED_LO_OFST 32
29172#define MAE_MPORT_DESC_V2_RESERVED_LO_LEN 4
29173#define MAE_MPORT_DESC_V2_RESERVED_LO_LBN 256
29174#define MAE_MPORT_DESC_V2_RESERVED_LO_WIDTH 32
29175#define MAE_MPORT_DESC_V2_RESERVED_HI_OFST 36
29176#define MAE_MPORT_DESC_V2_RESERVED_HI_LEN 4
29177#define MAE_MPORT_DESC_V2_RESERVED_HI_LBN 288
29178#define MAE_MPORT_DESC_V2_RESERVED_HI_WIDTH 32
29179#define MAE_MPORT_DESC_V2_RESERVED_LBN 256
29180#define MAE_MPORT_DESC_V2_RESERVED_WIDTH 64
29181/* Logical port index. Only valid when type NET Port. */
29182#define MAE_MPORT_DESC_V2_NET_PORT_IDX_OFST 40
29183#define MAE_MPORT_DESC_V2_NET_PORT_IDX_LEN 4
29184#define MAE_MPORT_DESC_V2_NET_PORT_IDX_LBN 320
29185#define MAE_MPORT_DESC_V2_NET_PORT_IDX_WIDTH 32
29186/* The m-port delivered to */
29187#define MAE_MPORT_DESC_V2_ALIAS_DELIVER_MPORT_ID_OFST 40
29188#define MAE_MPORT_DESC_V2_ALIAS_DELIVER_MPORT_ID_LEN 4
29189#define MAE_MPORT_DESC_V2_ALIAS_DELIVER_MPORT_ID_LBN 320
29190#define MAE_MPORT_DESC_V2_ALIAS_DELIVER_MPORT_ID_WIDTH 32
29191/* The type of thing that owns the VNIC */
29192#define MAE_MPORT_DESC_V2_VNIC_CLIENT_TYPE_OFST 40
29193#define MAE_MPORT_DESC_V2_VNIC_CLIENT_TYPE_LEN 4
29194#define MAE_MPORT_DESC_V2_VNIC_CLIENT_TYPE_FUNCTION 0x1 /* enum */
29195#define MAE_MPORT_DESC_V2_VNIC_CLIENT_TYPE_PLUGIN 0x2 /* enum */
29196#define MAE_MPORT_DESC_V2_VNIC_CLIENT_TYPE_LBN 320
29197#define MAE_MPORT_DESC_V2_VNIC_CLIENT_TYPE_WIDTH 32
29198/* The PCIe interface on which the function lives. CJK: We need an enumeration
29199 * of interfaces that we extend as new interface (types) appear. This belongs
29200 * elsewhere and should be referenced from here
29201 */
29202#define MAE_MPORT_DESC_V2_VNIC_FUNCTION_INTERFACE_OFST 44
29203#define MAE_MPORT_DESC_V2_VNIC_FUNCTION_INTERFACE_LEN 4
29204#define MAE_MPORT_DESC_V2_VNIC_FUNCTION_INTERFACE_LBN 352
29205#define MAE_MPORT_DESC_V2_VNIC_FUNCTION_INTERFACE_WIDTH 32
29206#define MAE_MPORT_DESC_V2_VNIC_FUNCTION_PF_IDX_OFST 48
29207#define MAE_MPORT_DESC_V2_VNIC_FUNCTION_PF_IDX_LEN 2
29208#define MAE_MPORT_DESC_V2_VNIC_FUNCTION_PF_IDX_LBN 384
29209#define MAE_MPORT_DESC_V2_VNIC_FUNCTION_PF_IDX_WIDTH 16
29210#define MAE_MPORT_DESC_V2_VNIC_FUNCTION_VF_IDX_OFST 50
29211#define MAE_MPORT_DESC_V2_VNIC_FUNCTION_VF_IDX_LEN 2
29212/* enum: Indicates that the function is a PF */
29213#define MAE_MPORT_DESC_V2_VF_IDX_NULL 0xffff
29214#define MAE_MPORT_DESC_V2_VNIC_FUNCTION_VF_IDX_LBN 400
29215#define MAE_MPORT_DESC_V2_VNIC_FUNCTION_VF_IDX_WIDTH 16
29216/* Reserved. Should be ignored for now. */
29217#define MAE_MPORT_DESC_V2_VNIC_PLUGIN_TBD_OFST 44
29218#define MAE_MPORT_DESC_V2_VNIC_PLUGIN_TBD_LEN 4
29219#define MAE_MPORT_DESC_V2_VNIC_PLUGIN_TBD_LBN 352
29220#define MAE_MPORT_DESC_V2_VNIC_PLUGIN_TBD_WIDTH 32
29221/* A client handle for the VNIC's owner. Only valid for type VNIC. */
29222#define MAE_MPORT_DESC_V2_VNIC_CLIENT_HANDLE_OFST 52
29223#define MAE_MPORT_DESC_V2_VNIC_CLIENT_HANDLE_LEN 4
29224#define MAE_MPORT_DESC_V2_VNIC_CLIENT_HANDLE_LBN 416
29225#define MAE_MPORT_DESC_V2_VNIC_CLIENT_HANDLE_WIDTH 32
29226
29227
29228/***********************************/
29229/* MC_CMD_MAE_MPORT_ENUMERATE
29230 * Deprecated in favour of MAE_MPORT_READ_JOURNAL. Support for this command
29231 * will be removed at some future point.
29232 */
29233#define MC_CMD_MAE_MPORT_ENUMERATE 0x17c
29234#undef MC_CMD_0x17c_PRIVILEGE_CTG
29235
29236#define MC_CMD_0x17c_PRIVILEGE_CTG SRIOV_CTG_GENERAL
29237
29238/* MC_CMD_MAE_MPORT_ENUMERATE_IN msgrequest */
29239#define MC_CMD_MAE_MPORT_ENUMERATE_IN_LEN 0
29240
29241/* MC_CMD_MAE_MPORT_ENUMERATE_OUT msgresponse */
29242#define MC_CMD_MAE_MPORT_ENUMERATE_OUT_LENMIN 8
29243#define MC_CMD_MAE_MPORT_ENUMERATE_OUT_LENMAX 252
29244#define MC_CMD_MAE_MPORT_ENUMERATE_OUT_LENMAX_MCDI2 1020
29245#define MC_CMD_MAE_MPORT_ENUMERATE_OUT_LEN(num) (8+1*(num))
29246#define MC_CMD_MAE_MPORT_ENUMERATE_OUT_MPORT_DESC_DATA_NUM(len) (((len)-8)/1)
29247#define MC_CMD_MAE_MPORT_ENUMERATE_OUT_MPORT_DESC_COUNT_OFST 0
29248#define MC_CMD_MAE_MPORT_ENUMERATE_OUT_MPORT_DESC_COUNT_LEN 4
29249#define MC_CMD_MAE_MPORT_ENUMERATE_OUT_SIZEOF_MPORT_DESC_OFST 4
29250#define MC_CMD_MAE_MPORT_ENUMERATE_OUT_SIZEOF_MPORT_DESC_LEN 4
29251/* Any array of MAE_MPORT_DESC structures. The MAE_MPORT_DESC structure may
29252 * grow in future version of this command. Drivers should use a stride of
29253 * SIZEOF_MPORT_DESC. Fields beyond SIZEOF_MPORT_DESC are not present.
29254 */
29255#define MC_CMD_MAE_MPORT_ENUMERATE_OUT_MPORT_DESC_DATA_OFST 8
29256#define MC_CMD_MAE_MPORT_ENUMERATE_OUT_MPORT_DESC_DATA_LEN 1
29257#define MC_CMD_MAE_MPORT_ENUMERATE_OUT_MPORT_DESC_DATA_MINNUM 0
29258#define MC_CMD_MAE_MPORT_ENUMERATE_OUT_MPORT_DESC_DATA_MAXNUM 244
29259#define MC_CMD_MAE_MPORT_ENUMERATE_OUT_MPORT_DESC_DATA_MAXNUM_MCDI2 1012
29260
29261
29262/***********************************/
29263/* MC_CMD_MAE_MPORT_READ_JOURNAL
29264 * Firmware maintains a per-client journal of mport creations and deletions.
29265 * This journal is clear-on-read, i.e. repeated calls of this command will
29266 * drain the buffer. Whenever the caller resets its function via FLR or
29267 * MC_CMD_ENTITY_RESET, the journal is regenerated from a blank start.
29268 */
29269#define MC_CMD_MAE_MPORT_READ_JOURNAL 0x147
29270#undef MC_CMD_0x147_PRIVILEGE_CTG
29271
29272#define MC_CMD_0x147_PRIVILEGE_CTG SRIOV_CTG_MAE
29273
29274/* MC_CMD_MAE_MPORT_READ_JOURNAL_IN msgrequest */
29275#define MC_CMD_MAE_MPORT_READ_JOURNAL_IN_LEN 4
29276/* Any unused flags are reserved and must be set to zero. */
29277#define MC_CMD_MAE_MPORT_READ_JOURNAL_IN_FLAGS_OFST 0
29278#define MC_CMD_MAE_MPORT_READ_JOURNAL_IN_FLAGS_LEN 4
29279
29280/* MC_CMD_MAE_MPORT_READ_JOURNAL_OUT msgresponse */
29281#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_LENMIN 12
29282#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_LENMAX 252
29283#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_LENMAX_MCDI2 1020
29284#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_LEN(num) (12+1*(num))
29285#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MPORT_DESC_DATA_NUM(len) (((len)-12)/1)
29286/* Any unused flags are reserved and must be ignored. */
29287#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_FLAGS_OFST 0
29288#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_FLAGS_LEN 4
29289#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MORE_OFST 0
29290#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MORE_LBN 0
29291#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MORE_WIDTH 1
29292/* The number of MAE_MPORT_DESC structures in MPORT_DESC_DATA. May be zero. */
29293#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MPORT_DESC_COUNT_OFST 4
29294#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MPORT_DESC_COUNT_LEN 4
29295#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_SIZEOF_MPORT_DESC_OFST 8
29296#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_SIZEOF_MPORT_DESC_LEN 4
29297/* Any array of MAE_MPORT_DESC structures. The MAE_MPORT_DESC structure may
29298 * grow in future version of this command. Drivers should use a stride of
29299 * SIZEOF_MPORT_DESC. Fields beyond SIZEOF_MPORT_DESC are not present.
29300 */
29301#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MPORT_DESC_DATA_OFST 12
29302#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MPORT_DESC_DATA_LEN 1
29303#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MPORT_DESC_DATA_MINNUM 0
29304#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MPORT_DESC_DATA_MAXNUM 240
29305#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MPORT_DESC_DATA_MAXNUM_MCDI2 1008
29306
29307/* TABLE_FIELD_DESCR structuredef: An individual table field descriptor. This
29308 * describes the location and properties of one N-bit field within a wider
29309 * M-bit key/mask/response value.
29310 */
29311#define TABLE_FIELD_DESCR_LEN 8
29312/* Identifier for this field. */
29313#define TABLE_FIELD_DESCR_FIELD_ID_OFST 0
29314#define TABLE_FIELD_DESCR_FIELD_ID_LEN 2
29315/* Enum values, see field(s): */
29316/* TABLE_FIELD_ID */
29317#define TABLE_FIELD_DESCR_FIELD_ID_LBN 0
29318#define TABLE_FIELD_DESCR_FIELD_ID_WIDTH 16
29319/* Lowest (least significant) bit number of the bits of this field. */
29320#define TABLE_FIELD_DESCR_LBN_OFST 2
29321#define TABLE_FIELD_DESCR_LBN_LEN 2
29322#define TABLE_FIELD_DESCR_LBN_LBN 16
29323#define TABLE_FIELD_DESCR_LBN_WIDTH 16
29324/* Width of this field in bits. */
29325#define TABLE_FIELD_DESCR_WIDTH_OFST 4
29326#define TABLE_FIELD_DESCR_WIDTH_LEN 2
29327#define TABLE_FIELD_DESCR_WIDTH_LBN 32
29328#define TABLE_FIELD_DESCR_WIDTH_WIDTH 16
29329/* The mask type for this field. (Note that masking is relevant to keys; fields
29330 * of responses are always reported with the EXACT type.)
29331 */
29332#define TABLE_FIELD_DESCR_MASK_TYPE_OFST 6
29333#define TABLE_FIELD_DESCR_MASK_TYPE_LEN 1
29334/* enum: Field must never be selected in the mask. */
29335#define TABLE_FIELD_DESCR_MASK_NEVER 0x0
29336/* enum: Exact match: field must always be selected in the mask. */
29337#define TABLE_FIELD_DESCR_MASK_EXACT 0x1
29338/* enum: Ternary match: arbitrary mask bits are allowed. */
29339#define TABLE_FIELD_DESCR_MASK_TERNARY 0x2
29340/* enum: Whole field match: mask must be all 1 bits, or all 0 bits. */
29341#define TABLE_FIELD_DESCR_MASK_WHOLE_FIELD 0x3
29342/* enum: Longest prefix match: mask must be 1 bit(s) followed by 0 bit(s). */
29343#define TABLE_FIELD_DESCR_MASK_LPM 0x4
29344#define TABLE_FIELD_DESCR_MASK_TYPE_LBN 48
29345#define TABLE_FIELD_DESCR_MASK_TYPE_WIDTH 8
29346/* A version code that allows field semantics to be extended. All fields
29347 * currently use version 0.
29348 */
29349#define TABLE_FIELD_DESCR_SCHEME_OFST 7
29350#define TABLE_FIELD_DESCR_SCHEME_LEN 1
29351#define TABLE_FIELD_DESCR_SCHEME_LBN 56
29352#define TABLE_FIELD_DESCR_SCHEME_WIDTH 8
29353
29354
29355/***********************************/
29356/* MC_CMD_TABLE_LIST
29357 * Return the list of tables which may be accessed via this table API.
29358 */
29359#define MC_CMD_TABLE_LIST 0x1c9
29360#undef MC_CMD_0x1c9_PRIVILEGE_CTG
29361
29362#define MC_CMD_0x1c9_PRIVILEGE_CTG SRIOV_CTG_GENERAL
29363
29364/* MC_CMD_TABLE_LIST_IN msgrequest */
29365#define MC_CMD_TABLE_LIST_IN_LEN 4
29366/* Index of the first item to be returned in the TABLE_ID sequence. (Set to 0
29367 * for the first call; further calls are only required if the whole sequence
29368 * does not fit within the maximum MCDI message size.)
29369 */
29370#define MC_CMD_TABLE_LIST_IN_FIRST_TABLE_ID_INDEX_OFST 0
29371#define MC_CMD_TABLE_LIST_IN_FIRST_TABLE_ID_INDEX_LEN 4
29372
29373/* MC_CMD_TABLE_LIST_OUT msgresponse */
29374#define MC_CMD_TABLE_LIST_OUT_LENMIN 4
29375#define MC_CMD_TABLE_LIST_OUT_LENMAX 252
29376#define MC_CMD_TABLE_LIST_OUT_LENMAX_MCDI2 1020
29377#define MC_CMD_TABLE_LIST_OUT_LEN(num) (4+4*(num))
29378#define MC_CMD_TABLE_LIST_OUT_TABLE_ID_NUM(len) (((len)-4)/4)
29379/* The total number of tables. */
29380#define MC_CMD_TABLE_LIST_OUT_N_TABLES_OFST 0
29381#define MC_CMD_TABLE_LIST_OUT_N_TABLES_LEN 4
29382/* A sequence of table identifiers. If all N_TABLES items do not fit, further
29383 * items can be obtained by repeating the call with a non-zero
29384 * FIRST_TABLE_ID_INDEX.
29385 */
29386#define MC_CMD_TABLE_LIST_OUT_TABLE_ID_OFST 4
29387#define MC_CMD_TABLE_LIST_OUT_TABLE_ID_LEN 4
29388#define MC_CMD_TABLE_LIST_OUT_TABLE_ID_MINNUM 0
29389#define MC_CMD_TABLE_LIST_OUT_TABLE_ID_MAXNUM 62
29390#define MC_CMD_TABLE_LIST_OUT_TABLE_ID_MAXNUM_MCDI2 254
29391/* Enum values, see field(s): */
29392/* TABLE_ID */
29393
29394
29395/***********************************/
29396/* MC_CMD_TABLE_DESCRIPTOR
29397 * Request the table descriptor for a particular table. This describes
29398 * properties of the table and the format of the key and response. May return
29399 * EINVAL for unknown table ID.
29400 */
29401#define MC_CMD_TABLE_DESCRIPTOR 0x1ca
29402#undef MC_CMD_0x1ca_PRIVILEGE_CTG
29403
29404#define MC_CMD_0x1ca_PRIVILEGE_CTG SRIOV_CTG_GENERAL
29405
29406/* MC_CMD_TABLE_DESCRIPTOR_IN msgrequest */
29407#define MC_CMD_TABLE_DESCRIPTOR_IN_LEN 8
29408/* Identifier for this field. */
29409#define MC_CMD_TABLE_DESCRIPTOR_IN_TABLE_ID_OFST 0
29410#define MC_CMD_TABLE_DESCRIPTOR_IN_TABLE_ID_LEN 4
29411/* Enum values, see field(s): */
29412/* TABLE_ID */
29413/* Index of the first item to be returned in the FIELDS sequence. (Set to 0 for
29414 * the first call; further calls are only required if the whole sequence does
29415 * not fit within the maximum MCDI message size.)
29416 */
29417#define MC_CMD_TABLE_DESCRIPTOR_IN_FIRST_FIELDS_INDEX_OFST 4
29418#define MC_CMD_TABLE_DESCRIPTOR_IN_FIRST_FIELDS_INDEX_LEN 4
29419
29420/* MC_CMD_TABLE_DESCRIPTOR_OUT msgresponse */
29421#define MC_CMD_TABLE_DESCRIPTOR_OUT_LENMIN 28
29422#define MC_CMD_TABLE_DESCRIPTOR_OUT_LENMAX 252
29423#define MC_CMD_TABLE_DESCRIPTOR_OUT_LENMAX_MCDI2 1020
29424#define MC_CMD_TABLE_DESCRIPTOR_OUT_LEN(num) (20+8*(num))
29425#define MC_CMD_TABLE_DESCRIPTOR_OUT_FIELDS_NUM(len) (((len)-20)/8)
29426/* Maximum number of entries in this table. */
29427#define MC_CMD_TABLE_DESCRIPTOR_OUT_MAX_ENTRIES_OFST 0
29428#define MC_CMD_TABLE_DESCRIPTOR_OUT_MAX_ENTRIES_LEN 4
29429/* The type of table. (This is really just informational; the important
29430 * properties of a table that affect programming can be deduced from other
29431 * items in the table or field descriptor.)
29432 */
29433#define MC_CMD_TABLE_DESCRIPTOR_OUT_TYPE_OFST 4
29434#define MC_CMD_TABLE_DESCRIPTOR_OUT_TYPE_LEN 2
29435/* enum: Direct table (essentially just an array). Behaves like a BCAM for
29436 * programming purposes, where the fact that the key is actually used as an
29437 * array index is really just an implementation detail.
29438 */
29439#define MC_CMD_TABLE_DESCRIPTOR_OUT_TYPE_DIRECT 0x1
29440/* enum: BCAM (binary CAM) table: exact match on all key fields." */
29441#define MC_CMD_TABLE_DESCRIPTOR_OUT_TYPE_BCAM 0x2
29442/* enum: TCAM (ternary CAM) table: matches fields with a mask. Each entry may
29443 * have its own different mask.
29444 */
29445#define MC_CMD_TABLE_DESCRIPTOR_OUT_TYPE_TCAM 0x3
29446/* enum: STCAM (semi-TCAM) table: like a TCAM but entries shared a limited
29447 * number of unique masks.
29448 */
29449#define MC_CMD_TABLE_DESCRIPTOR_OUT_TYPE_STCAM 0x4
29450/* Width of key (and corresponding mask, for TCAM or STCAM) in bits. */
29451#define MC_CMD_TABLE_DESCRIPTOR_OUT_KEY_WIDTH_OFST 6
29452#define MC_CMD_TABLE_DESCRIPTOR_OUT_KEY_WIDTH_LEN 2
29453/* Width of response in bits. */
29454#define MC_CMD_TABLE_DESCRIPTOR_OUT_RESP_WIDTH_OFST 8
29455#define MC_CMD_TABLE_DESCRIPTOR_OUT_RESP_WIDTH_LEN 2
29456/* The total number of fields in the key. */
29457#define MC_CMD_TABLE_DESCRIPTOR_OUT_N_KEY_FIELDS_OFST 10
29458#define MC_CMD_TABLE_DESCRIPTOR_OUT_N_KEY_FIELDS_LEN 2
29459/* The total number of fields in the response. */
29460#define MC_CMD_TABLE_DESCRIPTOR_OUT_N_RESP_FIELDS_OFST 12
29461#define MC_CMD_TABLE_DESCRIPTOR_OUT_N_RESP_FIELDS_LEN 2
29462/* Number of priorities for STCAM or TCAM; otherwise 0. The priority of a table
29463 * entry (relevant when more than one masked entry matches) ranges from
29464 * 0=highest to N_PRIORITIES-1=lowest.
29465 */
29466#define MC_CMD_TABLE_DESCRIPTOR_OUT_N_PRIORITIES_OFST 14
29467#define MC_CMD_TABLE_DESCRIPTOR_OUT_N_PRIORITIES_LEN 2
29468/* Maximum number of masks for STCAM; otherwise 0. */
29469#define MC_CMD_TABLE_DESCRIPTOR_OUT_MAX_MASKS_OFST 16
29470#define MC_CMD_TABLE_DESCRIPTOR_OUT_MAX_MASKS_LEN 2
29471/* Flags. */
29472#define MC_CMD_TABLE_DESCRIPTOR_OUT_FLAGS_OFST 18
29473#define MC_CMD_TABLE_DESCRIPTOR_OUT_FLAGS_LEN 1
29474#define MC_CMD_TABLE_DESCRIPTOR_OUT_ALLOC_MASKS_OFST 18
29475#define MC_CMD_TABLE_DESCRIPTOR_OUT_ALLOC_MASKS_LBN 0
29476#define MC_CMD_TABLE_DESCRIPTOR_OUT_ALLOC_MASKS_WIDTH 1
29477/* Access scheme version code, allowing the method of accessing table entries
29478 * to change semantics in future. A client which does not understand the value
29479 * of this field should assume that it cannot program this table. Currently
29480 * always set to 0 indicating the original MC_CMD_TABLE_INSERT/UPDATE/DELETE
29481 * semantics.
29482 */
29483#define MC_CMD_TABLE_DESCRIPTOR_OUT_SCHEME_OFST 19
29484#define MC_CMD_TABLE_DESCRIPTOR_OUT_SCHEME_LEN 1
29485/* A sequence of TABLE_FIELD_DESCR structures: N_KEY_FIELDS items describing
29486 * the key, followed by N_RESP_FIELDS items describing the response. If all
29487 * N_KEY_FIELDS+N_RESP_FIELDS items do not fit, further items can be obtained
29488 * by repeating the call with a non-zero FIRST_FIELDS_INDEX.
29489 */
29490#define MC_CMD_TABLE_DESCRIPTOR_OUT_FIELDS_OFST 20
29491#define MC_CMD_TABLE_DESCRIPTOR_OUT_FIELDS_LEN 8
29492#define MC_CMD_TABLE_DESCRIPTOR_OUT_FIELDS_LO_OFST 20
29493#define MC_CMD_TABLE_DESCRIPTOR_OUT_FIELDS_LO_LEN 4
29494#define MC_CMD_TABLE_DESCRIPTOR_OUT_FIELDS_LO_LBN 160
29495#define MC_CMD_TABLE_DESCRIPTOR_OUT_FIELDS_LO_WIDTH 32
29496#define MC_CMD_TABLE_DESCRIPTOR_OUT_FIELDS_HI_OFST 24
29497#define MC_CMD_TABLE_DESCRIPTOR_OUT_FIELDS_HI_LEN 4
29498#define MC_CMD_TABLE_DESCRIPTOR_OUT_FIELDS_HI_LBN 192
29499#define MC_CMD_TABLE_DESCRIPTOR_OUT_FIELDS_HI_WIDTH 32
29500#define MC_CMD_TABLE_DESCRIPTOR_OUT_FIELDS_MINNUM 1
29501#define MC_CMD_TABLE_DESCRIPTOR_OUT_FIELDS_MAXNUM 29
29502#define MC_CMD_TABLE_DESCRIPTOR_OUT_FIELDS_MAXNUM_MCDI2 125
29503
29504
29505/***********************************/
29506/* MC_CMD_TABLE_INSERT
29507 * Insert a new entry into a table. The entry must not currently exist. May
29508 * return EINVAL for unknown table ID or other bad request parameters, EEXIST
29509 * if the entry already exists, ENOSPC if there is no space or EPERM if the
29510 * operation is not permitted. In case of an error, the additional MCDI error
29511 * argument field returns the raw error code from the underlying CAM driver.
29512 */
29513#define MC_CMD_TABLE_INSERT 0x1cd
29514#undef MC_CMD_0x1cd_PRIVILEGE_CTG
29515
29516#define MC_CMD_0x1cd_PRIVILEGE_CTG SRIOV_CTG_GENERAL
29517
29518/* MC_CMD_TABLE_INSERT_IN msgrequest */
29519#define MC_CMD_TABLE_INSERT_IN_LENMIN 16
29520#define MC_CMD_TABLE_INSERT_IN_LENMAX 252
29521#define MC_CMD_TABLE_INSERT_IN_LENMAX_MCDI2 1020
29522#define MC_CMD_TABLE_INSERT_IN_LEN(num) (12+4*(num))
29523#define MC_CMD_TABLE_INSERT_IN_DATA_NUM(len) (((len)-12)/4)
29524/* Table identifier. */
29525#define MC_CMD_TABLE_INSERT_IN_TABLE_ID_OFST 0
29526#define MC_CMD_TABLE_INSERT_IN_TABLE_ID_LEN 4
29527/* Enum values, see field(s): */
29528/* TABLE_ID */
29529/* Width in bits of supplied key data (must match table properties). */
29530#define MC_CMD_TABLE_INSERT_IN_KEY_WIDTH_OFST 4
29531#define MC_CMD_TABLE_INSERT_IN_KEY_WIDTH_LEN 2
29532/* Width in bits of supplied mask data (0 for direct/BCAM tables, or for STCAM
29533 * when allocated MASK_ID is used instead).
29534 */
29535#define MC_CMD_TABLE_INSERT_IN_MASK_WIDTH_OFST 6
29536#define MC_CMD_TABLE_INSERT_IN_MASK_WIDTH_LEN 2
29537/* Width in bits of supplied response data (for INSERT and UPDATE operations
29538 * this must match the table properties; for DELETE operations, no response
29539 * data is required and this must be 0).
29540 */
29541#define MC_CMD_TABLE_INSERT_IN_RESP_WIDTH_OFST 8
29542#define MC_CMD_TABLE_INSERT_IN_RESP_WIDTH_LEN 2
29543/* Mask ID for STCAM table - used instead of mask data if the table descriptor
29544 * reports ALLOC_MASKS==1. Otherwise set to 0.
29545 */
29546#define MC_CMD_TABLE_INSERT_IN_MASK_ID_OFST 6
29547#define MC_CMD_TABLE_INSERT_IN_MASK_ID_LEN 2
29548/* Priority for TCAM or STCAM, in range 0..N_PRIORITIES-1, otherwise 0. */
29549#define MC_CMD_TABLE_INSERT_IN_PRIORITY_OFST 8
29550#define MC_CMD_TABLE_INSERT_IN_PRIORITY_LEN 2
29551/* (32-bit alignment padding - set to 0) */
29552#define MC_CMD_TABLE_INSERT_IN_RESERVED_OFST 10
29553#define MC_CMD_TABLE_INSERT_IN_RESERVED_LEN 2
29554/* Sequence of key, mask (if MASK_WIDTH > 0), and response (if RESP_WIDTH > 0)
29555 * data values. Each of these items is logically treated as a single wide N-bit
29556 * value, in which the individual fields have been placed within that value per
29557 * the LBN and WIDTH information from the table field descriptors. The wide
29558 * N-bit value is padded with 0 bits at the MSB end if necessary to make a
29559 * multiple of 32 bits. The value is then packed into this command as a
29560 * sequence of 32-bit words, bits [31:0] first, then bits [63:32], etc.
29561 */
29562#define MC_CMD_TABLE_INSERT_IN_DATA_OFST 12
29563#define MC_CMD_TABLE_INSERT_IN_DATA_LEN 4
29564#define MC_CMD_TABLE_INSERT_IN_DATA_MINNUM 1
29565#define MC_CMD_TABLE_INSERT_IN_DATA_MAXNUM 60
29566#define MC_CMD_TABLE_INSERT_IN_DATA_MAXNUM_MCDI2 252
29567
29568/* MC_CMD_TABLE_INSERT_OUT msgresponse */
29569#define MC_CMD_TABLE_INSERT_OUT_LEN 0
29570
29571
29572/***********************************/
29573/* MC_CMD_TABLE_UPDATE
29574 * Update an existing entry in a table with a new response value. May return
29575 * EINVAL for unknown table ID or other bad request parameters, ENOENT if the
29576 * entry does not already exist, or EPERM if the operation is not permitted. In
29577 * case of an error, the additional MCDI error argument field returns the raw
29578 * error code from the underlying CAM driver.
29579 */
29580#define MC_CMD_TABLE_UPDATE 0x1ce
29581#undef MC_CMD_0x1ce_PRIVILEGE_CTG
29582
29583#define MC_CMD_0x1ce_PRIVILEGE_CTG SRIOV_CTG_GENERAL
29584
29585/* MC_CMD_TABLE_UPDATE_IN msgrequest */
29586#define MC_CMD_TABLE_UPDATE_IN_LENMIN 16
29587#define MC_CMD_TABLE_UPDATE_IN_LENMAX 252
29588#define MC_CMD_TABLE_UPDATE_IN_LENMAX_MCDI2 1020
29589#define MC_CMD_TABLE_UPDATE_IN_LEN(num) (12+4*(num))
29590#define MC_CMD_TABLE_UPDATE_IN_DATA_NUM(len) (((len)-12)/4)
29591/* Table identifier. */
29592#define MC_CMD_TABLE_UPDATE_IN_TABLE_ID_OFST 0
29593#define MC_CMD_TABLE_UPDATE_IN_TABLE_ID_LEN 4
29594/* Enum values, see field(s): */
29595/* TABLE_ID */
29596/* Width in bits of supplied key data (must match table properties). */
29597#define MC_CMD_TABLE_UPDATE_IN_KEY_WIDTH_OFST 4
29598#define MC_CMD_TABLE_UPDATE_IN_KEY_WIDTH_LEN 2
29599/* Width in bits of supplied mask data (0 for direct/BCAM tables, or for STCAM
29600 * when allocated MASK_ID is used instead).
29601 */
29602#define MC_CMD_TABLE_UPDATE_IN_MASK_WIDTH_OFST 6
29603#define MC_CMD_TABLE_UPDATE_IN_MASK_WIDTH_LEN 2
29604/* Width in bits of supplied response data (for INSERT and UPDATE operations
29605 * this must match the table properties; for DELETE operations, no response
29606 * data is required and this must be 0).
29607 */
29608#define MC_CMD_TABLE_UPDATE_IN_RESP_WIDTH_OFST 8
29609#define MC_CMD_TABLE_UPDATE_IN_RESP_WIDTH_LEN 2
29610/* Mask ID for STCAM table - used instead of mask data if the table descriptor
29611 * reports ALLOC_MASKS==1. Otherwise set to 0.
29612 */
29613#define MC_CMD_TABLE_UPDATE_IN_MASK_ID_OFST 6
29614#define MC_CMD_TABLE_UPDATE_IN_MASK_ID_LEN 2
29615/* Priority for TCAM or STCAM, in range 0..N_PRIORITIES-1, otherwise 0. */
29616#define MC_CMD_TABLE_UPDATE_IN_PRIORITY_OFST 8
29617#define MC_CMD_TABLE_UPDATE_IN_PRIORITY_LEN 2
29618/* (32-bit alignment padding - set to 0) */
29619#define MC_CMD_TABLE_UPDATE_IN_RESERVED_OFST 10
29620#define MC_CMD_TABLE_UPDATE_IN_RESERVED_LEN 2
29621/* Sequence of key, mask (if MASK_WIDTH > 0), and response (if RESP_WIDTH > 0)
29622 * data values. Each of these items is logically treated as a single wide N-bit
29623 * value, in which the individual fields have been placed within that value per
29624 * the LBN and WIDTH information from the table field descriptors. The wide
29625 * N-bit value is padded with 0 bits at the MSB end if necessary to make a
29626 * multiple of 32 bits. The value is then packed into this command as a
29627 * sequence of 32-bit words, bits [31:0] first, then bits [63:32], etc.
29628 */
29629#define MC_CMD_TABLE_UPDATE_IN_DATA_OFST 12
29630#define MC_CMD_TABLE_UPDATE_IN_DATA_LEN 4
29631#define MC_CMD_TABLE_UPDATE_IN_DATA_MINNUM 1
29632#define MC_CMD_TABLE_UPDATE_IN_DATA_MAXNUM 60
29633#define MC_CMD_TABLE_UPDATE_IN_DATA_MAXNUM_MCDI2 252
29634
29635/* MC_CMD_TABLE_UPDATE_OUT msgresponse */
29636#define MC_CMD_TABLE_UPDATE_OUT_LEN 0
29637
29638
29639/***********************************/
29640/* MC_CMD_TABLE_DELETE
29641 * Delete an existing entry in a table. May return EINVAL for unknown table ID
29642 * or other bad request parameters, ENOENT if the entry does not exist, or
29643 * EPERM if the operation is not permitted. In case of an error, the additional
29644 * MCDI error argument field returns the raw error code from the underlying CAM
29645 * driver.
29646 */
29647#define MC_CMD_TABLE_DELETE 0x1cf
29648#undef MC_CMD_0x1cf_PRIVILEGE_CTG
29649
29650#define MC_CMD_0x1cf_PRIVILEGE_CTG SRIOV_CTG_GENERAL
29651
29652/* MC_CMD_TABLE_DELETE_IN msgrequest */
29653#define MC_CMD_TABLE_DELETE_IN_LENMIN 16
29654#define MC_CMD_TABLE_DELETE_IN_LENMAX 252
29655#define MC_CMD_TABLE_DELETE_IN_LENMAX_MCDI2 1020
29656#define MC_CMD_TABLE_DELETE_IN_LEN(num) (12+4*(num))
29657#define MC_CMD_TABLE_DELETE_IN_DATA_NUM(len) (((len)-12)/4)
29658/* Table identifier. */
29659#define MC_CMD_TABLE_DELETE_IN_TABLE_ID_OFST 0
29660#define MC_CMD_TABLE_DELETE_IN_TABLE_ID_LEN 4
29661/* Enum values, see field(s): */
29662/* TABLE_ID */
29663/* Width in bits of supplied key data (must match table properties). */
29664#define MC_CMD_TABLE_DELETE_IN_KEY_WIDTH_OFST 4
29665#define MC_CMD_TABLE_DELETE_IN_KEY_WIDTH_LEN 2
29666/* Width in bits of supplied mask data (0 for direct/BCAM tables, or for STCAM
29667 * when allocated MASK_ID is used instead).
29668 */
29669#define MC_CMD_TABLE_DELETE_IN_MASK_WIDTH_OFST 6
29670#define MC_CMD_TABLE_DELETE_IN_MASK_WIDTH_LEN 2
29671/* Width in bits of supplied response data (for INSERT and UPDATE operations
29672 * this must match the table properties; for DELETE operations, no response
29673 * data is required and this must be 0).
29674 */
29675#define MC_CMD_TABLE_DELETE_IN_RESP_WIDTH_OFST 8
29676#define MC_CMD_TABLE_DELETE_IN_RESP_WIDTH_LEN 2
29677/* Mask ID for STCAM table - used instead of mask data if the table descriptor
29678 * reports ALLOC_MASKS==1. Otherwise set to 0.
29679 */
29680#define MC_CMD_TABLE_DELETE_IN_MASK_ID_OFST 6
29681#define MC_CMD_TABLE_DELETE_IN_MASK_ID_LEN 2
29682/* Priority for TCAM or STCAM, in range 0..N_PRIORITIES-1, otherwise 0. */
29683#define MC_CMD_TABLE_DELETE_IN_PRIORITY_OFST 8
29684#define MC_CMD_TABLE_DELETE_IN_PRIORITY_LEN 2
29685/* (32-bit alignment padding - set to 0) */
29686#define MC_CMD_TABLE_DELETE_IN_RESERVED_OFST 10
29687#define MC_CMD_TABLE_DELETE_IN_RESERVED_LEN 2
29688/* Sequence of key, mask (if MASK_WIDTH > 0), and response (if RESP_WIDTH > 0)
29689 * data values. Each of these items is logically treated as a single wide N-bit
29690 * value, in which the individual fields have been placed within that value per
29691 * the LBN and WIDTH information from the table field descriptors. The wide
29692 * N-bit value is padded with 0 bits at the MSB end if necessary to make a
29693 * multiple of 32 bits. The value is then packed into this command as a
29694 * sequence of 32-bit words, bits [31:0] first, then bits [63:32], etc.
29695 */
29696#define MC_CMD_TABLE_DELETE_IN_DATA_OFST 12
29697#define MC_CMD_TABLE_DELETE_IN_DATA_LEN 4
29698#define MC_CMD_TABLE_DELETE_IN_DATA_MINNUM 1
29699#define MC_CMD_TABLE_DELETE_IN_DATA_MAXNUM 60
29700#define MC_CMD_TABLE_DELETE_IN_DATA_MAXNUM_MCDI2 252
29701
29702/* MC_CMD_TABLE_DELETE_OUT msgresponse */
29703#define MC_CMD_TABLE_DELETE_OUT_LEN 0
29704
29705
29706#endif /* MCDI_PCOL_H */
29707

source code of linux/drivers/net/ethernet/sfc/mcdi_pcol.h